WO2017071459A1 - 显示面板及其驱动方法和显示装置 - Google Patents

显示面板及其驱动方法和显示装置 Download PDF

Info

Publication number
WO2017071459A1
WO2017071459A1 PCT/CN2016/101615 CN2016101615W WO2017071459A1 WO 2017071459 A1 WO2017071459 A1 WO 2017071459A1 CN 2016101615 W CN2016101615 W CN 2016101615W WO 2017071459 A1 WO2017071459 A1 WO 2017071459A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
data
signal
display panel
common terminals
Prior art date
Application number
PCT/CN2016/101615
Other languages
English (en)
French (fr)
Inventor
苗京花
陈忠君
董学
陈小川
许睿
李牧冰
杨明
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/528,565 priority Critical patent/US10453377B2/en
Publication of WO2017071459A1 publication Critical patent/WO2017071459A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display panel and a driving method thereof, and a display device including the same.
  • Embodiments of the present disclosure provide a display panel and a driving method thereof, and a display device seeking to realize a narrow bezel or a borderless design.
  • a display panel includes: a plurality of gate lines extending in a first direction; and a plurality of data lines extending in a second direction substantially perpendicular to the first direction And a driving circuit disposed at one end of the data line and including: a plurality of scan signal output terminals, each connected to a corresponding one of the gate lines; a plurality of gray scale signal output terminals, each connected to the a respective one of the data lines; a gate driving unit configured to sequentially supply the scan signals to the plurality of gate lines via the plurality of scan signal output ends; and a source driving unit configured to pass the plurality of The gray scale signal output ends provide corresponding gray scale signals to the plurality of data lines.
  • a display panel comprising: a plurality of pixel units arranged in an array, each of the pixel units having a corresponding pixel thin film transistor; a plurality of strips extending in a first direction a gate line, each of the gate lines being connected to a corresponding row of pixel cells in the array; in a second direction substantially perpendicular to the first direction a plurality of data lines extending upwardly, each of the data lines being connected to a corresponding one of the column of pixel units; a driving circuit disposed at one end of the data line and including: a plurality of common terminals for outputting a scan signal and a corresponding gray scale signal; a switch network operative to selectively couple the common terminal to the gate line or the data line; and a drive unit configured to a) be separated in time
  • the scan signals are sequentially supplied to the plurality of common terminals in a plurality of first time periods, and in each of the first time periods in which the scan signals are supplied to
  • the driving unit is further configured to sequentially provide a flip signal to the plurality of common terminals in a plurality of third time periods immediately following the respective second time period, and wherein the flipping a signal is provided to each of the third time periods of one of the common terminals, causing the switch network to couple the plurality of common terminals to the plurality of gate lines, respectively, to store the charged gate voltage
  • the capacitor discharges, the flip signal having a polarity opposite to the polarity of the scan signal.
  • the switch network includes a plurality of first switches operative to couple the plurality of common terminals to the respective ones in response to a first gate control signal provided by the drive unit a plurality of gate lines, the first gate control signal being synchronized with one of the scan signal and the flip signal; and a plurality of second switches operative to be responsive to a portion provided by the drive unit
  • the plurality of common terminals are respectively coupled to the plurality of gate lines, the second gate control signal being synchronized with the other of the scan signal and the flip signal.
  • the first switch and the second switch connected to the same gate line share the same common terminal.
  • each of the first switches includes a transistor that has a gate that receives the first gate control signal, a first pole that is connected to a respective one of the common terminals, and a second pole that is connected to a corresponding one of the gate lines.
  • each of the second switches includes a transistor having a gate for receiving the second gate control signal, a first pole connected to a respective one of the common terminals, And a second pole connected to a corresponding one of the gate lines.
  • the driving unit is further configured to, in each of the second time periods, provide the plurality of common terminals for use in a corresponding row of pixel units in a first time interval a gray scale signal of an odd pixel unit, and causing the switch network to couple the plurality of common terminals to odd data lines of the data lines, respectively; and providing a plurality of common terminals to the plurality of common terminals in a second time interval Grayscale signals for even pixel cells in the respective row of pixel cells, and causing the switch network to couple the plurality of common terminals to even data lines of the data lines, respectively.
  • the switch network further includes: a plurality of third switches operable to respond to the first time interval in response to the first data control signal provided by the drive unit a common terminal coupled to the odd data line of the data line, respectively; and a plurality of fourth switches operative to be responsive to the second data control signal provided by the drive unit in the second time interval
  • the plurality of common terminals are respectively coupled to even data lines of the data lines.
  • the drive unit is further configured such that the first data control signal and the second data control signal are provided in succession.
  • each of the third switches is paired with a respective one of the fourth switches, wherein in each pair the third switch and the fourth switch share the same common terminal and are connected to An odd data line of the third switch is adjacent to an even data line connected to the fourth switch.
  • each of the third switches includes a transistor having a gate for receiving the first data control signal, a first pole connected to a respective one of the common terminals, and Connected to a second pole of a corresponding one of the odd data lines.
  • each of the fourth switches includes a transistor having a gate for receiving the second data control signal, a first pole connected to a respective one of the common terminals, and Connected to a second pole of a respective one of the even data lines.
  • a display device comprising: a timing controller configured to generate output image data based on input image data; and In the above-described display panel, the display panel is configured to display an image based on the output image data.
  • the driving unit is further configured to sequentially provide a flip signal to the plurality of common terminals in a plurality of third time periods immediately following the respective second time period, and wherein the flipping a signal is provided to each of the third time periods of one of the common terminals, causing the switch network to couple the plurality of common terminals to the plurality of gate lines, respectively, to store the charged gate voltage
  • the capacitor discharges, the flip signal having a polarity opposite to the polarity of the scan signal.
  • the timing controller is further configured to generate first data corresponding to the scan signal and second data corresponding to the flip signal.
  • the drive unit is further configured to generate the scan signal, the flip signal, and the gray scale signal based on the first data, the second data, and the output image data, respectively.
  • a method of driving a display panel comprising: for each row of pixel units in the array: connecting to the row of pixels in a first time period A gate line of the cell provides the scan signal; and a corresponding gray scale signal is provided to the plurality of data lines in a second time period immediately following the first time period.
  • providing the scan signal to a gate line connected to the row of pixel cells comprises: charging, by the scan signal, a gate voltage storage capacitor connected to the gate line, the charged gate voltage storage capacitor
  • the pixel thin film transistor of the row of pixel cells is enabled to remain in an on state during the second period of time.
  • providing the respective grayscale signals to the plurality of data lines includes providing odd data lines in the row of pixel cells to odd data lines in the row of data lines in a first time interval a grayscale signal; and in a second time interval, providing an even number of data lines in the data line with grayscale signals for even pixel cells in the row of pixel cells.
  • the method further includes providing a flip signal to a gate line connected to the row of pixel cells in a third time period immediately following the second time period, the flip signal having The polarities of the opposite polarity of the scan signal.
  • the method further includes generating first data corresponding to the scan signal and second data corresponding to the flip signal before providing the scan signal, so that the drive unit can respectively The scan signal and the flip signal are generated based on the first data and the second data.
  • Embodiments of the present disclosure arrange the gate drive unit at one end of the data line of the display panel, such as the bottom end of the display panel, thereby enabling a narrow bezel or borderless design of the display panel.
  • FIG. 1 is a schematic view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 2 is a schematic view of a display panel according to another embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of an example implementation of the display panel shown in FIG. 2;
  • FIG. 4 is a timing chart of the display panel shown in FIG. 3 before polarity inversion
  • Figure 5 is a timing diagram of the display panel shown in Figure 3 after polarity inversion
  • FIG. 6 is a block diagram of a display device in accordance with an embodiment of the present disclosure.
  • Figure 7 is a digital data table for generating the scan signal, the flip signal, and the gray scale signal shown in Figure 4;
  • Figure 8 is a digital data table for generating the scan signal, the flip signal, and the gray scale signal shown in Figure 5.
  • FIG. 1 is a schematic diagram of a display panel 100 in accordance with an embodiment of the present disclosure.
  • the display panel 100 includes a plurality of gate lines GLn1, GLn2, GLn3, a plurality of data lines Dm1(R), Dm1(G), Dm1(B), Dm2(R), Dm2(G), Dm2(B And the drive circuit 110.
  • the gate lines GLn1, GLn2, GLn3 extend in the first direction (horizontal direction in FIG. 1), and the data lines Dm1(R), Dm1(G), Dm1(B), Dm2(R), Dm2(G), Dm2 (B) extending in a second direction (vertical direction in Fig. 1) substantially perpendicular to the first direction.
  • a plurality of pixel units R, G, B are defined.
  • the driving circuit 110 is disposed at one end of the data lines Dm1(R), Dm1(G), Dm1(B), Dm2(R), Dm2(G), Dm2(B) (the bottom of the display panel 100 in FIG. 1) And including a plurality of scan signal output terminals 101a, 101b, 101c, a plurality of gray scale signal output terminals 102a, 102b, 102c, 102d, 102e, 102f, and a gate drive unit 112 And source drive unit 114.
  • Each of the plurality of scan signal output terminals 101a, 101b, 101c is connected to a corresponding one of the gate lines GLn1, GLn2, GLn3, and a plurality of gray scale signal output terminals 102a, 102b, 102c, 102d, 102e, 102f Each of them is connected to a corresponding one of the data lines Dm1(R), Dm1(G), Dm1(B), Dm2(R), Dm2(G), Dm2(B).
  • the gate driving unit 112 is configured to sequentially supply scan signals to the plurality of gate lines GLn1, GLn2, GLn3 via the plurality of scan signal output terminals 101a, 101b, 101c.
  • the source driving unit 114 is configured to provide a corresponding gray scale signal to the plurality of data lines via the plurality of gray scale signal output terminals 102a, 102b, 102c, 102d, 102e, 102f.
  • gate driving units are fabricated on the left and right sides of a display panel to form, for example, a gate driver on array (GOA) circuit.
  • the gate driving unit 112 is disposed on the data lines Dm1(R), Dm1(G), Dm1(B), Dm2(R), Dm2(G), Dm2(B) One end, such as the bottom end of the display panel 100. This can further reduce the size of the bezel of the display panel 100, thereby achieving a narrow bezel or a borderless design.
  • the inventors have further recognized that the gate drive function provided by the gate drive unit 112 and the source drive function provided by the source drive unit 114 can be implemented by a single integrated circuit, thereby further reducing the area occupied by the drive circuit 110.
  • FIG. 2 is a schematic diagram of a display panel 200 in accordance with another embodiment of the present disclosure.
  • the display panel 200 includes a plurality of pixel units represented by R, G, B, a plurality of gate lines GLn1, GLn2, GLn3, a plurality of data lines Dm1 (R), Dm1 (G), Dm1 (B), Dm2(R), Dm2(G), Dm2(B), drive circuit 210, and a plurality of gate voltage storage capacitors Cn1, Cn2, Cn3.
  • Each of the pixel units R, G, B is arranged in an array, and each pixel unit has a corresponding pixel thin film transistor ("TFT").
  • TFT pixel thin film transistor
  • Each of the gate lines GLn1, GLn2, GLn3 is connected to a corresponding one of the pixel units in the array, and the data lines Dm1(R), Dm1(G), Dm1(B), Dm2(R), Dm2(G)
  • Each of Dm2(B) is connected to a corresponding column of pixel cells in the array.
  • the driving circuit 210 is disposed at one end of the data lines Dm1(R), Dm1(G), Dm1(B), Dm2(R), Dm2(G), Dm2(B) (the bottom of the display panel 200 in FIG. 2) And includes a plurality of common terminals COM1, COM2, COM3, a switch network 212, and a drive unit 214.
  • a plurality of common terminals COM1, COM2, COM3 are used to output the scan signals generated by the drive unit 214 and the corresponding gray scale signals.
  • the scan signal (gate turn-on voltage) is used to turn on a pixel thin film transistor of one row of pixel cells.
  • a gray scale signal (grayscale voltage) is used to cause the pixel unit to present a corresponding gray scale to display an image on the display panel.
  • the switch network 212 is operable to selectively couple the common terminals COM1, COM2, COM3 to the gate lines GLn1, GLn2, GLn3 or the data lines Dm1(R), Dm1(G), Dm1(B) , Dm2 (R), Dm2 (G), Dm2 (B).
  • Switch network 212 includes a plurality of switches 201, 202, 203, 204.
  • the plurality of first switches 201 are operable to couple the plurality of common terminals COM1, COM2, COM3 to the plurality of gate lines, respectively, in response to a first gate control signal Gate SW1 provided by the drive unit 214 GLn1, GLn2, GLn3.
  • the plurality of second switches 202 are operable to couple the plurality of common terminals COM1, COM2, COM3 to the plurality of gate lines, respectively, in response to a second gate control signal Gate SW2 provided by the drive unit 214 GLn1, GLn2, GLn3.
  • a plurality of third switches 203 are operable to couple the plurality of common terminals COM1, COM2, COM3 to the respective time intervals in a first time interval in response to the first data control signal Data SW1 provided by the drive unit 214
  • a plurality of fourth switches 204 are operative to couple the plurality of common terminals COM1, COM2, COM3 to the second time interval in response to the second data control signal Data SW2 provided by the drive unit 214 The even data lines in the data lines Dm1(R), Dm1(G), Dm1(B), Dm2(R), Dm2(G), Dm2(B).
  • the common terminal COM1 is coupled to the gate line GLn1, the data line Dm1(R) or the data line Dm1(G) via the switch network 212
  • the common terminal COM2 is coupled to the gate line GLn2 and the data line Dm1 via the switch network 212.
  • the common terminal COM3 is coupled to the gate line GLn3, the data line Dm2 (G), or the data line Dm2 (B) via the switch network 212.
  • each of the common terminals COM1, COM2, COM3 is shown coupled to two data lines via the switch network 212, other embodiments are possible.
  • each common terminal can be coupled to fewer or more data lines via switch network 212.
  • the driving unit 214 is configured to sequentially supply the scan signals to the plurality of common terminals COM1, COM2, COM3 in a plurality of first time periods separated in time, and Wherein the scan signal is supplied to each of the first time periods of one of the common terminals COM1, COM2, COM3, so that the switch network 212 couples the plurality of common terminals COM1, COM2, COM3 to the respective A plurality of gate lines GLn1, GLn2, GLn3 are described such that the scan signal is applied to one of the gate lines GLn1, GLn2, GLn3.
  • the driving unit 214 is further configured to provide the gray scale signal to the plurality of common terminals COM1, COM2, COM3 and to the common in each of the second time periods immediately following the respective first time period
  • Each of the terminals COM1, COM2, COM3 is coupled to a corresponding one of the data lines Dm1(R), Dm1(G), Dm1(B), Dm2(R), Dm2(G), Dm2(B)
  • the gray scale signal is caused to be transmitted to the array of pixel units R, G, B.
  • the scan signal and the grayscale signal are provided in a first time period and a second time period, respectively.
  • the pixel thin film transistor ("TFT") of the row of pixel cells is required to remain in the on state during the second period of time so that the grayscale signal can be written into the pixel cell.
  • the display panel 200 further includes a plurality of gate voltage storage capacitors Cn1, Cn2, Cn3, each of which is connected to a corresponding one of the gate lines GLn1, GLn2, GLn3 and a predetermined voltage (for example, a ground voltage). between.
  • the gate voltage storage capacitor Cn1 is connected to the gate line GLn1
  • the gate voltage storage capacitor Cn2 is connected to the gate line GLn2
  • the gate voltage storage capacitor Cn3 is connected to the gate line GLn3.
  • each of the gate voltage storage capacitors Cn1, Cn2, Cn3 is operable to enable a pixel thin film transistor of a row of pixel cells connected to the gate line after being charged by the scan signal applied to the corresponding gate line The on state is maintained during the second time period in which the gray scale signal for the row of pixel cells is provided.
  • FIG. 3 is a schematic diagram of an example implementation of the display panel 200 shown in FIG. 2.
  • each of the switches 201, 202, 203, 204 in the switch network 212 is implemented by a transistor.
  • Each transistor 201 has a first gate for receiving the first gate control signal Gate SW1, and a first one connected to a corresponding one of the common terminals COM1, COM2, COM3 And a second pole connected to a corresponding one of the gate lines GLn1, GLn2, GLn3.
  • Each transistor 202 has a gate for receiving the second gate control signal Gate SW2, a first pole connected to a corresponding one of the common terminals COM1, COM2, COM3, and a gate line GLn1 connected thereto , the second pole of the corresponding one of GLn2, GLn3.
  • Each transistor 203 has a gate for receiving the first data control signal Data SW1, a first pole connected to a corresponding one of the common terminals COM1, COM2, COM3, and a connection to the odd data line The second pole of the corresponding one.
  • Each transistor 204 has a gate for receiving the second data control signal Data SW2, a first pole connected to a respective one of the common terminals COM1, COM2, COM3, and a connection to the even data line The second pole of the corresponding one.
  • each of the switches 201, 202, 203, 204 can be a thin film transistor or other suitable type of transistor. While each of the switches 201, 202, 203, 204 is shown as an N-type transistor, a P-type transistor can be used in other embodiments. As is known, the gate voltage for turning on the P-type transistor is a low level voltage.
  • the polarity inversion is in the form of column inversion in which the gray scale signals supplied to the two columns of pixel cells adjacent to each other have opposite polarities.
  • other forms of polarity inversion are possible, such as dot inversion or frame inversion.
  • phase 1 the first gate control signal Gate SW1 causes each of the first switches 201 to be turned on.
  • the scan signal VGH output via the common terminal COM1 is transferred to the gate voltage storage capacitor Cn1.
  • the gate voltage storage capacitor Cn1 is charged, and the voltage on the gate line GLn1 rises.
  • the voltage on gate line GLn1 peaks.
  • the gate voltage storage capacitor Cn1 capacitance value is selected such that the voltage on the gate line GLn1 in the 2nd and 3rd stages enables the pixel thin film transistor connected to the gate line GLn1 to remain on.
  • the first data control signal Data SW1 is made with the odd data lines (data line Dm1 (R), data line Dm1 (B), data line Dm2 in FIG. 3) (G))
  • Each of the connected third switches 203 is turned on. Since the pixel thin film transistors connected to the gate line GLn1 are turned on, the gray scale signals LR(m1n1), LB(m1n1), and LG(m2n1) from the driving unit 214 are respectively written to the odd pixel units connected to the gate line GLn1.
  • the second data control signal The Data SW2 turns on the fourth switches 204 connected to the even data lines (the data line Dm1 (G), the data line Dm2 (R), and the data line Dm2 (B) in Fig. 3). Since the pixel thin film transistors connected to the gate line GLn1 are turned on, the gray scale signals LG(m1n1), LR(m2n1), and LB(m2n1) from the driving unit 214 are respectively written to the even pixel units connected to the gate line GLn1.
  • phase 4 the second gate control signal Gate SW2 turns each of the second switches 202 on.
  • the flip signal VGL output via the common terminal COM1 is transferred to the gate voltage storage capacitor Cn1.
  • the gate voltage storage capacitor Cn1 is reversely charged, and the voltage on the gate line GLn1 is lowered.
  • phase 4 ends the voltage on gate line GLn1 drops to a minimum.
  • the pixel thin film transistor of the pixel cell of the n1th row is turned off. This ensures normal display of the next frame of image and avoids phenomena such as artifacts.
  • phase 5 reset phase
  • all external signals including scan signals and grayscale signals
  • the first gate control signal Gate SW1 causes each of the first switches 201 to be turned on.
  • the scan signal VGH output via the common terminal COM2 is transferred to the gate voltage storage capacitor Cn2.
  • the gate voltage storage capacitor Cn2 is charged, and the voltage on the gate line GLn2 rises.
  • the voltage on gate line GLn2 peaks.
  • the gate voltage storage capacitor Cn2 capacitance value is selected such that the voltage on the gate line GLn2 in the phases 7 and 8 enables the pixel thin film transistor connected to the gate line GLn2 to remain on.
  • the first data control signal Data SW1 is made with the odd data lines (data line Dm1 (R), data line Dm1 (B), data line Dm2 in FIG. 3) (G))
  • Each of the connected third switches 203 is turned on. Since the pixel thin film transistors connected to the gate line GLn2 are turned on, the gray scale signals LR (m1n2), LB (m1n2), and LG (m2n2) from the driving unit 214 are respectively written to the odd pixel units connected to the gate line GLn2.
  • the second data control signal Data SW2 is made with the even data lines (data line Dm1 (G), data line Dm2 (R), data line Dm2 in FIG. 3 (B))
  • Each of the connected fourth switches 204 is turned on. Since the pixel thin film transistors connected to the gate line GLn2 are turned on, the gray scale signals LG(m1n2), LR(m2n2), and LB(m2n2) from the driving unit 214 are respectively written to the even pixel units connected to the gate line GLn2.
  • phase 9 the second gate control signal Gate SW2 turns each of the second switches 202 on.
  • the flip signal VGL output via the common terminal COM2 is transferred to the gate voltage storage capacitor Cn2.
  • the gate voltage storage capacitor Cn2 is reversely charged and gated
  • the voltage on line GLn2 is reduced.
  • the voltage on gate line GLn2 is minimized.
  • the pixel thin film transistor of the pixel cell of the nth row is turned off.
  • FIG. 5 is a timing chart of the display panel shown in FIG. 3 after polarity inversion (column inversion), in which the polarity of the gray scale signal supplied to each column of pixel units is reversed compared to before the polarity is inverted. turn.
  • phase 1 the second gate control signal Gate SW2 turns each second switch 202 on.
  • the scan signal VGH output via the common terminal COM1 is transferred to the gate voltage storage capacitor Cn1.
  • the gate voltage storage capacitor Cn1 is charged, and the voltage on the gate line GLn1 rises.
  • the voltage on gate line GLn1 peaks.
  • the second data control signal Data SW2 is made to correspond to the even data lines (data line Dm1 (G), data line Dm2 (R), data line Dm2 in FIG. 3 (B))
  • Each of the connected fourth switches 204 is turned on. Since the pixel thin film transistors connected to the gate line GLn1 are turned on, the gray scale signals LG(m1n1), LR(m2n1), and LB(m2n1) from the driving unit 214 are respectively written to the even pixel units connected to the gate line GLn1.
  • the first data control signal Data SW1 is made with the odd data lines (data line Dm1 (R), data line Dm1 (B), data line Dm2 in FIG. 3) (G))
  • Each of the connected third switches 203 is turned on. Since the pixel thin film transistors connected to the gate line GLn1 are turned on, the gray scale signals LR(m1n1), LB(m1n1), and LG(m2n1) from the driving unit 214 are respectively written to the odd pixel units connected to the gate line GLn1.
  • phase 4 the first gate control signal Gate SW1 causes each of the first switches 201 to be turned on.
  • the flip signal VGL output via the common terminal COM1 is transferred to the gate voltage storage capacitor Cn1.
  • the gate voltage storage capacitor Cn1 is reversely charged, and the voltage on the gate line GLn1 is lowered.
  • phase 4 ends the voltage on gate line GLn1 drops to a minimum.
  • the pixel thin film transistor of the pixel cell of the n1th row is turned off.
  • phase 5 reset phase
  • all external signals including scan signals and grayscale signals
  • phase 6 the second gate control signal Gate SW2 turns each of the second switches 202 on.
  • the scan signal VGH output via the common terminal COM2 is transferred to the gate voltage storage capacitor Cn2.
  • the gate voltage storage capacitor Cn2 is charged, and the voltage on the gate line GLn2 rises.
  • the voltage on gate line GLn2 peaks.
  • the second data control signal The Data SW2 turns on the fourth switches 204 connected to the even data lines (the data line Dm1 (G), the data line Dm2 (R), and the data line Dm2 (B) in Fig. 3). Since the pixel thin film transistors connected to the gate line GLn2 are turned on, the gray scale signals LG(m1n2), LR(m2n2), and LB(m2n2) from the driving unit 214 are respectively written to the even pixel units connected to the gate line GLn2.
  • the first data control signal Data SW1 is made with the odd data lines (data line Dm1 (R), data line Dm1 (B), data line Dm2 in FIG. 3) (G))
  • Each of the connected third switches 203 is turned on. Since the pixel thin film transistors connected to the gate line GLn2 are turned on, the gray scale signals LR (m1n2), LB (m1n2), and LG (m2n2) from the driving unit 214 are respectively written to the odd pixel units connected to the gate line GLn2.
  • phase 9 the first gate control signal Gate SW1 causes each of the first switches 201 to be turned on.
  • the flip signal VGL output via the common terminal COM2 is transferred to the gate voltage storage capacitor Cn2.
  • the gate voltage storage capacitor Cn2 is reversely charged, and the voltage on the gate line GLn2 is lowered.
  • the voltage on gate line GLn2 is minimized.
  • the pixel thin film transistor of the pixel cell of the nth row is turned off.
  • the driving unit 214 can be implemented with an existing source driver chip.
  • drive unit 214 can be implemented with other hardware components, such as an application specific integrated circuit ASIC, a complex programmable logic device CPLD, or a field programmable gate array FPGA.
  • FIG. 6 is a block diagram of a display device 600 in accordance with an embodiment of the present disclosure.
  • the display device 600 includes a display panel 200 and a timing controller 610.
  • the display panel 200 includes an array of pixel cells and a drive unit 214, the detailed description of which is omitted herein.
  • the timing controller 610 receives the synchronization signal SYNC and the input image data R, G, B from, for example, a system interface, and is configured to generate output image data DAT based on the input image data R, G, B.
  • the output image data DAT is supplied to the display panel 200 for displaying an image.
  • the timing controller 610 also provides a control signal CONT, such as a clock signal, to the drive unit 214.
  • the driving unit 214 converts the output image data DAT into a gray scale signal in response to the control signal CONT and supplies it to the pixel array.
  • the timing controller 610 is further configured to generate first data corresponding to the scan signal VGH and second data corresponding to the flip signal VGL.
  • the driving unit 214 is also configured to generate the scan signal and the flip signal based on the first data and the second data, respectively. For example, when the display panel 200 has 256 gray levels, the sweep The first data corresponding to the trace signal VGH may be +255, and the second data corresponding to the flip signal VGL may be -255.
  • the digital data corresponding to the default gate line voltage signal can be zero.
  • the digital data may also be provided by the timing controller 610 to the drive unit 214, and the corresponding voltage signal generated by the drive unit 214. Accordingly, the drive unit 214 can generate a voltage signal as shown in FIGS. 4 and 5 based on the digital data received from the timing controller 610.
  • Fig. 7 is a digital data table for generating the scan signal VGH, the flip signal VGL, and the gray scale signal shown in Fig. 4.
  • the data in the table can be divided into groups, each consisting of four items, as indicated by the thick solid line.
  • Each row of data in the table corresponds to a signal applied to a corresponding row of pixel cells.
  • the first item in each group corresponds to a signal generated by the driving unit 214 in phase 1 of FIG. 4 and applied to the first row of pixel units via the common terminals COM1, COM2, COM3, in each group
  • the second item corresponds to the signal generated by the drive unit 214 in stage 2 of FIG. 4 and applied to the first row of pixel units via the common terminals COM1, COM2, COM3, and the third item in each group corresponds to the stage of FIG.
  • the signals generated by the drive unit 214 and applied to the first row of pixel units via the common terminals COM1, COM2, COM3, and the fourth item in each group is generated by the drive unit 214 in phase 4 of FIG. 4 and via The common terminals COM1, COM2, COM3 are applied to signals of the first row of pixel units.
  • Fig. 8 is a digital data table for generating the scan signal VGH, the flip signal VGL, and the gray scale signal shown in Fig. 5. Compared with FIG. 7, the polarity of the pixel values in FIG. 8 is inverted in columns.
  • the data in the table can be divided into groups, each of which includes four items, as indicated by the thick solid lines.
  • the fourth item in each group corresponds to the generation of the drive unit 214 in phase 1 of FIG. 5 and via the common terminals COM1, COM2, COM3.
  • the signals applied to the first row of pixel cells corresponds to the signal generated by the drive unit 214 in phase 2 of FIG. 5 and applied to the first row of pixel cells via the common terminals COM1, COM2, COM3,
  • the second item in each group corresponds to a signal generated by the driving unit 214 in step 3 of FIG.
  • a method of driving the display panel 200 as described in the above embodiments is provided.
  • the method includes providing, for each row of pixel cells in the array, the scan signal to a gate line connected to the row of pixel cells in a first time period; and second immediately following the first time period A corresponding gray scale signal is provided to the plurality of data lines in a time period.
  • providing the scan signal includes: charging, by the scan signal, a gate voltage storage capacitor connected to the gate line, and the charged gate voltage storage capacitor enables the pixel thin film transistor of the row of pixel units to Maintained in an on state during the second period of time.
  • providing a corresponding grayscale signal comprises: providing a grayscale signal for odd pixel cells in the row of pixel cells to odd data lines in the data line in a first time interval; In a second time interval, grayscale signals for even pixel cells in the row of pixel cells are provided to even data lines in the data line.
  • the method further includes providing a flip signal to the gate line connected to the row of pixel cells in a third time period immediately following the second time period, the flip signal having the scan The polarity of the opposite polarity of the signal.
  • the method further includes generating first data corresponding to the scan signal and second data corresponding to the flip signal before providing the scan signal, such that the drive unit can be based on The first data and the second data generate the scan signal and the flip signal.
  • a separate gate driving unit and a source driving unit or a single driving circuit are disposed at one end of a data line of the display panel, such as a bottom end of the display panel, thereby saving left and right sides of the display panel Circuit footprint. This is good for implementation Shows the product's narrow border or borderless design.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • General Engineering & Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Nonlinear Science (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示面板(100)，其包括在第一方向上延伸的多条栅线(GLn1，GLn2，GLn3)、在与所述第一方向基本上垂直的第二方向上延伸的多条数据线(Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B))、和驱动电路(110)，驱动电路(110)设置在数据线(Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B))的一端，用于向栅线(GLn1，GLn2，GLn3)提供扫描信号并向数据线提供灰阶信号。

Description

显示面板及其驱动方法和显示装置
相关申请的交叉引用
本申请要求2015年10月28日提交的中国专利申请号201510711721.8的权益，其全部公开内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其驱动方法、以及包括该显示面板的显示装置。
背景技术
现有的显示屏通常将栅极驱动单元制作在屏幕的左右两侧，使得窄边框设计难以实现。这影响了用户的观看体验。
如果可以实现窄边框或是无边框设计，将极大地提升用户的观看体验。因此，期望的是提供使得能够实现窄边框显示屏或无边框显示屏的手段。
发明内容
本公开的实施例提供一种显示面板及其驱动方法、以及显示装置，其寻求实现窄边框或无边框设计。
根据本公开的第一个方面，提供一种显示面板，包括：多条栅线，在第一方向上延伸；多条数据线，在与所述第一方向基本上垂直的第二方向上延伸；以及驱动电路，布置在所述数据线的一端并且包括：多个扫描信号输出端，每个连接到所述栅线中的相应一条；多个灰阶信号输出端，每个连接到所述数据线中的相应一条；栅极驱动单元，被配置成经由所述多个扫描信号输出端顺序地向所述多条栅线提供扫描信号；和源极驱动单元，被配置成经由所述多个灰阶信号输出端向所述多条数据线提供相应的灰阶信号。
根据本公开的第二个方面，提供一种显示面板，包括：布置成阵列的多个像素单元，所述像素单元中的每个具有相应的像素薄膜晶体管；在第一方向上延伸的多条栅线，所述栅线中的每条连接到所述阵列中的相应一行像素单元；在与所述第一方向基本上垂直的第二方向 上延伸的多条数据线，所述数据线中的每条连接到所述阵列中的相应一列像素单元；驱动电路，布置在所述数据线的一端并且包括：多个公共端子，用于输出扫描信号和相应的灰阶信号；开关网络，可操作用于将所述公共端子选择性地耦合到所述栅线或所述数据线；以及驱动单元，被配置成a)在时间上分离的多个第一时间段中顺序地向所述多个公共端子提供所述扫描信号，并且在其中所述扫描信号被提供给所述公共端子之一的每个第一时间段中，使所述开关网络将所述多个公共端子分别耦合到所述多条栅线以使得所述扫描信号被施加到所述栅线之一，并且b)在紧随相应第一时间段的各第二时间段中的每个中，向所述多个公共端子提供所述灰阶信号并且将所述公共端子中的每个耦合到所述数据线中的相应一条以使得所述灰阶信号被传送到所述像素单元的阵列；以及多个栅极电压存储电容，每个连接在所述栅线中的相应一条与一预定电压之间，并且可操作用于在由施加到该相应的栅线的扫描信号充电之后使得与该栅线相连的一行像素单元的像素薄膜晶体管能够在其中用于该行像素单元的灰阶信号被提供的所述第二时间段期间维持在开启状态。
在一些实施例中，所述驱动单元还被配置成在紧随相应的第二时间段的多个第三时间段中顺序地向所述多个公共端子提供翻转信号，并且在其中所述翻转信号被提供给所述公共端子之一的每个第三时间段中，使所述开关网络将所述多个公共端子分别耦合到所述多条栅线以对被充电了的栅极电压存储电容放电，所述翻转信号具有与所述扫描信号的极性相反的极性。
在一些实施例中，所述开关网络包括：多个第一开关，可操作用于响应于由所述驱动单元提供的第一栅极控制信号而将所述多个公共端子分别耦合到所述多条栅线，所述第一栅极控制信号与所述扫描信号和所述翻转信号中的一者同步；以及多个第二开关，可操作用于响应于由所述驱动单元提供的第二栅极控制信号而将所述多个公共端子分别耦合到所述多条栅线，所述第二栅极控制信号与所述扫描信号和所述翻转信号中的另一者同步。
在一些实施例中，连接到同一条栅线的第一开关和第二开关共享同一个公共端子。
在一些实施例中，所述第一开关中的每个包括晶体管，其具有用 于接收所述第一栅极控制信号的栅极、连接到所述公共端子中的相应一个的第一极、以及连接到所述栅线中的相应一条的第二极。
在一些实施例中，所述第二开关中的每个包括晶体管，其具有用于接收所述第二栅极控制信号的栅极、连接到所述公共端子中的相应一个的第一极、以及连接到所述栅线中的相应一条的第二极。
在一些实施例中，所述驱动单元还被配置成在所述第二时间段中的每个中：在第一时间间隔中，向所述多个公共端子提供用于相应一行像素单元中的奇数像素单元的灰阶信号，并且使所述开关网络将所述多个公共端子分别耦合到所述数据线中的奇数数据线；以及在第二时间间隔中，向所述多个公共端子提供用于该相应一行像素单元中的偶数像素单元的灰阶信号，并且使所述开关网络将所述多个公共端子分别耦合到所述数据线中的偶数数据线。
在一些实施例中，所述开关网络还包括：多个第三开关，可操作用于响应于由所述驱动单元提供的第一数据控制信号而在所述第一时间间隔中将所述多个公共端子分别耦合到所述数据线中的奇数数据线；以及多个第四开关，可操作用于响应于由所述驱动单元提供的第二数据控制信号而在所述第二时间间隔中将所述多个公共端子分别耦合到所述数据线中的偶数数据线。
在一些实施例中，所述驱动单元还被配置使得所述第一数据控制信号和所述第二数据控制信号被接连地提供。
在一些实施例中，所述第三开关中的每个与所述第四开关中的相应一个配对，其中在每个配对中该第三开关和第四开关共享同一个公共端子，并且连接到该第三开关的奇数数据线与连接到该第四开关的偶数数据线相邻。
在一些实施例中，所述第三开关中的每个包括晶体管，其具有用于接收所述第一数据控制信号的栅极、连接到所述公共端子中的相应一个的第一极、以及连接到所述奇数数据线中的相应一条的第二极。
在一些实施例中，所述第四开关中的每个包括晶体管，其具有用于接收所述第二数据控制信号的栅极、连接到所述公共端子中的相应一个的第一极、以及连接到所述偶数数据线中的相应一条的第二极。
根据本公开的第三个方面，提供了一种显示装置，包括：时序控制器，被配置成基于输入图像数据生成输出图像数据；以及如第二方 面所述的显示面板，所述显示面板被配置成基于所述输出图像数据显示图像。
在一些实施例中，所述驱动单元还被配置成在紧随相应的第二时间段的多个第三时间段中顺序地向所述多个公共端子提供翻转信号，并且在其中所述翻转信号被提供给所述公共端子之一的每个第三时间段中，使所述开关网络将所述多个公共端子分别耦合到所述多条栅线以对被充电了的栅极电压存储电容放电，所述翻转信号具有与所述扫描信号的极性相反的极性。所述时序控制器还被配置成生成与所述扫描信号对应的第一数据和与所述翻转信号对应的第二数据。所述驱动单元还被配置成分别基于所述第一数据、第二数据和所述输出图像数据生成所述扫描信号、所述翻转信号和所述灰阶信号。
根据本公开的第四方面，提供了一种驱动如第二方面所述的显示面板的方法，包括：针对所述阵列中的每一行像素单元：在第一时间段中向连接到该行像素单元的栅线提供所述扫描信号；以及在紧随所述第一时间段的第二时间段中向所述多条数据线提供相应的灰阶信号。
在一些实施例中，向连接到该行像素单元的栅线提供所述扫描信号包括：用所述扫描信号向连接到该栅线的栅极电压存储电容充电，经充电的栅极电压存储电容使得该行像素单元的像素薄膜晶体管能够在所述第二时间段期间维持在开启状态。
在一些实施例中，向所述多条数据线提供相应的灰阶信号包括：在第一时间间隔中，向所述数据线中的奇数数据线提供用于该行像素单元中的奇数像素单元的灰阶信号；以及在第二时间间隔中，向所述数据线中的偶数数据线提供用于该行像素单元中的偶数像素单元的灰阶信号。
在一些实施例中，所述的方法还包括：在紧随所述第二时间段的第三时间段中，向连接到该行像素单元的栅线提供翻转信号，所述翻转信号具有与所述扫描信号的极性相反的极性。
在一些实施例中，所述的方法还包括在提供所述扫描信号之前，生成与所述扫描信号对应的第一数据和与所述翻转信号对应的第二数据，使得所述驱动单元能够分别基于所述第一数据和第二数据生成所述扫描信号和所述翻转信号。
与其中将栅极驱动单元布置在显示面板左右两侧的现有技术相比， 本公开的实施例将栅极驱动单元布置在显示面板的数据线的一端，例如显示面板的底端，从而能够实现显示面板的窄边框或者无边框设计。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。
图1是根据本公开实施例的显示面板的示意图；
图2是根据本公开另一实施例的显示面板的示意图；
图3是图2中所示的显示面板的示例实现方式的示意图；
图4是图3中所示的显示面板在极性反转前的时序图；
图5是图3中所示的显示面板在极性反转后的时序图；
图6是根据本公开实施例的显示装置的框图；
图7是用于生成图4中所示的扫描信号、翻转信号和灰阶信号的数字数据表；并且
图8是用于生成图5中所示的扫描信号、翻转信号和灰阶信号的数字数据表。
具体实施方式
以下结合附图对本公开的实施例进行详细说明。应当理解的是，此处所描述的实施例仅用于说明和解释本公开，并不用于限制本公开。
图1是根据本公开实施例的显示面板100的示意图。
参照图1，显示面板100包括多条栅线GLn1，GLn2，GLn3、多条数据线Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B)和驱动电路110。
栅线GLn1，GLn2，GLn3在第一方向(图1中水平方向)上延伸，并且数据线Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B)在与所述第一方向基本上垂直的第二方向(图1中垂直方向)上延伸。由此，限定多个像素单元R，G，B。
驱动电路110布置在所述数据线Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B)的一端(图1中在显示面板100的底端)，并且包括多个扫描信号输出端101a，101b，101c、多个灰阶信号输出端102a，102b，102c，102d，102e，102f、栅极驱动单元112 和源极驱动单元114。
多个扫描信号输出端101a，101b，101c中的每个连接到所述栅线GLn1，GLn2，GLn3中的相应一条，并且多个灰阶信号输出端102a，102b，102c，102d，102e，102f中的每个连接到所述数据线Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B)中的相应一条。
栅极驱动单元112被配置成经由所述多个扫描信号输出端101a，101b，101c顺序地向所述多条栅线GLn1，GLn2，GLn3提供扫描信号。源极驱动单元114被配置成经由所述多个灰阶信号输出端102a，102b，102c，102d，102e，102f向所述多条数据线提供相应的灰阶信号。
传统上，栅极驱动单元被制作在显示面板的左右两侧，形成例如阵列基板行驱动(gate driver on array，GOA)电路。相比之下，根据本公开的实施例，栅极驱动单元112设置在数据线Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B)的一端，例如显示面板100的底端。这可以进一步减小显示面板100的边框的尺寸，从而实现窄边框或者无边框设计。
本发明人进一步认识到，栅极驱动单元112提供的栅极驱动功能和源极驱动单元114提供的源极驱动功能可以由单个的集成电路实现，从而进一步减小驱动电路110占用的面积。
图2是根据本公开另一实施例的显示面板200的示意图。
参照图2，显示面板200包括由R，G，B表示的多个像素单元、多条栅线GLn1，GLn2，GLn3、多条数据线Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B)、驱动电路210和多个栅极电压存储电容Cn1，Cn2，Cn3。
各像素单元R，G，B布置成阵列，并且每个像素单元具有相应的像素薄膜晶体管(“TFT”)。栅线GLn1，GLn2，GLn3中的每条连接到所述阵列中的相应一行像素单元，并且数据线Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B)中的每条连接到所述阵列中的相应一列像素单元。
驱动电路210布置在所述数据线Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B)的一端(图2中在显示面板200的底端)，并且包括多个公共端子COM1，COM2，COM3、开关网络212和驱动单元214。
多个公共端子COM1，COM2，COM3用于输出由驱动单元214生成的扫描信号和相应的灰阶信号。扫描信号(栅极开启电压)用于打开一行像素单元的像素薄膜晶体管。灰阶信号(灰阶电压)用于使像素单元呈现对应的灰阶，从而在显示面板上显示图像。
开关网络212可操作用于将所述公共端子COM1，COM2，COM3选择性地耦合到所述栅线GLn1，GLn2，GLn3或所述数据线Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B)。开关网络212包括多个开关201，202，203，204。
多个第一开关201可操作用于响应于由所述驱动单元214提供的第一栅极控制信号Gate SW1而将所述多个公共端子COM1，COM2，COM3分别耦合到所述多条栅线GLn1，GLn2，GLn3。
多个第二开关202可操作用于响应于由所述驱动单元214提供的第二栅极控制信号Gate SW2而将所述多个公共端子COM1，COM2，COM3分别耦合到所述多条栅线GLn1，GLn2，GLn3。
多个第三开关203可操作用于响应于由所述驱动单元214提供的第一数据控制信号Data SW1而在第一时间间隔中将所述多个公共端子COM1，COM2，COM3分别耦合到所述数据线Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B)中的奇数数据线。
多个第四开关204可操作用于响应于由所述驱动单元214提供的第二数据控制信号Data SW2而在第二时间间隔中将所述多个公共端子COM1，COM2，COM3分别耦合到所述数据线Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B)中的偶数数据线。
在图2的示例中，公共端子COM1经由开关网络212耦合到栅线GLn1、数据线Dm1(R)或数据线Dm1(G)，公共端子COM2经由开关网络212耦合到栅线GLn2、数据线Dm1(B)或数据线Dm2(R)，并且公共端子COM3经由开关网络212耦合到栅线GLn3、数据线Dm2(G)或数据线Dm2(B)。
虽然公共端子COM1，COM2，COM3中的每个被示出为经由开关网络212耦合到两条数据线，但是其他实施例是可能的。例如，每个公共端子可以经由开关网络212被耦合到更少或更多的数据线。
驱动单元214被配置成在时间上分离的多个第一时间段中顺序地向所述多个公共端子COM1，COM2，COM3提供所述扫描信号，并且在 其中所述扫描信号被提供给所述公共端子COM1，COM2，COM3之一的每个第一时间段中，使所述开关网络212将所述多个公共端子COM1，COM2，COM3分别耦合到所述多条栅线GLn1，GLn2，GLn3以使得所述扫描信号被施加到所述栅线GLn1，GLn2，GLn3之一。
驱动单元214还被配置成在紧随相应第一时间段的各第二时间段中的每个中，向所述多个公共端子COM1，COM2，COM3提供所述灰阶信号并且将所述公共端子COM1，COM2，COM3中的每个耦合到所述数据线Dm1(R)，Dm1(G)，Dm1(B)，Dm2(R)，Dm2(G)，Dm2(B)中的相应一条以使得所述灰阶信号被传送到所述像素单元R，G，B的阵列。
对于每一行像素单元而言，扫描信号和灰阶信号分别在第一时间段和第二时间段中被提供。在这种情况下，要求该行像素单元的像素薄膜晶体管(“TFT”)在第二时间段期间仍然维持在开启状态，以使得灰阶信号能够被写入像素单元中。
为了实现上述目的，显示面板200还包括多个栅极电压存储电容Cn1，Cn2，Cn3，每个连接在所述栅线GLn1，GLn2，GLn3中的相应一条与一预定电压(例如，地电压)之间。在图2的示例中，栅极电压存储电容Cn1连接到栅线GLn1，栅极电压存储电容Cn2连接到栅线GLn2，并且栅极电压存储电容Cn3连接到栅线GLn3。
栅极电压存储电容Cn1、Cn2、Cn3的电容值被选取以使得Cn1、Cn2、Cn3在充满电后能够维持栅极开启电压持续一预定时间段。具体地，栅极电压存储电容Cn1，Cn2，Cn3中的每个可操作用于在由施加到该相应的栅线的扫描信号充电之后使得与该栅线相连的一行像素单元的像素薄膜晶体管能够在其中用于该行像素单元的灰阶信号被提供的所述第二时间段期间维持在开启状态。
将理解的是，在图1和2中，三条栅线GLn1、GLn2、GLn3和六条数据线Dm1(R)、Dm1(G)、Dm1(B)、Dm2(R)、Dm2(G)、Dm2(B)仅仅是示例性的，并且不应当被视为限制本公开的范围。
图3是图2中所示的显示面板200的示例实现方式的示意图。
参照图3，开关网络212中的各个开关201，202，203，204每个都由晶体管实现。
每个晶体管201具有用于接收所述第一栅极控制信号Gate SW1的栅极、连接到所述公共端子COM1，COM2，COM3中的相应一个的第一 极、以及连接到所述栅线GLn1、GLn2、GLn3中的相应一条的第二极。
每个晶体管202具有用于接收所述第二栅极控制信号Gate SW2的栅极、连接到所述公共端子COM1，COM2，COM3中的相应一个的第一极、以及连接到所述栅线GLn1、GLn2、GLn3中的相应一条的第二极。
每个晶体管203具有用于接收所述第一数据控制信号Data SW1的栅极、连接到所述公共端子COM1，COM2，COM3中的相应一个的第一极、以及连接到所述奇数数据线中的相应一条的第二极。
每个晶体管204具有用于接收所述第二数据控制信号Data SW2的栅极、连接到所述公共端子COM1，COM2，COM3中的相应一个的第一极、以及连接到所述偶数数据线中的相应一条的第二极。
在图3的示例中，各个开关201，202，203，204可以为薄膜晶体管或其他合适类型的晶体管。虽然各个开关201，202，203，204被示出为N型晶体管，但是在其他实施例中可以使用P型晶体管。如已知的，用于导通P型晶体管的栅极电压为低电平电压。
下面结合图4和图5来说明图3的显示面板200的操作。
图4是图3中所示的显示面板在极性反转前的时序图。在图4的示例中，极性反转为列反转的形式，其中提供给彼此相邻的两列像素单元的灰阶信号具有相反的极性。在其他实施例中，其他形式的极性反转是可能的，例如点反转或帧反转。
在阶段1(第一时间段)中，第一栅极控制信号Gate SW1使各第一开关201开启。经由公共端子COM1输出的扫描信号VGH被传送到栅极电压存储电容Cn1。栅极电压存储电容Cn1被充电，并且栅线GLn1上的电压升高。当阶段1结束时，栅线GLn1上的电压达到峰值。需要说明的是，栅极电压存储电容Cn1电容值被选取使得在2、3阶段中栅线GLn1上的电压能够使得连接到栅线GLn1的像素薄膜晶体管维持开启。
在阶段2(第二时间段的第一时间间隔)中，第一数据控制信号Data SW1使与奇数数据线(图3中的数据线Dm1(R)、数据线Dm1(B)、数据线Dm2(G))相连的各第三开关203导通。由于连接到栅线GLn1的像素薄膜晶体管开启，来自驱动单元214的灰阶信号LR(m1n1)、LB(m1n1)和LG(m2n1)被分别写入连接到栅线GLn1的奇数像素单元。
在阶段3(第二时间段的第二时间间隔)中，第二数据控制信号 Data SW2使与偶数数据线(图3中的数据线Dm1(G)、数据线Dm2(R)、数据线Dm2(B))相连的各第四开关204导通。由于连接到栅线GLn1的像素薄膜晶体管开启，来自驱动单元214的灰阶信号LG(m1n1)、LR(m2n1)和LB(m2n1)被分别写入连接到栅线GLn1的偶数像素单元。
在阶段4(第三时间段)中，第二栅极控制信号Gate SW2使各第二开关202开启。经由公共端子COM1输出的翻转信号VGL被传送到栅极电压存储电容Cn1。栅极电压存储电容Cn1被反向充电，并且栅线GLn1上电压降低。当阶段4结束时，栅线GLn1上的电压降到最低。第n1行像素单元的像素薄膜晶体管被关断。这可以确保下一帧图像的正常显示，避免诸如伪影之类的现象。
在阶段5(复位阶段)中，全部外部信号(包括扫描信号和灰阶信号)均为低电平。需要说明的是，此阶段也可省略。
在阶段6(第一时间段)中，第一栅极控制信号Gate SW1使各第一开关201开启。经由公共端子COM2输出的扫描信号VGH被传送到栅极电压存储电容Cn2。栅极电压存储电容Cn2被充电，并且栅线GLn2上的电压升高。当阶段6结束时，栅线GLn2上的电压达到峰值。需要说明的是，栅极电压存储电容Cn2电容值被选取使得在7、8阶段中栅线GLn2上的电压能够使得连接到栅线GLn2的像素薄膜晶体管维持开启。
在阶段7(第二时间段的第一时间间隔)中，第一数据控制信号Data SW1使与奇数数据线(图3中的数据线Dm1(R)、数据线Dm1(B)、数据线Dm2(G))相连的各第三开关203导通。由于连接到栅线GLn2的像素薄膜晶体管开启，来自驱动单元214的灰阶信号LR(m1n2)、LB(m1n2)和LG(m2n2)被分别写入连接到栅线GLn2的奇数像素单元。
在阶段8(第二时间段的第二时间间隔)中，第二数据控制信号Data SW2使与偶数数据线(图3中的数据线Dm1(G)、数据线Dm2(R)、数据线Dm2(B))相连的各第四开关204导通。由于连接到栅线GLn2的像素薄膜晶体管开启，来自驱动单元214的灰阶信号LG(m1n2)、LR(m2n2)和LB(m2n2)被分别写入连接到栅线GLn2的偶数像素单元。
在阶段9(第三时间段)中，第二栅极控制信号Gate SW2使各第二开关202开启。经由公共端子COM2输出的翻转信号VGL被传送到栅极电压存储电容Cn2。栅极电压存储电容Cn2被反向充电，并且栅 线GLn2上电压降低。当阶段9结束时，栅线GLn2上的电压降到最低。第n2行像素单元的像素薄膜晶体管被关断。
以后各行像素单元重复上述操作，此处不再叙述。
图5是图3中所示的显示面板在极性反转(列反转)后的时序图，其中提供给各列像素单元的灰阶信号的极性与极性反转之前相比被反转。
在阶段1(第一时间段)中，第二栅极控制信号Gate SW2使各第二开关202开启。经由公共端子COM1输出的扫描信号VGH被传送到栅极电压存储电容Cn1。栅极电压存储电容Cn1被充电，并且栅线GLn1上的电压升高。当阶段1结束时，栅线GLn1上的电压达到峰值。
在阶段2(第二时间段的第一时间间隔)中，第二数据控制信号Data SW2使与偶数数据线(图3中的数据线Dm1(G)、数据线Dm2(R)、数据线Dm2(B))相连的各第四开关204导通。由于连接到栅线GLn1的像素薄膜晶体管开启，来自驱动单元214的灰阶信号LG(m1n1)、LR(m2n1)和LB(m2n1)被分别写入连接到栅线GLn1的偶数像素单元。
在阶段3(第二时间段的第二时间间隔)中，第一数据控制信号Data SW1使与奇数数据线(图3中的数据线Dm1(R)、数据线Dm1(B)、数据线Dm2(G))相连的各第三开关203导通。由于连接到栅线GLn1的像素薄膜晶体管开启，来自驱动单元214的灰阶信号LR(m1n1)、LB(m1n1)和LG(m2n1)被分别写入连接到栅线GLn1的奇数像素单元。
在阶段4(第三时间段)中，第一栅极控制信号Gate SW1使各第一开关201开启。经由公共端子COM1输出的翻转信号VGL被传送到栅极电压存储电容Cn1。栅极电压存储电容Cn1被反向充电，并且栅线GLn1上电压降低。当阶段4结束时，栅线GLn1上的电压降到最低。第n1行像素单元的像素薄膜晶体管被关断。
在阶段5(复位阶段)中，全部外部信号(包括扫描信号和灰阶信号)均为低电平。需要说明的是，此阶段也可省略。
在阶段6(第一时间段)中，第二栅极控制信号Gate SW2使各第二开关202开启。经由公共端子COM2输出的扫描信号VGH被传送到栅极电压存储电容Cn2。栅极电压存储电容Cn2被充电，并且栅线GLn2上的电压升高。当阶段6结束时，栅线GLn2上的电压达到峰值。
在阶段7(第二时间段的第一时间间隔)中，第二数据控制信号 Data SW2使与偶数数据线(图3中的数据线Dm1(G)、数据线Dm2(R)、数据线Dm2(B))相连的各第四开关204导通。由于连接到栅线GLn2的像素薄膜晶体管开启，来自驱动单元214的灰阶信号LG(m1n2)、LR(m2n2)和LB(m2n2)被分别写入连接到栅线GLn2的偶数像素单元。
在阶段8(第二时间段的第二时间间隔)中，第一数据控制信号Data SW1使与奇数数据线(图3中的数据线Dm1(R)、数据线Dm1(B)、数据线Dm2(G))相连的各第三开关203导通。由于连接到栅线GLn2的像素薄膜晶体管开启，来自驱动单元214的灰阶信号LR(m1n2)、LB(m1n2)和LG(m2n2)被分别写入连接到栅线GLn2的奇数像素单元。
在阶段9(第三时间段)中，第一栅极控制信号Gate SW1使各第一开关201开启。经由公共端子COM2输出的翻转信号VGL被传送到栅极电压存储电容Cn2。栅极电压存储电容Cn2被反向充电，并且栅线GLn2上电压降低。当阶段9结束时，栅线GLn2上的电压降到最低。第n2行像素单元的像素薄膜晶体管被关断。
以后各行像素单元重复上述操作，此处不再叙述。
在上面的实施例中，驱动单元214可以用现有的源极驱动芯片实现。可替换地，驱动单元214可以用其他硬件组件实现，例如专用集成电路ASIC、复杂可编程逻辑器件CPLD、或现场可编程门阵列FPGA。
图6是根据本公开实施例的显示装置600的框图。
参照图6，显示装置600包括显示面板200和时序控制器610。
如前所述，显示面板200包括像素单元的阵列和驱动单元214，其详细描述在此被省略。
时序控制器610从例如系统接口接收同步信号SYNC和输入图像数据R，G，B，并且被配置成基于输入图像数据R，G，B生成输出图像数据DAT。输出图像数据DAT被提供给显示面板200以用于显示图像。时序控制器610还向驱动单元214提供控制信号CONT，例如时钟信号。驱动单元214响应于控制信号CONT将输出图像数据DAT转换成灰阶信号，并将其提供给像素阵列。
在本实施例中，时序控制器610还被配置成生成与所述扫描信号VGH对应的第一数据和与所述翻转信号VGL对应的第二数据。驱动单元214还被配置成分别基于所述第一数据和第二数据生成所述扫描信号和所述翻转信号。例如，当显示面板200具有256个灰阶时，扫 描信号VGH对应的第一数据可以为+255，并且翻转信号VGL对应的第二数据可以为-255。此外，与默认的栅线电压信号对应的数字数据可以为0。
将理解的是，与图4和5中所示的第一栅极控制信号Gate SW1、第二栅极控制信号Gate SW2、第一数据控制信号Data SW1和第二数据控制信号Data SW2相对应的数字数据也可以由时序控制器610提供给驱动单元214，并且由驱动单元214生成对应的电压信号。因此，驱动单元214可以基于从时序控制器610接收的数字数据生成如图4和5中所示的电压信号。
图7是用于生成图4中所示的扫描信号VGH、翻转信号VGL和灰阶信号的数字数据表。
参照图7，表格顶部的符号“+”和“-”表示各信号的极性。在表格中，数字(255和0)表示用于在第一时间段和第三时间段中生成电压信号的数据，并且R，G，B表示用于在第二时间段中生成灰阶信号的像素值。
表格中的数据可以划分为组，每个包括四个项目，如粗实线所指示的。表格中的每一行数据对应于施加到相应一行像素单元的信号。以第一行为例，各个组中的第一个项目对应于图4的阶段1中由驱动单元214生成并经由公共端子COM1、COM2、COM3施加到第一行像素单元的信号，各个组中的第二个项目对应于图4的阶段2中由驱动单元214生成并经由公共端子COM1、COM2、COM3施加到第一行像素单元的信号，各个组中的第三个项目对应于图4的阶段3中由驱动单元214生成并经由公共端子COM1、COM2、COM3施加到第一行像素单元的信号，并且各个组中的第四个项目对应于图4的阶段4中由驱动单元214生成并经由公共端子COM1、COM2、COM3施加到第一行像素单元的信号。
图8是用于生成图5中所示的扫描信号VGH、翻转信号VGL和灰阶信号的数字数据表。与图7相比，图8中的像素值的极性被按列反转。
与图7类似，表格中的数据可以划分为组，每个包括四个项目，如粗实线所指示的。以第一行为例，各个组中的第四个项目对应于图5的阶段1中由驱动单元214生成并经由公共端子COM1、COM2、COM3 施加到第一行像素单元的信号，各个组中的第三个项目对应于图5的阶段2中由驱动单元214生成并经由公共端子COM1、COM2、COM3施加到第一行像素单元的信号，各个组中的第二个项目对应于图5的阶段3中由驱动单元214生成并经由公共端子COM1、COM2、COM3施加到第一行像素单元的信号，并且各个组中的第一个项目对应于图5的阶段4中由驱动单元214生成并经由公共端子COM1、COM2、COM3施加到第一行像素单元的信号。
根据本公开的另一个方面，提供一种驱动如上面实施例所述的显示面板200的方法。
该方法包括：针对所述阵列中的每一行像素单元，在第一时间段中向连接到该行像素单元的栅线提供所述扫描信号；以及在紧随所述第一时间段的第二时间段中向所述多条数据线提供相应的灰阶信号。
在一些实施例中，提供所述扫描信号包括：用所述扫描信号向连接到该栅线的栅极电压存储电容充电，经充电的栅极电压存储电容使得该行像素单元的像素薄膜晶体管能够在所述第二时间段期间维持在开启状态。
在一些实施例中，提供相应的灰阶信号包括：在第一时间间隔中，向所述数据线中的奇数数据线提供用于该行像素单元中的奇数像素单元的灰阶信号；以及在第二时间间隔中，向所述数据线中的偶数数据线提供用于该行像素单元中的偶数像素单元的灰阶信号。
在一些实施例中，该方法还包括：在紧随所述第二时间段的第三时间段中，向连接到该行像素单元的栅线提供翻转信号，所述翻转信号具有与所述扫描信号的极性相反的极性。
在一些实施例中，该方法还包括在提供所述扫描信号之前，生成与所述扫描信号对应的第一数据和与所述翻转信号对应的第二数据，使得所述驱动单元能够分别基于所述第一数据和第二数据生成所述扫描信号和所述翻转信号。
驱动方法的细节已经在上面结合图3-7对显示面板200的操作的描述中进行了说明，并且在此为了简单起见而被省略。
根据本公开的实施例，分离的栅极驱动单元与源极驱动单元或者单个的驱动电路被设置在显示面板的数据线的一端，例如显示面板的底端，从而节省了显示面板左右两侧的电路占用面积。这有利于实现 显示产品的窄边框或者无边框设计。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (20)

  1. 一种显示面板，包括：
    多条栅线，在第一方向上延伸；
    多条数据线，在与所述第一方向基本上垂直的第二方向上延伸；以及
    驱动电路，布置在所述数据线的一端并且包括：
    多个扫描信号输出端，每个连接到所述栅线中的相应一条；
    多个灰阶信号输出端，每个连接到所述数据线中的相应一条；
    栅极驱动单元，被配置成经由所述多个扫描信号输出端顺序地向所述多条栅线提供扫描信号；和
    源极驱动单元，被配置成经由所述多个灰阶信号输出端向所述多条数据线提供相应的灰阶信号。
  2. 一种显示面板，包括：
    布置成阵列的多个像素单元，所述像素单元中的每个具有相应的像素薄膜晶体管；
    在第一方向上延伸的多条栅线，所述栅线中的每条连接到所述阵列中的相应一行像素单元；
    在与所述第一方向基本上垂直的第二方向上延伸的多条数据线，所述数据线中的每条连接到所述阵列中的相应一列像素单元；
    驱动电路，布置在所述数据线的一端并且包括：
    多个公共端子，用于输出扫描信号和相应的灰阶信号；
    开关网络，可操作用于将所述公共端子选择性地耦合到所述栅线或所述数据线；以及
    驱动单元，被配置成a)在时间上分离的多个第一时间段中顺序地向所述多个公共端子提供所述扫描信号，并且在其中所述扫描信号被提供给所述公共端子之一的每个第一时间段中，使所述开关网络将所述多个公共端子分别耦合到所述多条栅线以使得所述扫描信号被施加到所述栅线之一，并且b)在紧随相应第一时间段的各第二时间段中的每个中，向所述多个公共端子提供所述灰阶信号并且将所述公共端子中的每个耦合到所述数据线中的相应一条以使得所述灰阶信号被传送到所述像素单元的阵列；以及
    多个栅极电压存储电容，每个连接在所述栅线中的相应一条与一预定电压之间，并且可操作用于在由施加到该相应的栅线的扫描信号充电之后使得与该栅线相连的一行像素单元的像素薄膜晶体管能够在其中用于该行像素单元的灰阶信号被提供的所述第二时间段期间维持在开启状态。
  3. 根据权利要求2所述的显示面板，其中所述驱动单元还被配置成在紧随相应的第二时间段的多个第三时间段中顺序地向所述多个公共端子提供翻转信号，并且在其中所述翻转信号被提供给所述公共端子之一的每个第三时间段中，使所述开关网络将所述多个公共端子分别耦合到所述多条栅线以对被充电了的栅极电压存储电容放电，所述翻转信号具有与所述扫描信号的极性相反的极性。
  4. 根据权利要求3所述的显示面板，其中所述开关网络包括：
    多个第一开关，可操作用于响应于由所述驱动单元提供的第一栅极控制信号而将所述多个公共端子分别耦合到所述多条栅线，所述第一栅极控制信号与所述扫描信号和所述翻转信号中的一者同步；以及
    多个第二开关，可操作用于响应于由所述驱动单元提供的第二栅极控制信号而将所述多个公共端子分别耦合到所述多条栅线，所述第二栅极控制信号与所述扫描信号和所述翻转信号中的另一者同步。
  5. 根据权利要求4所述的显示面板，其中连接到同一条栅线的第一开关和第二开关共享同一个公共端子。
  6. 根据权利要求4所述的显示面板，其中所述第一开关中的每个包括晶体管，其具有用于接收所述第一栅极控制信号的栅极、连接到所述公共端子中的相应一个的第一极、以及连接到所述栅线中的相应一条的第二极。
  7. 根据权利要求4所述的显示面板，其中所述第二开关中的每个包括晶体管，其具有用于接收所述第二栅极控制信号的栅极、连接到所述公共端子中的相应一个的第一极、以及连接到所述栅线中的相应一条的第二极。
  8. 根据权利要求2所述的显示面板，其中所述驱动单元还被配置成在所述第二时间段中的每个中：
    在第一时间间隔中，向所述多个公共端子提供用于相应一行像素单元中的奇数像素单元的灰阶信号，并且使所述开关网络将所述多个 公共端子分别耦合到所述数据线中的奇数数据线；以及
    在第二时间间隔中，向所述多个公共端子提供用于该相应一行像素单元中的偶数像素单元的灰阶信号，并且使所述开关网络将所述多个公共端子分别耦合到所述数据线中的偶数数据线。
  9. 根据权利要求8所述的显示面板，其中所述开关网络还包括：
    多个第三开关，可操作用于响应于由所述驱动单元提供的第一数据控制信号而在所述第一时间间隔中将所述多个公共端子分别耦合到所述数据线中的奇数数据线；以及
    多个第四开关，可操作用于响应于由所述驱动单元提供的第二数据控制信号而在所述第二时间间隔中将所述多个公共端子分别耦合到所述数据线中的偶数数据线。
  10. 根据权利要求9所述的显示面板，其中所述驱动单元还被配置使得所述第一数据控制信号和所述第二数据控制信号被接连地提供。
  11. 根据权利要求9所述的显示面板，其中所述第三开关中的每个与所述第四开关中的相应一个配对，其中在每个配对中该第三开关和第四开关共享同一个公共端子，并且连接到该第三开关的奇数数据线与连接到该第四开关的偶数数据线相邻。
  12. 根据权利要求9所述的显示面板，其中所述第三开关中的每个包括晶体管，其具有用于接收所述第一数据控制信号的栅极、连接到所述公共端子中的相应一个的第一极、以及连接到所述奇数数据线中的相应一条的第二极。
  13. 根据权利要求9所述的显示面板，其中所述第四开关中的每个包括晶体管，其具有用于接收所述第二数据控制信号的栅极、连接到所述公共端子中的相应一个的第一极、以及连接到所述偶数数据线中的相应一条的第二极。
  14. 一种显示装置，包括：
    时序控制器，被配置成基于输入图像数据生成输出图像数据；以及
    如权利要求2-13中任一项所述的显示面板，所述显示面板被配置成基于所述输出图像数据显示图像。
  15. 根据权利要求14所述的显示装置，其中所述驱动单元还被配置成在紧随相应的第二时间段的多个第三时间段中顺序地向所述多个 公共端子提供翻转信号，并且在其中所述翻转信号被提供给所述公共端子之一的每个第三时间段中，使所述开关网络将所述多个公共端子分别耦合到所述多条栅线以对被充电了的栅极电压存储电容放电，所述翻转信号具有与所述扫描信号的极性相反的极性；
    其中所述时序控制器还被配置成生成与所述扫描信号对应的第一数据和与所述翻转信号对应的第二数据；并且
    其中所述驱动单元还被配置成分别基于所述第一数据、第二数据和所述输出图像数据生成所述扫描信号、所述翻转信号和所述灰阶信号。
  16. 一种驱动如权利要求2所述的显示面板的方法，包括：
    针对所述阵列中的每一行像素单元：
    在第一时间段中向连接到该行像素单元的栅线提供所述扫描信号；以及
    在紧随所述第一时间段的第二时间段中向所述多条数据线提供相应的灰阶信号。
  17. 根据权利要求16所述的方法，其中向连接到该行像素单元的栅线提供所述扫描信号包括：
    用所述扫描信号向连接到该栅线的栅极电压存储电容充电，经充电的栅极电压存储电容使得该行像素单元的像素薄膜晶体管能够在所述第二时间段期间维持在开启状态。
  18. 根据权利要求17所述的方法，其中向所述多条数据线提供相应的灰阶信号包括：
    在第一时间间隔中，向所述数据线中的奇数数据线提供用于该行像素单元中的奇数像素单元的灰阶信号；以及
    在第二时间间隔中，向所述数据线中的偶数数据线提供用于该行像素单元中的偶数像素单元的灰阶信号。
  19. 根据权利要求16所述的方法，还包括：
    在紧随所述第二时间段的第三时间段中，向连接到该行像素单元的栅线提供翻转信号，所述翻转信号具有与所述扫描信号的极性相反的极性。
  20. 根据权利要求19所述的方法，还包括在提供所述扫描信号之前，生成与所述扫描信号对应的第一数据和与所述翻转信号对应的第 二数据，使得所述驱动单元能够分别基于所述第一数据和第二数据生成所述扫描信号和所述翻转信号。
PCT/CN2016/101615 2015-10-28 2016-10-10 显示面板及其驱动方法和显示装置 WO2017071459A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/528,565 US10453377B2 (en) 2015-10-28 2016-10-10 Display panel and driving method thereof, and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510711721.8A CN105206242B (zh) 2015-10-28 2015-10-28 驱动电路及其驱动方法、显示面板
CN201510711721.8 2015-10-28

Publications (1)

Publication Number Publication Date
WO2017071459A1 true WO2017071459A1 (zh) 2017-05-04

Family

ID=54953873

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/101615 WO2017071459A1 (zh) 2015-10-28 2016-10-10 显示面板及其驱动方法和显示装置

Country Status (3)

Country Link
US (1) US10453377B2 (zh)
CN (1) CN105206242B (zh)
WO (1) WO2017071459A1 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105161069A (zh) * 2015-10-27 2015-12-16 京东方科技集团股份有限公司 一种显示面板的显示控制方法、显示控制电路及显示装置
CN105206242B (zh) * 2015-10-28 2017-11-07 京东方科技集团股份有限公司 驱动电路及其驱动方法、显示面板
CN105974700B (zh) * 2016-06-30 2019-10-18 维沃移动通信有限公司 一种显示屏及电子设备
CN106932980A (zh) * 2017-03-29 2017-07-07 武汉华星光电技术有限公司 一种goa阵列基板及液晶面板
CN107068035B (zh) * 2017-04-06 2020-12-18 京东方科技集团股份有限公司 一种显示方法、显示装置
CN107992229B (zh) * 2017-12-05 2020-12-01 上海中航光电子有限公司 触控显示面板和触控显示装置
CN108538234A (zh) * 2018-04-20 2018-09-14 京东方科技集团股份有限公司 一种信号控制装置及控制方法、显示设备
CN108847181B (zh) * 2018-07-13 2021-01-26 京东方科技集团股份有限公司 一种灰阶调节电路和显示装置
CN209103800U (zh) * 2018-11-29 2019-07-12 惠科股份有限公司 显示面板驱动电路
CN110164351A (zh) * 2019-04-22 2019-08-23 北京集创北方科技股份有限公司 驱动电路、驱动装置、显示设备以及驱动方法
CN110211525A (zh) * 2019-05-27 2019-09-06 福建华佳彩有限公司 一种面板设计架构
KR20210010686A (ko) * 2019-07-17 2021-01-28 삼성디스플레이 주식회사 표시 장치
TWI748645B (zh) * 2019-09-11 2021-12-01 矽創電子股份有限公司 顯示面板驅動晶片、顯示面板驅動架構及其顯示裝置
CN111240061B (zh) 2020-03-18 2021-09-14 合肥鑫晟光电科技有限公司 阵列基板及其驱动方法、显示装置
CN114072918A (zh) 2020-05-15 2022-02-18 京东方科技集团股份有限公司 显示面板及其驱动方法、显示装置
CN113781951B (zh) * 2020-06-09 2022-10-04 京东方科技集团股份有限公司 一种显示面板及驱动方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102436796A (zh) * 2011-12-19 2012-05-02 北京大学深圳研究生院 一种显示装置及其数据驱动电路
CN102456316A (zh) * 2011-12-15 2012-05-16 北京大学深圳研究生院 一种数据驱动电路及其显示装置
CN102723064A (zh) * 2012-03-28 2012-10-10 北京大学深圳研究生院 驱动电路单元、栅极驱动电路及显示装置
CN104424907A (zh) * 2013-08-28 2015-03-18 辛纳普蒂克斯显像装置株式会社 显示驱动装置及显示装置
US20150091883A1 (en) * 2013-10-01 2015-04-02 Samsung Display Co., Ltd. Display device and driving method thereof
CN105206242A (zh) * 2015-10-28 2015-12-30 京东方科技集团股份有限公司 驱动电路及其驱动方法、显示面板

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201204027Y (zh) * 2008-02-29 2009-03-04 上海广电光电子有限公司 可减少栅极驱动电路数量的电路及液晶显示装置
TW201020609A (en) * 2008-11-26 2010-06-01 Chunghwa Picture Tubes Ltd LCD panel having shared shorting bars for array test and panel test
TWI404011B (zh) * 2009-03-18 2013-08-01 Pervasive Display Co Ltd 非揮發性顯示模組及非揮發性顯示裝置
KR101668671B1 (ko) * 2010-05-12 2016-10-25 삼성디스플레이 주식회사 표시 장치
KR101984189B1 (ko) * 2011-12-16 2019-06-03 엘지디스플레이 주식회사 터치스크린 내장형 액정표시장치 및 그 구동 방법
US20130257837A1 (en) * 2012-03-28 2013-10-03 Shenzhen China Star Optoelectronics Technology Co. Ltd. Liquid crystal display device, driving circuit, and driving method thereof
US8830154B2 (en) * 2012-04-16 2014-09-09 Shenzhen China Star Optoelectronics Technology Co., Ltd Liquid crystal display device and driving circuit with reduced number of scan drivers and data drivers
CN103000152B (zh) * 2012-11-29 2015-04-22 北京京东方光电科技有限公司 控制栅极线信号值方法和设备、栅极驱动电路、显示装置
CN104112432B (zh) * 2013-04-17 2016-10-26 瀚宇彩晶股份有限公司 显示器
TWI505010B (zh) * 2013-11-12 2015-10-21 E Ink Holdings Inc 主動元件陣列基板
CN105527825B (zh) * 2014-09-28 2018-02-27 联想(北京)有限公司 电子设备和显示方法
CN104360558A (zh) * 2014-12-08 2015-02-18 重庆京东方光电科技有限公司 一种阵列基板、显示面板及显示装置
CN104751766B (zh) * 2015-04-08 2017-08-29 京东方科技集团股份有限公司 一种显示面板、其驱动方法及显示装置
CN104900181A (zh) * 2015-07-03 2015-09-09 京东方科技集团股份有限公司 一种阵列基板及其驱动方法和显示装置
CN105047122A (zh) * 2015-09-08 2015-11-11 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN105161069A (zh) * 2015-10-27 2015-12-16 京东方科技集团股份有限公司 一种显示面板的显示控制方法、显示控制电路及显示装置
US10720109B2 (en) * 2017-08-16 2020-07-21 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Organic light emitting diode display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102456316A (zh) * 2011-12-15 2012-05-16 北京大学深圳研究生院 一种数据驱动电路及其显示装置
CN102436796A (zh) * 2011-12-19 2012-05-02 北京大学深圳研究生院 一种显示装置及其数据驱动电路
CN102723064A (zh) * 2012-03-28 2012-10-10 北京大学深圳研究生院 驱动电路单元、栅极驱动电路及显示装置
CN104424907A (zh) * 2013-08-28 2015-03-18 辛纳普蒂克斯显像装置株式会社 显示驱动装置及显示装置
US20150091883A1 (en) * 2013-10-01 2015-04-02 Samsung Display Co., Ltd. Display device and driving method thereof
CN105206242A (zh) * 2015-10-28 2015-12-30 京东方科技集团股份有限公司 驱动电路及其驱动方法、显示面板

Also Published As

Publication number Publication date
CN105206242A (zh) 2015-12-30
US10453377B2 (en) 2019-10-22
US20170269416A1 (en) 2017-09-21
CN105206242B (zh) 2017-11-07

Similar Documents

Publication Publication Date Title
WO2017071459A1 (zh) 显示面板及其驱动方法和显示装置
US10872578B2 (en) Shift register unit, gate driving circuit and driving method thereof
KR102381885B1 (ko) 디스플레이 장치
KR101909675B1 (ko) 표시 장치
US10115366B2 (en) Liquid crystal display device for improving the characteristics of gate drive voltage
US10891886B2 (en) Shift register, gate line driving method, array substrate and display device for high and low resolution areas
US10943552B2 (en) Shift register unit, gate drive circuit and method of driving the same
US11024245B2 (en) Gate driver and display device using the same
WO2016161776A1 (zh) 显示面板、显示面板驱动方法及显示装置
EP3113167B1 (en) Method of driving display panel and display apparatus for performing the same
US10534477B2 (en) Gate driver and display device having in-cell touch sensor using the same
JP5377822B2 (ja) 表示装置用スキャン駆動装置、それを含む表示装置及び表示装置の駆動方法
US9317151B2 (en) Low complexity gate line driver circuitry
CN108630139B (zh) 图像显示处理方法及装置、显示装置及存储介质
KR102268519B1 (ko) 두얼 출력 gip 구조
US9686533B2 (en) 3D panel, method for driving 3D panel and electronic device
US20090096737A1 (en) Display device, driving device and driving method thereof
CN100359555C (zh) 液晶显示器的驱动装置
US9607564B2 (en) Clock generator circuit of liquid crystal display device and operation method thereof
KR20140036729A (ko) 게이트 쉬프트 레지스터 및 이를 이용한 평판 표시 장치
KR101830604B1 (ko) 평판 표시장치
KR20110035517A (ko) 액정표시장치
US10482834B2 (en) Pixel circuit, display device, display apparatus and driving method
US9734777B2 (en) Display device
KR102283377B1 (ko) 표시장치와 그 게이트 구동 회로

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15528565

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16858895

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16858895

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16858895

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 14/03/2019)