WO2016161691A1 - 阵列基板、显示装置及用于制备阵列基板的方法 - Google Patents

阵列基板、显示装置及用于制备阵列基板的方法 Download PDF

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Publication number
WO2016161691A1
WO2016161691A1 PCT/CN2015/078871 CN2015078871W WO2016161691A1 WO 2016161691 A1 WO2016161691 A1 WO 2016161691A1 CN 2015078871 W CN2015078871 W CN 2015078871W WO 2016161691 A1 WO2016161691 A1 WO 2016161691A1
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Prior art keywords
layer
metal layer
light absorbing
photoresist
gate
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English (en)
French (fr)
Inventor
徐向阳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/785,978 priority Critical patent/US9887255B2/en
Publication of WO2016161691A1 publication Critical patent/WO2016161691A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, and to a display device having the array substrate, and a method for preparing the array substrate.
  • AMOLED Active-matrix Organic Light Emitting Diode
  • LCD Organic Organic Light Emitting Diode
  • AMOLED display technology eliminates the need for backlights and requires only a very thin coating of organic material to achieve illumination.
  • the principle of illumination of AMOLED display technology is that when a current flows through an organic material coating, the organic material in the organic material coating emits light.
  • the AMOLED display panel can be made lighter and thinner, has a larger viewing angle, and can significantly save power.
  • the AMOLED display panel has a gate metal layer, a source metal layer, and a drain metal layer. These metal layers have strong reflective properties.
  • the ambient light can be irradiated onto the metal layers through the open area of the cover of the display panel and strongly reflected with the metal layer, thereby affecting the display effect of the AMOLED display panel.
  • the prior art generally adopts a method of attaching a circular polarizer to a cover plate to achieve the purpose of blocking part of ambient light from being irradiated onto the metal layer of the display panel.
  • a method in which a part of the ambient light is blocked by the circular polarizer to illuminate the metal layer of the display panel is that since the light-shielding area of the circular polarizer does not completely match the set area of the metal layer of the display panel, on the one hand, the circular polarizer cannot The ambient light that illuminates the metal layer is completely blocked.
  • the circular polarizer blocks useful ambient light that is irradiated to an area other than the metal layer, thereby significantly reducing the brightness of the display panel. In order to compensate for the reduced brightness, it is necessary to increase the power consumption of the display panel accordingly. However, the increase in power consumption leads to a significant reduction in the life of the display panel and an increase in the overall thickness of the display panel.
  • the technical problem to be solved by the present invention is to effectively block ambient light from being irradiated onto the metal layer of the display panel without increasing the power consumption of the display panel.
  • the present invention provides an array substrate, a preparation method thereof, and a display device.
  • an array substrate comprising:
  • a bottom gate type thin film transistor unit located on the light absorbing layer
  • the projection of the light absorbing layer covers a gate metal layer, a source metal layer and a drain metal layer of the bottom gate type thin film transistor unit.
  • the projection of the light absorbing layer further covers an active layer of the bottom gate type thin film transistor unit.
  • the light absorbing layer is an organic light absorbing layer.
  • the bottom gate type thin film transistor unit comprises:
  • the gate metal layer on the light absorbing layer
  • the source metal layer and the drain metal layer on the etch stop layer, the source metal layer and the drain metal layer respectively pass through the first via and the second pass A hole connects the active layer.
  • a display device having the above array substrate is provided.
  • the display device further includes:
  • a method for preparing the above array substrate comprising:
  • a light absorbing layer and a bottom gate type thin film transistor unit are formed on the base substrate, including the substrate Forming the light absorbing layer and the gate metal layer on the substrate; forming the light absorbing layer and the gate metal layer on the substrate, comprising:
  • the photoresist is exposed and developed using a gray tone or halftone mask to form an unexposed photoresist topography, a partially exposed photoresist topography, and a fully exposed area;
  • the remaining photoresist is removed by a second ashing process.
  • the photoresist is exposed and developed using a gray tone or halftone mask to form an unexposed photoresist topography, a partially exposed photoresist topography, and a fully exposed area, specifically:
  • forming the light absorbing layer and the bottom gate type thin film transistor unit on the base substrate further includes:
  • the present invention by providing a light absorbing layer covering each metal layer of the bottom gate type thin film transistor unit inside the array substrate, it is possible to effectively block all ambient light that is irradiated onto each metal layer of the gate thin film transistor unit.
  • the light absorbing layer does not block the useful ambient light that is irradiated to the area other than the metal layer, thereby not reducing the brightness of the display panel, and avoiding the increase of the power consumption of the display panel and the life of the display panel caused by the use of the circular polarizer in the prior art. The appearance of the phenomenon.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic flow chart showing a method for preparing an array substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic flow chart showing a method of forming a light absorbing layer and a gate metal layer in an embodiment of the present invention
  • FIG. 4a is a schematic view showing a method of forming a light absorbing layer and a gate metal layer in an embodiment of the present invention, in which a light absorbing layer, a gate metal layer, and a photoresist are sequentially deposited on a substrate;
  • 4b is a schematic view showing an exposure and development process in a method of forming a light absorbing layer and a gate metal layer in an embodiment of the present invention
  • 4c is a schematic view showing the first etching in the method of forming the light absorbing layer and the gate metal layer in the embodiment of the present invention
  • 4d is a schematic view showing the first photoresist after ashing in the method of forming the light absorbing layer and the gate metal layer in the embodiment of the present invention
  • 4e is a schematic view showing the second etching after the method of forming the light absorbing layer and the gate metal layer in the embodiment of the present invention
  • 4f is a schematic view showing the second photoresist after ashing in the method of forming the light absorbing layer and the gate metal layer in the embodiment of the present invention
  • FIG. 5 is a view showing the structure of a halftone mask for forming an organic light absorbing layer and a gate metal layer in an embodiment of the present invention
  • FIG. 6 is a schematic structural view of a display device according to an embodiment of the present invention.
  • an embodiment of the present invention provides an array substrate.
  • FIG. 1 is a schematic structural view of an array substrate 10 according to an embodiment of the present invention.
  • the array substrate 10 of the present embodiment mainly includes a base substrate 1, a light absorbing layer 2, and a bottom gate type thin film transistor unit.
  • the light absorbing layer 2 is located on the base substrate
  • the bottom gate type thin film transistor unit is located on the light absorbing layer 2.
  • the direction in which the light absorbing layer 2 faces the base substrate 1 is the light outgoing direction.
  • the position of the light absorbing layer 2 is set such that the projection of the light absorbing layer 2 covers the gate metal layer 3, the source metal layer 7, and the drain metal layer 8 of the bottom gate type thin film transistor unit.
  • the light absorbing layer 2 covering each metal layer of the bottom gate type thin film transistor unit inside the array substrate 10, it is possible to effectively block all ambient light that is irradiated onto each metal layer of the gate thin film transistor unit. .
  • the light absorbing layer 2 does not block the useful ambient light that is irradiated to the area other than the metal layer, thereby not reducing the brightness of the display panel, and avoiding the increase of the power consumption of the display panel and the life of the display panel caused by the use of the circular polarizer in the prior art. The emergence of small phenomena.
  • the thin film transistor unit can mainly realize the transfer of an electrical signal between the source metal layer 7 and the drain metal layer 8 by forming a conductive channel in the active layer 5.
  • the illumination affects the ability of the conductive channel in the active layer 5 to transport carriers, thereby affecting the operation of the thin film transistor unit. Therefore, in a preferred embodiment of the present invention, still referring to FIG. 1, the projection of the light absorbing layer 2 covers the active layer of the bottom gate type thin film transistor unit in addition to the metal layers of the bottom gate type thin film transistor unit. 5.
  • the ambient light irradiated to the active layer 5 is blocked by the light absorbing layer 2, the transmission capability of the conductive communication in the active layer 5 to the carriers is improved, and the working effect of the thin film transistor unit is improved.
  • the light absorbing layer 2 described in this embodiment may be an organic light absorbing layer such as a black matrix, or may be an inorganic light absorbing layer such as a ferrous metal layer. In a preferred embodiment of the invention, the light absorbing layer 2 is preferably an organic light absorbing layer.
  • the bottom gate type thin film transistor unit includes a gate metal layer 3, a gate insulating layer 4, an active layer 5, an etch barrier layer 6, and a source metal layer 7. And a drain metal layer 8.
  • the gate metal layer 3 is located on the light absorbing layer 2.
  • the gate insulating layer 4 is on the gate metal layer 3.
  • the active layer 5 is on the gate insulating layer 4.
  • the etch barrier layer 6 is disposed on the active layer 5, and the first via hole 61 and the second via hole 62 are further formed on the etch barrier layer 6.
  • the source metal layer 7 and the drain metal layer 8 disposed in the same layer are both located on the etch barrier layer 6, and the source metal layer 7 is connected to the active layer 5 through the first via 61, and the drain metal layer 8 is passed through the second layer.
  • the via 62 is connected to the active layer 5.
  • FIG. 2 is a schematic flow chart of a method for preparing an array substrate 10 according to an embodiment of the present invention.
  • the method for preparing the array substrate 10 in the embodiment of the present invention mainly includes the following steps:
  • Step 101 Providing a base substrate 1.
  • Step 102 forming a light absorbing layer 2 and a bottom gate type thin film transistor unit on the base substrate 1, and projecting the projection of the light absorbing layer 2 to cover the gate metal layer 3, the source metal layer 7, and the drain of the bottom gate type thin film transistor unit Metal layer 8.
  • a method of forming the light-absorbing layer 2 and the gate metal layer 3 of the bottom-gate thin film transistor unit on the base substrate 1 will be described in detail below with reference to FIGS. 3 and 4a to 4f.
  • the light absorbing layer 2 of the genus layer can effectively block all ambient light that is irradiated onto the metal layers of each layer of the gate-type thin film transistor unit, thereby ensuring the display effect of the display panel and reducing the manufacturing cost of the display panel.
  • the light absorbing layer 2 does not block the useful ambient light that is irradiated to the area other than the metal layer, thereby not reducing the brightness of the display panel, and avoiding the increase of the power consumption of the display panel and the life of the display panel caused by the use of the circular polarizer in the prior art. The emergence of small phenomena.
  • FIG. 3 it is a schematic flow chart of a method for forming the light absorbing layer 2 and the gate metal layer 3 in the embodiment of the present invention.
  • the method for forming the light absorbing layer 2 and the gate metal layer 3 in the embodiment of the present invention mainly includes the following steps:
  • Step 201 sequentially depositing the light absorbing layer 2 and the gate metal layer 3 on the base substrate 1.
  • Step 202 Applying a photoresist 9 on the gate metal layer 3.
  • FIG. 4a a schematic view after sequentially depositing the light absorbing layer 2, the gate metal layer 3, and the photoresist 9 on the base substrate 1 is as shown in FIG. 4a.
  • the thickness of the light absorbing layer 2 is preferably a thickness of
  • the material of the gate metal layer 3 is preferably chromium, molybdenum, aluminum, copper or the like.
  • Step 203 Exposing and developing the photoresist using a gray tone or halftone mask to form an unexposed photoresist topography, a partially exposed photoresist topography, and a fully exposed area.
  • the photoresist 9 is exposed using a gray tone or halftone mask to form the photoresist 9 into an unexposed area, a partially exposed area, and a fully exposed area.
  • the photoresist 9 of the fully exposed region is completely removed by development, the photoresist 9 of the partially exposed region is partially removed to form a partially exposed photoresist topography, and the photoresist 9 of the unexposed region is left to form an unexposed photoresist. appearance.
  • the structure of the halftone mask 100 is as shown in FIG.
  • the halftone template 100 is divided into seven regions arranged in order.
  • the first region 101, the third region 103, and the seventh region 107 are all completely transparent regions.
  • the second region 102, the fourth region 104, and the sixth region 106 are partially light transmissive regions.
  • the fifth region 105 is an opaque region.
  • a schematic view of the photoresist 9 coated in step 202 after exposure and development by the halftone mask 100 shown in FIG. 5 is shown in FIG. 4b.
  • the photoresist 9 corresponding to the completely transparent region is completely removed.
  • the photoresist 9 corresponding to the partially transparent region is partially removed to form a partially exposed photoresist topography.
  • the photoresist 9 corresponding to the opaque region is retained to form an unexposed photoresist topography.
  • Step 204 The gate metal layer 3 and the light absorbing layer 2 exposed on the outside of the photoresist 9 are removed by a first etching process.
  • the gate metal layer 3 and the light absorbing layer 2 of the fully exposed region are removed by a first etching process, preferably a first wet etching process.
  • a first etching process preferably a first wet etching process.
  • Step 205 removing the photoresist 9 other than the unexposed photoresist topography by the first ashing process.
  • Step 206 removing the gate metal layer 3 of the region other than the unexposed photoresist topography by a second etching process.
  • the gate metal layer 3 of the region other than the unexposed photoresist topography is removed by a second etching process, preferably a second wet etching process.
  • a second etching process preferably a second wet etching process.
  • Step 207 The remaining photoresist 9 is removed by a second ashing process.
  • the light absorbing layer 2 and the gate metal layer 3 shown in FIG. 1 can be formed.
  • the two exposure and development processes of the prior art forming the light absorbing layer 2 and the gate metal layer 3 are integrated into one exposure and development process by using a gray tone or halftone mask, thereby improving production efficiency.
  • the product characteristics of the array substrate 10 are ensured.
  • the method for forming a bottom gate type thin film transistor unit on the base substrate 1 in the embodiment of the present invention further includes the following steps:
  • Step 301 Forming a gate insulating layer 4 on the gate metal layer 3.
  • an inorganic film SiOx or SiOx/SiNx is plated on the gate metal layer 3 to form the gate insulating layer 4.
  • Step 302 Forming the active layer 5 on the gate insulating layer 4.
  • the method of forming the active layer 5 on the gate insulating layer 4 is: first, at an appropriate thickness (preferably A semiconductor film (ZnO, InZnO, ZnSnO, GaInZnO, ZrInZnO) is deposited on the gate insulating layer 4. Next, a layer of photoresist is coated on the semiconductor film layer, and the photoresist is exposed and developed using a gray tone or halftone mask. Then, the semiconductor film exposed to the outside of the photoresist is removed by a wet etching process. Finally, the remaining photoresist is removed by an ashing process, and the remaining semiconductor film is the active layer 5.
  • an appropriate thickness preferably A semiconductor film (ZnO, InZnO, ZnSnO, GaInZnO, ZrInZnO) is deposited on the gate insulating layer 4.
  • a layer of photoresist is coated on the semiconductor film layer, and the photoresist is exposed and developed using a gray tone or halftone mask. Then,
  • Step 303 forming an etch stop layer 6 on the active layer 5, and opening the first via hole and the second via hole on the etch stop layer 6.
  • the method of forming the etch stop layer 6 on the active layer 5 is: first, at an appropriate thickness (preferably An inorganic film (SiOx) is plated on the active layer 5. Next, a layer of photoresist is coated on the inorganic film, and the photoresist is exposed and developed using a mask. Then, the inorganic film exposed to the outside of the photoresist is removed by a dry etching process. Finally, the remaining photoresist is removed by an ashing process, and the remaining inorganic film is an etch stop layer 6 having a first via and a second via.
  • an appropriate thickness preferably An inorganic film (SiOx) is plated on the active layer 5.
  • a layer of photoresist is coated on the inorganic film, and the photoresist is exposed and developed using a mask. Then, the inorganic film exposed to the outside of the photoresist is removed by a dry etching process. Finally, the remaining photoresist is removed by an ashing
  • Step 304 forming a source metal layer 7 and a drain metal layer 8 on the etch barrier layer 6, and connecting the source metal layer 7 and the drain metal layer 8 through the first via and the second via, respectively.
  • Layer 5 a source metal layer 7 and a drain metal layer 8 on the etch barrier layer 6, and connecting the source metal layer 7 and the drain metal layer 8 through the first via and the second via, respectively.
  • the method of forming the source metal layer 7 and the drain metal layer 8 on the etch barrier layer 6 is: first, at an appropriate thickness (preferably A metal layer is deposited on the etch stop layer 6. Next, a layer of photoresist is applied over the metal layer, and the photoresist is exposed and developed using a mask. Then, the metal layer exposed to the outside of the photoresist is removed by a wet etching process. Finally, the remaining photoresist is removed by an ashing process, and the remaining metal layers are the source metal layer 7 and the drain metal layer 8.
  • an appropriate thickness preferably A metal layer is deposited on the etch stop layer 6.
  • a layer of photoresist is applied over the metal layer, and the photoresist is exposed and developed using a mask. Then, the metal layer exposed to the outside of the photoresist is removed by a wet etching process. Finally, the remaining photoresist is removed by an ashing process, and the remaining metal layers are the source metal layer 7 and the drain metal layer 8.
  • the embodiment of the invention further provides a display device having the array substrate 10 described above.
  • FIG. 6 is a schematic structural view of a display device according to an embodiment of the present invention.
  • the display device described in this embodiment includes an array substrate 10, a passivation layer 11, a pixel electrode layer 12, a pixel insulating layer 13, an organic layer 14, a cathode metal layer 15, and a package cover 16.
  • the passivation layer 11 is on the array substrate 10.
  • the pixel electrode layer 12 is located on the passivation layer 11.
  • the pixel insulating layer 13 is located on the pixel electrode layer 12.
  • the organic layer 14 is on the pixel insulating layer 13.
  • the cathode metal layer 15 is located on the organic layer 14.
  • the package cover 16 is located on the cathode metal layer 15.
  • the method for preparing the above display device includes the following steps in addition to the above method for preparing the array substrate 10, and further includes the steps of:
  • Step 401 Forming a passivation layer 11 on the array substrate 10.
  • the method of forming the passivation layer 11 on the array substrate 10 is: first, at an appropriate thickness (preferably A protective film (SiOx or SiOx/SiNx) is plated on the array substrate 10. Next, a layer of photoresist is coated on the protective film, and the photoresist is exposed and developed using a mask. Then, the protective film exposed to the outside of the photoresist is removed by a dry etching process. Finally, the remaining photoresist is removed by an ashing process, and the remaining protective film is the passivation layer 11.
  • an appropriate thickness preferably A protective film (SiOx or SiOx/SiNx) is plated on the array substrate 10.
  • a layer of photoresist is coated on the protective film, and the photoresist is exposed and developed using a mask. Then, the protective film exposed to the outside of the photoresist is removed by a dry etching process. Finally, the remaining photoresist is removed by an ashing process, and the remaining protective film
  • Step 402 Forming the pixel electrode layer 12 on the passivation layer 11.
  • the method of forming the pixel electrode layer 12 on the passivation layer 11 is: first, at an appropriate thickness (preferably A transparent electrode (ITO or IZO) is plated on the passivation layer 11. Next, a layer of photoresist is coated on the transparent electrode, and the photoresist is exposed and developed using a mask. Then, the transparent electrode exposed to the outside of the photoresist is removed by a wet etching process. Finally, the remaining photoresist is removed by an ashing process, and the remaining transparent electrode is the pixel electrode layer 12.
  • an appropriate thickness preferably A transparent electrode (ITO or IZO) is plated on the passivation layer 11.
  • a layer of photoresist is coated on the transparent electrode, and the photoresist is exposed and developed using a mask. Then, the transparent electrode exposed to the outside of the photoresist is removed by a wet etching process. Finally, the remaining photoresist is removed by an ashing process, and the remaining transparent electrode is the pixel electrode layer
  • Step 403 Forming the pixel insulating layer 13 on the pixel electrode layer 12.
  • the method of forming the pixel insulating layer 13 on the pixel electrode layer 12 is: first, at an appropriate thickness (preferably An inorganic film (SiOx) is plated on the pixel electrode layer 12. Next, a layer of photoresist is coated on the inorganic film, and the photoresist is exposed and developed using a mask. Then, the inorganic film exposed to the outside of the photoresist is removed by a wet etching process. Finally, the remaining photoresist is removed by an ashing process, and the remaining inorganic film is the pixel insulating layer 13.
  • an appropriate thickness preferably An inorganic film (SiOx) is plated on the pixel electrode layer 12.
  • a layer of photoresist is coated on the inorganic film, and the photoresist is exposed and developed using a mask. Then, the inorganic film exposed to the outside of the photoresist is removed by a wet etching process. Finally, the remaining photoresist is removed by an a
  • Step 404 Forming the organic layer 14 on the pixel insulating layer 13.
  • Step 405 Forming a cathode metal layer 15 on the organic layer 14.
  • Step 406 Install the package cover 16.
  • a hole injection layer, a hole transport layer, and an organic light are formed on the pixel insulating layer 13 by an evaporation process.
  • a layer, an electron transport layer, and an electron injection layer are formed to form the organic layer 14.
  • a cathode metal layer 15 is formed on the organic layer 14 by a sputtering process.
  • the display panel is packaged using a packaging process.
  • the light absorbing layer 2 covering each metal layer of the bottom gate type thin film transistor unit inside the array substrate 10, it is possible to effectively block all ambient light that is irradiated onto each metal layer of the gate thin film transistor unit. It ensures the display effect of the display panel and reduces the manufacturing cost of the display panel.
  • the light absorbing layer 2 does not block the useful ambient light that is irradiated to the area other than the metal layer, thereby not reducing the brightness of the display panel, and avoiding the increase of the power consumption of the display panel and the life of the display panel caused by the use of the circular polarizer in the prior art. The emergence of small phenomena.

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Abstract

一种阵列基板、显示装置及用于制备阵列基板的方法，阵列基板(10)包括依次设置的衬底基板(1)、吸光层(2)和底栅型薄膜晶体管单元；吸光层(2)的投影覆盖底栅型薄膜晶体管单元的栅极金属层(3)、源极金属层(7)和漏极金属层(8)。由此能在不降低显示面板的亮度的基础上，有效遮挡所有照射到栅型薄膜晶体管单元的各层金属层上的环境光。

Description

阵列基板、显示装置及用于制备阵列基板的方法
本申请要求享有2015年4月10日提交的名称为“阵列基板、显示装置及用于制备阵列基板的方法”的中国专利申请CN201510167361.X的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板，还涉及一种具有该阵列基板的显示装置，以及用于制备该阵列基板的方法。
背景技术
主动有机发光二极管(Active-matrix Organic Light Emitting Diode，简称为AMOLED)是一种利用有机半导体材料制成的、用直流电压驱动的薄膜发光器件。与传统的LCD显示技术不同，AMOLED显示技术无需背光灯，仅需非常薄的有机材料涂层即可实现发光。AMOLED显示技术的发光原理是：当有电流通过有机材料涂层时，有机材料涂层内的有机材料就会发光。AMOLED显示面板可以做得更轻更薄，可视角度更大，并且能够显著节省电能。
AMOLED显示面板具有栅极金属层、源极金属层和漏极金属层。这些金属层的反光能力强。环境光可以通过显示面板的盖板的开口区域照射到这些金属层上并与金属层发生强烈的反射，从而影响AMOLED显示面板的显示效果。
现有技术通常采用在盖板上贴合一片圆偏光片的方法，来实现阻挡部分环境光照射到显示面板的金属层上的目的。然而，通过圆偏光片阻挡部分环境光照射到显示面板的金属层的方法的缺陷在于：由于圆偏光片的遮光区域与显示面板的金属层的设置区域不完全吻合，因此一方面圆偏光片不能完全遮挡照射到金属层的所有环境光，另一方面圆偏光片会遮挡住照射到金属层以外区域的有用环境光，从而使显示面板的亮度明显降低。为了补偿降低的亮度，需要相应地增加显示面板的功耗。但是，功耗的增加又会带来显示面板寿命的大幅缩短以及显示面板整体厚度的增加。
发明内容
本发明所要解决的技术问题是在不增加显示面板功耗的情况下有效阻挡环境光照射到显示面板的金属层上。
为了解决上述技术问题，本发明提供了一种阵列基板及其制备方法、显示装置。
根据本发明的第一个方面，提供了一种阵列基板，其包括：
衬底基板；
位于所述衬底基板上的吸光层；以及
位于所述吸光层上的底栅型薄膜晶体管单元；
其中，所述吸光层的投影覆盖所述底栅型薄膜晶体管单元的栅极金属层、源极金属层和漏极金属层。
优选的是，所述吸光层的投影还覆盖所述底栅型薄膜晶体管单元的有源层。
优选的是，所述吸光层为有机吸光层。
优选的是，所述底栅型薄膜晶体管单元包括：
位于所述吸光层上的所述栅极金属层；
位于所述栅极金属层上的栅极绝缘层；
位于所述栅极绝缘层上的有源层；
位于所述有源层上的刻蚀阻挡层，其上开设有第一过孔和第二过孔；以及
位于所述刻蚀阻挡层上的所述源极金属层和所述漏极金属层，所述源极金属层和所述漏极金属层分别通过所述第一过孔和所述第二过孔连接所述有源层。
根据本发明的第二个方面，提供了一种具有上述阵列基板的显示装置。
优选的是，所述显示装置还包括：
位于所述阵列基板上的钝化层；
位于所述钝化层上的像素电极层；
位于所述像素电极层上的像素绝缘层；
位于所述像素绝缘层上的有机层；
位于所述有机层上的阴极金属层；以及
位于所述阴极金属层上的封装盖板。
根据本发明的第三个方面，提供了一种用于制备上述阵列基板的方法，该方法包括：
提供衬底基板；
在所述衬底基板上形成吸光层和底栅型薄膜晶体管单元，并使所述吸光层的投影覆盖所述底栅型薄膜晶体管单元的栅极金属层、源极金属层和漏极金属层。
优选的是，在所述衬底基板上形成吸光层和底栅型薄膜晶体管单元，包括在所述衬底 基板上形成所述吸光层和所述栅极金属层；在所述衬底基板上形成所述吸光层和所述栅极金属层，包括：
在所述衬底基板上依次沉积吸光层和栅极金属层；
在所述栅极金属层上涂布光刻胶；
采用灰色调或半色调掩模板对所述光刻胶进行曝光和显影，形成未曝光光刻胶形貌、部分曝光光刻胶形貌和完全曝光区域；
通过第一次刻蚀工艺去掉暴露在光刻胶外面的栅极金属层和吸光层；
通过第一次灰化工艺去掉除所述未曝光光刻胶形貌以外的光刻胶；
通过第二次刻蚀工艺去掉未曝光光刻胶形貌以外区域的栅极金属层；
通过第二次灰化工艺去掉剩余的光刻胶。
优选的是，采用灰色调或半色调掩模板对所述光刻胶进行曝光和显影，形成未曝光光刻胶形貌、部分曝光光刻胶形貌和完全曝光区域，具体为：
采用灰色调或半色调掩模板对所述光刻胶进行曝光，使光刻胶形成未曝光区域、部分曝光区域和所述完全曝光区域，通过显影完全去掉所述完全曝光区域的光刻胶，部分去掉所述部分曝光区域的光刻胶以形成所述部分曝光光刻胶形貌，保留未曝光区域的光刻胶以形成所述未曝光光刻胶形貌。
优选的是，在所述衬底基板上形成吸光层和底栅型薄膜晶体管单元，还包括：
在所述栅极金属层上形成栅极绝缘层；
在所述栅极绝缘层上形成有源层；
在所述有源层上形成刻蚀阻挡层，并使所述刻蚀阻挡层上开设有第一过孔和第二过孔；
在所述刻蚀阻挡层上形成所述源极金属层和所述漏极金属层，并使所述源极金属层和所述漏极金属层分别通过所述第一过孔和所述第二过孔连接所述有源层。
与现有技术相比，上述方案中的一个或多个实施例可以具有如下优点或有益效果：
本发明通过在阵列基板内部设置投影覆盖底栅型薄膜晶体管单元的各层金属层的吸光层，能够有效遮挡所有照射到栅型薄膜晶体管单元的各层金属层上的环境光。另外，吸光层不会遮挡照射到金属层以外区域的有用环境光，从而不会降低显示面板的亮度，避免了现有技术中采用圆偏光片导致的显示面板功耗增加和显示面板寿命减小的现象的出现。
本发明的其它特征和优点将在随后的说明书中阐述，并且部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1示出了本发明实施例阵列基板的结构示意图；
图2示出了本发明实施例用于制备阵列基板的方法的流程示意图；
图3示出了本发明实施例中形成吸光层和栅极金属层的方法的流程示意图；
图4a示出了本发明实施例中形成吸光层和栅极金属层的方法中在衬底基板上依次沉积吸光层、栅极金属层和光刻胶后的示意图；
图4b示出了本发明实施例中形成吸光层和栅极金属层的方法中曝光显影工艺后的示意图；
图4c示出了本发明实施例中形成吸光层和栅极金属层的方法中第一次刻蚀后的示意图；
图4d示出了本发明实施例中形成吸光层和栅极金属层的方法中第一次光刻胶灰化后的示意图；
图4e示出了本发明实施例中形成吸光层和栅极金属层的方法中第二次刻蚀后的示意图；
图4f示出了本发明实施例中形成吸光层和栅极金属层的方法中第二次光刻胶灰化后的示意图；
图5示出了本发明实施例中用于形成有机吸光层和栅极金属层的半色调掩模板的结构示意图；以及
图6示出了本发明实施例显示装置的结构示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
为了实现在不增加显示面板功耗的情况下有效阻挡环境光照射到显示面板的金属层上的目的，本发明实施例提供了一种阵列基板。
如图1所示，是本发明实施例的阵列基板10的结构示意图。本实施例的阵列基板10主要包括衬底基板1、吸光层2和底栅型薄膜晶体管单元。其中，吸光层2位于衬底基板 1上，底栅型薄膜晶体管单元位于吸光层2上。吸光层2朝向衬底基板1的方向为出光方向。另外，吸光层2的设置位置需满足：吸光层2的投影覆盖底栅型薄膜晶体管单元的栅极金属层3、源极金属层7和漏极金属层8。
本实施例中，通过在阵列基板10内部设置投影覆盖底栅型薄膜晶体管单元的各层金属层的吸光层2，能够有效遮挡所有照射到栅型薄膜晶体管单元的各层金属层上的环境光。另外，吸光层2不会遮挡照射到金属层以外区域的有用环境光，从而不会降低显示面板的亮度，避免了现有技术中采用圆偏光片导致的显示面板功耗增加和显示面板寿命减小的现象的出现。
薄膜晶体管单元主要通过在有源层5中形成导电沟道，使得源极金属层7和漏极金属层8之间可以实现电信号的传递。然而，光照会影响有源层5内的导电沟道对载流子的传输能力，进而影响薄膜晶体管单元的工作效果。因此，在本发明一优选的实施例中，仍参照图1，吸光层2的投影除了覆盖底栅型薄膜晶体管单元的各层金属层之外，还覆盖底栅型薄膜晶体管单元的有源层5。本实施例通过吸光层2遮挡照射到有源层5的环境光，提高了有源层5内的导电沟通对载流子的传输能力，提高了薄膜晶体管单元的工作效果。
本实施例所述的吸光层2可以为诸如黑色矩阵的有机吸光层，也可以为诸如黑色金属层的无机吸光层。在本发明一优选的实施例中，吸光层2优选为有机吸光层。
仍参照图1，在本发明一优选的实施例中，底栅型薄膜晶体管单元包括栅极金属层3、栅极绝缘层4、有源层5、刻蚀阻挡层6、源极金属层7和漏极金属层8。
具体地，栅极金属层3位于吸光层2上。栅极绝缘层4位于栅极金属层3上。有源层5位于栅极绝缘层4上。刻蚀阻挡层6位于有源层5上，在刻蚀阻挡层6上还开设有第一过孔61和第二过孔62。同层设置的源极金属层7和漏极金属层8均位于刻蚀阻挡层6上，并且源极金属层7通过第一过孔61连接有源层5，漏极金属层8通过第二过孔62连接有源层5。
如图2所示，是本发明实施例用于制备阵列基板10的方法的流程示意图。本发明实施例用于制备阵列基板10的方法，主要包括以下步骤：
步骤101：提供衬底基板1。
步骤102：在衬底基板1上形成吸光层2和底栅型薄膜晶体管单元，并使吸光层2的投影覆盖底栅型薄膜晶体管单元的栅极金属层3、源极金属层7和漏极金属层8。具体地，在衬底基板1上形成吸光层2和底栅型薄膜晶体管单元的栅极金属层3的方法，将在下文中结合图3、图4a～图4f进行详细地阐述。
本实施例中，通过在阵列基板10内部设置投影覆盖底栅型薄膜晶体管单元的各层金 属层的吸光层2，能够有效遮挡所有照射到栅型薄膜晶体管单元的各层金属层上的环境光，保证了显示面板的显示效果的同时，降低了显示面板的制造成本。另外，吸光层2不会遮挡照射到金属层以外区域的有用环境光，从而不会降低显示面板的亮度，避免了现有技术中采用圆偏光片导致的显示面板功耗增加和显示面板寿命减小的现象的出现。
如图3所示，是本发明实施例中形成吸光层2和栅极金属层3的方法的流程示意图。本发明实施例中形成吸光层2和栅极金属层3的方法，主要包括以下步骤：
步骤201：在衬底基板1上依次沉积吸光层2和栅极金属层3。
步骤202：在栅极金属层3上涂布光刻胶9。
具体地，在衬底基板1上依次沉积吸光层2、栅极金属层3和光刻胶9之后的示意图如图4a所示。吸光层2的厚度优选为厚度为
Figure PCTCN2015078871-appb-000001
另外，栅极金属层3的材料优选为铬、钼、铝、铜等。
步骤203：采用灰色调或半色调掩模板对光刻胶进行曝光和显影，形成未曝光光刻胶形貌、部分曝光光刻胶形貌和完全曝光区域。
具体地，采用灰色调或半色调掩模板对光刻胶9进行曝光，使光刻胶9形成未曝光区域、部分曝光区域和完全曝光区域。通过显影完全去掉完全曝光区域的光刻胶9，部分去掉部分曝光区域的光刻胶9以形成部分曝光光刻胶形貌，保留未曝光区域的光刻胶9以形成未曝光光刻胶形貌。
在本实施例中，半色调掩模板100的结构如图5所示。将半色调模板100划分为依次排列的七个区域。其中，第一区域101、第三区域103和第七区域107均为完全透光区域。第二区域102、第四区域104和第六区域106为部分透光区域。第五区域105为不透光区域。采用图5所示的半色调掩模板100对步骤202中涂布的光刻胶9进行曝光显影工艺后的示意图如图4b所示。其中，完全透光区域对应的光刻胶9被完全去掉。部分透光区域对应的光刻胶9被部分去掉，形成部分曝光光刻胶形貌。不透光区域对应的光刻胶9得以保留，形成未曝光光刻胶形貌。
步骤204：通过第一次刻蚀工艺去掉暴露在光刻胶9外面的栅极金属层3和吸光层2。
具体地，通过第一次刻蚀工艺(优选为第一次湿刻工艺)去掉完全曝光区域的栅极金属层3和吸光层2。第一次刻蚀后的示意图如图4c所示。
步骤205：通过第一次灰化工艺去掉除未曝光光刻胶形貌以外的光刻胶9。
具体地，通过灰化工艺将不需要的光刻胶9灰化掉，去掉未曝光光刻胶形貌以外的光刻胶9。第一次灰化工艺后的示意图如图4d所示。
步骤206：通过第二次刻蚀工艺去掉未曝光光刻胶形貌以外区域的栅极金属层3。
具体地，通过第二次刻蚀工艺(优选为第二次湿刻工艺)去掉未曝光光刻胶形貌以外区域的栅极金属层3。第二次刻蚀工艺后的示意图如图4e所示。
步骤207：通过第二次灰化工艺去掉剩余的光刻胶9。
具体地，如图4f所示，通过第二次灰化工艺将剩余的光刻胶9去掉后，即可形成图1中所示的吸光层2和栅极金属层3。
在本实施例中，通过采用灰色调或半色调掩模板，将现有技术形成吸光层2和栅极金属层3的两道曝光显影工艺整合成一道曝光显影工艺，在提高生产效率的同时，保证了阵列基板10的产品特性。
本发明实施例中在衬底基板1上形成底栅型薄膜晶体管单元的方法还包括以下步骤：
步骤301：在栅极金属层3上形成栅极绝缘层4。
具体地，按适当的厚度(优选为
Figure PCTCN2015078871-appb-000002
)在栅极金属层3上镀无机膜(SiOx或者SiOx/SiNx))，以形成栅极绝缘层4。
步骤302：在栅极绝缘层4上形成有源层5。
具体地，在栅极绝缘层4上形成有源层5的方法为：首先，按适当的厚度(优选为
Figure PCTCN2015078871-appb-000003
)在栅极绝缘层4上沉积一层半导体膜(ZnO，InZnO，ZnSnO，GaInZnO，ZrInZnO)。其次，在半导体膜层上涂布一层光刻胶，并采用灰色调或半色调掩模板对光刻胶进行曝光和显影。然后，通过湿刻工艺去掉暴露在光刻胶外面的半导体膜。最后，通过灰化工艺去掉剩余的光刻胶，剩余的半导体膜即为有源层5。
步骤303：在有源层5上形成刻蚀阻挡层6，并使刻蚀阻挡层6上开设有第一过孔和第二过孔。
具体地，在有源层5上形成刻蚀阻挡层6的方法为：首先，按适当的厚度(优选为
Figure PCTCN2015078871-appb-000004
)在有源层5上镀无机膜(SiOx)。其次，在无机膜上涂布一层光刻胶，并采用掩模板对光刻胶进行曝光显影。然后，通过干刻工艺去掉暴露在光刻胶外面的无机膜。最后，通过灰化工艺去掉剩余的光刻胶，剩余的无机膜即为具有第一过孔和第二过孔的刻蚀阻挡层6。
步骤304：在刻蚀阻挡层6上形成源极金属层7和漏极金属层8，并使源极金属层7和漏极金属层8分别通过第一过孔和第二过孔连接有源层5。
具体地，在刻蚀阻挡层6上形成源极金属层7和漏极金属层8的方法为：首先，按适当的厚度(优选为
Figure PCTCN2015078871-appb-000005
)在刻蚀阻挡层6上沉积一层金属层。其次，在金属层上涂布一层光刻胶，并采用掩模板对光刻胶进行曝光和显影。然后，通过湿刻工艺去掉暴露在光刻胶外面的金属层。最后，通过灰化工艺去掉剩余的光刻胶，剩余的金属层即为源极 金属层7和漏极金属层8。
本发明实施例还提供了一种具有上述阵列基板10的显示装置。
如图6所示，是本发明实施例显示装置的结构示意图。本实施例所述的显示装置包括阵列基板10、钝化层11、像素电极层12、像素绝缘层13、有机层14、阴极金属层15和封装盖板16。
具体地，钝化层11位于阵列基板10上。像素电极层12位于钝化层11上。像素绝缘层13位于像素电极层12上。有机层14位于像素绝缘层13上。阴极金属层15位于有机层14上。封装盖板16位于阴极金属层15上。
用于制备上述显示装置的方法除了包括以上用于制备阵列基板10的方法以下，还包括步骤：
步骤401：在阵列基板10上形成钝化层11。
具体地，在阵列基板10上形成钝化层11的方法为：首先，按适当的厚度(优选为
Figure PCTCN2015078871-appb-000006
)在阵列基板10上镀保护膜(SiOx或者SiOx/SiNx)。其次，在保护膜上涂布一层光刻胶，并采用掩模板对光刻胶进行曝光和显影。然后，通过干刻工艺去掉暴露在光刻胶外面的保护膜。最后，通过灰化工艺去掉剩余的光刻胶，剩余的保护膜即为钝化层11。
步骤402：在钝化层11上形成像素电极层12。
具体地，在钝化层11上形成像素电极层12的方法为：首先，按适当的厚度(优选为
Figure PCTCN2015078871-appb-000007
)在钝化层11上镀透明电极(ITO或者IZO)。其次，在透明电极上涂布一层光刻胶，并采用掩模板对光刻胶进行曝光和显影。然后，通过湿刻工艺去掉暴露在光刻胶外面的透明电极。最后，通过灰化工艺去掉剩余的光刻胶，剩余的透明电极即为像素电极层12。
步骤403：在像素电极层12上形成像素绝缘层13。
具体地，在像素电极层12上形成像素绝缘层13的方法为：首先，按适当的厚度(优选为
Figure PCTCN2015078871-appb-000008
)在像素电极层12上镀无机膜(SiOx)。其次，在无机膜上涂布一层光刻胶，并采用掩模板对光刻胶进行曝光和显影。然后，通过湿刻工艺去掉暴露在光刻胶外面的无机膜。最后，通过灰化工艺去掉剩余的光刻胶，剩余的无机膜即为像素绝缘层13。
步骤404：在像素绝缘层13上形成有机层14。
步骤405：在有机层14上形成阴极金属层15。
步骤406：安装封装盖板16。
具体地，采用蒸镀工艺在像素绝缘层13上形成空穴注入层、空穴传输层、有机发光 层、电子传输层和电子注入层，以形成有机层14。然后，再采用溅射工艺在有机层14上形成阴极金属层15。最后，采用封装工艺对显示面板进行封装。
本实施例中，通过在阵列基板10内部设置投影覆盖底栅型薄膜晶体管单元的各层金属层的吸光层2，能够有效遮挡所有照射到栅型薄膜晶体管单元的各层金属层上的环境光，保证了显示面板的显示效果的同时，降低了显示面板的制造成本。另外，吸光层2不会遮挡照射到金属层以外区域的有用环境光，从而不会降低显示面板的亮度，避免了现有技术中采用圆偏光片导致的显示面板功耗增加和显示面板寿命减小的现象的出现。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板；
    位于所述衬底基板上的吸光层；以及
    位于所述吸光层上的底栅型薄膜晶体管单元；
    其中，所述吸光层的投影覆盖所述底栅型薄膜晶体管单元的栅极金属层、源极金属层和漏极金属层。
  2. 根据权利要求1所述的阵列基板，其中，所述吸光层为有机吸光层。
  3. 根据权利要求1所述的阵列基板，其中，所述底栅型薄膜晶体管单元包括：
    位于所述吸光层上的所述栅极金属层；
    位于所述栅极金属层上的栅极绝缘层；
    位于所述栅极绝缘层上的有源层；
    位于所述有源层上的刻蚀阻挡层，其上开设有第一过孔和第二过孔；以及
    位于所述刻蚀阻挡层上的所述源极金属层和所述漏极金属层，所述源极金属层和所述漏极金属层分别通过所述第一过孔和所述第二过孔连接所述有源层。
  4. 根据权利要求1所述的阵列基板，其中，所述吸光层的投影还覆盖所述底栅型薄膜晶体管单元的有源层。
  5. 根据权利要求4所述的阵列基板，其中，所述吸光层为有机吸光层。
  6. 根据权利要求4所述的阵列基板，其中，所述底栅型薄膜晶体管单元包括：
    位于所述吸光层上的所述栅极金属层；
    位于所述栅极金属层上的栅极绝缘层；
    位于所述栅极绝缘层上的有源层；
    位于所述有源层上的刻蚀阻挡层，其上开设有第一过孔和第二过孔；以及
    位于所述刻蚀阻挡层上的所述源极金属层和所述漏极金属层，所述源极金属层和所述漏极金属层分别通过所述第一过孔和所述第二过孔连接所述有源层。
  7. 一种显示装置，包括阵列基板，所述阵列基板包括：
    衬底基板；
    位于所述衬底基板上的吸光层；以及
    位于所述吸光层上的底栅型薄膜晶体管单元；
    其中，所述吸光层的投影覆盖所述底栅型薄膜晶体管单元的栅极金属层、源极金属层和漏极金属层。
  8. 根据权利要求7所述的显示装置，其中，还包括：
    位于所述阵列基板上的钝化层；
    位于所述钝化层上的像素电极层；
    位于所述像素电极层上的像素绝缘层；
    位于所述像素绝缘层上的有机层；
    位于所述有机层上的阴极金属层；以及
    位于所述阴极金属层上的封装盖板。
  9. 根据权利要求7所述的显示装置，其中，所述吸光层为有机吸光层。
  10. 根据权利要求9所述的显示装置，其中，还包括：
    位于所述阵列基板上的钝化层；
    位于所述钝化层上的像素电极层；
    位于所述像素电极层上的像素绝缘层；
    位于所述像素绝缘层上的有机层；
    位于所述有机层上的阴极金属层；以及
    位于所述阴极金属层上的封装盖板。
  11. 根据权利要求7所述的显示装置，其中，所述底栅型薄膜晶体管单元包括：
    位于所述吸光层上的所述栅极金属层；
    位于所述栅极金属层上的栅极绝缘层；
    位于所述栅极绝缘层上的有源层；
    位于所述有源层上的刻蚀阻挡层，其上开设有第一过孔和第二过孔；以及
    位于所述刻蚀阻挡层上的所述源极金属层和所述漏极金属层，所述源极金属层和所述漏极金属层分别通过所述第一过孔和所述第二过孔连接所述有源层。
  12. 根据权利要求11所述的显示装置，其中，还包括：
    位于所述阵列基板上的钝化层；
    位于所述钝化层上的像素电极层；
    位于所述像素电极层上的像素绝缘层；
    位于所述像素绝缘层上的有机层；
    位于所述有机层上的阴极金属层；以及
    位于所述阴极金属层上的封装盖板。
  13. 根据权利要求7所述的显示装置，其中，所述吸光层的投影还覆盖所述底栅型薄膜晶体管单元的有源层。
  14. 根据权利要求13所述的显示装置，其中，所述吸光层为有机吸光层。
  15. 根据权利要求13所述的显示装置，其中，所述底栅型薄膜晶体管单元包括：
    位于所述吸光层上的所述栅极金属层；
    位于所述栅极金属层上的栅极绝缘层；
    位于所述栅极绝缘层上的有源层；
    位于所述有源层上的刻蚀阻挡层，其上开设有第一过孔和第二过孔；以及
    位于所述刻蚀阻挡层上的所述源极金属层和所述漏极金属层，所述源极金属层和所述漏极金属层分别通过所述第一过孔和所述第二过孔连接所述有源层。
  16. 一种用于制备阵列基板的方法，包括：
    提供衬底基板；
    在所述衬底基板上形成吸光层和底栅型薄膜晶体管单元，并使所述吸光层的投影覆盖所述底栅型薄膜晶体管单元的栅极金属层、源极金属层和漏极金属层。
  17. 根据权利要求16所述的方法，其中：在所述衬底基板上形成吸光层和底栅型薄膜晶体管单元，包括在所述衬底基板上形成所述吸光层和所述栅极金属层；在所述衬底基板上形成所述吸光层和所述栅极金属层，包括：
    在所述衬底基板上依次沉积吸光层和栅极金属层；
    在所述栅极金属层上涂布光刻胶；
    采用灰色调或半色调掩模板对所述光刻胶进行曝光和显影，形成未曝光光刻胶形貌、部分曝光光刻胶形貌和完全曝光区域；
    通过第一次刻蚀工艺去掉暴露在光刻胶外面的栅极金属层和吸光层；
    通过第一次灰化工艺去掉除所述未曝光光刻胶形貌以外的光刻胶；
    通过第二次刻蚀工艺去掉未曝光光刻胶形貌以外区域的栅极金属层；
    通过第二次灰化工艺去掉剩余的光刻胶。
  18. 根据权利要求17所述的方法，其中，在所述衬底基板上形成吸光层和底栅型薄膜晶体管单元，还包括：
    在所述栅极金属层上形成栅极绝缘层；
    在所述栅极绝缘层上形成有源层；
    在所述有源层上形成刻蚀阻挡层，并使所述刻蚀阻挡层上开设有第一过孔和第二过孔；
    在所述刻蚀阻挡层上形成所述源极金属层和所述漏极金属层，并使所述源极金属层和所述漏极金属层分别通过所述第一过孔和所述第二过孔连接所述有源层。
  19. 根据权利要求17所述的方法，其中，采用灰色调或半色调掩模板对所述光刻胶进行曝光和显影，形成未曝光光刻胶形貌、部分曝光光刻胶形貌和完全曝光区域，具体为：
    采用灰色调或半色调掩模板对所述光刻胶进行曝光，使光刻胶形成未曝光区域、部分曝光区域和所述完全曝光区域，通过显影完全去掉所述完全曝光区域的光刻胶，部分去掉所述部分曝光区域的光刻胶以形成所述部分曝光光刻胶形貌，保留未曝光区域的光刻胶以形成所述未曝光光刻胶形貌。
  20. 根据权利要求19所述的方法，其中，在所述衬底基板上形成吸光层和底栅型薄膜晶体管单元，还包括：
    在所述栅极金属层上形成栅极绝缘层；
    在所述栅极绝缘层上形成有源层；
    在所述有源层上形成刻蚀阻挡层，并使所述刻蚀阻挡层上开设有第一过孔和第二过孔；
    在所述刻蚀阻挡层上形成所述源极金属层和所述漏极金属层，并使所述源极金属层和所述漏极金属层分别通过所述第一过孔和所述第二过孔连接所述有源层。
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