WO2016149958A1 - 液晶显示面板、阵列基板及其薄膜晶体管的制造方法 - Google Patents

液晶显示面板、阵列基板及其薄膜晶体管的制造方法 Download PDF

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WO2016149958A1
WO2016149958A1 PCT/CN2015/075765 CN2015075765W WO2016149958A1 WO 2016149958 A1 WO2016149958 A1 WO 2016149958A1 CN 2015075765 W CN2015075765 W CN 2015075765W WO 2016149958 A1 WO2016149958 A1 WO 2016149958A1
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layer
metal layer
electrode
thin film
film transistor
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French (fr)
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高冬子
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a method of manufacturing a thin film transistor of a liquid crystal display panel, an array substrate, and both.
  • TFT Thin film transistor Transistor
  • the industry generally uses aluminum metal Al and molybdenum metal Mo to manufacture thin film transistors, generally a layer of molybdenum metal is disposed above the aluminum metal layer, and in order to reduce the resistance of the thin film transistor, the thickness of the aluminum metal layer is designed to be large, however, due to the melting point of aluminum Lower (660 ° C), the high temperature environment required in the process causes the aluminum atoms to squeeze each other, and the aluminum metal layer is very easy to generate a hillock due to the extrusion deformation, and the resulting bump can cause serious A short circuit occurs between the gate electrode, the source electrode, and the drain electrode of the thin film transistor, thereby affecting the picture display quality of the liquid crystal display panel.
  • the embodiments of the present invention provide a liquid crystal display panel, an array substrate, and a method for manufacturing the same, which can suppress protrusions generated by deformation of an aluminum metal layer in a high temperature environment, and ensure picture display quality of the liquid crystal display panel.
  • the manufacturing method includes: providing a substrate; forming a first metal layer on the substrate, the first metal layer comprising an aluminum metal layer, an aluminum oxide layer and a molybdenum metal layer which are sequentially stacked; and patterning the first metal layer to form a thin film a gate electrode of the transistor; a gate insulating layer, a semiconductor layer and an ohmic contact layer are sequentially formed on the gate electrode; a second metal layer is formed on the ohmic contact layer; and the second metal layer is patterned to form a source electrode of the thin film transistor and Leakage electrode.
  • the step of forming the first metal layer on the ohmic contact layer comprises: bombarding the aluminum target with a plasma to sputter aluminum on the substrate; and introducing oxygen to cause oxidation of aluminum during sputtering to form an aluminum oxide layer Forming a molybdenum metal layer on the aluminum oxide layer.
  • the second metal layer includes an aluminum metal layer, an aluminum oxide layer, and a molybdenum metal layer which are sequentially stacked.
  • the manufacturing method further includes: forming a passivation layer on the source electrode and the drain electrode; forming a contact hole on the passivation layer to expose the source electrode or the drain electrode; forming a pixel electrode on the passivation layer, and the pixel electrode passes The contact hole is electrically connected to one of the source electrode and the drain electrode.
  • the contact holes are formed by dry etching.
  • the substrate comprises a substrate sheet and an oxide layer formed on the substrate sheet.
  • the array substrate includes a substrate and a thin film transistor array and a pixel electrode formed on the substrate.
  • the gate electrode of the thin film transistor includes an aluminum metal layer, an aluminum oxide layer and a molybdenum metal layer which are sequentially stacked, and the pixel electrode passes through the contact hole and the source of the thin film transistor.
  • One of the electrode and the drain electrode is electrically connected.
  • the source electrode and the drain electrode of the thin film transistor also include an aluminum metal layer, an aluminum oxide layer, and a molybdenum metal layer which are sequentially stacked.
  • the thin film transistor further includes a gate insulating layer formed on the gate electrode, a semiconductor layer formed on the gate insulating layer, and an ohmic contact layer formed on the semiconductor layer, and the source electrode and the drain electrode are formed on the ohmic contact layer.
  • the array substrate comprises a substrate and a thin film transistor array and a pixel electrode formed on the substrate, wherein the gate electrode of the thin film transistor comprises an aluminum metal layer, an aluminum oxide layer and a molybdenum metal layer which are sequentially stacked, and the pixel electrode passes through the contact hole and the source electrode of the thin film transistor One of the drain electrodes is electrically connected.
  • the source electrode and the drain electrode of the thin film transistor also include an aluminum metal layer, an aluminum oxide layer, and a molybdenum metal layer which are sequentially stacked.
  • the thin film transistor further includes a gate insulating layer formed on the gate electrode, a semiconductor layer formed on the gate insulating layer, and an ohmic contact layer formed on the semiconductor layer, and the source electrode and the drain electrode are formed on the ohmic contact layer.
  • the liquid crystal display panel, the array substrate and the method for manufacturing the same according to the embodiment of the present invention by adding an aluminum oxide layer in the aluminum metal layer and the molybdenum metal layer for manufacturing the gate electrode, the melting point and hardness of the aluminum oxide are much higher than that of the aluminum. Therefore, the protrusion generated by the deformation of the aluminum metal layer in a high temperature environment can be suppressed, thereby avoiding a short circuit between the gate electrode of the thin film transistor and the source electrode and the drain electrode, thereby ensuring the picture display quality.
  • FIG. 1 is a flow chart showing an embodiment of a method of manufacturing a thin film transistor of the present invention
  • FIG. 2 is a schematic view showing an embodiment of a gate electrode forming a thin film transistor
  • FIG. 3 is a schematic view showing an embodiment of forming a source electrode and a drain electrode of a thin film transistor
  • FIG. 4 is a flow chart showing another embodiment of a method of manufacturing a thin film transistor of the present invention.
  • FIG. 1 is a flow chart showing an embodiment of a method of manufacturing a thin film transistor of the present invention. As shown in FIG. 1, the manufacturing method of the thin film transistor includes the following:
  • Step S11 providing a substrate.
  • the substrate 11 corresponds to an array substrate for forming a liquid crystal display panel, and the substrate 11 may be a glass substrate, a plastic substrate or a flexible substrate.
  • the substrate 11 may further include a substrate sheet and an oxide layer formed on the substrate sheet.
  • the oxide layer includes a silicon nitride (SiNx) layer, a silicon oxide (SiOx) layer, and a combination of the two, the oxide layer is used to prevent impurities in the substrate sheet from diffusing upward in a subsequent process to affect the low temperature polysilicon formed after
  • the quality of the film, silicon nitride layer and silicon oxide layer can be chemical vapor deposition (Chemical Vapor deposition, CVD), plasma chemical vapor deposition
  • the deposition, PECVD) formation may also be carried out by sputtering, vacuum evaporation or low pressure chemical vapor deposition, but is not limited thereto.
  • Step S12 forming a first metal layer on the substrate, the first metal layer including an aluminum metal layer, an aluminum oxide layer, and a molybdenum metal layer which are sequentially stacked.
  • the first metal layer 12 is formed on the substrate 11 by first bombarding the aluminum target with a plasma to sputter aluminum on the substrate 11 (or the above oxide layer) to form an aluminum metal layer. 121; then, when aluminum sputtering is about to be completed, an appropriate amount of oxygen is introduced, so that aluminum is oxidized with oxygen while being sputtered onto the substrate, thereby forming an aluminum oxide layer 122 on the surface of the aluminum metal layer 121; finally, A surface of the aluminum oxide layer 122 forms a molybdenum metal layer 123.
  • the aluminum metal layer 121 and the molybdenum metal layer 123 may be formed on the substrate 11 (or the above oxide layer) by a magnetron sputtering process.
  • Step S13 patterning the first metal layer to form a gate electrode of the thin film transistor.
  • the plurality of gate electrodes 124 of the liquid crystal display panel can be formed by etching the first metal layer 12, wherein the first metal layer 12 can be etched by using an etching solution containing phosphoric acid, nitric acid, acetic acid, and deionized water.
  • etching solution containing phosphoric acid, nitric acid, acetic acid, and deionized water.
  • dry etching can also be used.
  • Step S14 sequentially forming a gate insulating layer, a semiconductor layer, and an ohmic contact layer on the gate electrode.
  • Step S15 forming a second metal layer on the ohmic contact layer.
  • Step S16 patterning the second metal layer to form a source electrode and a drain electrode.
  • a gate insulating layer 125, a semiconductor layer 126, an ohmic contact layer 127, a source electrode 128, and a drain electrode 129 as shown in FIG. 3 are formed on the gate electrode 124 shown in FIG.
  • Step S16 may employ the same or different patterning process as for the first metal layer 12.
  • the method of manufacturing the thin film transistor of the present embodiment by adding an aluminum oxide layer 122 to the aluminum metal layer 121 and the molybdenum metal layer 123 of the gate electrode 124, since the melting point and hardness of the aluminum oxide are much higher than that of the aluminum, it is suppressed.
  • the aluminum metal layer 121 is deformed by deformation in a high temperature environment, thereby avoiding a short circuit between the gate electrode 124, the source electrode 128, and the drain electrode 129 of the thin film transistor, thereby ensuring picture display quality.
  • the method of manufacturing the thin film transistor may further include the following steps:
  • a passivation layer 130 is formed on the source electrode 128 and the drain electrode 129.
  • a contact hole 131 is formed on the passivation layer 130 to expose the drain electrode 129, wherein the contact hole 131 is preferably formed by dry etching.
  • the pixel electrode 132 is formed on the passivation layer 130, and the pixel electrode 132 is electrically connected to the drain electrode 129 through the contact hole 131.
  • the gate electrode 124 of the thin film transistor array is electrically connected to the gate line formed on the substrate 11 (array substrate), and the source electrode 128 of the thin film transistor array is electrically connected to the data line formed on the array substrate, and the gate line is electrically connected.
  • the pixel display area where the pixel electrode 132 is located is formed perpendicularly to the data line.
  • the contact hole 131 may be formed on the passivation layer 130 to expose the source electrode 128, and the pixel electrode 132 is electrically connected to the source electrode 128 through the contact hole 131. At this time, the drain electrode 129 is formed on the array substrate. The upper data line corresponds to the electrical connection.
  • FIG. 4 is a flow chart showing another embodiment of a method of manufacturing a thin film transistor of the present invention.
  • the source electrode 128 and the drain electrode 129 of the thin film transistor are fabricated using the same material as the gate electrode 124, that is, for fabricating the source electrode 128 and the drain electrode.
  • the second metal layer of 129 also includes the aluminum metal layer 121, the aluminum oxide layer 122, and the molybdenum metal layer 123 which are sequentially stacked.
  • the manufacturing method of the thin film transistor of this embodiment includes the following:
  • Step S41 providing a substrate.
  • Step S42 forming a first metal layer on the substrate, the first metal layer including an aluminum metal layer, an aluminum oxide layer, and a molybdenum metal layer which are sequentially stacked.
  • Step S43 patterning the first metal layer to form a gate electrode of the thin film transistor.
  • Step S44 sequentially forming a gate insulating layer, a semiconductor layer, and an ohmic contact layer on the gate electrode.
  • Step S45 forming a second metal layer on the ohmic contact layer, the second metal layer also including an aluminum metal layer, an aluminum oxide layer, and a molybdenum metal layer which are sequentially stacked.
  • Step S46 patterning the second metal layer to form a source electrode and a drain electrode.
  • the embodiment of the present invention further provides an array substrate and a liquid crystal display panel including the thin film transistor obtained by the above manufacturing method, and thus has the same advantageous effects.
  • the liquid crystal display panel, the array substrate, and the thin film transistor manufacturing method thereof increase the aluminum oxide layer in the aluminum metal layer and the molybdenum metal layer of the gate electrode, because of the melting point and hardness of the aluminum oxide. It is much higher than aluminum, so it can suppress the protrusion caused by deformation of the aluminum metal layer under high temperature environment, thereby avoiding short circuit between the gate electrode, the source electrode and the drain electrode of the thin film transistor, thereby ensuring the picture display quality.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种液晶显示面板、阵列基板及其薄膜晶体管的制造方法。所述制造方法包括：提供基体（11）；在基体（11）上形成第一金属层（12），第一金属层（12）包括依次层叠的铝金属层（121）、氧化铝层（122）及钼金属层（123）；对第一金属层（12）进行图案化以形成栅电极（124）；在栅电极（124）上依序形成栅绝缘层（125）、半导体层（126）及欧姆接触层（127）；在欧姆接触层（127）上形成第二金属层；对第二金属层进行图案化以形成源电极（128）和漏电极（129）。能够抑制铝金属层（121）在高温环境下发生变形产生的凸起，避免薄膜晶体管的栅电极（124）与源电极（128）、漏电极（129）之间发生短路，确保液晶显示面板的画面显示质量。

Description

液晶显示面板、阵列基板及其薄膜晶体管的制造方法
【技术领域】
本发明涉及液晶显示技术领域，具体而言，涉及一种液晶显示面板、阵列基板及两者的薄膜晶体管的制造方法。
【背景技术】
薄膜晶体管（Thin Film Transistor，TFT）与像素电极连接，且其栅电极与液晶显示面板的栅极线（gate lines）连接以在接收到栅极驱动信号时开启，其源电极与液晶显示面板的数据线（gate lines）连接以将接收到的灰阶电压传递至像素电极进行画面显示。当前，业界普遍采用铝金属Al和钼金属Mo制造薄膜晶体管，一般为铝金属层的上方设置钼金属层，并且为降低薄膜晶体管的电阻，设计铝金属层的厚度较大，然而由于铝的熔点较低（660℃），制程中所需的高温环境使得铝原子之间相互挤压，铝金属层极易因挤压变形而产生凸起（hillock），所产生的凸起在严重时可以导致薄膜晶体管的栅电极、源电极以及漏电极之间发生短路，从而影响液晶显示面板的画面显示质量。
【发明内容】
鉴于此，本发明实施例提供一种液晶显示面板、阵列基板及其薄膜晶体管的制造方法，能够抑制铝金属层在高温环境下发生变形产生的凸起，确保液晶显示面板的画面显示质量。
本发明采用的一个技术方案是提供一种薄膜晶体管的制造方法。所述制造方法包括：提供一基体；在基体上形成第一金属层，第一金属层包括依次层叠的铝金属层、氧化铝层及钼金属层；对第一金属层进行图案化以形成薄膜晶体管的栅电极；在栅电极上依序形成栅绝缘层、半导体层及欧姆接触层；在欧姆接触层上形成第二金属层；对第二金属层进行图案化以形成薄膜晶体管的源电极和漏电极。
其中，在欧姆接触层上形成第一金属层的步骤包括：采用等离子体轰击铝靶材，以将铝溅射于基体上；通入氧气，使得铝在溅射时发生氧化反应形成氧化铝层；在氧化铝层上形成钼金属层。
其中，第二金属层包括依次层叠的铝金属层、氧化铝层及钼金属层。
其中，所述制造方法还包括：在源电极和漏电极上形成钝化层；在钝化层上形成接触孔以暴露源电极或漏电极；在钝化层上形成像素电极，且像素电极通过接触孔与源电极和漏电极中的一个电连接。
其中，通过干法刻蚀的方式形成接触孔。
其中，基体包括衬底板材以及形成于衬底板材上的氧化层。
本发明采用的另一个技术方案是提供一种阵列基板。所述阵列基板包括基体以及形成于基体上的薄膜晶体管阵列及像素电极，薄膜晶体管的栅电极包括依次层叠的铝金属层、氧化铝层及钼金属层，像素电极通过接触孔与薄膜晶体管的源电极和漏电极中的一个电连接。
其中，薄膜晶体管的源电极和漏电极也包括依次层叠的铝金属层、氧化铝层以及钼金属层。
其中，所述薄膜晶体管还包括形成于栅电极上的栅绝缘层、形成于栅绝缘层上的半导体层、形成于半导体层上的欧姆接触层，源电极和漏电极形成于欧姆接触层上。
本发明采用的又一个技术方案是提供一种液晶显示面板。其阵列基板包括基体以及形成于基体上的薄膜晶体管阵列及像素电极，薄膜晶体管的栅电极包括依次层叠的铝金属层、氧化铝层及钼金属层，像素电极通过接触孔与薄膜晶体管的源电极和漏电极中的一个电连接。
其中，薄膜晶体管的源电极和漏电极也包括依次层叠的铝金属层、氧化铝层以及钼金属层。
其中，所述薄膜晶体管还包括形成于栅电极上的栅绝缘层、形成于栅绝缘层上的半导体层、形成于半导体层上的欧姆接触层，源电极和漏电极形成于欧姆接触层上。
本发明实施例的液晶显示面板、阵列基板及其薄膜晶体管的制造方法，通过在制造栅电极的铝金属层和钼金属层中增加氧化铝层，由于氧化铝的熔点和硬度均远高于铝，因此可抑制铝金属层在高温环境下发生变形产生的凸起，从而避免薄膜晶体管的栅电极与源电极、漏电极之间发生短路，进而确保画面显示质量。
【附图说明】
图1是本发明的薄膜晶体管的制造方法一实施例的流程图；
图2是形成薄膜晶体管的栅电极一实施例的示意图；
图3是形成薄膜晶体管的源电极和漏电极一实施例的示意图；
图4是本发明的薄膜晶体管的制造方法另一实施例的流程图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，本发明以下所描述的实施例仅仅是本发明的一部分实施例，而不是本发明全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本发明所保护的范围。
图1是本发明的薄膜晶体管的制造方法一实施例的流程图。如图1所示，所述薄膜晶体管的制造方法包括以下：
步骤S11：提供一基体。
如图2所示，基体11对应用于形成液晶显示面板的阵列基板，所述基体11可为玻璃基体、塑料基体或可挠式基体。
当然，基体11还可以包括衬底板材及形成于衬底板材上的氧化层。所述氧化层包括氮化硅（SiNx）层、氧化硅（SiOx）层以及两者组合，所述氧化层用于防止衬底板材内的杂质在后续工艺中向上扩散而影响之后形成的低温多晶硅薄膜的品质，氮化硅层和氧化硅层可以采用化学气相沉积（Chemical vapor deposition，CVD）、等离子化学气相沉积（Plasma Enhanced Chemical vapor deposition，PECVD）形成，还可以采用溅射、真空蒸镀或低压化学气相沉积等方法，但不限于此。
步骤S12：在基体上形成第一金属层，所述第一金属层包括依次层叠的铝金属层、氧化铝层以及钼金属层。
结合图2所示，在基体11上形成第一金属层12的方式可以为：首先采用等离子体轰击铝靶材，以将铝溅射于基体11（或者上述氧化层）之上形成铝金属层121；然后，在铝溅射将要完成时，通入适量氧气，使得铝在溅射到基板上的同时与氧气发生氧化反应，从而在铝金属层121的表面形成氧化铝层122；最后，在氧化铝层122的表面形成钼金属层123。其中，本发明实施例可以采用磁控溅射工艺在基体11（或者上述氧化层）之上形成铝金属层121及钼金属层123。
步骤S13：对第一金属层进行图案化以形成薄膜晶体管的栅电极。
具体可通过对第一金属层12进行刻蚀来形成液晶显示面板的多个栅电极124，其中可利用包含有磷酸、硝酸、醋酸以及去离子水的蚀刻液对第一金属层12进行蚀刻，当然也可以采用干法蚀刻。
步骤S14：在栅电极上依序形成栅绝缘层、半导体层及欧姆接触层。
步骤S15：在欧姆接触层上形成第二金属层。
步骤S16：对第二金属层进行图案化以形成源电极和漏电极。
在图2所示的栅电极124上形成如图3所示的栅绝缘层125、半导体层126、欧姆接触层127、源电极128和漏电极129。
步骤S16可采用与对第一金属层12相同或不同的图案化工艺。
本实施例的薄膜晶体管的制造方法，通过在制造栅电极124的铝金属层121和钼金属层123中增加一氧化铝层122，由于氧化铝的熔点和硬度均远高于铝，因此可抑制铝金属层121在高温环境下发生变形产生的凸起，从而避免薄膜晶体管的栅电极124、源电极128以及漏电极129之间发生短路，进而确保画面显示质量。
后续，结合图3所示的实施例，薄膜晶体管的制造方法还可以包括以下步骤：
在源电极128和漏电极129上形成钝化层130。
在钝化层130上形成接触孔131以暴露漏电极129，其中，优选通过干法刻蚀的方式形成接触孔131。
在钝化层130上形成像素电极132，且像素电极132通过接触孔131与漏电极129电连接。另外，薄膜晶体管阵列的栅电极124与形成于基体11（阵列基板）上的栅极线对应电连接，薄膜晶体管阵列的源电极128与形成于阵列基板上的数据线对应电连接，栅极线和数据线垂直交叉形成像素电极132所在的像素显示区域。
在其他实施例中，也可以在钝化层130上形成接触孔131以暴露源电极128，使像素电极132通过接触孔131与源电极128电连接，此时，漏电极129与形成于阵列基板上的数据线对应电连接。
图4是本发明的薄膜晶体管的制造方法另一实施例的流程图。在上述实施例的描述基础上但与之不同的是，本实施例采用与栅电极124相同的材料制造所述薄膜晶体管的源电极128和漏电极129，即用于制造源电极128和漏电极129的第二金属层也包括依次层叠的所述铝金属层121、所述氧化铝层122及所述钼金属层123。
如图4所示，本实施例的所述薄膜晶体管的制造方法包括以下：
步骤S41：提供一基体。
步骤S42：在基体上形成第一金属层，所述第一金属层包括依次层叠的铝金属层、氧化铝层以及钼金属层。
步骤S43：对第一金属层进行图案化以形成薄膜晶体管的栅电极。
步骤S44：在栅电极上依序形成栅绝缘层、半导体层及欧姆接触层。
步骤S45：在欧姆接触层上形成第二金属层，所述第二金属层也包括依次层叠的铝金属层、氧化铝层以及钼金属层。
步骤S46：对第二金属层进行图案化以形成源电极和漏电极。
本发明实施例进一步提供一种包含采用上述制造方法得到的薄膜晶体管的阵列基板以及液晶显示面板，因此具有与其相同的有益效果。
综上所述，本发明实施例的液晶显示面板、阵列基板及其薄膜晶体管的制造方法，通过在制造栅电极的铝金属层和钼金属层中增加氧化铝层，由于氧化铝的熔点和硬度均远高于铝，因此可抑制铝金属层在高温环境下发生变形产生的凸起，从而避免薄膜晶体管的栅电极、源电极以及漏电极之间发生短路，进而确保画面显示质量。
基于此，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (12)

  1. 一种薄膜晶体管的制造方法，其中，所述方法包括：
    提供一基体；
    在所述基体上形成第一金属层，其中所述第一金属层包括依次层叠的铝金属层、氧化铝层及钼金属层；
    对所述第一金属层进行图案化以形成所述薄膜晶体管的栅电极；
    在所述栅电极上依序形成栅绝缘层、半导体层及欧姆接触层；
    在所述欧姆接触层上形成第二金属层；
    对所述第二金属层进行图案化以形成所述薄膜晶体管的源电极和漏电极。
  2. 根据权利要求1所述的方法，其中，所述在所述欧姆接触层上形成第一金属层的步骤包括：
    采用等离子体轰击铝靶材，以将铝溅射于所述基体上；
    通入氧气，使得所述铝在溅射时发生氧化反应形成氧化铝层；
    在所述氧化铝层上形成所述钼金属层。
  3. 根据权利要求1或2所述的方法，其中，所述第二金属层也包括依次层叠的所述铝金属层、所述氧化铝层及所述钼金属层。
  4. 根据权利要求1所述的方法，其中，所述方法还包括：
    在由所述源电极和所述漏电极组成的源漏电极层上形成钝化层；
    在所述钝化层上形成接触孔以暴露所述源电极或所述漏电极；
    在所述钝化层上形成像素电极，且所述像素电极通过所述接触孔与所述源电极和所述漏电极中的一个电连接。
  5. 根据权利要求4所述的方法，其中，通过干法刻蚀的方式形成所述接触孔。
  6. 根据权利要求1所述的方法，其中，所述基体包括衬底板材以及形成于所述衬底板材上的氧化层。
  7. 一种阵列基板，包括基体以及形成于所述基体上的薄膜晶体管阵列及像素电极，其中，所述薄膜晶体管的栅电极包括依次层叠的铝金属层、氧化铝层及钼金属层，所述像素电极通过接触孔与所述薄膜晶体管的源电极和漏电极中的一个电连接。
  8. 根据权利要求7所述的阵列基板，其中，所述源电极和所述漏电极包括依次层叠的所述铝金属层、所述氧化铝层、所述钼金属层。
  9. 根据权利要求7所述的阵列基板，其中，所述薄膜晶体管还包括形成于所述栅电极上的栅绝缘层、形成于所述栅绝缘层上的半导体层、形成于所述半导体层上的欧姆接触层，所述源电极和所述漏电极形成于所述欧姆接触层上。
  10. 一种液晶显示面板，其中，所述液晶显示面板的阵列基板包括基体以及形成于所述基体上的薄膜晶体管阵列及像素电极，所述薄膜晶体管的栅电极包括依次层叠的铝金属层、氧化铝层及钼金属层，所述像素电极通过接触孔与所述薄膜晶体管的源电极和漏电极中的一个电连接。
  11. 根据权利要求10所述的液晶显示面板，其中，所述源电极和所述漏电极包括依次层叠的所述铝金属层、所述氧化铝层、所述钼金属层。
  12. 根据权利要求10所述的液晶显示面板，其中，所述薄膜晶体管还包括形成于所述栅电极上的栅绝缘层、形成于所述栅绝缘层上的半导体层、形成于所述半导体层上的欧姆接触层，所述源电极和所述漏电极形成于所述欧姆接触层上。
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