WO2016138741A1 - 像素结构的制造方法 - Google Patents

像素结构的制造方法 Download PDF

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WO2016138741A1
WO2016138741A1 PCT/CN2015/086497 CN2015086497W WO2016138741A1 WO 2016138741 A1 WO2016138741 A1 WO 2016138741A1 CN 2015086497 W CN2015086497 W CN 2015086497W WO 2016138741 A1 WO2016138741 A1 WO 2016138741A1
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source
drain
photoresist pattern
pixel structure
fabricating
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PCT/CN2015/086497
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English (en)
French (fr)
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金晓涛
谌泽林
欧飞
杨晓峰
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US14/913,475 priority Critical patent/US9818774B2/en
Priority to EP15883792.2A priority patent/EP3267473B1/en
Publication of WO2016138741A1 publication Critical patent/WO2016138741A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Definitions

  • Embodiments of the present invention relate to a method of fabricating a pixel structure.
  • a gate electrode 12, a gate insulating layer 13, a semiconductor layer 17, an ITO (indium tin oxide) layer 14, and a source/drain electrode layer are sequentially formed on the glass substrate 11, and are passed through the photoresist pattern 18.
  • the source and drain electrodes are formed by etching the source and drain electrode layers to form the source 16 and the drain 15 .
  • the source 16 and the drain 15 are structures after the source/drain electrode layer etching process is completed by using the photoresist pattern 18 . .
  • the semiconductor layer 17 is etched by the photoresist pattern 18 to form the channel 19
  • part of the indium is contained when the plasma bombards the ITO due to the blocking of the outer edge of the photoresist pattern 18.
  • the substance 20 remains on both sides of the source 16 and the drain 15, resulting in poor quality of the TFT-LCD; and, due to the blocking of the inner edge of the photoresist 18, the channel 19 formed by etching the semiconductor layer 17 is caused.
  • the width is smaller than the distance between the source 16 and the drain 15, that is, there is a semiconductor step, resulting in a higher leakage current.
  • an embodiment of the present invention provides a method of fabricating a pixel structure, including: forming a gate, a gate insulating layer, an active layer, a pixel electrode layer, and a source/drain electrode layer on a substrate, and using the light Etching the source and drain electrode layers to form a source and a drain; and patterning the photoresist pattern to cause the ashed photoresist pattern to be related to the source and the drain
  • the edges are aligned; the silicon oxide generated when the photoresist pattern is ashed is etched; and the semiconductor layer between the source and the drain is etched by an etching process to form a channel.
  • FIG. 1 is a cross-sectional view showing the structure of a pixel structure in the prior art
  • Figure 2 is a cross-sectional view showing the structure of Figure 1 after forming a channel
  • FIG. 3 is a cross-sectional view of the structure photoresist pattern of FIG. 1 after ashing
  • FIG. 4 is a cross-sectional view of the structure photoresist pattern of FIG. 3 before ashing
  • Figure 5 is a cross-sectional view of the structure of Figure 4 after etching silicon oxide
  • Figure 6 is a cross-sectional view of the structure of Figure 5 after etching the semiconductor layer
  • Figure 7 is a cross-sectional view of the structure of Figure 6 after stripping the photoresist.
  • Embodiments of the present invention provide a method of fabricating a pixel structure, which can solve the problem that residual indium species remain on both sides of the source and drain, and the channel width between the source and the drain is small.
  • the manufacturing method includes:
  • a gate electrode, a gate insulating layer, an active layer, a pixel electrode layer, and a source/drain electrode layer on a substrate for example, a glass substrate, a quartz substrate, or the like
  • a substrate for example, a glass substrate, a quartz substrate, or the like
  • the source and drain electrode layers are etched to form a source and a drain.
  • the photoresist pattern 18 includes a first photoresist pattern 181 and a second photoresist pattern 182 that are independent of each other, wherein the width of the first photoresist pattern 181 after ashing is The widths of the source electrodes 16 are equal such that the structure after the ashing of the first photoresist pattern 181 is aligned with the edge of the source electrode 16; the width of the second photoresist pattern 182 after ashing is equal to the width of the drain electrode 15, To make the first The structure after the ashing of the two photoresist patterns 182 is aligned with the edges of the drain 15.
  • the time for ashing the first photoresist pattern 181 is determined according to the area of the non-overlapping region between the first photoresist pattern 181 and the source 16
  • the time for ashing the second photoresist pattern 182 is determined according to the second The area of the non-overlapping region between the photoresist 182 and the drain 15 is determined.
  • the non-overlapping region between the first photoresist pattern 181 and the source electrode 16 includes a first non-overlapping region 21 and a second non-overlapping region 22, and a second photoresist pattern 182 and a drain electrode 15
  • the non-overlapping regions between the three include a third unoverlapping region 23 and a fourth non-overlapping region 24.
  • the gas of the ashing photoresist pattern 18 is O 2 , or a mixed gas of O 2 and SF 6 , the source RF power is 1000 W to 3000 W, the bias RF power is 500 to 1500 W, and the pressure is 100 to 300 mtorr.
  • the width of the silicon oxide being etched is equal to the distance between the source electrode 16 and the drain electrode 15 such that the edge of the structure after the silicon oxide is etched is opposite to the drain of the source electrode 16 respectively.
  • the source lower edge 25 and drain 15 of the pole 15 are aligned with respect to the drain lower edge 26 of the source 16.
  • the gas generated when the silicon oxide is the ashing photoresist pattern 18 oxidizes the semiconductor layer 17.
  • the source RF power of the etched silicon oxide is 2000 W to 4000 W
  • the bias RF power is 2000 to 4000 W
  • the pressure is 10 to 100 mtorr.
  • the silicon oxide substance is stable, etching is required by high energy, so the etching process selects a higher radio frequency power.
  • the etching process may be a dry etching process.
  • the width of the semiconductor layer 17 is etched to be equal to the distance between the source 16 and the drain 15, so that the edge of the etched structure of the semiconductor layer 17 is opposite to the source 16 respectively.
  • the source lower edge 25 and the drain 15 of the drain 15 are aligned with respect to the drain lower edge 26 of the source 16.
  • the width at which the semiconductor layer 17 is etched is the width of the channel 19.
  • the gas for etching the semiconductor layer between the source and the drain is a mixed gas of He, Cl 2 and SF 6 , the source RF power is 200 W to 1000 W, the bias RF power is 200 W to 1000 W, and the pressure is 100. ⁇ 100mtorr.
  • the channel etching in order to ensure that the channel surface is uniformly flat, the channel etching needs to ensure a lower etching rate, and therefore the channel etching selects lower RF energy.
  • the method further includes: stripping the photoresist covered on the source and the drain pattern.
  • FIG. 7 it is a cross-sectional view of the TFT after the photoresist pattern 18 is peeled off.
  • the width of the etched photoresist pattern can be equal to the width of the source or the drain, thereby avoiding plasma.
  • the body bombards the ITO layer part of the indium-containing material remains on both sides of the source and the drain, thereby improving the quality of the TFT-LCD; and the channel width formed by the etching is equal to the distance between the source and the drain, thereby Semiconductor steps can be avoided to reduce leakage current.
  • the method for fabricating the pixel structure provided by the embodiment of the present invention may be applied to etching the semiconductor layer to form a channel, but is not limited thereto.

Abstract

一种像素结构的制造方法被提供。该制造方法包括：在基板(11)上形成栅极(12)、栅极绝缘层(13)、有源层(17)、像素电极层(14)以及源漏电极层，并利用光刻胶图案(18)刻蚀所述源漏电极层而形成源极(16)和漏极(15)；对所述光刻胶图案(18)进行灰化，以使得灰化后的光刻胶图案(18)与所述源极(16)和所述漏极(15)的边缘均对齐；对灰化所述光刻胶图案(18)时生成的氧化硅进行刻蚀；采用刻蚀工艺刻蚀所述源极(16)和所述漏极(15)之间的半导体层(17)而形成沟道(19)。该制造方法能够消除源极和漏极两侧的残留的含铟物质，且能够解决源极和漏极之间的沟道宽度较小的问题。

Description

像素结构的制造方法 技术领域
本发明的实施例涉及一种像素结构的制造方法。
背景技术
随着薄膜晶体管液晶显示屏(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)等显示器件的高速发展，对TFT-LCD的各项性能要求越来越高。目前，如图1所示，依次在玻璃基板11上形成栅极12、栅极绝缘层13、半导体层17、ITO(氧化铟锡)层14以及源漏电极层，利用光刻胶图案18通过刻蚀工艺而刻蚀源漏电极层而形成源极16、漏极15，其中，此时源极16和漏极15是利用光刻胶图案18完成源漏极电极层刻蚀工艺后的结构。
如图2所示，接下来，利用光刻胶图案18对半导体层17进行刻蚀以形成沟道19时，由于光刻胶图案18外侧边缘的阻挡，导致等离子体轰击ITO时，部分含铟物质20残留在源极16和漏极15的两侧，从而导致TFT-LCD的品质较差；并且，由于光刻胶18内侧边缘的阻挡，导致对半导体层17进行刻蚀形成的沟道19的宽度小于源极16和漏极15之间的距离，即存在半导体台阶，导致漏电流较高。
发明内容
本发明实施例的目的在于提供一种像素结构的制造方法，能够消除源极和漏极两侧的残留含铟物质，且能够解决源极和漏极之间的沟道宽度较小的问题。
一方面，本发明的实施例提供一种像素结构的制造方法，该制造方法包括：在基板上形成栅极、栅极绝缘层、有源层、像素电极层以及源漏电极层，并利用光刻胶图案刻蚀所述源漏电极层而形成源极和漏极；对所述光刻胶图案进行灰化，以使得灰化后的光刻胶图案与所述源极和所述漏极的边缘均对齐；对灰化所述光刻胶图案时生成的氧化硅进行刻蚀；以及采用刻蚀工艺刻蚀所述源极和所述漏极之间的半导体层而形成沟道。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为现有技术中形成像素结构时的结构截面图；
图2为图1中的结构形成沟道后的结构截面图；
图3为图1中的结构光刻胶图案灰化后的截面图；
图4为图3中的结构光刻胶图案灰化前的截面图；
图5为图4中的结构刻蚀氧化硅后的截面图；
图6为图5中的结构刻蚀半导体层后的截面图；
图7为图6中的结构剥离光刻胶后的截面图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种像素结构的制造方法，能够解决在源极和漏极两侧残留含铟物质，以及源极和漏极之间的沟道宽度较小的问题。
该制造方法包括：
301、在基板(例如玻璃基板、石英基板等)上形成栅极、栅极绝缘层、有源层、像素电极层和源漏电极层，并利用源漏极掩模形成的光刻胶图案而刻蚀源漏电极层而形成源极和漏极。
302、对所述光刻胶图案进行灰化，以使得灰化后的光刻胶图案的结构与源极和漏极的边缘均对齐。
可选地，如图3所示，光刻胶图案18包括相互独立的第一光刻胶图案181与第二光刻胶图案182，其中，第一光刻胶图案181灰化后的宽度与源极16的宽度相等，以使得第一光刻胶图案181灰化后的结构与源极16的边缘均对齐；第二光刻胶图案182灰化后的宽度与漏极15的宽度相等，以使得第 二光刻胶图案182灰化后的结构与漏极15的边缘均对齐。
可选地，灰化第一光刻胶图案181的时间根据第一光刻胶图案181与源极16之间未重叠区域的面积确定，灰化第二光刻胶图案182的时间根据第二光刻胶182与漏极15之间未重叠区域的面积确定。如图4所示，第一光刻胶图案181与源极16之间的未重叠区域包括第一未重叠区域21和第二未重叠区域22，第二光刻胶图案182与漏极15之间的未重叠区域包括第三未重叠区域23和第四未重叠区域24。
示例性地，灰化光刻胶图案18的气体为O2，或O2和SF6的混合气体，源射频功率为1000W～3000W，偏置射频功率为500～1500W，压力为100～300mtorr。
303、对灰化光刻胶图案时生成的氧化硅进行刻蚀。
可选地，如图5所示，氧化硅被刻蚀的宽度等于源极16和漏极15之间的距离，以使得氧化硅被刻蚀后的结构的边缘分别与源极16相对于漏极15的源极下边缘25和漏极15相对于源极16的漏极下边缘26对齐。
其中，氧化硅为灰化光刻胶图案18时所生成的气体对半导体层17进行氧化生成。
示例性地，刻蚀氧化硅的源射频功率为2000W～4000W，偏置射频功率为2000～4000W，压力为10～100mtorr。在本发明实施例中，由于氧化硅物质稳定，需要通过高能量进行刻蚀，因此刻蚀工艺选择较高射频功率。
304、采用刻蚀工艺刻蚀源极和漏极之间的半导体层17。
示例性地，所述刻蚀工艺可以为干刻蚀工艺。
可选地，如图6所示，半导体层17被刻蚀的宽度等于源极16和漏极15之间的距离，以使得半导体层17被刻蚀后的结构的边缘分别与源极16相对于漏极15的源极下边缘25和漏极15相对于源极16的漏极下边缘26对齐。其中，半导体层17被刻蚀的宽度即沟道19的宽度。
示例性地，刻蚀源极和漏极之间的半导体层的气体为He、Cl2和SF6的混合气体，源射频功率为200W～1000W，偏置射频功率为200W～1000W，压力为100～100mtorr。在本发明实施例中，为了保证沟道表面均匀平坦，沟道刻蚀需要保证较低的刻蚀速率，因此沟道刻蚀选择较低射频能量。
可选地，步骤304之后，还可以包括：剥离源极和漏极上覆盖的光刻胶 图案。如图7所示，为剥离光刻胶图案18后的TFT剖视图。
本发明实施例提供的像素结构的制造方法，通过对光刻胶图案两侧进行灰化，能够实现灰化后的光刻胶图案的宽度与源极或漏极的宽度相等，从而可以避免等离子体轰击ITO层时，部分含铟物质残留在源极和漏极的两侧，进而可以提高TFT-LCD的品质；且刻蚀形成的沟道宽度等于源极和漏极之间的距离，从而可以避免半导体台阶，进而降低漏电流。
本发明实施例提供的像素结构的制造方法，可以适用于对半导体层进行刻蚀以形成沟道，但不仅限于此。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2015年3月2日递交的中国专利申请第201510093438.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (10)

  1. 一种像素结构的制造方法，包括：
    在基板上形成栅极、栅极绝缘层、有源层、像素电极层以及源漏电极层，并利用光刻胶图案刻蚀所述源漏电极层而形成源极和漏极；
    对所述光刻胶图案进行灰化，以使得灰化后的光刻胶图案与所述源极和所述漏极的边缘均对齐；
    对灰化所述光刻胶图案时生成的氧化硅进行刻蚀；
    采用刻蚀工艺刻蚀所述源极和所述漏极之间的半导体层而形成沟道。
  2. 根据权利要求1所述的像素结构的制造方法，其中所述光刻胶图案包括相互独立的第一光刻胶图案与第二光刻胶图案，其中，所述第一光刻胶图案灰化后的宽度与所述源极的宽度相等，以使得所述第一光刻胶图案灰化后的结构与所述源极的边缘对齐；所述第二光刻胶图案灰化后的宽度与所述漏极的宽度相等，以使得所述第二光刻胶图案灰化后的结构与所述漏极的边缘对齐。
  3. 根据权利要求2所述的像素结构的制造方法，其中灰化所述第一光刻胶图案的时间根据所述第一光刻胶图案与所述源极之间未重叠区域的面积确定，灰化所述第二光刻胶图案的时间根据所述第二光刻胶图案与所述漏极之间未重叠区域的面积确定。
  4. 根据权利要求1所述的像素结构的制造方法，其中灰化所述光刻胶图案的气体为O2，或O2和SF6的混合气体，源射频功率为1000W～3000W，偏置射频功率为500～1500W，压力为100～300mtorr。
  5. 根据权利要求1所述的像素结构的制造方法，其中所述氧化硅为灰化所述光刻胶图案时所生成的气体对所述半导体层进行氧化生成。
  6. 根据权利要求1所述的像素结构的制造方法，其中刻蚀所述氧化硅的源射频功率为2000W～4000W，偏置射频功率为2000～4000W，压力为10～100mtorr。
  7. 根据权利要求1所述的像素结构的制造方法，其中所述氧化硅被刻蚀的宽度等于所述源极和所述漏极之间的距离，以使得所述氧化硅被刻蚀后的结构的边缘分别与所述源极相对于所述漏极的下边缘和所述漏极相对于所述 源极的下边缘对齐。
  8. 根据权利要求1所述的像素结构的制造方法，其中刻蚀所述源极和所述漏极之间的所述半导体层的气体为He、Cl2和SF6的混合气体，源射频功率为200W～1000W，偏置射频功率为200W～1000W，压力为100～100mtorr。
  9. 根据权利要求1所述的像素结构的制造方法，其中所述半导体层被刻蚀的宽度等于所述源极和所述漏极之间的距离，以使得所述半导体层被刻蚀后的结构的边缘分别与所述源极相对于所述漏极的下边缘和所述漏极相对于所述源极的下边缘对齐。
  10. 根据权利要求1所述的像素结构的制造方法，还包括：
    剥离所述源极和所述漏极上覆盖的所述光刻胶图案。
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