WO2016136230A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2016136230A1
WO2016136230A1 PCT/JP2016/000925 JP2016000925W WO2016136230A1 WO 2016136230 A1 WO2016136230 A1 WO 2016136230A1 JP 2016000925 W JP2016000925 W JP 2016000925W WO 2016136230 A1 WO2016136230 A1 WO 2016136230A1
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WO
WIPO (PCT)
Prior art keywords
layer
trench
peak position
insulating film
gate insulating
Prior art date
Application number
PCT/JP2016/000925
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English (en)
Japanese (ja)
Inventor
正清 住友
荻野　誠裕
加藤　之啓
Original Assignee
株式会社デンソー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2016028255A external-priority patent/JP6720569B2/ja
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to CN201680011373.6A priority Critical patent/CN107251231B/zh
Priority to US15/544,898 priority patent/US10103255B2/en
Publication of WO2016136230A1 publication Critical patent/WO2016136230A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to a semiconductor device in which a trench gate type insulated gate bipolar transistor (hereinafter simply referred to as IGBT) is formed.
  • IGBT trench gate type insulated gate bipolar transistor
  • semiconductor devices in which IGBTs are formed are known as semiconductor devices used in electronic equipment such as industrial motors (see, for example, Patent Document 1).
  • a base layer is formed on a surface layer portion of a semiconductor substrate having an N ⁇ type drift layer, and a carrier storage layer (hereinafter simply referred to as a CS layer) is formed between the base layer and the drift layer. ) Is formed.
  • a plurality of trenches are formed so as to penetrate the base layer and the CS layer, and each trench is filled with a gate insulating film formed on the wall surface and a gate electrode formed on the gate insulating film.
  • An N + -type emitter region is formed in the surface layer portion of the base layer so as to be in contact with the trench.
  • a P + -type collector layer is formed on the back side of the semiconductor substrate.
  • An emitter electrode that is electrically connected to the base layer and the emitter region is formed on the front surface side of the semiconductor substrate, and a collector electrode that is electrically connected to the collector layer is formed on the back surface side of the semiconductor substrate.
  • the base layer is in contact with the trench.
  • An N-type inversion layer that is, a channel
  • an electron storage layer is formed in a portion of the drift layer and the CS layer in contact with the trench.
  • the ON voltage can be reduced by the CS layer, there is a problem that the switching controllability at the time of transition from the OFF state to the ON state is deteriorated by forming the CS layer. is there.
  • the off state is a state where no current flows between the collector electrode and the emitter electrode
  • the on state is a state where a current flows between the collector electrode and the emitter electrode.
  • the gate potential when a predetermined voltage is applied to the gate electrode, the gate potential gradually rises, and current starts to flow between the collector electrode and the emitter electrode when the gate potential exceeds the threshold voltage Vth. At this time, the holes supplied to the drift layer are suppressed from coming out of the emitter electrode by the CS layer, and are attracted to the accumulation layer. Since holes are likely to be accumulated near the CS layer, holes are likely to be accumulated in a portion of the accumulation layer located near the CS layer. Since the gate potential fluctuates due to holes accumulated in this portion, switching controllability is degraded.
  • An object of the present disclosure is to provide a semiconductor device capable of suppressing a decrease in switching controllability while reducing an on-voltage.
  • a semiconductor device includes a semiconductor substrate having a first conductivity type drift layer, a second conductivity type base layer formed on the drift layer, the drift layer, and the drift layer formed on the drift layer.
  • a carrier storage layer of a first conductivity type having a higher impurity concentration than the layer a collector layer of a second conductivity type formed on the opposite side of the drift layer from the base layer side; the base layer;
  • the gate insulating film has a thickness of at least a part of a portion of the trench formed on a side surface located on the collector layer side from a peak position where the impurity concentration of the carrier storage layer is highest. It is thicker than the thickness of the portion formed on the side surface located closer to the opening of the trench than the peak position.
  • the above semiconductor device even when carriers are accumulated near the side surface of the trench located near the CS layer when shifting from the off state to the on state, at least a part of the side surface of the trench has a thick gate insulation. Since the film is formed, fluctuation of the gate potential due to carriers can be suppressed in the portion where the gate insulating film is thickened. For this reason, it can suppress that switching control property falls, aiming at reduction of ON voltage.
  • FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment.
  • FIG. 2 is a schematic diagram showing a state in the middle of transition of the semiconductor device from the off state to the on state
  • FIG. 3 is a diagram showing a relationship between voltage and time between a collector electrode and an emitter electrode of a semiconductor device having a uniform gate insulating film thickness
  • 4 is a diagram showing the relationship between the voltage between the collector electrode and the emitter electrode of the semiconductor device shown in FIG. 1 and time
  • FIG. 5 is a cross-sectional view of the semiconductor device according to the second embodiment.
  • FIG. 6 is a cross-sectional view of a semiconductor device according to another embodiment.
  • a first embodiment will be described. Note that the semiconductor device of this embodiment is preferably used as a power switching element used in a power supply circuit such as an inverter or a DC / DC converter.
  • the semiconductor device has an N ⁇ type semiconductor substrate 10 that functions as a drift layer 11.
  • a CS layer 13 having a higher impurity concentration than the P-type base layer 12 and the drift layer 11 is formed on the drift layer 11 (that is, on the one surface 10a side of the semiconductor substrate 10).
  • the CS layer 13 is formed between the drift layer 11 and the base layer 12. That is, on the drift layer 11, the CS layer 13 and the base layer 12 are sequentially arranged from the drift layer 11 side.
  • a plurality of trenches 14 are formed so as to penetrate the base layer 12 and the CS layer 13 and reach the drift layer 11, and the base layer 12 and the CS layer 13 are divided by the plurality of trenches 14.
  • the plurality of trenches 14 are formed at regular intervals in a stripe shape along one direction (that is, the depth direction in the drawing in FIG. 1) of the surface direction of the one surface 10a of the semiconductor substrate 10.
  • the trench 14 is embedded with a gate insulating film 15 formed so as to cover the wall surface of each trench 14 and a gate electrode 16 made of polysilicon or the like formed on the gate insulating film 15.
  • a trench gate structure is configured.
  • the trench gate structure of the present embodiment will be specifically described.
  • the trench 14 forms the opening of the trench 14 and is formed to the middle of the CS layer 13.
  • the trench 14 communicates with the first trench 14 a and reaches the drift layer 11. It is comprised by the trench 14b.
  • the second trench 14b is connected to the first trench 14a at a peak position where the impurity concentration of the CS layer 13 is highest. That is, the first trench 14 a is formed from the one surface 10 a of the semiconductor substrate 10 to the peak position of the CS layer 13.
  • the peak position is indicated by a dotted line.
  • the CS layer 13 is formed by a general semiconductor process, and is formed by performing heat treatment after ion implantation of N-type impurities. For this reason, the peak position of the CS layer 13 is an intermediate position in the stacking direction of the drift layer 11 and the base layer 12. In other words, the peak position of the CS layer 13 is inside the CS layer 13. In other words, it can be said that the peak position of the CS layer 13 is present at a position between the interface between the CS layer 13 and the drift layer 11 and the interface between the CS layer 13 and the base layer 12 in this embodiment.
  • the interval between the opposing side surfaces is longer than the interval between the opposing side surfaces of the first trench 14a. That is, the trench 14 has a so-called bowl shape.
  • the connecting portion between the first trench 14a and the second trench 14b has a curved shape (that is, a rounded shape) and is smoothly connected. Further, although not particularly shown here, the connecting portion between the first trench 14a and the second trench 14b may be steeply changed so as to be substantially perpendicular.
  • the portion formed on the side surface of the second trench 14b is thicker than the portion formed on the side surface of the first trench 14a. That is, the gate insulating film 15 is a portion of the trench 14 formed on the side surface located on the other surface 10b side of the semiconductor substrate 10 (that is, the collector layer 22 side described later) from the peak position of the CS layer 13.
  • the thickness is made thicker than the thickness of the portion formed on the side surface located closer to the opening of the trench 14 than the peak position.
  • the thickness of the portion of the gate insulating film 15 formed on the side surface in contact with the CS layer 13 located on the other surface 10b side of the semiconductor substrate 10 from the peak position in the trench 14 is larger than the peak position. It is thicker than the thickness of the portion formed on the side surface located on the opening side of the trench 14.
  • the portion of the gate insulating film 15 formed on the bottom surface of the second trench 14b is thicker than the portion formed on the side surface of the first trench 14a. That is, all the portions formed on the wall surface of the second trench 14b are thicker than the portions formed on the side surface of the first trench 14a.
  • the gate insulating film 15 has a portion formed on the side surface of the first trench 14a having a thickness of 100 nm and a portion formed in the second trench 14b having a thickness of 200 nm. ing.
  • the gate insulating film 15 formed on the side surface of the trench 14 here is deposited on the side surface of the trench 14 by a CVD method or the like, and is formed on the side surface of the trench 14 by a thermal oxidation method or the like. Is included.
  • the trench gate structure is configured as described above. For this reason, the interval between adjacent trenches 14 is set such that the interval A between adjacent second trenches 14b is shorter than the interval B between adjacent first trenches 14a.
  • an N + type emitter region 17 and a P + type body region 18 sandwiched between the emitter regions 17 are formed.
  • the emitter region 17 is configured to have a higher impurity concentration than the drift layer 11, terminates in the base layer 12, and is in contact with the side surface of the trench 14.
  • the body region 18 has a higher impurity concentration than the base layer 12 and is formed so as to terminate in the base layer 12, similarly to the emitter region 17.
  • the emitter region 17 extends in a rod shape so as to be in contact with the side surface of the trench 14 along the extending direction of the trench 14 in the region between the trenches 14, and terminates inside the tip of the trench 14. It is said that.
  • the body region 18 is extended in a rod shape along the extending direction of the trench 14 while being sandwiched between the two emitter regions 17, and is terminated at the inner side of the tip of the trench 14. Note that the body region 18 of the present embodiment is formed deeper than the emitter region 17 with respect to the one surface 10 a of the semiconductor substrate 10.
  • An interlayer insulating film 19 made of BPSG or the like is formed on one surface 10a of the semiconductor substrate 10, and a contact hole 19a that exposes a part of the emitter region 17 and the body region 18 is formed in the interlayer insulating film 19. Yes.
  • an emitter electrode 20 that is electrically connected to the emitter region 17 and the body region 18 through a contact hole 19a is formed.
  • An N-type field stop layer (hereinafter simply referred to as an FS layer) 21 is formed on the side of the drift layer 11 opposite to the base layer 12 side (that is, the other surface 10b side of the semiconductor substrate 10).
  • this FS layer 21 is not necessarily required, it is possible to improve the breakdown voltage and steady loss performance by preventing the depletion layer from spreading, and to increase the injection amount of holes injected from the other surface 10b side of the semiconductor substrate 10. Be prepared to control.
  • a P + -type collector layer 22 is formed on the opposite side of the drift layer 11 across the FS layer 21, and the collector layer 22 is formed on the collector layer 22 (that is, on the other surface 10 b of the semiconductor substrate 10).
  • a collector electrode 23 to be electrically connected is formed.
  • N + type and N ⁇ type correspond to the first conductivity type
  • P type and P + type correspond to the second conductivity type.
  • the emitter electrode 20 is grounded and a positive voltage is applied to the collector electrode 23. Then, when a predetermined voltage is applied from a gate control circuit (not shown) so that the gate potential of the gate electrode 16 becomes equal to or higher than the threshold voltage Vth of the insulated gate structure, as shown in FIG.
  • An N-type inversion layer (that is, a channel) 31 that connects the emitter region 17, the CS layer 13, and the drift layer 11 is formed at a portion that contacts the trench 14, and a portion of the drift layer 11 and CS13 layer that contacts the trench 14
  • an electron storage layer 32 is formed. Then, electrons are supplied from the emitter region 17 to the drift layer 11 through the inversion layer, and holes are supplied from the collector layer 22 to the drift layer 11. It becomes.
  • the interlayer insulating film 19 and the emitter electrode 20 are omitted.
  • the gate potential of the gate electrode 16 gradually increases according to the voltage applied from the gate control circuit, and when the gate potential becomes equal to or higher than the threshold voltage Vth between the collector electrode 23 and the emitter electrode 20, a current is generated. Start flowing. At this time, the holes supplied to the drift layer 11 are suppressed from coming out of the emitter electrode 20 by the CS layer 13 and are attracted to the storage layer 32. In particular, since holes are likely to be accumulated in the vicinity of the CS layer 13, a large amount of holes are likely to be accumulated in the portion of the accumulation layer 32 that is in contact with the side surface of the second trench 14b.
  • the gate potential of the gate electrode 16 is likely to fluctuate due to holes accumulated in the accumulation layer 32. That is, as shown in FIG. 3, there is a fluctuation in which the voltage between the collector electrode and the emitter electrode sharply increases before the gate potential becomes sufficiently high (that is, the voltage between the collector electrode and the emitter electrode becomes constant). appear. After the gate potential has become sufficiently high, a stable current flows between the collector electrode 23 and the emitter electrode 20, so that there is no problem even if the gate potential is increased by holes.
  • the thickness of the portion formed on the side surface of the second trench 14b in the gate insulating film 15 is made larger than the thickness of the portion formed in the first trench 14a. That is, the gate insulating film 15 in contact with the portion of the storage layer 32 where holes are likely to be stored is thickened. For this reason, as shown in FIG. 4, even if a large amount of holes are accumulated in the accumulation layer 32 near the CS layer 13, it is possible to suppress the gate potential from fluctuating due to the holes. Therefore, when the semiconductor device is turned from the off state to the on state, the voltage between the collector electrode and the emitter electrode becomes sharp before the gate potential becomes sufficiently high (that is, the voltage between the collector electrode and the emitter electrode becomes constant). The rise can be suppressed (that is, the waveform can be gradually reduced), and the switching controllability can be prevented from being lowered.
  • FIG. 3 is a simulation result when the thickness of the gate insulating film 15 is 100 nm
  • FIG. 4 shows the thickness of the portion formed on the side surface of the first trench 14a in the gate insulating film 15. It is a simulation result when the thickness of the part formed in the side surface of 100 nm and the 2nd trench 14b is 200 nm.
  • Rg in FIGS. 3 and 4 indicates the magnitude of the gate resistance. As shown in FIGS. 3 and 4, even when the magnitude of the gate resistance Rg is changed, the basic waveform does not substantially change, although the point in time when the current starts to flow is different.
  • the thickness of the gate insulating film 15 is uniform (that is, FIG. 3), a change in which the voltage between the collector electrode and the emitter electrode rises sharply occurs when switching from the off state to the on state. .
  • the potential barrier is constituted by the CS layer 13 so that the holes are prevented from coming out of the emitter electrode 20, the potential barrier has a particularly large peak position in the CS layer 13. For this reason, holes are likely to concentrate at the peak position of the CS layer 13, and easily accumulate in a portion of the accumulation layer 32 formed particularly near the peak position. That is, holes are most easily accumulated in the portion of the accumulation layer 32 formed in the CS layer 13 located on the collector layer 22 side from the peak position.
  • the gate insulating film 15 is formed such that the portion of the trench 14 formed on the side surface in contact with the CS layer 13 located closer to the collector layer 22 than the peak position is thicker than the peak position. 14 is thicker than the portion formed on the side surface located on the opening side. That is, the gate insulating film 15 is thickened particularly in a portion in contact with the accumulation layer 32 where holes are likely to be accumulated. For this reason, it is possible to effectively suppress the gate potential from rising sharply when switching from the off state to the on state.
  • the portion of the gate insulating film 15 formed on the side surface of the second trench 14b is thicker than the portion formed on the side surface of the first trench 14a. For this reason, even if a large amount of holes are accumulated in the accumulation layer 32 in the vicinity of the CS layer 13, the gate potential can be prevented from fluctuating due to the holes. Therefore, when the semiconductor device is changed from the off state to the on state, it is possible to suppress a fluctuation in which the voltage between the collector electrode and the emitter electrode suddenly increases, and to suppress a decrease in switching controllability (that is, FIG. 4). That is, according to the semiconductor device of this embodiment, it is possible to suppress the switching controllability from decreasing while increasing the impurity concentration of the CS layer 13 and reducing the on-voltage.
  • the gate insulating film 15 has a portion formed on the side surface in contact with the CS layer 13 located on the collector layer 22 side of the peak position in the trench 14 with respect to the peak position. It is thicker than the thickness of the portion formed on the side surface located on the opening side of the trench 14. That is, the gate insulating film 15 is thickened particularly in a portion in contact with the accumulation layer 32 where holes are likely to be accumulated. For this reason, it can suppress more effectively that a gate potential fluctuates.
  • the portion of the gate insulating film 15 formed on the bottom surface of the second trench 14b is also thicker than the portion formed on the first trench 14a. For this reason, holes are likely to be accumulated in the accumulation layer 32 in the vicinity of the CS layer 13, but are also accumulated in a portion that is in contact with a position away from the CS layer 13 (that is, the bottom surface of the second trench 14b). It is also possible to suppress the gate potential from fluctuating due to the accumulated holes.
  • the interval between adjacent trenches 14 is set such that the interval A between adjacent second trenches 14b is shorter than the interval B between adjacent first trenches 14a. For this reason, holes can be accumulated in the drift layer 11 more than when the interval between adjacent trenches 14 is constant at the interval B between the first trenches 14a, and the on-voltage can be further reduced. Can do.
  • the trench 14 has a constant interval between opposing side surfaces in a direction orthogonal to the one surface 10 a of the semiconductor substrate 10. That is, it is composed of only one trench.
  • the gate electrode 16 is connected to the first gate electrode 16 a formed from the opening side of the trench 14 to the peak position, the first gate electrode 16 a at the peak position, and disposed on the bottom surface side of the trench 14.
  • the second gate electrode 16b is configured.
  • the width of the first gate electrode 16a is longer than the width of the second gate electrode 16b.
  • first gate electrode 16a and the second gate electrode 16b are electrically connected.
  • the widths of the first and second gate electrodes 16a and 16b are directions orthogonal to the extending direction of the trench 14 and parallel to the surface direction of the one surface 10a of the semiconductor substrate 10 (that is, FIG. 5 in the left-right direction). That is, also in this embodiment, the gate insulating film 15 is formed on the side surface in contact with the CS layer 13 located on the collector layer 22 side of the peak position in the trench 14 as in the first embodiment.
  • the thickness of the portion is larger than the thickness of the portion formed on the side surface located on the opening side of the trench 14 from the peak position.
  • the gate insulating film 15 has a portion formed on the side surface of the trench 14 on the side of the collector layer 22 with respect to the peak position of the CS layer 13 so that the thickness is larger than the peak position. Since it becomes thicker than the thickness of the part formed in the side surface located in the opening part side of the trench 14, the effect similar to the said 1st Embodiment can be acquired.
  • the first conductivity type is N type and the second conductivity type is P type has been described.
  • the first conductivity type is P type
  • the second conductivity type is N type.
  • the gate insulating film 15 may have a portion formed on the bottom surface of the second trench 14b having a thickness equal to that formed on the side surface of the first trench 14a. That is, the thickness of the portion formed on the bottom surface of the second trench 14b in the gate insulating film 15 may be made thinner than the thickness of the portion formed on the side surface of the second trench 14b.
  • the gate insulating film 15 has a thickness of a portion formed on the bottom surface of the trench 14 in a portion formed on the opening side of the trench 14 with respect to the peak position of the CS layer 13. It may be made equal to the thickness.
  • the gate insulating film 15 is an example in which the portion formed on the side surface of the second trench 14b is entirely thicker than the portion formed on the side surface of the first trench 14a.
  • the gate insulating film 15 is at the thickened portion. Fluctuation of the gate potential can be suppressed.
  • the gate insulating film 15 has a thickness of at least a part of a portion formed on the side surface located on the collector layer 22 side from the peak position where the impurity concentration of the CS layer 13 in the trench 14 is the highest.
  • the gate potential can be prevented from fluctuating in the thickened portion.
  • the gate insulating film 15 has a side surface in which only the thickness of the portion of the trench 14 that is in contact with the drift layer 11 is located closer to the opening of the trench 14 than the peak position. It may be made thicker than the thickness of the part formed in.
  • the gate insulating film 15 has only the thickness of the portion of the trench 14 in contact with the CS layer 13 located on the collector layer 22 side of the peak position. It may be thicker than the thickness of the part formed in the side surface located in the opening part side of the trench 14 rather than.
  • the CS layer 13 divides the base layer 12 into an upper region and a lower region within the base layer 12, not between the drift layer 11 and the base layer 12. It may be formed. That is, the lower region of the base layer 12, the CS layer 13, and the upper region of the base layer 12 may be arranged on the drift layer 11 in order.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur qui est pourvu : d'un substrat semi-conducteur (10) ayant une couche de migration (11) ; d'une couche de base (12) et d'une couche de stockage de porteurs (13), qui se trouvent sur la couche de migration ; d'une couche de collecteur (22) formée sur le côté de la couche de migration opposé au côté couche de base ; d'une pluralité de tranchées (14), qui atteignent la couche de migration par pénétration dans la couche de base et la couche de stockage de porteurs ; d'électrodes de grille (16) formées sur des films d'isolation de grille respectifs dans les tranchées ; d'une zone d'émetteur (17), qui est formée dans une partie de couche de surface de la couche de base et qui est en contact avec les tranchées. L'épaisseur d'au moins une partie d'une partie d'un film d'isolation de grille, qui est formée sur la surface latérale de tranchée positionnée davantage vers le côté couche de collecteur qu'une position de crête où la concentration en impuretés de la couche de stockage de porteurs est la plus forte, est supérieure à l'épaisseur d'une partie du film d'isolation de grille formée sur la surface latérale de tranchée positionnée davantage vers le côté ouverture de tranchée que la position de crête.
PCT/JP2016/000925 2015-02-25 2016-02-22 Dispositif à semi-conducteur WO2016136230A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201680011373.6A CN107251231B (zh) 2015-02-25 2016-02-22 半导体装置
US15/544,898 US10103255B2 (en) 2015-02-25 2016-02-22 Semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2015-035360 2015-02-25
JP2015035360 2015-02-25
JP2016028255A JP6720569B2 (ja) 2015-02-25 2016-02-17 半導体装置
JP2016-028255 2016-02-17

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WO2016136230A1 true WO2016136230A1 (fr) 2016-09-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018082010A (ja) * 2016-11-15 2018-05-24 株式会社デンソー 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7910439B2 (en) * 2008-06-11 2011-03-22 Maxpower Semiconductor Inc. Super self-aligned trench MOSFET devices, methods, and systems
JP2012080074A (ja) * 2010-09-08 2012-04-19 Denso Corp 半導体装置
JP2012216675A (ja) * 2011-03-31 2012-11-08 Toyota Motor Corp 半導体装置及びその製造方法
JP2014197702A (ja) * 2010-12-08 2014-10-16 株式会社デンソー 絶縁ゲート型半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7910439B2 (en) * 2008-06-11 2011-03-22 Maxpower Semiconductor Inc. Super self-aligned trench MOSFET devices, methods, and systems
JP2012080074A (ja) * 2010-09-08 2012-04-19 Denso Corp 半導体装置
JP2014197702A (ja) * 2010-12-08 2014-10-16 株式会社デンソー 絶縁ゲート型半導体装置
JP2012216675A (ja) * 2011-03-31 2012-11-08 Toyota Motor Corp 半導体装置及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018082010A (ja) * 2016-11-15 2018-05-24 株式会社デンソー 半導体装置

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