WO2016127645A1 - 封装方法及封装结构 - Google Patents

封装方法及封装结构 Download PDF

Info

Publication number
WO2016127645A1
WO2016127645A1 PCT/CN2015/090085 CN2015090085W WO2016127645A1 WO 2016127645 A1 WO2016127645 A1 WO 2016127645A1 CN 2015090085 W CN2015090085 W CN 2015090085W WO 2016127645 A1 WO2016127645 A1 WO 2016127645A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
adhesive layer
layer
forming
package structure
Prior art date
Application number
PCT/CN2015/090085
Other languages
English (en)
French (fr)
Inventor
王之奇
喻琼
王蔚
Original Assignee
苏州晶方半导体科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州晶方半导体科技股份有限公司 filed Critical 苏州晶方半导体科技股份有限公司
Priority to JP2017542891A priority Critical patent/JP2018505564A/ja
Priority to KR1020177024914A priority patent/KR20170108161A/ko
Priority to US15/549,987 priority patent/US10529758B2/en
Publication of WO2016127645A1 publication Critical patent/WO2016127645A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14698—Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a wafer level packaging method and a package structure of an image sensing chip.
  • Wafer Level Chip Size Packaging technology is a technology that performs a package test on a whole wafer and then cuts a single finished chip package.
  • the size of the packaged chip package is the same as that of the die.
  • Wafer-level chip-scale packaging technology changes the traditional packaging such as Ceramic Leadless Chip Carrier, Organic Leadless Chip Carrier and digital camera modular mode, which is in line with the market for microelectronics Products are increasingly light, small, short, thin and low-cost.
  • the chip size packaged by wafer level chip size packaging technology is highly miniaturized, and the chip cost is significantly reduced as the chip size decreases and the wafer size increases.
  • Wafer-level chip-scale packaging technology is a technology that integrates IC design, wafer fabrication, package testing, and substrate manufacturing. It is a hot spot and future development trend in the current packaging field.
  • a cover substrate is usually covered on the side of the semiconductor wafer on which the device is formed to protect the device from damage and contamination during the packaging process. Play a protective role.
  • the substrate 10 includes a sensing region 20 formed on the substrate 10, and a pad 21 is formed on the substrate 10 on both sides of the sensing device.
  • the other side surface of the substrate 10 opposite to the sensing region 20 is formed with a through hole exposing the pad 21, the via sidewall and the surface of the substrate 10 having an insulating layer 11, a pad 21 and
  • the surface of the portion of the insulating layer 11 has a wiring layer 12 which is covered by a solder resist layer 13 having an opening having solder balls 14 connecting the wiring layers 12.
  • One side surface of the substrate 10 having the sensing region 20 is covered by the upper cover substrate 30, and the upper cover substrate 30 and the surface of the substrate 10 have a cavity wall 31, the cavity wall 31 and the upper cover substrate 30.
  • a cavity is formed between the substrates 10 such that the sensing region 20 is located within the cavity to prevent contamination and damage to the device.
  • the thickness of the upper cover substrate 30 is generally large, generally about 400 ⁇ m, to meet the process requirements, which makes the chip package formed by the wafer after the package is thicker, and the module on the subsequent chip package
  • the overall thickness is also too thick to meet the market's growing demand for electronic products.
  • the upper cover substrate of the wafer surface after the package is completed is removed (please refer to FIG. 2), so that the sensing region 20 is exposed, although the thickness of the wafer package is decreased, the sensing region 20 is It is susceptible to contamination and damage, which affects the overall performance of the package structure.
  • the problem to be solved by the present invention is to provide a packaging method and a package structure for reducing the thickness of the package structure.
  • the present invention provides a packaging method comprising:
  • first substrate and a second substrate having a first surface and a second surface opposite the first surface, passing any surface of the first substrate and the first surface of the second substrate Adhesive layer bonding;
  • the second surface of the second substrate is pressed against the first surface of the substrate, and the groove structure forms a cavity with the substrate such that the sensing region is located within the cavity.
  • the method further includes: after the second surface of the second substrate is pressed against the first surface of the substrate, performing a packaging process on the second surface of the substrate; removing the first substrate and the adhesive layer.
  • the encapsulating treatment on the second surface of the substrate comprises: thinning and etching the second surface of the substrate to form a through hole, the bottom portion of the through hole exposing a part of the surface of the bonding pad; a second surface and a sidewall surface of the via hole form an insulating layer; a metal layer connecting the pads is formed on the surface of the insulating layer; and a solder resist layer having an opening is formed on the surface of the metal layer and the surface of the insulating layer, the opening A portion of the surface of the metal layer is exposed; an external protrusion is formed on the surface of the metal layer.
  • the metal layer fills the through hole and the surface is flush with the second surface of the substrate; the opening in the solder resist layer exposes a top surface of the metal layer; forming a connecting metal layer in the opening An external projection on the top surface.
  • the first substrate has a thickness of 300 ⁇ m to 500 ⁇ m.
  • the second substrate has a thickness of 100 ⁇ m to 200 ⁇ m.
  • the method of bonding one side surface of the first substrate and the first surface of the second substrate by an adhesive layer comprises: forming an adhesive layer on one side surface of the first substrate, and then The first surface of the second substrate is laminated with the adhesive; or an adhesive layer is formed on the first surface of the second substrate, and then any surface of the first substrate is laminated with the adhesive.
  • the adhesive layer comprises a first adhesive layer and a second adhesive layer.
  • the method of bonding the one surface of the first substrate and the first surface of the second substrate by an adhesive layer comprises: forming a first adhesive layer on one side surface of the first substrate, and second Forming a second adhesive layer on the first surface of the substrate, or forming a second adhesive layer on one side surface of the first substrate, forming a first adhesive layer on the first surface of the second substrate; and then the first substrate And the second substrate is laminated through the first adhesive layer and the second adhesive.
  • the adhesive layer can be formed by a spray coating, spin coating or pasting process.
  • the first adhesive layer is a laser irradiation decomposing adhesive layer
  • the laser irradiation decomposition method is used. Treating the adhesive layer to remove the adhesive layer to remove the first substrate; or
  • the adhesive layer is a heat-decomposable adhesive layer
  • the adhesive layer is treated by a thermal decomposition method to lose the viscosity of the adhesive layer to remove the first substrate.
  • the adhesive layer on the surface of the second substrate may be removed by cleaning the surface of the second substrate.
  • the method for forming the groove structure comprises:
  • the substrate comprises a plurality of cells, each of the cells corresponding to the sensing region and a plurality of pads around the sensing region; the adjacent cells have a scribe line; the second substrate is not pressed against the first substrate
  • the groove structure formed on the other side surface has a plurality of grooves respectively corresponding to the plurality of sensing regions on the plurality of cells; after removing the first substrate and the adhesive layer, the substrate and the first substrate along the scribe line Cutting is performed to form a plurality of chip packages.
  • an embodiment of the present invention provides a package structure, including:
  • first substrate and a second substrate having a first surface and a second surface opposite to the first surface, and any surface of the first substrate and the first surface of the second substrate pass the adhesive Layer bonding
  • a substrate having a first surface and a second surface opposite the first surface, the first surface of the substrate having a sensing region and a plurality of pads located around the sensing region;
  • the second surface of the second substrate is pressed against the first surface of the substrate, the groove structure forms a cavity with the substrate, and the sensing region is located in the cavity.
  • the material of the first substrate is glass, silicon wafer, ceramic or plastic.
  • the first substrate has a thickness of 300 ⁇ m to 500 ⁇ m.
  • the material of the second substrate is a light transmissive material.
  • the second substrate has a thickness of 100 ⁇ m to 200 ⁇ m.
  • the adhesive layer comprises a first adhesive layer and a second adhesive layer.
  • the first adhesive layer is located on the first substrate surface, and the second adhesive layer is located on the first surface of the second substrate; or the second adhesive layer is located on the first substrate surface, the first An adhesive layer is on the first surface of the second substrate.
  • the adhesive layer is a laser irradiation decomposition type adhesive layer; or the adhesive layer is a heat decomposition type adhesive layer.
  • the groove structure comprises:
  • the substrate comprises a plurality of cells, each of the cells correspondingly forming a sensing region and a plurality of pads around the sensing region; a cutting channel between adjacent cells; and the second substrate is not pressed with the first substrate
  • the groove structure of the other side surface of the joint has a plurality of grooves respectively corresponding to a plurality of sensing regions on a plurality of units.
  • the package structure further includes: a through hole in the second surface of the substrate, the bottom portion of the through hole exposing a part of the surface of the pad; and the insulation on the second surface of the substrate and the sidewall surface of the through hole a layer; a metal layer on the surface of the insulating layer connecting the pads; a solder resist layer on the surface of the metal layer and having an opening on the surface of the insulating layer, the opening exposing a portion of the surface of the metal layer; and an external connection on the surface of the metal layer Raised.
  • the metal layer fills the through hole and the surface is flush with the surface of the insulating layer; the opening in the solder resist layer exposes a top surface of the metal layer; and a top of the connecting metal layer is formed in the opening The external protrusion of the surface.
  • an embodiment of the present invention further provides a package structure, including:
  • a substrate having a first surface and a second surface opposite the first surface
  • a substrate having a first surface and a second surface opposite the first surface, the first surface of the substrate having a sensing region and a plurality of pads located around the sensing region;
  • the second surface of the substrate is pressed against the first surface of the substrate, the groove structure and the substrate form a cavity, and the sensing area is located in the cavity;
  • the substrate has a thickness of 100 ⁇ m to 200 ⁇ m.
  • the package structure includes a first substrate and a second substrate, and one side surface of the first substrate and the first surface of the second substrate are adhered by an adhesive layer a groove structure on the second surface of the second substrate; a second surface of the second substrate is pressed against the first surface of the substrate, and the groove structure forms a cavity with the substrate, so that A sensing area on the substrate is located within the cavity.
  • the first substrate and the second substrate form a double-layered upper cover substrate structure, which facilitates subsequent removal of the first substrate therein and reduces the thickness of the formed package structure. There is no need to use a process such as etching or grinding to reduce the thickness of the upper cover substrate, thereby ensuring the thickness of the package structure while ensuring that the surface of the remaining second substrate is flat, which can protect the sensing area.
  • 1 to 2 are schematic cross-sectional structural views of a prior art package structure of the present invention
  • 3 to 13 are schematic structural views showing a process of forming a package structure according to an embodiment of the present invention.
  • the thickness of the upper cover substrate of the package structure is large, which cannot meet the market demand for an increasingly thinner electronic product.
  • the package The upper cover substrate of the structure is required to have high light transmittance. If the upper cover substrate is thinned by a grinding process or an etching process, the surface of the upper cover substrate becomes rough, which affects the penetration of the upper cover substrate. Light, and the process is complex and the cost is high. The removal of the upper cover substrate, while reducing the thickness of the package structure, affects the performance of the package structure.
  • the double-layer substrate formed by pressing the first substrate and the second substrate is used as the upper cover substrate of the package structure, so that the first substrate having a larger thickness can be removed after the package structure is formed.
  • the thickness of the package structure is reduced, and the second substrate can still protect the device from being affected by the performance of the package structure.
  • a first substrate 100 is provided.
  • the material of the first substrate 100 may be glass, silicon wafer, ceramic or plastic.
  • the first substrate 100 is used as a part of a double-layered upper cover substrate of a subsequently formed package structure for protecting a sensing area of a subsequently provided substrate surface to be packaged.
  • the material of the first substrate 100 is a hard material. High strength and corrosion resistance, can withstand external stresses and various chemical contaminations in subsequent packaging processes.
  • the light-transmitting or opaque material can be used as the material of the first substrate 100 without affecting the performance of the package structure.
  • the thickness of the first substrate 100 is 300 ⁇ m to 500 ⁇ m, so that the first substrate 100 has sufficient thickness and strength to meet the needs of subsequent fabrication.
  • a second substrate 200 is provided, the second substrate 200 having a first surface 200a and a second surface 200b opposite the first surface 200a.
  • the second substrate 200 has a high light transmissivity and is a light transmissive material, and the surface of the second substrate 200 is flat and smooth, and does not cause scattering, diffuse reflection, or the like on the incident light, thereby ensuring the The two substrates 200 have high light transmittance.
  • the subsequently provided substrate to be packaged includes a sensing area, and the sensing area is an optical sensing area.
  • the second substrate 200 is finally retained in the package structure, is located above the optical sensing area, and is selected from a light-transmitting material. The material of the second substrate 200 facilitates light to be transmitted through the second substrate 200 to the optical sensing region.
  • the material of the second substrate 200 may be inorganic glass or organic glass.
  • the area and shape of the second substrate 200 are the same as the area and shape of the first substrate 100 (please refer to FIG. 4 ), so that after the second substrate 200 and the first substrate 100 are subsequently pressed together, the second substrate 200 and The first substrates 100 can be completely overlapped.
  • the second substrate 200 has a thickness of 100 ⁇ m to 200 ⁇ m. Since the second substrate 200 is finally retained in the package structure, the thickness of the second substrate 200 cannot be excessively large, otherwise the thickness of the package structure may not meet the thinning requirements of the electronic product. The thickness of the second substrate 200 is not too small. If the thickness of the second substrate 200 is less than 100 ⁇ m, the strength of the second substrate 200 is weak, the external stress that can be withstood is reduced, and the chipping is prone to occur. It is impossible to adequately protect the sensing area in the package structure, which may easily cause the failure of the package structure.
  • the second substrate 200 has two surfaces, and any one of the surfaces may be selected as the first surface 200a, and correspondingly, a surface corresponding to the first surface 200a serves as the second surface 200b.
  • the second substrate 200 and the first substrate 100 are bonded by an adhesive layer to form a double-layer upper cover substrate.
  • FIG. 5 to FIG. 6 a schematic structural view of the second substrate 200 (please refer to FIG. 4 ) and the first substrate 100 (please refer to FIG. 3 ) are bonded through an adhesive layer in this embodiment.
  • an adhesive layer 101 is formed on either surface of the first substrate 100.
  • the adhesive layer 101 may be formed on either side of the first substrate 100.
  • the adhesive layer 101 has adhesiveness for pressing the first substrate 100 and the subsequently provided second substrate into a single body to form a double-layered upper cover substrate structure.
  • the material of the adhesive layer 101 may be a polymer material, and may be, for example, an epoxy resin, a polyimide resin, a benzocyclobutene resin, a polybenzoxazole resin, a polybutylene terephthalate, Polymeric materials such as polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, or polyvinyl alcohol.
  • the adhesive layer 101 may be formed by a spraying, spin coating or pasting process to form a uniform thickness adhesive layer 101 on one side surface of the first substrate 100, and to flatten the surface of the adhesive layer 101. .
  • the first substrate 100 and the second substrate are pressed together to form a double-layer upper cover substrate, and after the package is completed, the first substrate 100 can be smoothly peeled off from the second substrate, the adhesive layer 101
  • the material may be a thermally decomposable adhesive layer.
  • the adhesive layer 101 is subjected to heat treatment to decompose the material of the adhesive layer 101, so that the viscosity of the adhesive layer 101 disappears, and the first substrate 101 is peeled off.
  • any surface of the first substrate 100 and the first surface 200a of the second substrate 200 are bonded by an adhesive layer 101.
  • the first surface 200a of the second substrate 200 is pressed against the adhesive layer 101 on the surface of the first substrate 100, so that the first substrate 100 and the second substrate 200 are pressed together to form an integral body.
  • a double-layered upper cover substrate since the first substrate 100 and the second substrate 200 are bonded by the adhesive layer 101, the first substrate 100 and the second substrate 200 are easily separated later.
  • the first substrate 100 and the second substrate 200 are pressed together to form a double-layered upper cover substrate, so that the upper cover substrate has a sufficient thickness to satisfy the thickness of the upper cover substrate in the subsequent packaging process. And strength requirements.
  • any surface of the first substrate 100 may be pressed together to make the first substrate 100.
  • the second substrate 200 is bonded to the second substrate 200 by the adhesive layer 101 to form a double-layered upper cover substrate.
  • another method for bonding the second substrate and the first substrate through an adhesive layer to form a double-layer upper cover substrate including: on the first substrate 100 (please Forming a first adhesive layer with reference to any surface of FIG. 3), forming a second adhesive layer on the first surface 200a of the second substrate 200 (please refer to FIG. 4) (please refer to FIG. 4), or on the first substrate Forming a second adhesive layer on any surface of 100, forming a first adhesive layer on the first surface 200a of the second substrate 200; then passing the first substrate 100 and the second substrate 200 through the first adhesive layer
  • the second adhesive layer is laminated, and the first adhesive layer and the second adhesive layer constitute an adhesive layer that bonds the first substrate 100 and the second substrate 200.
  • the material of the first adhesive layer and the second adhesive layer may be a polymer material, and may be, for example, an epoxy resin, a polyimide resin, a benzocyclobutene resin, a polybenzoxazole resin, a poly pair.
  • a polymer material such as an alcohol.
  • the first adhesive layer and the second adhesive layer may be formed by a spray coating, a spin coating or a pasting process.
  • the first adhesive layer in the adhesive layer may be irradiated with a laser-disassembled adhesive layer, and the second adhesive layer may be any adhesive. Polymer material. Subsequently, the first adhesive layer is decomposed by laser irradiation to lose the viscosity, and the first substrate 100 and the second substrate 200 are separated.
  • first adhesive layer having a lower thickness may be used, for example, the thickness of the first adhesive layer is less than 3 microns, in particular, the first adhesive layer may have a thickness of 0.2 micron to 0.9 micron, or 1.1 micron to 2 micron.
  • the viscosity of the adhesive layer is increased to prevent the first substrate 100 and the second substrate 200 from separating during the subsequent packaging process.
  • the first adhesive layer and the second adhesive layer may also be thermal decomposition type adhesive layers, which may be subsequently subjected to heat decomposition treatment to make the first adhesive layer and the first adhesive layer The two adhesive layers lose their tackiness.
  • a groove structure is formed on the second surface 200b of the second substrate 200.
  • the groove structure comprises: a cavity wall material layer 201 on the second surface 200b of the second substrate 200; and a groove 202 located in the cavity wall material layer 201.
  • the forming method of the groove structure includes: forming a complete cavity wall material layer 201 on the second surface of the second substrate 200, and etching the cavity wall material layer 201 to the surface of the second substrate 200, a groove 202 is formed in the cavity wall material layer 201.
  • the groove position The position corresponds to the position of the sensing area on the subsequently provided substrate.
  • the depth of the groove 202 is greater than the height of the device in the sensing region on the subsequently provided substrate.
  • the material of the cavity wall material layer 201 is a photoresist, and the cavity wall material layer 201 may be formed on the second surface 200b of the second substrate 200 by a spraying, spin coating or adhesive process. Then, the cavity wall material layer 201 is exposed and developed to form the groove 202.
  • the material of the cavity wall material layer 201 may also be an insulating dielectric material such as silicon oxide, silicon nitride, silicon oxynitride or the like, and the cavity wall material layer 201 is formed by a deposition process. And the cavity wall material layer 201 is dry etched to form a recess 202 in the cavity wall material layer 201.
  • the groove structure may include a groove located in the second surface 200b of the second substrate 200.
  • the method for forming the groove structure includes: etching a second surface 200b of the second substrate 200, and forming a groove in the second substrate 200.
  • the second substrate 200 may be etched by a dry etching process to form the recess.
  • a substrate 300 having a first surface 401 and a second surface 402 opposite to the first surface 401 is provided.
  • the first surface 401 of the substrate 300 has a sensing area 301 and is located in the sensing area.
  • the substrate 300 is a wafer, including a sensing region 301 on the first surface 401, a plurality of discretely arranged pads 302 around the sensing region 301, a functional region (not shown), and a silicon substrate.
  • the sensing area 301 is an optical sensing area, and the pad 302 serves as an input/output terminal for connecting devices in the sensing area 301 to an external circuit.
  • Figure 8 is a schematic cross-sectional view of a substrate having a sensing region.
  • the substrate 300 may include a plurality of cells, each of which is formed with a sensing region 301 and a plurality of pads 302 located around the sensing region 301; After the package is completed, the dicing is performed to form a plurality of chip packages.
  • the second surface 200b of the second substrate 200 is pressed against the first surface 401 of the substrate 300, and the groove 202 (refer to FIG. 8) and the substrate 300 form a cavity.
  • the sensing zone 301 is located within the cavity.
  • an adhesive layer is formed on the surface of the cavity wall material layer 201 on the second surface 200b of the second substrate 200 to be pressed against the substrate 300, and the adhesive layer may be a polymer bonding material.
  • a polymer material such as silica gel, epoxy resin or benzocyclobutene can be formed by spraying, spin coating or pasting.
  • the adhesive layer can achieve both bonding and insulation and sealing.
  • the second surface 200b of the second substrate 200 is pressed against the first surface 401 of the substrate 300, and the cavity wall material layer 201, the second substrate 200, and the substrate 300 form a cavity, and the cavity position Corresponding to the sensing region 301 formed on the first surface 401 of the substrate 300, the sensing region 301 is located in the cavity, and the pad 302 around the sensing region 301 is located outside the cavity, and the substrate 300 is empty. Between the walls of the cavity wall material 201.
  • the sensing area 301 is located in the cavity, and is protected by the first substrate 100, the second substrate 200, and the cavity wall material layers 201 on both sides in a subsequent packaging process, thereby preventing the sensing area 301 from being subjected to Damage and pollution.
  • the second substrate 200 has a recess therein, and a side surface of the second substrate 200 having the recess may be formed into an adhesive layer to directly press the first surface 401 of the substrate 300.
  • a cavity is formed between the second substrate 200 and the substrate 300 such that the sensing region 301 is located in the cavity.
  • the second surface 200b of the second substrate 200 is pressed against the first surface 401 of the substrate 300, the second surface 402 of the substrate 300 is subjected to a packaging process.
  • the packaging process of the embodiment includes:
  • the second surface 402 of the substrate 300 is thinned to reduce the thickness of the substrate 300, and may be thinned by an etching or chemical mechanical polishing process to facilitate subsequent formation of via holes in the substrate 300.
  • the second surface 402 of the substrate 300 is then etched to form a via in the substrate 300, the bottom of the via exposing a portion of the surface of the pad 302, the via being used to form the metal connecting the pads 302 Connection structure.
  • An insulating layer 311 is formed on the second surface 402 of the substrate 300 and the sidewall surface of the through hole.
  • the material of the insulating layer 311 may be an insulating dielectric material such as silicon oxide or silicon nitride for forming the substrate 300 and subsequent layers.
  • the metal layer is insulated; and a metal layer 312 connecting the pads 302 is formed on the surface of the insulating layer 311, and the metal layer 312 is electrically connected to the pad 302.
  • a solder resist layer 313 having an opening is formed on the surface of the metal layer 312 and the surface of the insulating layer 311.
  • the material of the solder resist layer 313 is an insulating dielectric material such as silicon oxide or silicon nitride for protecting the metal layer 312.
  • the opening exposes a portion of the surface of the metal layer 312 to facilitate subsequent formation of solder joints on the surface of the metal layer 312.
  • the external protrusion 314 is formed on the surface of the metal layer 312.
  • the external protrusion 314 may be a connection structure such as a solder ball or a metal pillar, and a metal material such as copper, aluminum, gold, tin or lead may be used.
  • the packaging process includes: after thinning the second surface 402 of the substrate 300 , the second surface 402 of the substrate 300 Etching, forming a via hole in the substrate 300, the bottom portion of the via hole exposing a portion of the surface of the pad 302; forming an insulating layer 303 on the second surface 402 of the substrate 300 and the sidewall surface of the via hole;
  • the surface of the insulating layer 303 forms a metal layer 304 connecting the pads 302, the metal layer 304 fills the through holes and the surface of the metal layer is flush with the surface of the insulating layer 303; the surface of the metal layer 304 and the insulation
  • a surface of the layer 303 is formed with a solder resist layer 305 having an opening, the opening in the solder resist layer 305 exposing a top surface of the metal layer 304; and an external bump 306 connecting the top surface of the metal layer 304 is formed in the opening,
  • the external bump 306 connecting the top surface of the metal layer 304 is formed in the opening,
  • the first substrate 100 please refer to FIGS. 10 and 11
  • the adhesive layer 101 (refer to FIGS. 10 and 11) are removed.
  • 12 and 13 correspond to the structures formed by the two embodiments of the above package processing, respectively.
  • a package structure is formed, but the thickness of the upper cover substrate on the first surface 401 of the substrate 300 of the package structure is large, and the first substrate 100 is removed.
  • the thickness of the upper cover substrate on the first surface 401 of the substrate 300 can be lowered, and the remaining second substrate 200 can still protect the sensing region 301 on the substrate 300.
  • the adhesive layer 101 between the first substrate 100 and the second substrate 200 is thermally decomposed.
  • the adhesive layer can decompose the material of the adhesive layer 101 and lose its viscosity under heating. Therefore, in this embodiment, the adhesive layer 101 is treated by a thermal decomposition method to make the adhesive layer 101 lose its viscosity, so that the first substrate is detached from the surface of the adhesive layer 101 to remove the first Substrate 100.
  • the heating temperature is lower than the melting point of the external protrusion 314 to avoid affecting the performance of the package structure.
  • the adhesive layer between the first substrate 100 and the second substrate 200 includes a first adhesive layer and a second adhesive layer, and the first adhesive layer is laser irradiated.
  • the adhesive layer may be treated by a laser irradiation decomposition method to decompose the material of the first adhesive layer to lose viscosity.
  • the laser irradiation decomposition method may use a yttrium aluminum garnet laser having a wavelength of 1064 nm and an output power of 15 W to 40 W.
  • lasers of other wavelengths, such as ultraviolet wavelength lasers may also be used. Irradiation is performed.
  • the adhesive layer 101 includes a first adhesive layer and a second adhesive layer, and the first adhesive layer and the second adhesive layer are both thermally decomposable adhesive layers.
  • the adhesive layer may be treated by a thermal decomposition method to lose the viscosity of both the first adhesive layer and the second adhesive layer, thereby separating the first substrate 100 and the second substrate 200.
  • the first substrate 100 is removed by a wet or dry etching process, it is easy to affect the materials and devices of other parts of the package structure, and the above method can avoid the above effects.
  • the surface of the second substrate 200 may be cleaned to remove the adhesive layer 101 remaining on the surface of the second substrate 200 to expose the surface of the second substrate 200.
  • the cleaning agent used in the cleaning process does not cause corrosion to the second substrate 200, thereby not affecting the flatness and light transmittance of the surface of the second substrate 200.
  • the thickness of the first substrate 100 is large, after the first substrate 100 is removed, the thickness of the formed package structure is lowered, and the remaining second substrate 200 can still protect the sensing area, thereby ensuring The performance of the package structure is not affected by the outside world.
  • the first substrate and the second substrate are bonded by an adhesive layer, and then a groove structure is formed on the second surface of the second substrate or inside the second substrate, and is first with the substrate.
  • the surface is pressed, and the groove structure forms a cavity with the substrate such that the sensing area of the surface of the substrate is located in the cavity.
  • the first substrate and the second substrate form a double-layered upper cover substrate structure, and after being pressed against the substrate, the sensing area on the substrate can be protected in a subsequent packaging process.
  • the upper cover substrate is a double junction The structure facilitates subsequent removal of the first substrate therein, reducing the thickness of the formed package structure.
  • a package structure formed by the above method is also provided.
  • the package structure includes: a first substrate 100 and a second substrate 200, the second substrate 200 having a first surface 200a and a second surface 200b opposite to the first surface 200a, Any surface of the first substrate 100 and the first surface 200a of the second substrate 200 are bonded by the adhesive layer 101; a groove structure of the second surface 200b of the second substrate 200; the substrate 300, the The substrate 300 has a first surface 401 and a second surface 402 opposite to the first surface 401.
  • the first surface 401 of the substrate 300 has a sensing area 301 and a plurality of pads 302 around the sensing area 301.
  • the second surface 200b of the second substrate 200 is pressed against the first surface 401 of the substrate 300, and the groove structure forms a cavity with the substrate 300, and the sensing region 301 is located in the cavity.
  • the material of the first substrate 100 is glass, silicon wafer, ceramic or plastic.
  • the first substrate 100 is used as a part of the double-layer upper cover substrate of the package structure for protecting the sensing area of the surface of the substrate. Therefore, the material of the first substrate 100 is required to be a hard material to have high strength and resistance. Corrosive, used to withstand external stresses and various chemical contamination.
  • the thickness of the first substrate 100 is 300 ⁇ m to 500 ⁇ m, so that the first substrate 100 has sufficient thickness and strength to meet the needs of subsequent fabrication.
  • the second substrate 200 has a high light transmissivity and is a light transmissive material, and the surface of the second substrate 200 is flat and smooth, and does not cause scattering, diffuse reflection, or the like on the incident light, thereby ensuring the The two substrates 200 have high light transmittance.
  • the substrate includes a sensing area, and the sensing area is an optical sensing area.
  • the second substrate 200 is finally retained in the package structure and is located above the optical sensing region, so that a light-transmitting material needs to be selected as the material of the second substrate 200, so that light is transmitted through the second substrate 200 to the optical sensing region.
  • the material of the second substrate 200 is inorganic glass or organic glass.
  • the area and shape of the second substrate 200 are the same as the area and shape of the first substrate 100, so that the second substrate 200 completely overlaps with the first substrate 100.
  • the second substrate 200 has a thickness of 100 ⁇ m to 200 ⁇ m. Since the second substrate 200 is finally retained in the package structure, the thickness of the second substrate 200 cannot be too large, otherwise the package may be caused. The structural thickness cannot meet the thinning requirements of electronic products. The thickness of the second substrate 200 is not too small. If the thickness of the second substrate 200 is less than 100 ⁇ m, the strength of the second substrate 200 is weak, the external stress that can be withstood is reduced, and the chipping is prone to occur. It is impossible to adequately protect the sensing area in the package structure, which may easily cause the failure of the package structure.
  • the second substrate 200 has two surfaces, and any one of the surfaces may be selected as the first surface 200a, and correspondingly, a surface corresponding to the first surface 200a serves as the second surface 200b.
  • the first surface 200a of the second substrate 200 is bonded to any surface of the first substrate 100 by an adhesive layer 101.
  • the adhesive layer 101 has a viscosity, and the material of the adhesive layer 101 may be a polymer material, for example, an epoxy resin, a polyimide resin, a benzocyclobutene resin, a polybenzoxazole resin, Polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, or A polymer material such as polyvinyl alcohol.
  • the material of the adhesive layer 101 may be a thermal decomposition type adhesive layer. Subsequent heat treatment of the adhesive layer 101 can cause the material of the adhesive layer 101 to be decomposed, and the viscosity of the adhesive layer 101 disappears, thereby causing the first substrate 101 to fall off.
  • the adhesive layer 101 may further include a first adhesive layer and a second adhesive layer.
  • the first adhesive layer is on the surface of the first substrate 100, and the second adhesive layer is on the first surface 200a of the second substrate 200; in another embodiment of the present invention The second adhesive layer is located on the surface of the first substrate 100, and the first adhesive layer is located on the first surface 200a of the second substrate 200.
  • the material of the first adhesive layer and the second adhesive layer may be a polymer material, and may be, for example, an epoxy resin, a polyimide resin, a benzocyclobutene resin, a polybenzoxazole resin, a poly pair.
  • a polymer material such as an alcohol.
  • the first adhesive layer in the adhesive layer 101 may be irradiated with a laser-disassembled adhesive layer, and the second adhesive layer may be any polymer material having a viscosity.
  • the first adhesive layer can be decomposed by laser irradiation to lose the viscosity, and the first substrate 100 and the second substrate 200 can be separated.
  • the thickness of the first adhesive layer is less than 3 micrometers. Specifically, the thickness of the first adhesive layer may be 0.2 micrometers to 0.9. Micron, or 1.1 microns to 2 microns.
  • the first adhesive layer and the second adhesive layer may also be thermal decomposition type adhesive layers, which may be subsequently subjected to heat decomposition treatment to make the first adhesive layer and the first adhesive layer The two adhesive layers lose their tackiness.
  • the groove structure comprises: a cavity wall material layer 201 on the second surface 200b of the second substrate 200; and a groove 202 located in the cavity wall material layer 201.
  • the material of the cavity wall material layer 201 is a photoresist, and may also be an insulating dielectric material such as silicon oxide, silicon nitride or silicon oxynitride.
  • the groove structure may include a groove located in a side surface of the second substrate 200 that is not pressed against the first substrate 100.
  • the substrate 300 is a wafer, including a sensing region 301 on the first surface 401, surrounding a plurality of discretely arranged pads 302 around the sensing region 301, a functional region (not shown), and a silicon substrate.
  • the sensing area 301 is an optical sensing area, and the pad 302 serves as an input/output terminal for connecting devices in the sensing area 301 to an external circuit.
  • the substrate 300 may include a plurality of cells, each of which is formed with a sensing region 301 and a plurality of pads 302 located around the sensing region 301; Cutting to form a plurality of chip packages.
  • the groove structure on the second surface of the second substrate has a plurality of grooves respectively corresponding to a plurality of sensing regions on a plurality of cells.
  • the second surface 200b of the second substrate 200 is pressed against the first surface 401 of the substrate 300, and the cavity wall material layer 201, the second substrate 200, and the substrate 300 form a cavity, and the cavity position is
  • the sensing area 301 formed on the first surface 401 of the substrate 300 corresponds to the sensing area 301 located in the cavity, and the pad 302 around the sensing area 301 is located outside the cavity, the substrate 300 and the cavity Between the wall material layers 201.
  • the sensing area 301 is protected by the first substrate 100, the second substrate 200, and the cavity wall material layers 201 on both sides, thereby preventing the sensing area 301 from being damaged and contaminated.
  • the package structure further includes: a second portion located on the substrate 300. a through hole in the surface 402, the bottom portion of the through hole exposing a part of the surface of the pad 302; an insulating layer 311 on the second surface 402 of the substrate 300 and the sidewall surface of the through hole; and a surface connection welding on the insulating layer 311 a metal layer 312 of the pad 302; a solder resist layer 313 having an opening on the surface of the metal layer 312 and a surface of the insulating layer 311, the opening exposing a surface of the portion of the metal layer 312; and an external protrusion 314 on the surface of the metal layer 312
  • the external protrusion may be a connection structure such as a solder ball or a metal pillar, and a metal material such as copper, aluminum, gold, tin or lead may be used.
  • the package structure further includes: a through hole in the second surface 402 of the substrate 300, the bottom portion of the through hole exposing a part of the surface of the pad 302; a second surface 402 of the substrate 300 and an insulating layer 303 of the sidewall surface of the via; a metal layer 304 located on the surface of the insulating layer 30.
  • the metal layer 304 fills the via and the metal layer
  • the surface is flush with the surface of the insulating layer 303; the opening in the solder resist layer 305 exposes a top surface of the metal layer 304; and an external protrusion 306 connecting the top surface of the metal layer 304 is formed in the opening, the external bump It may be a connection structure such as a solder ball or a metal pillar, and the material of the metal pillar may be a metal material such as copper, aluminum, gold, tin or lead.
  • Embodiments of the present invention also provide another package structure formed by the above method.
  • the package structure includes: a second substrate 200 having a first surface 200a and a second surface 200b opposite to the first surface 200a, the second substrate a thickness of 100 ⁇ m to 200 ⁇ m; a groove structure on the second surface 200b of the second substrate 200; a substrate 300 having a first surface 401 and a second surface 402 opposite to the first surface 401, The first surface of the substrate 401 has a sensing area 301 and a plurality of pads 302 around the sensing area 301; the second surface 200b of the second substrate 200 is pressed against the first surface 401 of the substrate 300, the groove A cavity is formed between the structure and the substrate 300 such that the sensing zone 301 is located within the cavity.
  • the second substrate 200 has a high light transmissivity and is a light transmissive material, and the surface of the second substrate 200 is flat and smooth, and does not cause scattering, diffuse reflection, or the like on the incident light, thereby ensuring the The two substrates 200 have high light transmittance.
  • the material of the second substrate 200 may be inorganic glass or organic glass.
  • the second substrate 200 has a thickness of 100 ⁇ m to 200 ⁇ m and a small thickness, so that the package structure The thickness is low, meeting the thinning requirements of electronic products.
  • the thickness of the second substrate 200 is not too small. If the thickness of the second substrate 200 is less than 100 ⁇ m, the strength of the second substrate 200 is weak, the external stress that can be withstood is reduced, and the chipping is prone to occur. It is impossible to protect the devices in the package structure enough to cause chip failure.
  • the groove structure comprises: a cavity wall material layer 201 on the second surface 200b of the second substrate 200; and a groove 202 located in the cavity wall material layer 201.
  • the material of the cavity wall material layer 201 is a photoresist, and may also be an insulating dielectric material such as silicon oxide, silicon nitride or silicon oxynitride.
  • the groove structure may include a groove located in the second surface 200b of the second substrate 200.
  • the substrate 300 is a wafer, including a sensing region 301 on the first surface 401, a plurality of discretely arranged pads 302 around the sensing region 301, a functional region (not shown), and a silicon substrate.
  • the sensing area 301 is an optical sensing area, and the pad 302 serves as an input/output terminal for connecting devices in the sensing area 301 to an external circuit.
  • the substrate 300 may include a plurality of cells, each of which is formed with a sensing region 301 and a plurality of pads 302 located around the sensing region 301; Cutting to form a plurality of chip packages.
  • the groove structure of the second surface 200b of the second substrate 200 has a plurality of grooves respectively corresponding to a plurality of sensing regions on a plurality of cells.
  • the second surface 200b of the second substrate 200 is pressed against the first surface 401 of the substrate 300, and the cavity wall material layer 201, the second substrate 200, and the substrate 300 form a cavity, and the cavity position is
  • the sensing area 301 formed on the first surface 401 of the second substrate 200 corresponds to the sensing area 301 located in the cavity, and the solder pad 302 around the sensing area 301 is located outside the cavity, and the substrate 300 is empty. Between the walls of the cavity wall material 201. The sensing area 301 is protected by the second substrate 200 and the cavity wall material layer 201 on both sides, thereby preventing the sensing area 301 from being damaged and contaminated.
  • the package structure further includes: a through hole in the second surface 402 of the substrate 300, the bottom portion of the through hole exposing a part of the surface of the pad 302;
  • the surface of the layer 311 has an open solder resist layer 313, the opening exposing a portion of the surface of the metal layer 312; an external bump 314 located on the surface of the metal layer 312, the external bump 314 may be a solder ball, a metal post or the like
  • the structure can be made of a metal material such as copper, aluminum, gold, tin or lead.
  • the package structure may further include: a through hole located in the second surface 402 of the substrate 300, the bottom portion of the through hole exposing a part of the surface of the pad 302; An insulating layer 303 located on the second surface 402 of the substrate 300 and the sidewall surface of the via hole; a metal layer 304 on the surface of the insulating layer 303 connected to the bonding pad 302, the metal layer 304 filling the via hole and the surface and the insulating layer 303 The surface is flush; the opening in the solder resist layer 305 exposes the top surface of the metal layer 304; and the external protrusion 306 connecting the top surface of the metal layer 304 is formed in the opening, and the external bump may be a solder ball, A metal column or the like may be a metal material such as copper, aluminum, gold, tin or lead.
  • the thickness of the second substrate 200 on the first surface 401 of the substrate 300 of the package structure is only 100 ⁇ m to 200 ⁇ m, and the thickness is small, so that the thickness of the package structure is low, which meets the thinning requirement of the electronic product, and
  • the second substrate 200 can provide sufficient protection to the sensing region 301 on the first surface 401 to prevent the sensing region 301 from being damaged and contaminated.
  • the technical solution of the present invention provides a packaging method in which one side surface of the first substrate and the first surface of the second substrate are bonded by an adhesive layer, and then a groove structure is formed on the second surface of the second substrate, and The first surface of the substrate is pressed, and the groove structure forms a cavity with the substrate such that the sensing region of the surface of the substrate is located within the cavity.
  • the first substrate and the second substrate form a double-layered upper cover substrate structure, and after being pressed against the substrate, the sensing area on the substrate can be protected in a subsequent packaging process.
  • the upper cover substrate has a two-layer structure, which facilitates subsequent removal of the first substrate therein, and reduces the thickness of the formed package structure.
  • the packaging method further includes performing a packaging process on the second surface of the substrate, then removing the first substrate and the adhesive layer to reduce the thickness of the package structure, and the remaining second substrate can still protect the sensing area In order to ensure that the performance of the package structure is not affected by the outside world.
  • the thickness of the second substrate may be 100 ⁇ m to 200 ⁇ m. Since the second substrate is finally retained in the package structure, the thickness of the second substrate may not be too large, otherwise the thickness of the package structure may not meet the thinness of the electronic product. The thickness of the second substrate is not too small. If the thickness of the second substrate is less than 100 ⁇ m, the strength of the second substrate is weak, and the external stress that can be withstood is reduced. Fragmentation occurs, and it is impossible to adequately protect the sensing area in the package structure, which may easily cause the package structure to fail.
  • the adhesive layer comprises a first adhesive layer and a second adhesive layer, wherein the first adhesive layer is a laser irradiation decomposing adhesive layer, which can decompose the material of the first adhesive layer under the action of laser illumination And lose the viscosity. Therefore, the adhesive layer can be treated by a laser irradiation decomposition method to lose the viscosity of the adhesive layer, thereby causing the first substrate to fall off from the surface of the adhesive layer to remove the first substrate. By removing the first substrate by the above method, it is possible to avoid affecting materials and devices of other parts of the package structure.
  • the first adhesive layer is a laser irradiation decomposing adhesive layer, which can decompose the material of the first adhesive layer under the action of laser illumination And lose the viscosity. Therefore, the adhesive layer can be treated by a laser irradiation decomposition method to lose the viscosity of the adhesive layer, thereby causing the first substrate to fall off from the surface of the adhesive layer to remove the first substrate.
  • the adhesive layer may also be a thermally decomposable adhesive layer, which can decompose the material of the adhesive layer and lose its viscosity under heating. Therefore, the adhesive layer may be treated by a thermal decomposition method to lose the viscosity of the adhesive layer, thereby causing the first substrate to fall off from the surface of the adhesive layer to remove the first substrate. By removing the first substrate by the above method, it is possible to avoid affecting materials and devices of other parts of the package structure.
  • the technical solution of the present invention further provides a package structure formed by the above method, the package structure comprising a first substrate and a second substrate, wherein a side surface of the first substrate and a first surface of the second substrate pass through an adhesive layer Bonding a groove structure on the second surface of the second substrate; the second surface of the second substrate is pressed against the first surface of the substrate, and the groove structure forms a cavity between the substrate and the substrate
  • the sensing area on the substrate is located within the cavity.
  • the first substrate and the second substrate form a double-layered upper cover substrate structure, which facilitates subsequent removal of the first substrate therein and reduces the thickness of the formed package structure. There is no need to use a process such as etching or grinding to reduce the thickness of the upper cover substrate, thereby ensuring the thickness of the package structure while ensuring that the surface of the remaining second substrate is flat, which can protect the sensing area.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Micromachines (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

一种封装方法及封装结构，所述封装方法包括：提供第一基板（100）和第二基板（200），所述第二基板（200）具有第一表面（200a）和与所述第一表面（200a）相对的第二表面（200b），将所述第一基板（100）的一侧表面和第二基板（200）的第一表面（200a）通过粘胶层（101）粘接；在第二基板（200）的第二表面（200b）形成凹槽结构（202）；提供基底（300），所述基底（300）具有第一表面（401）和与所述第一表面（401）相对的第二表面（402），所述基底（300）的第一表面（401）具有感应区（301）以及位于感应区周围的若干焊垫（302）；将所述第二基板（200）的第二表面（200b）与基底（300）的第一表面（401）压合，所述凹槽结构（202）与基底（300）之间构成空腔，使所述感应区位于所述空腔内。

Description

封装方法及封装结构
本申请要求于2015年2月13日提交中国专利局、申请号为201510079349.3、发明名称为“封装方法及封装结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，特别涉及一种影像传感芯片的晶圆级封装方法及封装结构。
背景技术
晶圆级芯片封装(Wafer Level Chip Size Packaging，WLCSP)技术是对整片晶圆进行封装测试后再切割得到单个成品芯片封装体的技术，封装后的芯片封装体尺寸与裸片一致。
晶圆级芯片尺寸封装技术改变传统封装如陶瓷无引线芯片载具(Ceramic Leadless Chip Carrier)、有机无引线芯片载具(Organic Leadless Chip Carrier)和数码相机模块式的模式，顺应了市场对微电子产品日益轻、小、短、薄化和低价化要求。经晶圆级芯片尺寸封装技术封装后的芯片尺寸达到了高度微型化，芯片成本随着芯片尺寸的减小和晶圆尺寸的增大而显著降低。晶圆级芯片尺寸封装技术是可以将IC设计、晶圆制造、封装测试、基板制造整合为一体的技术，是当前封装领域的热点和未来发展的趋势。
晶圆级封装技术中，特别是对于影像传感芯片的封装，通常会在半导体晶圆形成有器件的一面上覆盖一个上盖基板，以保护器件在封装过程中不受损伤和污染，对器件起到保护作用。
请参考图1，晶圆级芯片封装结构的剖面结构示意图。包括：衬底10，所述衬底10上形成有感应区20，所述传感器件两侧的衬底10上形成有焊垫21，所 述衬底10的与感应区20相对的另一侧表面形成有通孔，所述通孔暴露出焊垫21，所述通孔侧壁以及衬底10表面具有绝缘层11，焊垫21以及部分绝缘层11表面具有线路层12，所述线路层12以及绝缘层11被具有开口的阻焊层13覆盖，所述开口处具有连接线路层12的焊球14。
所述衬底10的具有感应区20的一侧表面被上盖基板30覆盖，所述上盖基板30与衬底10表面之间具有空腔壁31，所述空腔壁31与上盖基板30、衬底10之间构成空腔，使所述感应区20位于所述空腔内，避免所述器件受到污染和损伤。
其中所述上盖基板30的厚度通常很大，一般为400μm左右，以满足制程要求，这就使得对封装后晶圆切割所形成的芯片封装体的尺寸偏厚，后续芯片封装体上模组的整体厚度也偏厚，不能满足市场对于电子产品日益薄化的需求。
为了降低晶圆封装的厚度，会将封装完成之后的晶圆表面的上盖基板去除(请参考图2)，使得所述感应区20暴露，虽然晶圆封装体的厚度下降，但是感应区20容易受到污染和损伤，从而影响封装结构的整体性能。
目前亟需一种封装方法，在不影响封装结构性能的同时，降低封装结构的厚度。
发明内容
本发明解决的问题是提供一种封装方法及封装结构，用于降低封装结构的厚度。
一方面，本发明提供一种封装方法，包括：
提供第一基板和第二基板，所述第二基板具有第一表面和与所述第一表面相对的第二表面，将所述第一基板的任一表面和第二基板的第一表面通过粘胶层粘接；
在第二基板的第二表面形成凹槽结构；
提供基底，所述基底具有第一表面和与所述第一表面相对的第二表面，所述基底的第一表面具有感应区以及位于感应区周围的若干焊垫；
将所述第二基板的第二表面与基底的第一表面压合，所述凹槽结构与基底之间构成空腔，使所述感应区位于所述空腔内。
可选的，该方法还包括：将所述第二基板的第二表面与基底的第一表面压合之后，对基底的第二表面进行封装处理；去除所述第一基板以及粘胶层。
可选的，所述对基底的第二表面进行的封装处理包括：对基底的第二表面进行减薄、刻蚀，形成通孔，所述通孔底部暴露出焊垫的部分表面；在基底的第二表面以及通孔的侧壁表面形成绝缘层；在所述绝缘层表面形成连接焊垫的金属层；在所述金属层表面以及绝缘层表面形成具有开口的阻焊层，所述开口暴露出部分金属层表面；在所述金属层表面形成外接凸起。
可选的，所述金属层填充满所述通孔且表面与基底的第二表面齐平；所述阻焊层内的开口暴露出金属层的顶部表面；在所述开口内形成连接金属层顶部表面的外接凸起。
可选的，所述第一基板的厚度为300μm～500μm。
可选的，所述第二基板的厚度为100μm～200μm。
可选的，所述将所述第一基板的一侧表面和第二基板的第一表面通过粘胶层粘接的方法包括：在第一基板的一侧表面形成粘胶层，然后将第二基板的第一表面与所述粘胶层压合；或者在第二基板的第一表面形成粘胶层，然后将第一基板的任一表面与所述粘胶层压合。
可选的，所述粘胶层包括第一粘胶层和第二粘胶层。
可选的，将所述第一基板的一侧表面和第二基板的第一表面通过粘胶层粘接的方法包括：在第一基板的一侧表面形成第一粘胶层、在第二基板的第一表面形成第二粘胶层，或者在第一基板的一侧表面形成第二粘胶层、在第二基板的第一表面形成第一粘胶层；然后将所述第一基板和第二基板通过所述第一粘胶层、第二粘胶层压合。
可选的，可以通过喷涂、旋涂或黏贴工艺形成所述粘胶层。
若所述第一粘胶层为激光照射分解型粘胶层，则采用激光照射分解法对所 述粘胶层进行处理，使所述粘胶层失去粘性，以去除所述第一基板；或者
若所述粘胶层为加热分解型粘胶层，则采用加热分解法对所述粘胶层进行处理，使所述粘胶层失去粘性，以去除所述第一基板。
可选的，可以通过对第二基板表面进行清洗，去除所述第二基板表面的粘胶层。
可选的，所述凹槽结构的形成方法包括：
在所述第二基板的第二表面上形成空腔壁材料层，刻蚀所述空腔壁材料层至第二基板表面，在所述空腔壁材料层内形成凹槽；或者
对所述第二基板的第二表面进行刻蚀，在所述第二基板内形成凹槽。
可选的，所述基底包括若干单元，每一单元对应形成有感应区以及位于感应区周围的若干焊垫；相邻单元之间具有切割道；所述第二基板未与第一基板压合的另一侧表面形成的凹槽结构具有若干凹槽，所述凹槽分别与若干单元上的若干感应区对应；在去除第一基板以及粘胶层之后，沿切割道对基底以及第一基板进行切割，形成若干芯片封装体。
另一方面，本发明实施例提供一种封装结构，包括：
第一基板和第二基板，所述第二基板具有第一表面和与所述第一表面相对的第二表面，所述第一基板的任一表面和第二基板的第一表面通过粘胶层粘接；
位于所述第二基板的第二表面的凹槽结构；
基底，所述基底具有第一表面和与所述第一表面相对的第二表面，所述基底的第一表面具有感应区以及位于感应区周围的若干焊垫；
所述第二基板的第二表面与基底的第一表面压合，所述凹槽结构与基底之间构成空腔，所述感应区位于所述空腔内。
可选的，所述第一基板的材料为玻璃、硅片、陶瓷或塑料。
可选的，所述第一基板的厚度为300μm～500μm。
可选的，所述第二基板的材料为透光材料。
可选的，所述第二基板的厚度为100μm～200μm。
可选的，所述粘胶层包括第一粘胶层和第二粘胶层。
可选的，所述第一粘胶层位于第一基板表面，第二粘胶层位于第二基板的第一表面上；或者，所述第二粘胶层位于第一基板表面，所述第一粘胶层位于在第二基板的第一表面上。
可选的，所述胶层为激光照射分解型粘胶层；或者所述粘胶层为加热分解型粘胶层。
可选的，所述凹槽结构包括：
所述第二基板的第二表面上的空腔壁材料层，位于所述空腔壁材料层内的凹槽；或者
位于所述第二基板的第二表面内的凹槽。
可选的，所述基底包括若干单元，每一单元对应形成有感应区以及位于感应区周围的若干焊垫；相邻单元之间具有切割道；位于所述第二基板未与第一基板压合的另一侧表面的凹槽结构具有若干凹槽，所述凹槽分别与若干单元上的若干感应区对应。
可选的，所述封装结构还包括：位于基底的第二表面内的通孔，所述通孔底部暴露出焊垫的部分表面；位于基底的第二表面以及通孔的侧壁表面的绝缘层；位于所述绝缘层表面连接焊垫的金属层；位于所述金属层表面以及绝缘层表面具有开口的阻焊层，所述开口暴露出部分金属层表面；位于所述金属层表面的外接凸起。
可选的，所述金属层填充满所述通孔且表面与绝缘层的表面齐平；所述阻焊层内的开口暴露出金属层的顶部表面；在所述开口内形成连接金属层顶部表面的外接凸起。
另一方面，本发明实施例还提供一种封装结构，包括：
基板，所述基板具有第一表面和与所述第一表面相对的第二表面；
位于所述基板的第二表面的凹槽结构；
基底，所述基底具有第一表面和与所述第一表面相对的第二表面，所述基底的第一表面具有感应区以及位于感应区周围的若干焊垫；
所述基板的第二表面与基底的第一表面压合，所述凹槽结构与基底之间构成空腔，所述感应区位于所述空腔内；
其中所述基板的厚度为100μm～200μm。
本发明实施例提供的封装方法以及该封装方法形成的封装结构中，封装结构包括第一基板和第二基板，所述第一基板的一侧表面和第二基板第一表面通过粘胶层粘接、位于所述第二基板第二表面的凹槽结构；所述第二基板的第二表面与基底的第一表面压合，所述凹槽结构与基底之间构成空腔，使所述基底上的感应区位于所述空腔内。所述第一基板和第二基板构成双层的上盖基板结构，便于后续去除其中的第一基板，降低形成的封装结构的厚度。而不需要采用刻蚀或研磨等工艺使所述上盖基板的厚度下降，从而在降低封装结构的厚度同时，确保保留的第二基板表面平整，其能够对感应区起到保护作用。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1至图2是本发明的现有技术的封装结构的剖面结构示意图；
图3至图13是本发明的实施例的封装结构的形成过程的结构示意图。
具体实施方式
如背景技术中所述，封装结构的上盖基板的厚度较大，不能满足市场对于电子产品日益薄化的需求。并且，对于具有光学传感单元的封装结构，所述封 装结构的上盖基板要求具有较高的透光性，如果采用研磨工艺或者刻蚀工艺对上盖基板进行减薄，会使得上盖基板的表面变的粗糙，影响所述上盖基板的透光性，且工艺复杂，成本较高。而去除所述上盖基板，虽然能够降低封装结构的厚度，但是会影响封装结构的性能。
本发明的实施例中，采用将第一基板和第二基板压合形成的双层基板作为封装结构的上盖基板，从而可以在形成封装结构之后，去除厚度较大的第一基板，使的封装结构的厚度下降，并且，所述第二基板依旧能够对器件起到保护作用，避免封装结构的性能受到影响。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
请参考图3，提供第一基板100。
所述第一基板100的材料可以为玻璃、硅片、陶瓷或塑料。所述第一基板100作为后续形成的封装结构的双层上盖基板的一部分，用于保护后续提供的待封装基底表面的感应区，所述第一基板100的材料为硬质材料，具有较高的强度和耐腐蚀性，可以承受后续封装过程中外界施加的应力以及各种化学污染。
由于所述第一基板100后续不会在封装结构中保留，所以透光或者不透光的材料均可以作为第一基板100的材料，不会对封装结构的性能造成影响。
本实施例中，所述第一基板100的厚度为300μm～500μm，使得所述第一基板100具有足够的厚度及强度，满足后续制成的需要。
请参考图4，提供第二基板200，所述第二基板200具有第一表面200a和与所述第一表面200a相对的第二表面200b。
所述第二基板200具有较高的透光性，为透光材料，且所述第二基板200的表面平整、光滑，不会对入射的光线产生散射、漫反射等，从而确保所述第二基板200具有较高的透光性。
后续提供的待封装的基底上包括感应区，所述感应区为光学感应区。所述第二基板200最终保留在封装结构中，位于光学感应区上方，选择透光材料作 为第二基板200的材料，便于光线透过所述第二基板200照射到所述光学感应区。
具体的，本实施例中，所述第二基板200的材料可以为无机玻璃或有机玻璃。
所述第二基板200的面积、形状与第一基板100(请参考图4)的面积、形状相同，使得后续将第二基板200与第一基板100压合后，所述第二基板200与第一基板100能够完全重叠。
所述第二基板200的厚度为100μm～200μm。由于所述第二基板200最终保留在封装结构中，所以所述第二基板200的厚度不能过大，否则会导致封装结构厚度不能满足电子产品的薄化要求。而所述第二基板200的厚度也不能过小，如果所述第二基板200的厚度小于100μm，会导致所述第二基板200的强度较弱，能够承受的外应力下降，容易发生碎裂，无法对封装结构内的感应区起到足够的保护作用，容易造成封装结构失效的问题。
所述第二基板200具有两个表面，可以选择其中任一表面作为第一表面200a，而相应的，与该第一表面200a对应的表面作为第二表面200b。
后续将所述第二基板200与第一基板100(请参考图3)通过粘胶层粘接，形成双层上盖基板。
请参考图5至图6，为本实施例中将第二基板200(请参考图4)与第一基板100(请参考图3)通过粘胶层粘接的结构示意图。
请参考图5，在第一基板100的任一表面形成粘胶层101。
所述粘胶层101可以形成在第一基板100的任意一侧表面。所述粘胶层101具有粘性，用于使第一基板100和后续提供的第二基板被压合为一体，形成双层上盖基板结构。
所述粘胶层101的材料可以为聚合物材料，例如可以是环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、或聚乙烯醇等聚合物材料。
可以通过喷涂、旋涂或黏贴工艺形成所述粘胶层101，以在所述第一基板100的一侧表面形成厚度均匀的粘胶层101，并且使所述粘胶层101的表面平整。
为了便于后续工艺中，将第一基板100和第二基板压合形成双层上盖基板，并在封装完成之后，能够顺利将第一基板100从第二基板上剥离，所述粘胶层101的材料可以是热分解型粘胶层。后续对所述粘胶层101进行加热处理，能够使粘胶层101的材料发生分解，使的所述粘胶层101的粘性消失，从而使第一基板101脱落。
请参考图6，将所述第一基板100的任一表面和第二基板200的第一表面200a通过粘胶层101粘接。
本实施例中，将第二基板200的第一表面200a与第一基板100表面上的粘胶层101压合，从而使得所述第一基板100和第二基板200被压合为一体，构成双层结构的上盖基板。并且，由于所述第一基板100和第二基板200之间通过粘胶层101粘接，后续也容易将所述第一基板100与第二基板200分开。
将所述第一基板100和第二基板200被压合为一体，形成双层结构的上盖基板，使所述上盖基板具有足够的厚度，能够满足后续封装制程中对于上盖基板的厚度和强度要求。
在本发明的其他实施例中，也可以在第二基板200的第一表面200a上形成粘胶层101之后，再与第一基板100的任一表面进行压合，使所述第一基板100和第二基板200通过粘胶层101粘接，形成双层结构的上盖基板。
在本发明的另一个实施例中，还提供另一种将所述第二基板与第一基板通过粘胶层粘接，形成双层上盖基板的方法，包括：在第一基板100(请参考图3)的任一表面形成第一粘胶层，在第二基板200(请参考图4)的第一表面200a(请参考图4)上形成第二粘胶层，或者在第一基板100任一表面形成第二粘胶层，在第二基板200的第一表面200a上形成第一粘胶层；然后将所述第一基板100和第二基板200通过所述第一粘胶层、第二粘胶层压合，所述第一粘胶层和第二粘胶层构成粘接第一基板100和第二基板200的粘胶层。
所述第一粘胶层和第二粘胶层的材料可以为聚合物材料，例如可以是环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、或聚乙烯醇等聚合物材料。可以通过喷涂、旋涂或黏贴工艺形成所述第一粘胶层和第二粘胶层。
为了便于后续将第一基板100、第二基板200分离，所述粘胶层中的第一粘胶层可以采用激光照射分解型粘胶层，而所述第二粘胶层可以采用任意具有粘性的聚合物材料。后续通过激光照射使所述第一粘胶层发生分解从而失去粘性，使第一基板100、第二基板200分离。
所述第一粘胶层的厚度越大，后续采用激光照射分解法对粘胶层进行处理时需要的激光功率就越大，激光照射产生的热量越高，使得分解效率较低，并且过高的热量容易对粘胶层两侧的第一基板和第二基板性能受到影响，为了避免上述问题，可以采用厚度较低的第一粘胶层，例如使所述第一粘胶层的厚度小于3微米，具体的，所述第一粘胶层的厚度可以是0.2微米～0.9微米，或1.1微米～2微米。
所述第一粘胶层的厚度较低时，粘性也较低，从而需要再形成第二粘胶层，提高第一基板100与第二基板200压合后的粘胶层的总厚度，从而提高粘胶层的粘性，避免所述第一基板100、第二基板200在后续封装过程中分离。
在本发明的其他实施例中，所述第一粘胶层和第二粘胶层还可以都是热分解型粘胶层，后续可以通过加热分解处理，使所述第一粘胶层和第二粘胶层失去粘性。
请参考图7，在第二基板200的第二表面200b形成凹槽结构。
本实施例中，所述凹槽结构包括：所述第二基板200的第二表面200b上的空腔壁材料层201；位于所述空腔壁材料层201内的凹槽202。
具体的，本实施例中，形成所述凹槽结构的形成方法包括：在所述第二基板200的第二表面上形成完整的空腔壁材料层201，刻蚀所述空腔壁材料层201至第二基板200表面，在所述空腔壁材料层201内形成凹槽202。所述凹槽位 置与后续提供的基底上的感应区的位置对应。所述凹槽202的深度大于后续提供的基底上的感应区内的器件高度。
本实施例中，所述空腔壁材料层201的材料为光刻胶，可以通过喷涂、旋涂或者黏贴工艺在第二基板200的第二表面200b上形成所述空腔壁材料层201，然后对所述空腔壁材料层201进行曝光、显影，形成所述凹槽202。
在本发明的其他实施例中，所述空腔壁材料层201的材料还可以是氧化硅、氮化硅、氮氧化硅等绝缘介质材料，通过沉积工艺形成所述空腔壁材料层201，并且对所述空腔壁材料层201进行干法刻蚀以在所述空腔壁材料层201内形成凹槽202。
在本发明的其他实施例中，所述凹槽结构可以包括位于所述第二基板200的第二表面200b内的凹槽。具体的，所述凹槽结构的形成方法包括：对所述第二基板200的第二表面200b进行刻蚀，在所述第二基板200内形成凹槽。可以采用干法刻蚀工艺对所述第二基板200进行刻蚀，形成所述凹槽。
请参考图8，提供基底300，所述基底300具有第一表面401和与所述第一表面401相对的第二表面402，所述基底300的第一表面401具有感应区301以及位于感应区301周围的若干焊垫302。
本实施例中，所述基底300为晶圆，包括位于第一表面401的感应区301、围绕感应区301周围的若干分立排布的焊垫302、功能区(未示出)和硅衬底。所述感应区301为光学感应区，所述焊垫302作为感应区301内的器件与外部电路连接的输入/输出端。
图8示出的是具有一个感应区的基底的剖面示意图。
在本发明的其他实施例中，所述基底300可以包括若干单元，每一单元对应形成有感应区301以及位于感应区301周围的若干焊垫302；相邻单元之间具有切割道，便于在封装完成之后，进行切割，形成多个芯片封装体。
请参考图9，将所述第二基板200的第二表面200b与基底300的第一表面401压合，所述凹槽202(请参考图8)与基底300之间构成空腔，使所述感应区301位于所述空腔内。
本实施例中，在所述第二基板200的第二表面200b上的空腔壁材料层201表面形成粘合层与基底300进行压合，所述粘合层可以为高分子粘接材料，例如硅胶、环氧树脂、苯并环丁烯等聚合物材料，可以采用喷涂、旋涂或者黏贴工艺形成所述粘合层。所述粘合层既可以实现粘接作用，又可以起到绝缘和密封作用。
将所述第二基板200的第二表面200b与基底300的第一表面401压合，所述空腔壁材料层201、第二基板200以及基底300之间构成空腔，所述空腔位置与基底300的第一表面401上形成的感应区301相对应，使所述感应区301位于空腔内，而所述感应区301周围的焊垫302位于空腔外侧、所述基底300与空腔壁材料层201之间。
所述感应区301位于空腔内，在后续的封装过程中，受到所述第一基板100、第二基板200以及两侧的空腔壁材料层201的保护，从而避免所述感应区301受到损伤和污染。
在本发明的其他实施例中，所述第二基板200内具有凹槽，可以将第二基板200具有凹槽的一侧表面形成粘合层，直接与基底300的第一表面401进行压合，使得所述第二基板200与基底300之间构成空腔，使所述感应区301位于空腔内。
将所述第二基板200的第二表面200b与基底300的第一表面401压合后，对基底300的第二表面402进行封装处理。
请参考图10，为对基底300的第二表面402进行封装处理的一个实施例，该实施例的封装处理包括：
首先，对基底300的第二表面402进行减薄，使所述基底300的厚度下降，可以采用刻蚀或者化学机械研磨工艺进行所减薄，以便于后续在所述基底300内形成通孔。
然后对基底300的第二表面402进行刻蚀，在所述基底300内形成通孔，所述通孔底部暴露出焊垫302的部分表面，所述通孔用于形成连接焊垫302的金属连接结构。
在基底300的第二表面402以及通孔的侧壁表面形成绝缘层311，所述绝缘层311的材料可以是氧化硅、氮化硅等绝缘介质材料，用于使所述基底300与后续形成的金属层绝缘；再在所述绝缘层311表面形成连接焊垫302的金属层312，所述金属层312与焊垫302电连接。
在所述金属层312表面以及绝缘层311表面形成具有开口的阻焊层313，所述阻焊层313的材料为氧化硅、氮化硅等绝缘介质材料，用于保护所述金属层312，所述开口暴露出部分金属层312表面，便于后续在所述金属层312表面形成焊点。
然后在所述金属层312表面形成外接凸起314，所述外接凸起314可以为焊球、金属柱等连接结构，可以采用铜、铝、金、锡或铅等金属材料。
请参考图11，为对基底300的第二表面402进行封装处理的另一个实施例，所述封装处理包括：对基底300的第二表面402进行减薄后，对基底300的第二表面402进行刻蚀，在所述基底300内形成通孔，所述通孔底部暴露出焊垫302的部分表面；在基底300的第二表面402以及通孔的侧壁表面形成绝缘层303；在所述绝缘层303表面形成连接焊垫302的金属层304，所述金属层304填充所述通孔且所述金属层的表面与绝缘层303的表面齐平；在所述金属层304表面以及绝缘层303表面形成具有开口的阻焊层305，所述阻焊层305内的开口暴露出金属层304的顶部表面；在所述开口内形成连接金属层304顶部表面的外接凸起306，所述外接凸起306为焊球、金属柱等连接结构，可以采用铜、铝、金、锡或铅等金属材料。
请参考图12和图13，去除所述第一基板100(请参考图10和图11)以及粘胶层101(请参考图10和图11)。图12和图13分别对应上述封装处理的两个实施例所形成的结构。
在对所述基底300的第二表面402完成封装处理之后，形成封装结构，但是所述封装结构的基底300的第一表面401上的上盖基板的厚度较大，去除所述第一基板100，可以降低基底300的第一表面401上的上盖基板厚度，并且保留的第二基板200依旧能够对所述基底300上的感应区301起到保护作用。
本实施例中，第一基板100和第二基板200之间的粘胶层101为热分解型 粘胶层，在加热作用下能够使粘胶层101的材料发生分解而失去粘性。所以，本实施例中，采用加热分解法对所述粘胶层101进行处理，使所述粘胶层101失去粘性，从而使第一基板从粘胶层101表面脱落，以去除所述第一基板100。所述加热温度小于外接凸起314的熔点，避免对封装结构的性能造成影响。
在本发明的其他实施例中，所述第一基板100和第二基板200之间的粘胶层包括第一粘胶层和第二粘胶层，并且所述第一粘胶层为激光照射分解型粘胶层，可以采用激光照射分解法对所述粘胶层进行处理，使第一粘胶层的材料发生分解而失去粘性。具体的，所述激光照射分解法可以采用波长为1064nm的钇铝石榴石激光，输出功率为15W～40W，在本发明的其他实施例中，还可以采用其他波长的激光，例如紫外波长的激光进行照射。
在本发明的其他实施例中，所述粘胶层101包括第一粘胶层和第二粘胶层，并且所述第一粘胶层和第二粘胶层均为热分解型粘胶层，可以采用加热分解法对所述粘胶层进行处理，使所述第一粘胶层和第二粘胶层均失去粘性，从而使第一基板100和第二基板200分离。
如果采用湿法或者干法刻蚀工艺去除第一基板100，容易对所述封装结构其他部分的材料以及器件造成影响，而采用上述方法则可以避免上述影响。
去除所述第一基板100之后，可以对所述第二基板200表面进行清洗，以去除第二基板200表面残留的粘胶层101，暴露出第二基板200的表面。所述清洗过程采用的清洗剂不会对第二基板200造成腐蚀，从而不会影响第二基板200表面的平整性和透光性。
由于所述第一基板100的厚度较大，去除所述第一基板100之后，使得形成的封装结构的厚度下降，并且保留的第二基板200依然能够对感应区起到保护作用，从而确保所述封装结构的性能不受外界的影响。
综上，本发明的实施中，将第一基板和第二基板通过粘胶层粘接，然后在第二基板的第二表面或者在第二基板内部形成凹槽结构，并与基底的第一表面压合，所述凹槽结构与基底之间构成空腔，使所述基底表面的感应区位于所述空腔内。所述第一基板与第二基板构成双层的上盖基板结构，与基底压合后，可以在后续的封装过程中保护基底上的感应区。而且所述上盖基板为双层结 构，便于后续去除其中的第一基板，降低形成的封装结构的厚度。
在本发明的其他实施例中，还提供一种采用上述方法形成的封装结构。
请参考图10和图11，所述封装结构包括：第一基板100和第二基板200，所述第二基板200具有第一表面200a和与所述第一表面200a相对的第二表面200b，所述第一基板100的任一表面和第二基板200的第一表面200a通过粘胶层101粘接；位于所述第二基板200的第二表面200b的凹槽结构；基底300，所述基底300具有第一表面401和与所述第一表面401相对的第二表面402，所述基底300的第一表面401具有感应区301以及位于感应区301周围的若干焊垫302；所述第二基板200的第二表面200b与基底300的第一表面401压合，所述凹槽结构与基底300之间构成空腔，所述感应区301位于所述空腔内。
所述第一基板100的材料为玻璃、硅片、陶瓷或塑料。所述第一基板100作为封装结构的双层上盖基板的一部分，用于保护基底表面的感应区，所以要求所述第一基板100的材料为硬质材料，以具有较高的强度和耐腐蚀性，用于承受外界施加的应力以及各种化学污染。
本实施例中，所述第一基板100的厚度为300μm～500μm，使得所述第一基板100具有足够的厚度及强度，满足后续制成的需要。
所述第二基板200具有较高的透光性，为透光材料，且所述第二基板200的表面平整、光滑，不会对入射的光线产生散射、漫反射等，从而确保所述第二基板200具有较高的透光性。所述基底上包括感应区，所述感应区为光学感应区。所述第二基板200最终保留在封装结构中，位于光学感应区上方，从而需要选择透光材料作为第二基板200的材料，便于光线透过所述第二基板200照射到所述光学感应区。具体的，本实施例中，所述第二基板200的材料为无机玻璃或有机玻璃。
所述第二基板200的面积、形状与第一基板100的面积、形状相同，使得所述第二基板200与第一基板100完全重叠。
所述第二基板200的厚度为100μm～200μm。由于所述第二基板200最终保留在封装结构中，所以所述第二基板200的厚度不能过大，否则会导致封装 结构厚度不能满足电子产品的薄化要求。而所述第二基板200的厚度也不能过小，如果所述第二基板200的厚度小于100μm，会导致所述第二基板200的强度较弱，能够承受的外应力下降，容易发生碎裂，无法对封装结构内的感应区起到足够的保护作用，容易造成封装结构失效的问题。
所述第二基板200具有两个表面，可以选择其中任一表面作为第一表面200a，而相应的，与该第一表面200a对应的表面作为第二表面200b。
所述第二基板200的第一表面200a与第一基板100的任一表面通过粘胶层101粘接。所述粘胶层101具有粘性，所述粘胶层101的材料可以为聚合物材料，例如可以是环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、或聚乙烯醇等聚合物材料。
本实施例中，所述粘胶层101的材料可以是热分解型粘胶层。后续对所述粘胶层101进行加热处理，能够使粘胶层101的材料发生分解，使所述粘胶层101的粘性消失，从而使第一基板101脱落。
在本发明的其他实施例中，所述粘胶层101还可以包括第一粘胶层和第二粘胶层。在本发明的一个实施的一个实施例中，第一粘胶层位于第一基板100表面，第二粘胶层位于第二基板200的第一表面200a上；在本发明的另一个实施例中，第二粘胶层位于第一基板100表面，第一粘胶层位于在第二基板200的第一表面200a上。
所述第一粘胶层和第二粘胶层的材料可以为聚合物材料，例如可以是环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、或聚乙烯醇等聚合物材料。
所述粘胶层101中的第一粘胶层可以采用激光照射分解型粘胶层，而所述第二粘胶层可以采用任意具有粘性的聚合物材料。通过激光照射使可以第一粘胶层发生分解从而失去粘性，使第一基板100、第二基板200分离。所述第一粘胶层的厚度小于3微米，具体的，所述第一粘胶层的厚度可以是0.2微米～0.9 微米，或1.1微米～2微米。
在本发明的其他实施例中，所述第一粘胶层和第二粘胶层还可以都是热分解型粘胶层，后续可以通过加热分解处理，使所述第一粘胶层和第二粘胶层失去粘性。
本实施例中，所述凹槽结构包括：所述第二基板200的第二表面200b上的空腔壁材料层201；位于所述空腔壁材料层201内的凹槽202。所述空腔壁材料层201的材料为光刻胶，还可以是氧化硅、氮化硅、氮氧化硅等绝缘介质材料。
在本发明的其他实施例中，所述凹槽结构可以包括位于所述第二基板200未与第一基板100压合的一侧表面内的凹槽。
本实施例中，所述基底300为晶圆，包括位于第一表面401的感应区301，围绕感应区301周围的若干分立排布的焊垫302、功能区(未示出)和硅衬底。所述感应区301为光学感应区，所述焊垫302作为感应区301内的器件与外部电路连接的输入/输出端。
在本发明的其他实施例中，所述基底300可以包括若干单元，每一单元对应形成有感应区301以及位于感应区301周围的若干焊垫302；相邻单元之间具有切割道，便于进行切割，形成多个芯片封装体。位于所述第二基板的第二表面的凹槽结构具有若干凹槽，所述凹槽分别与若干单元上的若干感应区对应。
所述第二基板200的第二表面200b与基底300的第一表面401压合，所述空腔壁材料层201、第二基板200以及基底300之间构成空腔，所述空腔位置与基底300的第一表面401上形成的感应区301相对应，使所述感应区301位于空腔内，而所述感应区301周围的焊垫302位于空腔外侧、所述基底300与空腔壁材料层201之间。所述感应区301受到所述第一基板100、第二基板200以及两侧的空腔壁材料层201的保护，从而避免所述感应区301受到损伤和污染。
请参考图10，本实施例中，所述封装结构还包括：位于基底300的第二 表面402内的通孔，所述通孔底部暴露出焊垫302的部分表面；位于基底300的第二表面402以及通孔的侧壁表面的绝缘层311；位于所述绝缘层311表面连接焊垫302的金属层312；位于所述金属层312表面以及绝缘层311表面具有开口的阻焊层313，所述开口暴露出部分金属层312表面；位于所述金属层312表面的外接凸起314，所述外接凸起可以是焊球、金属柱等连接结构，可以采用铜、铝、金、锡或铅等金属材料。
请参考图11，在本发明的另一实施例中，所述封装结构还包括：位于基底300的第二表面402内的通孔，所述通孔底部暴露出焊垫302的部分表面；位于基底300的第二表面402以及通孔的侧壁表面的绝缘层303；位于所述绝缘层30.表面连接焊垫302的金属层304，所述金属层304填充通孔且所述金属层的表面与绝缘层303表面齐平；所述阻焊层305内的开口暴露出金属层304的顶部表面；在所述开口内形成连接金属层304顶部表面的外接凸起306，所述外接凸起可以是焊球、金属柱等连接结构，所述金属柱的材料可以是铜、铝、金、锡或铅等金属材料。
本发明的实施例还提供另一种采用上述方法形成的封装结构。
请参考图12和图13，所述封装结构包括：第二基板200，所述第二基板200具有第一表面200a和与所述第一表面200a相对的第二表面200b，所述第二基板的厚度为100μm～200μm；位于所述第二基板200第二表面200b的凹槽结构；基底300，所述基底300具有第一表面401和与所述第一表面401相对的第二表面402，所述基底401的第一表面具有感应区301以及位于感应区301周围的若干焊垫302；所述第二基板200的第二表面200b与基底300的第一表面401压合，所述凹槽结构与基底300之间构成空腔，使所述感应区301位于所述空腔内。
所述第二基板200具有较高的透光性，为透光材料，且所述第二基板200的表面平整、光滑，不会对入射的光线产生散射、漫反射等，从而确保所述第二基板200具有较高的透光性。所述第二基板200的材料可以为无机玻璃或有机玻璃。
所述第二基板200的厚度为100μm～200μm，厚度较小，使所述封装结构 的厚度较低，满足电子产品的薄化需求。而所述第二基板200的厚度也不能过小，如果所述第二基板200的厚度小于100μm，会导致所述第二基板200的强度较弱，能够承受的外应力下降，容易发生碎裂，无法对封装结构内的器件起到足够的保护作用，容易造成芯片失效的问题。
本实施例中，所述凹槽结构包括：所述第二基板200的第二表面200b上的空腔壁材料层201；位于所述空腔壁材料层201内的凹槽202。所述空腔壁材料层201的材料为光刻胶，还可以是氧化硅、氮化硅、氮氧化硅等绝缘介质材料。在本发明的其他实施例中，所述凹槽结构可以包括位于所述第二基板200的第二表面200b内的凹槽。
本实施例中，所述基底300为晶圆，包括位于第一表面401的感应区301、围绕感应区301周围的若干分立排布的焊垫302、功能区(未示出)和硅衬底。所述感应区301为光学感应区，所述焊垫302作为感应区301内的器件与外部电路连接的输入/输出端。
在本发明的其他实施例中，所述基底300可以包括若干单元，每一单元对应形成有感应区301以及位于感应区301周围的若干焊垫302；相邻单元之间具有切割道，便于进行切割，形成多个芯片封装体。位于所述第二基板200的第二表面200b的凹槽结构具有若干凹槽，所述凹槽分别与若干单元上的若干感应区对应。
所述第二基板200的第二表面200b与基底300的第一表面401压合，所述空腔壁材料层201、第二基板200以及基底300之间构成空腔，所述空腔位置与第二基板200第一表面401上形成的感应区301相对应，使所述感应区301位于空腔内，而所述感应区301周围的焊垫302位于空腔外侧、所述基底300与空腔壁材料层201之间。所述感应区301受到所述第二基板200以及两侧的空腔壁材料层201的保护，从而避免所述感应区301受到损伤和污染。
请参考图12，在本发明的一个实施例中，所述封装结构还包括：位于基底300的第二表面402内的通孔，所述通孔底部暴露出焊垫302的部分表面；位于基底300的第二表面402以及通孔的侧壁表面的绝缘层311；位于所述绝缘层311表面连接焊垫302的金属层312；位于所述金属层312表面以及绝缘 层311表面具有开口的阻焊层313，所述开口暴露出部分金属层312表面；位于所述金属层312表面的外接凸起314，所述外接凸起314可以为焊球、金属柱等连接结构，可以采用铜、铝、金、锡或铅等金属材料。
请参考图13，在本发明的另一个实施例中，所述封装结构还可以包括：位于基底300的第二表面402内的通孔，所述通孔底部暴露出焊垫302的部分表面；位于基底300的第二表面402以及通孔的侧壁表面的绝缘层303；位于所述绝缘层303表面连接焊垫302的金属层304，所述金属层304填充通孔且表面与绝缘层303表面齐平；所述阻焊层305内的开口暴露出金属层304的顶部表面；在所述开口内形成连接金属层304顶部表面的外接凸起306，所述外接凸起可以为焊球、金属柱等连接结构，可以采用铜、铝、金、锡或铅等金属材料。
所述封装结构的基底300的第一表面401上的第二基板200厚度只有100μm～200μm，厚度较小，使所述封装结构的厚度较低，满足电子产品的薄化需求，而且，所述第二基板200能够对第一表面401上的感应区301起到足够的保护作用，避免所述感应区301受到损伤和污染。
本发明的技术方案提供一种封装方法，将第一基板的一侧表面和第二基板的第一表面通过粘胶层粘接，然后在第二基板的第二表面形成凹槽结构，并与基底的第一表面压合，所述凹槽结构与基底之间构成空腔，使所述基底表面的感应区位于所述空腔内。所述第一基板与第二基板构成双层的上盖基板结构，与基底压合后，可以在后续的封装过程中保护基底上的感应区。而且所述上盖基板为双层结构，便于后续去除其中的第一基板，降低形成的封装结构的厚度。
所述封装方法还包括对基底的第二表面进行封装处理，然后去除所述第一基板和粘胶层，使封装结构的厚度下降，并且保留的第二基板依然能够对感应区起到保护作用，从而确保所述封装结构的性能不受外界的影响。所述第二基板的厚度可以为100μm～200μm，由于所述第二基板最终保留在封装结构中，所以所述第二基板的厚度不能过大，否则会导致封装结构厚度不能满足电子产品的薄化要求；而所述第二基板的厚度也不能过小，如果所述第二基板的厚度小于100μm，会导致所述第二基板的强度较弱，能够承受的外应力下降，容易 发生碎裂，无法对封装结构内的感应区起到足够的保护作用，容易造成封装结构失效的问题。
所述粘胶层包括第一粘胶层和第二粘胶层，所述第一粘胶层为激光照射分解型粘胶层，在激光光照作用下能够使第一粘胶层的材料发生分解而失去粘性。所以，可以激光照射分解法对所述粘胶层进行处理，使所述粘胶层失去粘性，从而使第一基板从粘胶层表面脱落，以去除所述第一基板。采用上述方法去除第一基板，可以避免对所述封装结构其他部分的材料以及器件造成影响。
所述粘胶层还可以是热分解型粘胶层，在加热作用下能够使粘胶层的材料发生分解而失去粘性。所以，可以采用加热分解法对所述粘胶层进行处理，使所述粘胶层失去粘性，从而使第一基板从粘胶层表面脱落，以去除所述第一基板。采用上述方法去除第一基板，可以避免对所述封装结构其他部分的材料以及器件造成影响。
本发明的技术方案还提供一种采用上述方法形成的封装结构，所述封装结构包括第一基板和第二基板，所述第一基板的一侧表面和第二基板第一表面通过粘胶层粘接、位于所述第二基板第二表面的凹槽结构；所述第二基板的第二表面与基底的第一表面压合，所述凹槽结构与基底之间构成空腔，使所述基底上的感应区位于所述空腔内。所述第一基板和第二基板构成双层的上盖基板结构，便于后续去除其中的第一基板，降低形成的封装结构的厚度。而不需要采用刻蚀或研磨等工艺使所述上盖基板的厚度下降，从而在降低封装结构的厚度同时，确保保留的第二基板表面平整，其能够对感应区起到保护作用。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (27)

  1. 一种封装方法，其特征在于，包括：
    提供第一基板和第二基板，所述第二基板具有第一表面和与所述第一表面相对的第二表面，将所述第一基板的任一表面和第二基板的第一表面通过粘胶层粘接；
    在第二基板的第二表面形成凹槽结构；
    提供基底，所述基底具有第一表面和与所述第一表面相对的第二表面，所述基底的第一表面具有感应区以及位于感应区周围的若干焊垫；
    将所述第二基板的第二表面与基底的第一表面压合，所述凹槽结构与基底之间构成空腔，使所述感应区位于所述空腔内。
  2. 根据权利要求1所述的封装方法，其特征在于，还包括：将所述第二基板的第二表面与基底的第一表面压合之后，对基底的第二表面进行封装处理；去除所述第一基板以及粘胶层。
  3. 根据权利要求2所述的封装方法，其特征在于，所述对基底的第二表面进行的封装处理包括：对基底的第二表面进行减薄、刻蚀，形成通孔，所述通孔底部暴露出焊垫的部分表面；在基底的第二表面以及通孔的侧壁表面形成绝缘层；在所述绝缘层表面形成连接焊垫的金属层；在所述金属层表面以及绝缘层表面形成具有开口的阻焊层，所述开口暴露出部分金属层表面；在所述金属层表面形成外接凸起。
  4. 根据权利要求3所述的封装方法，其特征在于，所述金属层填充满所述通孔且表面与基底的第二表面齐平；所述阻焊层内的开口暴露出金属层的顶部表面；在所述开口内形成连接金属层顶部表面的外接凸起。
  5. 根据权利要求1所述的封装方法，其特征在于，所述第一基板的厚度为300μm～500μm。
  6. 根据权利要求1所述的封装方法，其特征在于，所述第二基板的厚度 为100μm～200μm。
  7. 根据权利要求1所述的封装方法，其特征在于，所述将所述第一基板的一侧表面和第二基板的第一表面通过粘胶层粘接的方法包括：在第一基板的一侧表面形成粘胶层，然后将第二基板的第一表面与所述粘胶层压合；或者在第二基板的第一表面形成粘胶层，然后将第一基板的任一表面与所述粘胶层压合。
  8. 根据权利要求1所述的封装方法，其特征在于，所述粘胶层包括第一粘胶层和第二粘胶层。
  9. 根据权利要求8所述的封装方法，其特征在于，将所述第一基板的一侧表面和第二基板的第一表面通过粘胶层粘接的方法包括：在第一基板的一侧表面形成第一粘胶层、在第二基板的第一表面形成第二粘胶层，或者在第一基板的一侧表面形成第二粘胶层、在第二基板的第一表面形成第一粘胶层；然后将所述第一基板和第二基板通过所述第一粘胶层、第二粘胶层压合。
  10. 根据权利要求7或8所述的封装方法，其特征在于，通过喷涂、旋涂或黏贴工艺形成所述粘胶层。
  11. 根据权利要求9所述的封装方法，其特征在于，
    若所述第一粘胶层为激光照射分解型粘胶层，则采用激光照射分解法对所述粘胶层进行处理，使所述粘胶层失去粘性，以去除所述第一基板；或者
    若所述粘胶层为加热分解型粘胶层，则采用加热分解法对所述粘胶层进行处理，使所述粘胶层失去粘性，以去除所述第一基板。
  12. 根据权利要求2所述的封装方法，其特征在于，通过对第二基板表面进行清洗，去除所述第二基板表面的粘胶层。
  13. 根据权利要求1所述的封装方法，其特征在于，所述凹槽结构的形成方法包括：
    在所述第二基板的第二表面上形成空腔壁材料层，刻蚀所述空腔壁材料层至第二基板表面，在所述空腔壁材料层内形成凹槽；或者
    对所述第二基板的第二表面进行刻蚀，在所述第二基板内形成凹槽。
  14. 根据权利要求1所述的封装方法，其特征在于，所述基底包括若干单元，每一单元对应形成有感应区以及位于感应区周围的若干焊垫；相邻单元之间具有切割道；所述第二基板未与第一基板压合的另一侧表面形成的凹槽结构具有若干凹槽，所述凹槽分别与若干单元上的若干感应区对应；在去除第一基板以及粘胶层之后，沿切割道对基底以及第一基板进行切割，形成若干芯片封装体。
  15. 一种封装结构，其特征在于，包括：
    第一基板和第二基板，所述第二基板具有第一表面和与所述第一表面相对的第二表面，所述第一基板的任一表面和第二基板的第一表面通过粘胶层粘接；
    位于所述第二基板的第二表面的凹槽结构；
    基底，所述基底具有第一表面和与所述第一表面相对的第二表面，所述基底的第一表面具有感应区以及位于感应区周围的若干焊垫；
    所述第二基板的第二表面与基底的第一表面压合，所述凹槽结构与基底之间构成空腔，所述感应区位于所述空腔内。
  16. 根据权利要求15所述的封装结构，其特征在于，所述第一基板的材料为玻璃、硅片、陶瓷或塑料。
  17. 根据权利要求15所述的封装结构，其特征在于，所述第一基板的厚度为300μm～500μm。
  18. 根据权利要求15所述的封装结构，其特征在于，所述第二基板的材料为透光材料。
  19. 根据权利要求15所述的封装结构，其特征在于，所述第二基板的厚度为100μm～200μm。
  20. 根据权利要求15所述的封装结构，其特征在于，所述粘胶层包括第一粘胶层和第二粘胶层。
  21. 根据权利要求20所述的封装结构，其特征在于，所述第一粘胶层位于第一基板表面，第二粘胶层位于第二基板的第一表面上；或者，所述第二粘胶层位于第一基板表面，所述第一粘胶层位于在第二基板的第一表面上。
  22. 根据权利要求20所述的封装结构，其特征在于，所述胶层为激光照射分解型粘胶层；或者所述粘胶层为加热分解型粘胶层。
  23. 根据权利要求15所述的封装结构，其特征在于，所述凹槽结构包括：
    所述第二基板的第二表面上的空腔壁材料层，位于所述空腔壁材料层内的凹槽；或者位于所述第二基板的第二表面内的凹槽。
  24. 根据权利要求15所述的封装结构，其特征在于，所述基底包括若干单元，每一单元对应形成有感应区以及位于感应区周围的若干焊垫；相邻单元之间具有切割道；位于所述第二基板未与第一基板压合的另一侧表面的凹槽结构具有若干凹槽，所述凹槽分别与若干单元上的若干感应区对应。
  25. 根据权利要求15所述的封装结构，其特征在于，还包括：位于基底的第二表面内的通孔，所述通孔底部暴露出焊垫的部分表面；位于基底的第二表面以及通孔的侧壁表面的绝缘层；位于所述绝缘层表面连接焊垫的金属层；位于所述金属层表面以及绝缘层表面具有开口的阻焊层，所述开口暴露出部分金属层表面；位于所述金属层表面的外接凸起。
  26. 根据权利要求25所述的封装结构，其特征在于，所述金属层填充满所述通孔且表面与绝缘层的表面齐平；所述阻焊层内的开口暴露出金属层的顶部表面；在所述开口内形成连接金属层顶部表面的外接凸起。
  27. 一种封装结构，其特征在于，包括：
    基板，所述基板具有第一表面和与所述第一表面相对的第二表面；
    位于所述基板的第二表面的凹槽结构；
    基底，所述基底具有第一表面和与所述第一表面相对的第二表面，所述基底的第一表面具有感应区以及位于感应区周围的若干焊垫；
    所述基板的第二表面与基底的第一表面压合，所述凹槽结构与基底之间构 成空腔，所述感应区位于所述空腔内；
    其中所述基板的厚度为100μm～200μm。
PCT/CN2015/090085 2015-02-13 2015-09-21 封装方法及封装结构 WO2016127645A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2017542891A JP2018505564A (ja) 2015-02-13 2015-09-21 パッケージ化方法およびパッケージ構造
KR1020177024914A KR20170108161A (ko) 2015-02-13 2015-09-21 패키징 방법 및 패키징 구조
US15/549,987 US10529758B2 (en) 2015-02-13 2015-09-21 Packaging method and packaging structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510079349.3 2015-02-13
CN201510079349.3A CN104637967A (zh) 2015-02-13 2015-02-13 封装方法及封装结构

Publications (1)

Publication Number Publication Date
WO2016127645A1 true WO2016127645A1 (zh) 2016-08-18

Family

ID=53216502

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/090085 WO2016127645A1 (zh) 2015-02-13 2015-09-21 封装方法及封装结构

Country Status (5)

Country Link
US (1) US10529758B2 (zh)
JP (1) JP2018505564A (zh)
KR (1) KR20170108161A (zh)
CN (1) CN104637967A (zh)
WO (1) WO2016127645A1 (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104637967A (zh) * 2015-02-13 2015-05-20 苏州晶方半导体科技股份有限公司 封装方法及封装结构
JP6564525B2 (ja) 2015-08-18 2019-08-21 蘇州晶方半導体科技股▲分▼有限公司Ｃｈｉｎａ Ｗａｆｅｒ Ｌｅｖｅｌ Ｃｓｐ Ｃｏ．， Ｌｔｄ． 半導体チップパッケージ構造およびそのためのパッケージング方法
CN105185751B (zh) * 2015-08-18 2018-08-24 苏州晶方半导体科技股份有限公司 半导体芯片封装结构及其封装方法
JP6557776B2 (ja) * 2015-09-02 2019-08-07 蘇州晶方半導体科技股▲分▼有限公司Ｃｈｉｎａ Ｗａｆｅｒ Ｌｅｖｅｌ Ｃｓｐ Ｃｏ．， Ｌｔｄ． パッケージ構造およびパッケージング方法
CN105118843B (zh) * 2015-09-02 2018-09-28 苏州晶方半导体科技股份有限公司 封装结构及封装方法
DE102015120647B4 (de) * 2015-11-27 2017-12-28 Snaptrack, Inc. Elektrisches Bauelement mit dünner Lot-Stopp-Schicht und Verfahren zur Herstellung
KR102431750B1 (ko) * 2016-03-04 2022-08-12 삼성디스플레이 주식회사 플렉서블 표시장치 및 그의 제조방법
JP6768394B2 (ja) * 2016-07-29 2020-10-14 株式会社ジャパンディスプレイ 電子機器
US9996725B2 (en) * 2016-11-03 2018-06-12 Optiz, Inc. Under screen sensor assembly
KR102430496B1 (ko) 2017-09-29 2022-08-08 삼성전자주식회사 이미지 센싱 장치 및 그 제조 방법
CN108962772B (zh) * 2018-07-19 2021-01-22 通富微电子股份有限公司 封装结构及其形成方法
CN110783317A (zh) * 2019-10-11 2020-02-11 安徽国晶微电子有限公司 感光芯片封装结构
CN116721932B (zh) * 2023-08-08 2023-11-14 苏州科阳半导体有限公司 一种传感器芯片的封装方法和封装结构

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1428868A (zh) * 2001-12-27 2003-07-09 精工爱普生株式会社 光器件及其制造方法、光模件、电路基板以及电子机器
US20090152658A1 (en) * 2007-12-18 2009-06-18 Todd Bolken Methods of packaging imager devices and optics modules, and resulting assemblies
CN101569012A (zh) * 2006-12-28 2009-10-28 富士胶片株式会社 制造固态成像装置的方法
CN102150269A (zh) * 2008-09-11 2011-08-10 富士胶片株式会社 用于制造固态成像装置的方法
US20120148186A1 (en) * 2010-12-08 2012-06-14 Stmicroelectronics (Grenoble 2) Sas Process for fabricating semiconductor devices and semiconductor devices
CN102610624A (zh) * 2012-03-13 2012-07-25 苏州晶方半导体股份有限公司 半导体封装方法
CN102623471A (zh) * 2012-03-27 2012-08-01 格科微电子（上海）有限公司 图像传感器的封装方法
CN202523711U (zh) * 2012-03-13 2012-11-07 苏州晶方半导体科技股份有限公司 半导体封装结构及封装模组
CN103137632A (zh) * 2011-11-21 2013-06-05 奥普蒂兹公司 用于cmos图像传感器的内插板封装及其制造方法
CN103904093A (zh) * 2014-04-01 2014-07-02 苏州晶方半导体科技股份有限公司 晶圆级封装结构以及封装方法
CN203967091U (zh) * 2014-04-01 2014-11-26 苏州晶方半导体科技股份有限公司 晶圆级封装结构
CN104637967A (zh) * 2015-02-13 2015-05-20 苏州晶方半导体科技股份有限公司 封装方法及封装结构
CN204497233U (zh) * 2015-02-13 2015-07-22 苏州晶方半导体科技股份有限公司 封装结构

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100738653B1 (ko) * 2005-09-02 2007-07-11 한국과학기술원 이미지 센서 모듈용 웨이퍼 레벨 칩 사이즈 패키지 및 이의제조방법
JP5070757B2 (ja) * 2006-08-01 2012-11-14 大日本印刷株式会社 センサーチップの製造方法
JP5334411B2 (ja) 2007-12-30 2013-11-06 株式会社フジクラ 貼り合わせ基板および貼り合せ基板を用いた半導体装置の製造方法

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1428868A (zh) * 2001-12-27 2003-07-09 精工爱普生株式会社 光器件及其制造方法、光模件、电路基板以及电子机器
CN101569012A (zh) * 2006-12-28 2009-10-28 富士胶片株式会社 制造固态成像装置的方法
US20090152658A1 (en) * 2007-12-18 2009-06-18 Todd Bolken Methods of packaging imager devices and optics modules, and resulting assemblies
CN102150269A (zh) * 2008-09-11 2011-08-10 富士胶片株式会社 用于制造固态成像装置的方法
US20120148186A1 (en) * 2010-12-08 2012-06-14 Stmicroelectronics (Grenoble 2) Sas Process for fabricating semiconductor devices and semiconductor devices
CN103137632A (zh) * 2011-11-21 2013-06-05 奥普蒂兹公司 用于cmos图像传感器的内插板封装及其制造方法
CN102610624A (zh) * 2012-03-13 2012-07-25 苏州晶方半导体股份有限公司 半导体封装方法
CN202523711U (zh) * 2012-03-13 2012-11-07 苏州晶方半导体科技股份有限公司 半导体封装结构及封装模组
CN102623471A (zh) * 2012-03-27 2012-08-01 格科微电子（上海）有限公司 图像传感器的封装方法
CN103904093A (zh) * 2014-04-01 2014-07-02 苏州晶方半导体科技股份有限公司 晶圆级封装结构以及封装方法
CN203967091U (zh) * 2014-04-01 2014-11-26 苏州晶方半导体科技股份有限公司 晶圆级封装结构
CN104637967A (zh) * 2015-02-13 2015-05-20 苏州晶方半导体科技股份有限公司 封装方法及封装结构
CN204497233U (zh) * 2015-02-13 2015-07-22 苏州晶方半导体科技股份有限公司 封装结构

Also Published As

Publication number Publication date
JP2018505564A (ja) 2018-02-22
KR20170108161A (ko) 2017-09-26
CN104637967A (zh) 2015-05-20
US10529758B2 (en) 2020-01-07
US20180047772A1 (en) 2018-02-15

Similar Documents

Publication Publication Date Title
WO2016127645A1 (zh) 封装方法及封装结构
US10276540B2 (en) Chip packaging method and chip packaging structure
TWI629759B (zh) 晶片封裝體及其製造方法
JP6315859B2 (ja) 撮像装置、半導体装置および撮像ユニット
US7875481B2 (en) Semiconductor apparatus and method for manufacturing the same
TWI642149B (zh) 晶片封裝體及其製造方法
US9799588B2 (en) Chip package and manufacturing method thereof
US20130307137A1 (en) Chip package and method for forming the same
US20170148756A1 (en) Semiconductor structure and method of manufacturing the same
TW201742200A (zh) 晶片封裝體及其製造方法
WO2017206795A1 (zh) 封装结构及封装方法
TWI503933B (zh) 半導體封裝件及其製法
TWI739697B (zh) 晶片封裝體及其製造方法
TWI612624B (zh) 封裝結構及封裝方法
US8748926B2 (en) Chip package with multiple spacers and method for forming the same
TW201711147A (zh) 封裝結構及其封裝方法
CN204497233U (zh) 封装结构
JP4008931B2 (ja) 半導体装置及びその製造方法
TWI612651B (zh) 封裝結構及封裝方法
CN111627857A (zh) 封装方法及封装结构
US20240178261A1 (en) Chip package and method for forming the same
TW202412294A (zh) 影像感測器封裝結構及相關方法
TW202422866A (zh) 晶片封裝體及其製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15881795

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2017542891

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 15549987

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20177024914

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 15881795

Country of ref document: EP

Kind code of ref document: A1