WO2016123982A1 - 薄膜晶体管的制备方法及薄膜晶体管、阵列基板 - Google Patents

薄膜晶体管的制备方法及薄膜晶体管、阵列基板 Download PDF

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WO2016123982A1
WO2016123982A1 PCT/CN2015/089829 CN2015089829W WO2016123982A1 WO 2016123982 A1 WO2016123982 A1 WO 2016123982A1 CN 2015089829 W CN2015089829 W CN 2015089829W WO 2016123982 A1 WO2016123982 A1 WO 2016123982A1
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composite film
film layer
layer
substrate
thin film
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PCT/CN2015/089829
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English (en)
French (fr)
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冯翔
魏向东
刘静
邱云
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US14/913,314 priority Critical patent/US20160351813A1/en
Publication of WO2016123982A1 publication Critical patent/WO2016123982A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H10K10/488—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising a layer of composite material having interpenetrating or embedded materials, e.g. a mixture of donor and acceptor moieties, that form a bulk heterojunction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/15—Deposition of organic active material using liquid deposition, e.g. spin coating characterised by the solvent used
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates

Definitions

  • the present disclosure belongs to the field of display technologies, and in particular, to a method for fabricating a thin film transistor and a thin film transistor and an array substrate.
  • OFT Organic Thin Film Transistor
  • the technical problem to be solved by the present disclosure is to provide a method for fabricating a thin film transistor and a thin film transistor and an array substrate according to the above-mentioned deficiencies in the prior art, the method for preparing the organic thin film transistor in forming a organic semiconductor layer during patterning
  • the film formation synchronization between the active layer patterns is strictly ensured, and the film formation difference between the active layer patterns of the respective organic thin film transistors on the substrate is eliminated or reduced.
  • the preparation method may include the following steps:
  • the patterned composite film layer is layered by an organic solvent vapor treatment method
  • Separate two metal electrodes are formed on opposite sides of the patterned composite film layer.
  • the patterned composite film layer may be layered into an organic semiconductor layer on top and a polymer insulation layer underneath by an organic solvent vapor treatment method; at least one end of the metal electrode is located at the organic semiconductor Above the layer.
  • the substrate may be an n-type phosphorus doped substrate having a silicon dioxide insulating layer on its surface.
  • forming a pattern comprising different surface energies over the substrate can include:
  • the self-assembled monolayer is patterned to form a pattern of grid-like structures of different surface energies over the substrate.
  • the method of forming the self-assembled monolayer may include: immersing the substrate in a solution containing a monomolecular material in an anhydrous argon or nitrogen atmosphere, the single molecule A hydrophobic group of the material is assembled on the surface of the silica insulating layer.
  • the method of performing hydrophobic group assembly on the substrate may include: immersing the substrate with a solution comprising octadecyltrichlorosilane, the soaking time is in the range of 1.5-2.5 h; wherein, dissolving The solvent of octadecyltrichlorosilane was toluene and the solution concentration was 10 mg/ml.
  • the method of patterning the self-assembled monolayer may include a UV ozone cleaning method of a metal mask, a UV ozone cleaning method with photoresist protection, and a plasma protected by a photoresist. Any one of a bulk method or a polydimethylsiloxane microcontact method.
  • the solvent is a solvent capable of simultaneously dissolving the organic semiconductor material and the polymer insulating material
  • the organic semiconductor material may be a crystallizable small molecule semiconductor material.
  • the organic semiconductor material may include any one of TES-ADT, TIPS_PEN, BTBT, DATT or DNTT
  • the insulating material may include polymethyl methacrylate or polystyrene.
  • the composite solution may be formed into a composite film layer by a spin coating method, wherein:
  • the solvent is a low boiling point organic solvent having a boiling temperature range of 60-150 ° C, and the spin coating speed of the composite solution containing the low boiling organic solvent is ⁇ 3500 rpm, and the rotation time ranges from 15 to 20 s;
  • the solvent is a high boiling organic solvent having a boiling temperature range of 150 to 250 ° C, and the spin coating speed of the composite solution containing the high boiling organic solvent is ⁇ 5000 rpm, and the rotation time ranges from 15 to 20 s.
  • the low boiling organic solvent may be any one or any combination of chloroform, tetrahydrofuran, toluene, o-xylene, p-xylene, m-xylene, chlorobenzene;
  • the high boiling organic solvent may be any one of 1,2 dichlorobenzene, 1,2,4 trichlorobenzene, dimethyl sulfoxide or any combination thereof.
  • the mass ratio of the organic semiconductor material may be less than or equal to the mass ratio of the polymer insulating material.
  • the mass ratio of the organic semiconductor material to the polymer insulating material may range from 1:99 to 1:4.
  • the concentration of the composite solution is 12.5 mg/ml.
  • patterning the composite film layer may be achieved by removing the composite film layer above the pattern region corresponding to a relatively low surface energy, comprising: pasting a sticky tape over the composite film layer The composite film layer above the pattern region having a relatively low surface energy is physically stripped by the tape.
  • the method before the patterning of the composite film layer, the method further includes:
  • An adhesive tape is pasted over the sacrificial layer, the sacrificial layer is physically peeled off by the tape, and the composite film layer over the relatively low pattern area is simultaneously peeled off.
  • the sacrificial layer may be formed by spin coating a solution comprising polymethyl methacrylate and/or polystyrene, dissolving polymethyl methacrylate and/or poly
  • the solvent for styrene is n-butyl acetate.
  • the solution may include polymethyl methacrylate having a molar mass of 120 kg/mol and/or polystyrene having a molar mass of 200 kg/mol.
  • the concentration of the solution may range from 70 to 90 mg/ml
  • spin coating ranges from 1800 to 2200 rpm
  • the rotational time ranges from 50 to 70 s
  • the sacrificial layer thickness ranges from 400 to 600 nm.
  • the solution may have a concentration of 80 mg/ml, a spin coating speed of 2000 rpm, a spin time of 60 s, and a sacrificial layer thickness of 500 nm.
  • a step of thermally curing the sacrificial layer may be further included, the temperature of the sacrificial layer being thermally cured is in the range of 70-90 ° C, and the heat curing time is in the range of 20-40 min.
  • the temperature at which the sacrificial layer is thermally cured may be 80 ° C and the heat curing time is 30 min.
  • layering the patterned composite film layer by an organic solvent vapor treatment method may include:
  • the organic semiconductor material moves over the patterned composite film layer and crystal grains increase during upward movement, the polymer insulating material moving below the patterned composite film layer.
  • the organic solvent may be any one of 1,2-dichloroethane, toluene, chlorobenzene, and chloroform.
  • the step of thermally curing the composite film layer may be further included, and the temperature of the composite film layer is thermally cured to a temperature range of 140-160 ° C, and the curing time range is It is 8-12min.
  • the temperature at which the composite film layer is thermally cured may be 150 ° C and the heat curing time is 10 min.
  • the two separated metal electrodes may be a source and a drain, and the metal electrode is formed by depositing a metal material through a metal mask, and between the source and the drain.
  • the separation region forms a channel region.
  • the source and the drain may have a thickness ranging from 60 to 100 nm; the channel region has a length ranging from 80 to 100 ⁇ m and a width ranging from 700 to 900 ⁇ m.
  • a second aspect of the present disclosure provides a thin film transistor formed using the above-described method of fabricating a thin film transistor.
  • a third aspect of the invention provides an array substrate which may include the above-described thin film transistor.
  • the beneficial effects of the present disclosure include: a method for preparing the thin film transistor, in the process of patterning the organic semiconductor layer, strictly ensuring film formation synchronization between active layer patterns, eliminating or reducing individual organic thin film transistors on the substrate The film formation difference between the active layer patterns ensures the device performance of the organic thin film transistor.
  • FIG. 1 is a flow chart of a method of fabricating a thin film transistor in accordance with an embodiment of the present disclosure
  • FIG. 2 is a schematic view of forming a pattern including different surface energies over a substrate in accordance with an embodiment of the present disclosure
  • 3A and 3B are schematic views of forming a composite film layer according to an embodiment of the present disclosure.
  • 4A and 4B are schematic views of removing a composite film layer above a pattern region corresponding to a relatively low surface energy according to an embodiment of the present disclosure
  • 5A and 5B are schematic views of layering a composite film layer by an organic solvent vapor treatment method according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of an organic thin film transistor formed over a substrate in accordance with an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a single organic thin film transistor according to an embodiment of the present disclosure.
  • the present disclosure provides a method of fabricating a thin film transistor and a thin film transistor formed by the method for fabricating the thin film transistor, which is an organic thin film transistor.
  • the thin film transistor is prepared by using a silicon wafer with a silicon dioxide insulating layer as a substrate, a silicon wafer as a gate of an organic thin film transistor device, a silicon oxide insulating layer of a silicon wafer and a polymer insulating material.
  • the insulating layer serves as a gate insulating layer of the organic thin film transistor device, and the organic semiconductor layer functions as an active layer of the organic thin film transistor device, and then forms a source and a drain of the organic thin film transistor device.
  • the film formation is synchronized between the active layer patterns of the organic thin film transistor device on the substrate, thereby eliminating or reducing the film formation difference between the respective active layer patterns on the substrate, thereby ensuring the device performance of the organic thin film transistor array.
  • the preparation method specifically includes the following steps:
  • step S1 a pattern including different surface energies is formed over the substrate.
  • FIG. 2 is a schematic view showing the formation of patterns including different surface energies on the substrate 1, wherein the different surface energies are determined by the patterned Self-Assembled Monolayer 2 (hereinafter referred to as SAM layer).
  • the substrate 1 is an n-type phosphorus doped substrate (not shown in FIG. 2) having a silicon dioxide insulating layer on the surface, and the thickness of the silicon dioxide insulating layer ranges from 200 to 400 nm.
  • forming a pattern including different surface energies over the substrate 1 includes:
  • a self-assembled monolayer that is covalently bonded to the substrate 1 is formed over the substrate 1, wherein the self-assembled single molecule is a single molecule with a hydrophobic group.
  • the self-assembled single molecule is a surfactant, and the organic thin film transistor will play an auxiliary role in the subsequent formation of the active layer.
  • the method for forming a self-assembled monolayer comprises: immersing the substrate 1 in a solution containing a monomolecular material in an anhydrous argon (or nitrogen) environment, so that the hydrophobic group of the monomolecular material is assembled in the dioxide The surface of the silicon insulation layer.
  • the method for performing hydrophobic group assembly on the substrate 1 comprises: immersing the hydroxylated clean substrate 1 with a solution comprising octadecyltrichlorosilane OTS, the soaking time is in the range of 1.5-2.5 h;
  • the solvent of octadecyltrichlorosilane was toluene and the solution concentration was 10 mg/ml.
  • the self-assembled monolayer is patterned to form a pattern of lattice-like structures of different surface energies over the substrate 1, that is, the patterned self-assembled monolayer 2.
  • the method of patterning the self-assembled monolayer includes a UV mask cleaning method of a metal mask, a UV-OZONE method, a UV-OZONE method with photoresist protection, and a plasma plasma protected by a photoresist.
  • any of the polydimethylsiloxane PDMS microcontact methods One. According to the process requirements, the method of the patterning process may select any one of the above methods, which is not limited herein.
  • the SAM layer is a monomolecular layer with a hydrophobic group
  • the surface energy of the SAM layer region on the substrate 1 is relatively low, and the surface energy of the substrate layer 1 without the SAM layer region is relatively high.
  • the surface area of the substrate 1 assembled with the self-assembled monolayer is relatively low, the hydrophilicity is weak, the hydrophobicity is strong, and the adhesion is small; the surface energy of the region without the self-assembled monolayer on the substrate 1 is relatively high, Strong hydrophilicity, weak hydrophobicity and high adhesion.
  • the self-assembled monolayer here uses octadecyltrichlorosilane and is not recommended to use octadecyltrichlorosilane and Perfluorosilane; at the same time, as long as a micropattern with relatively high surface energy/relatively low surface energy can be obtained on the substrate 1, the preparation method is not limited to the metal mask and the UV-OZONE method. Photoresist protection method, PDMS micro-contact method and the like are used, and are not limited herein.
  • a composite solution 30 containing an organic semiconductor material and a polymer insulating material is coated over the substrate 1, and a composite film layer 31 is formed.
  • the solvent in the composite solution 30 is a solvent capable of simultaneously dissolving the organic semiconductor material and the polymer insulating material
  • the organic semiconductor material includes any of TES-ADT, TIPS_PEN, BTBT, DATT or DNTT.
  • the polymer insulating material comprises polymethyl methacrylate PMMA or polystyrene PS.
  • the organic semiconductor material and the polymer insulating material may be selected from any of the above materials, or other materials having the same properties as those of the above materials, and are not limited herein.
  • the organic semiconductor material herein is, for example, a small molecule semiconductor material that can be crystallized, such as TES-ADT, TIPS_PEN, BTBT, DATT, DNTT, etc., the names of TES-ADT, TIPS_PEN, BTBT, DATT, DNTT, and a simplified structure.
  • TES-ADT TES-ADT
  • TIPS_PEN TIPS_PEN
  • BTBT DATT
  • DNTT DNTT
  • TES-ADT is 5,11-Bis(triethylsilylethynyl)anthradithiophene, and its structure is as follows:
  • TIPS_PEN is 6,13-Bis(triisopropylsilylethynyl)pentacene
  • Chinese name is TIPS-pentacene
  • its structure is as follows:
  • BTBT is benzothienobenzothiophene
  • the derivative of the molecule is a molecular material of a BTBT type molecule and a derivative thereof, and the derivative has a molecular formula of C n -BTBT, wherein 3 ⁇ n ⁇ 12.
  • C 8 -BTBT is one of its derivatives, the name is 2,7-Dioctyl[1]benzothieno[3,2-b][1]benzothiophene, and the structure is as follows:
  • DATT is dianthra[2,3-b:2',3'-f]thieno[3,2-b]thiophene, and the structure is as follows:
  • DNTT Dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene, and the structure is as follows:
  • the derivative of DNTT has the general formula C n -DNTT, where 3 ⁇ n ⁇ 12.
  • C 10 -DNTT is one of its derivatives, the name is 2,9-didecyldi-naphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene(C 10 - DNTT), the structure is as follows:
  • the polymer insulating material may use a conventional polymer material such as polymethyl methacrylate PMMA having a molar mass of 996 kg/mol, polystyrene PS having a molar mass of 200 kg/mol, or the like.
  • the mass ratio relationship between the organic semiconductor material and the polymer insulating material in the composite solution 30 it is desirable to make the polymer insulating material excessive, that is, the mass ratio of the organic semiconductor material is less than or equal to the mass of the polymer insulating material.
  • the ratio is such that the polymer insulating material encapsulates the small molecules of the organic semiconductor material during the spin coating process.
  • the mass ratio of the organic semiconductor material to the polymer insulating material is 1:99 to 1:4, that is, 1 part by mass of the organic semiconductor material may be matched with 4 to 99 parts by mass of the polymer insulating material.
  • the mass ratio of the organic semiconductor material and the polymer insulating material can be selected from the above mass ratios. Any one is not limited here.
  • the mass ratio of the organic semiconductor material to the polymer insulating material is 1:4, the concentration of the composite solution 30 is 12.5 mg/ml.
  • the composite solution 30 forms a composite film layer 31 by a spin coating method
  • the solvent is an organic solvent having a boiling temperature range of 60-250 ° C, wherein:
  • the solvent is a low boiling organic solvent having a boiling temperature range of 60-150 ° C, and the spin coating speed of the composite solution 30 containing a low boiling organic solvent is ⁇ 3500 rpm, and the rotation time ranges from 15 to 20 s.
  • the low boiling organic solvent is any one or any combination of chloroform, tetrahydrofuran, toluene, o-xylene, p-xylene, m-xylene, chlorobenzene;
  • the solvent is a high boiling organic solvent having a boiling temperature in the range of 150 to 250 ° C, and the spin coating speed of the composite solution 30 containing the high boiling organic solvent is ⁇ 5000 rpm, and the rotation time ranges from 15 to 20 s.
  • the high boiling organic solvent is any one or a combination of any of 1,2 dichlorobenzene, 1,2,4 trichlorobenzene, and dimethyl sulfoxide.
  • the solvent may be an organic solvent having a relatively low boiling point and capable of dissolving a two-component material of an organic semiconductor material and a polymer insulating material.
  • a high rotational speed can be considered, so that the composite solution 30 can be rapidly formed into a composite film layer 31, while not giving sufficient phase separation time for the organic semiconductor material and the polymer insulating material, blocking the organic semiconductor material and The polymer insulation forms a clear layer of interface.
  • the rotation time of the mixed solution may be the same as the rotation time of the mixed solution of the solvent having a lower boiling point, and at this time, spin coating of the mixed solution of the solvent having a lower spin rate than the solvent having a lower boiling point
  • the high rotation speed, the mixed solution has formed a composite film layer and solidified during the spin coating process, and can also block the sufficient phase separation of the organic semiconductor material and the polymer insulating material.
  • the solvent may be selected from any of the above materials, and the corresponding spin coating speed and rotation time are selected to form the composite film layer 31 of different thicknesses, which is not limited herein.
  • the prepared composite film layer 31 has a thickness ranging from 50 to 100 nm.
  • the organic semiconductor material partially realizes crystallization, but there is no clear interface between the organic semiconductor material and the polymer insulating material.
  • the step of thermally curing the composite film layer 31 is further included before the patterning of the composite film layer 31, and the heat curing composite
  • the temperature of the film layer 31 ranges from 140 to 160 ° C, and the heat curing time ranges from 8 to 12 minutes.
  • the composite solution 30 is spin-coated on the substrate 1 and the patterned self-assembled monolayer 2 which have been pretreated; as shown in FIG. 3B, after the spin coating and curing process, the composite solution 30 is as shown in FIG. 3B.
  • a composite film layer 31 is formed.
  • heat treatment with a hot stage at 150 ° C for 10 minutes was performed to strengthen the connection of the composite film layer 31 to the substrate 1.
  • the composite film layer 31 is patterned according to the pattern of different surface energies above the substrate 1, and the composite film layer 31 corresponding to the pattern region having a relatively high surface energy is retained.
  • the patterned composite film layer 31 is realized by removing the composite film layer 31 corresponding to the pattern region having a relatively low surface energy.
  • the corresponding surface energy can be removed by using different physical peeling methods.
  • the composite film layer 31 above the lower pattern area retains the composite film layer 31 corresponding to the relatively high pattern area of the surface energy to form the patterned composite film layer 32. It should be noted that the relatively high and relatively low surface energy values can be set as desired.
  • a relatively simple removal method is: a sticky adhesive tape is pasted on the composite film layer 31, and the composite film layer 31 above the pattern region corresponding to the relatively low surface energy is physically stripped by the tape to form a patterned composite film layer 32.
  • the physical peeling is performed by using a 3M tape. Since the adhesion of the composite film layer 31 to the region of the substrate 1 without the SAM layer is large (very strong), it is not easily peeled off; and the composite film layer 31 and the substrate 1 have SAM. The layer adhesion of the layer is small (very weak), so it is easily peeled off, resulting in a patterned composite film layer 32. In this manner, since the adhesive tape usually contains a polymer, the polymer may have a certain influence on the organic semiconductor material in the composite film layer 31.
  • Another alternative way of removing the composite film layer 31 above the pattern region having a relatively low surface energy is to form a sacrificial layer over the composite film layer 31, and then simultaneously removing the sacrificial layer and correspondingly through the tape.
  • the composite film layer 31 above the pattern region having a relatively low surface energy is present. That is, before removing the composite film layer 31 corresponding to the pattern region having a relatively low surface energy, the method further includes:
  • a sacrificial layer 4 is prepared over the composite film layer 31.
  • the sacrificial layer 4 is formed by spin coating a solution, and the solution comprises polymethyl methacrylate PMMA and/or polystyrene PS, and the solvent for dissolving polymethyl methacrylate PMMA and/or polystyrene PS is N-butyl acetate.
  • the solution for preparing the sacrificial layer 4 may be selected from any one or both of the above materials, or other materials having the same properties as the above materials, which are not limited herein.
  • the solution therein may include polymethyl methacrylate having a molar mass of 120 kg/mol.
  • PMMA or polystyrene PS having a molar mass of 200 kg/mol may also include polymethyl methacrylate PMMA having a molar mass of 120 kg/mol or polystyrene PS having a molar mass of 200 kg/mol;
  • the ester solvent does not affect the organic semiconductor material in the composite film layer 31, and the dissolution of the solvent on the composite film layer 31 in the preparation of the sacrificial layer 4 can be reduced, and the performance of the subsequently formed active layer can be ensured.
  • the concentration of the solution ranges from 70 to 90 mg/ml
  • the spin speed ranges from 1800 to 2200 rpm
  • the spin time ranges from 50 to 70 s
  • the sacrificial layer 4 thickness ranges from 400 to 600 nm.
  • the solution may be prepared at a concentration of 80 mg/ml, a spin coating speed of 2000 rpm, and a spin time of 60 s, and the thickness of the sacrificial layer 4 obtained is about 500 nm.
  • the solvent can be sufficiently volatilized by thermal curing while enhancing the adhesion between the sacrificial layer 4 and the composite film layer 31. That is, after the formation of the sacrificial layer 4, the step of thermally curing the sacrificial layer 4 is further included, and the temperature of the thermally cured sacrificial layer 4 is in the range of 70 to 90 ° C, and the thermal curing time is in the range of 20 to 40 min. Specifically, the heat curing temperature may be 80 ° C, and the heat curing treatment time is 30 min, which promotes planarization of the sacrificial layer 4 and connection with the composite film layer.
  • a tape 5 having adhesiveness is pasted over the sacrificial layer 4, the sacrificial layer 4 is physically peeled off by the tape 5, and the composite film layer 31 above the pattern region having a relatively low surface energy is simultaneously peeled off.
  • the physical peeling is performed by using the 3M tape 5, since the adhesive force of the composite film layer 31 and the SAM-free region on the substrate 1 is large (very strong), it is not easily peeled off; and the composite film layer 31 and the substrate 1 have SAM.
  • the area adhesion is very small (very weak), so it is easily peeled off.
  • the tape 5 is torn in the direction of the arrow, and the composite film layer 31 is peeled off along the cross section of the black line to obtain a patterned composite film layer 32 as shown in Fig. 4B.
  • the two components of the organic semiconductor material and the polymer insulating material in the composite film layer 31 at this time The phase separation is incomplete, so that the composite film layer 31 can be regarded as a whole, and the two components of the composite film layer 31 are not separated in the peeling process.
  • the composite film layer 31 is layered by an organic solvent vapor treatment.
  • the inside of the patterned composite film layer 32 is moved by the organic solvent vapor treatment method, so that the organic semiconductor material and the polymer insulating material form the organic semiconductor layer 34 on the upper side and the polymer insulating layer 33 is on the lower side. structure.
  • layering the patterned composite film layer 32 by an organic solvent vapor treatment method includes:
  • the substrate 1 is placed in a closed environment containing an organic solvent.
  • the organic solvent is any one of 1,2-dichloroethane, toluene, chlorobenzene, and chloroform.
  • the organic solvent may be selected from any of the above materials according to the needs of the process, and is not limited herein.
  • the patterned composite film layer 32 shown in Fig. 4B is placed in a closed environment and an organic solvent vapor environment 7 is created, as shown in Fig. 5A.
  • the sealed environment here may be an evacuatable glass container, and the organic solvent is placed in the glass container; the organic solvent needs to meet the requirements of simultaneously dissolving the organic semiconductor material and the polymer insulating material, and the optional organic solvent is 1,2- As the dichloroethane, a common organic solvent such as toluene, chlorobenzene, chloroform or the like can also be used.
  • the closed environment is evacuated to vaporize the organic solvent to form a closed steam environment.
  • a vapor atmosphere is provided in the glass vessel by vacuuming the enclosed environment to create an organic solvent vapor environment 7, i.e., vaporizing the organic solvent in a vacuum environment.
  • the sealed environment filled with an organic solvent provided herein allows the organic solvent to be immersed in the patterned composite film layer 32 to complete the steam annealing.
  • the organic semiconductor material slowly moves over the patterned composite film layer 32 and the crystal grains increase during the upward movement, and the polymer insulation material moves below the patterned composite film layer 32.
  • the phase separation of the organic semiconductor phase from the polymer insulating layer phase is more thorough than before the organic solvent vapor treatment.
  • the phase separation of the organic semiconductor material and the polymer insulating material in the patterned composite film layer 32 is incomplete; the steam of the organic solvent is immersed by steam annealing.
  • the organic semiconductor material is moved over the patterned composite film layer 32, and the polymer insulating material is moved below the patterned composite film layer 32 to promote phase separation of the composite film layer.
  • the patterned composite film layer 32 is layered to form the structure in which the organic semiconductor layer 34 is formed and the polymer insulating layer 33 is underneath in FIG. 5B; The organic semiconductor material crystallizes rapidly during the upward movement to increase the grain size, so that the film formation performance of the organic semiconductor layer 34 in the patterned composite film layer 32 is better.
  • the physical stripping process and the steam annealing process are combined, the patterned composite film layer 32 is physically stripped off, and the patterned composite film layer 32 is further phase-separated by steam annealing to complete the organic semiconductor layer 34.
  • the polymer insulating layer 33 has a two-layer structure at the lower portion.
  • step S5 separate metal electrodes are formed on opposite sides of the patterned composite film layer 32.
  • one end of any of the metal electrodes is located above the organic semiconductor layer 34, and the other end is located above the pattern region where the surface energy is relatively low.
  • the position of the above metal electrode is only an example; according to the structure of the thin film transistor, at least one end of the metal electrode may be located above the organic semiconductor layer, and the other end may be located above the pattern region where the surface energy is relatively low, or may be located at the corresponding surface
  • the upper layer structure of the relatively lower pattern region is not limited herein. In the actual preparation process, the layer structure corresponding to the pattern region corresponding to the relatively low surface energy can be adjusted according to the needs of the thin film transistor structure.
  • the two separated metal electrodes are a source 61 and a drain 62.
  • the source 61 and the drain 62 are both formed of a gold material, deposited by a metal mask, and between the source 61 and the drain 62.
  • the separated regions form a channel region.
  • source 61 and drain 62 have a thickness in the range of 60-100 nm; the channel region has a length in the range of 80-100 ⁇ m and a width in the range of 700-900 ⁇ m. Specifically, the channel width may be 800 ⁇ m.
  • FIG. 7 is a schematic structural view of a single organic thin film transistor formed by the above-described method for fabricating a thin film transistor using a silicon wafer with a silicon dioxide insulating layer as a substrate 1. Since the silicon wafer is electrically conductive, it can be directly The silicon wafer is used as a gate of the organic thin film transistor device; the preparation of the organic semiconductor layer 34 and the polymer insulating layer 33 is completed by a patterned self-assembled monolayer, a physical lift-off method, and an organic solvent vapor treatment method.
  • the silicon dioxide insulating layer and the polymer insulating layer 33 serve as a gate insulating layer of the organic thin film transistor device, and the organic semiconductor layer 34 serves as an active layer of the organic thin film transistor device; subsequently, the patterned organic semiconductor layer 34 and the polymer insulating layer Above the 33, a metal mask is vapor-deposited to form separate metal electrodes and a channel is formed, thereby completing an organic thin film transistor in which a bottom gate is in contact (contact with the active layer).
  • Embodiments of the present disclosure also provide an array substrate including the above organic thin film transistor.
  • the array substrate can be arranged by using a plurality of organic thin film transistors prepared by the preparation method of the organic thin film transistor of the first embodiment, and the plurality of organic thin film transistors are arranged in an array, and further forming gate lines and data lines disposed vertically and horizontally; Then, the pixel electrode or the like can be formed by using an existing process to form a liquid crystal type array substrate, or can be prepared to form an OLED. The device or the like forms an OLED type array substrate.
  • the pattern of the patterned self-assembled monolayer is complementary to the pattern of the gate of the organic thin film transistor.
  • the array substrate can be prepared to form an OLED display panel, a TN type (Twisted Nematic) liquid crystal display panel, a VA type (Vertical Alignment) liquid crystal display panel, and an ADS type (ADvanced Super Dimension Switch). Technology)
  • the array substrate in the liquid crystal display panel is not limited herein. Therefore, any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like can be formed.
  • the technical effect of patterning and phase separation of the organic semiconductor/polymer insulating composite material is achieved by a combination of a physical stripping process and a steam annealing process, namely: physical first
  • the patterned composite film layer is peeled off, and the phase separation of the organic semiconductor material and the polymer insulating material in the composite film layer is promoted by steam annealing, and the double layer structure of the upper portion of the organic semiconductor layer and the lower portion of the polymer insulating layer is completed.
  • the organic thin film transistor formed by the preparation method of the thin film transistor has better performance, so that the array substrate including the organic thin film transistor has better display performance.

Abstract

一种薄膜晶体管的制备方法及薄膜晶体管和阵列基板。该薄膜晶体管的制备方法包括：在基底（1）上方形成包括不同表面能的图案；将含有有机半导体材料和聚合物绝缘材料的复合溶液（30）涂覆在基底（1）上方，并形成复合膜层（31）；根据基底上方不同表面能的图案，图案化处理复合膜层（31），保留对应着表面能相对较高的图案区域的复合膜层（31）；通过有机溶剂蒸汽处理法使复合膜层（32）分层；在图案化的复合膜层（32）的相对两侧形成分离的两个金属电极。在该有机薄膜晶体管的制备方法中，在对有机半导体层（34）图案化的过程中，严格保证了图案与图案之间成膜同步，消除或减小了基底（1）上各个有机薄膜晶体管的有源层图案之间的成膜差异，从而保证了有机薄膜晶体管阵列的器件性能。

Description

薄膜晶体管的制备方法及薄膜晶体管、阵列基板 技术领域
本公开属于显示技术领域，具体涉及一种薄膜晶体管的制备方法及薄膜晶体管和阵列基板。
背景技术
有机薄膜晶体管(Organic Thin Film Transistor，简称OTFT)自从被发现以来一直受到学术界和产业界的广泛关注，其制备成本低，可满足柔性、大面积等硅半导体工艺无法满足的要求。但有机薄膜晶体管中有机半导体材料的图案化问题一直是饱受争议的话题，因为其无法与现有光刻工艺匹配，从而导致有机半导体材料无法用常规光刻法实现图案化，这让有机薄膜晶体管的产业化成为难题。
在学术界过去10多年的不断努力中，越来越多的有机薄膜晶体管图案化工艺被研发出来，其中，对于蒸镀法制备有机薄膜晶体管，可以采用传统的金属掩模板(mask)蒸镀工艺；对于溶液法制备的有机薄膜晶体管，图案化的方式多种多样，其中包括，先导材料光聚合法、喷墨打印法、丝网印刷法、微接触法、润湿/去润湿图案化法等。这些方法都可以在制备有机半导体的基底上直接形成图案化的有机半导体膜层，但这也导致了有机半导体层在图案化过程中，图案与图案之间成膜不同步的问题，导致基底上各个图案之间的成膜差异较大，从而影响有机薄膜晶体管阵列的器件性能，这是工业生产中不希望看到的事情。
可见，设计一种能使得基底上有源层图案之间的成膜同步的薄膜晶体管的制备方法成为目前亟待解决的技术问题。
发明内容
本公开所要解决的技术问题是针对现有技术中存在的上述不足，提供一种薄膜晶体管的制备方法及薄膜晶体管和阵列基板，该有机薄膜晶体管的制备方法在形成有机半导体层在图案化过程中，严格保证了有源层图案之间成膜同步，消除或减小了基底上各个有机薄膜晶体管的有源层图案之间的成膜差异。
为解决上述技术问题，本公开的第一方面提出了一种薄膜晶体管的制 备方法，该方法可以包括步骤：
在基底上方形成包括不同表面能的图案；
将含有有机半导体材料和聚合物绝缘材料的复合溶液涂覆在所述基底上方，并形成复合膜层；
根据所述基底上方不同表面能的图案，图案化处理所述复合膜层，保留对应着表面能相对较高的图案区域的所述复合膜层；
通过有机溶剂蒸汽处理法使图案化的所述复合膜层分层；
在图案化的所述复合膜层的相对两侧形成分离的两个金属电极。
根据一个实施例，可以通过有机溶剂蒸汽处理法使图案化的所述复合膜层分层为有机半导体层在上、聚合物绝缘层在下的结构；所述金属电极的至少一端位于所述有机半导体层上方。
根据另一实施例，所述基底可以为表面具有二氧化硅绝缘层的n型掺磷基底。
根据又一实施例，在所述基底上方形成包括不同表面能的图案可以包括：
在所述基底上方形成与所述基底以共价键连接的自组装单分子层，其中的自组装单分子为带有疏水基团的单分子材料；
对所述自组装单分子层进行图案化处理，在所述基底上方形成不同表面能的格栅状结构的图案。
在示例性实施例中，形成所述自组装单分子层的方法可以包括：在无水的氩气或氮气环境下，将所述基底浸泡在含有单分子材料的溶液中，将所述单分子材料的疏水基团装配在所述二氧化硅绝缘层的表面。
在示例性实施例中，对所述基底进行疏水基团装配的方法可以包括：采用包括八烷基三氯硅烷的溶液对所述基底进行浸泡，浸泡时间范围为1.5-2.5h；其中，溶解八烷基三氯硅烷的溶剂为甲苯，溶液浓度为10mg/ml。
在示例性实施例中，对所述自组装单分子层进行图案化处理的方法可以包括金属掩模板的紫外臭氧清洗法、有光刻胶保护的紫外臭氧清洗法、有光刻胶保护的等离子体法或聚二甲基硅氧烷微接触法中的任一种。
根据再一实施例，在所述复合溶液中，其中的溶剂为能够同时溶解所述有机半导体材料和所述聚合物绝缘材料的溶剂，所述有机半导体材料可以为可结晶的小分子半导体材料。具体地，有机半导体材料可以包括TES-ADT、TIPS_PEN、BTBT、DATT或DNTT中的任一种，所述聚合物 绝缘材料可以包括聚甲基丙烯酸甲酯或聚苯乙烯。
根据另外的实施例，所述复合溶液可以通过旋涂方法形成所述复合膜层，其中：
所述溶剂为沸点温度范围为60-150℃的低沸点有机溶剂，含有所述低沸点有机溶剂的所述复合溶液的旋涂转速≥3500rpm，旋转时间范围为15-20s；
或者，所述溶剂为沸点温度范围为150-250℃的高沸点有机溶剂，含有所述高沸点有机溶剂的所述复合溶液的旋涂转速≥5000rpm，旋转时间范围为15-20s。
在示例性实施例中，所述低沸点有机溶剂可以为氯仿、四氢呋喃、甲苯、邻二甲苯、对二甲苯、间二甲苯、氯苯的任一种或任意几种组合；
所述高沸点有机溶剂可以为1，2二氯苯、1，2，4三氯苯、二甲基亚砜中的任一种或任意几种组合。
根据一个实施例，在所述复合溶液中，所述有机半导体材料的质量配比可以小于等于所述聚合物绝缘材料的质量配比。具体地，所述有机半导体材料与所述聚合物绝缘材料的质量配比范围可以为1∶99-1∶4。
在示例性实施例中，当所述有机半导体材料与所述聚合物绝缘材料的质量配比为1∶4时，所述复合溶液的浓度为12.5mg/ml。
根据另一实施例，图案化处理所述复合膜层可以通过去除对应着表面能相对较低的图案区域上方的所述复合膜层实现，包括：在所述复合膜层上方粘贴具有粘性的胶带，通过所述胶带物理剥离对应着表面能相对较低的图案区域上方的所述复合膜层。
在示例性实施例中，在图案化处理所述复合膜层之前，还可以包括：
在所述复合膜层上方制备牺牲层；
在所述牺牲层上方粘贴具有粘性的胶带，通过所述胶带物理剥离所述牺牲层以及同时剥离表面能相对较低的图案区域上方的所述复合膜层。
在示例性实施例中，所述牺牲层可以通过对溶液进行旋涂的方式形成，所述溶液包括聚甲基丙烯酸甲酯和/或聚苯乙烯，溶解聚甲基丙烯酸甲酯和/或聚苯乙烯的溶剂为醋酸正丁酯。
在示例性实施例中，所述溶液可以包括摩尔质量为120kg/mol的聚甲基丙烯酸甲酯和/或摩尔质量为200kg/mol的聚苯乙烯。
在示例性实施例中，所述溶液的浓度范围可以为70-90mg/ml，旋涂 转速范围为1800-2200rpm，旋转时间范围为50-70s，所述牺牲层厚度范围为400-600nm。
在示例性实施例中，所述溶液的浓度可以为80mg/ml，旋涂转速为2000rpm，旋转时间为60s，所述牺牲层厚度为500nm。
根据一个实施例，在形成所述牺牲层后，还可以包括热固化所述牺牲层的步骤，热固化所述牺牲层的温度范围为70-90℃，热固化时间范围为20-40min。
根据另一实施例，热固化所述牺牲层的温度可以为80℃，热固化时间为30min。
根据实施例，通过有机溶剂蒸汽处理法使图案化的所述复合膜层分层可以包括：
将所述基底置于含有机溶剂的密闭环境中；
对密闭环境抽真空，使得所述有机溶剂汽化，从而形成密闭的蒸汽环境；
所述有机半导体材料移动到图案化的所述复合膜层的上方并在向上移动的过程中结晶晶粒增大，所述聚合物绝缘材料移动到图案化的所述复合膜层的下方。
在示例性实施例中，所述有机溶剂可以为1，2-二氯乙烷、甲苯、氯苯、氯仿中的任一种。
根据又一实施例，在图案化处理所述复合膜层之前，还可以包括热固化所述复合膜层的步骤，热固化所述复合膜层的温度范围为140-160℃，热固化时间范围为8-12min。
在示例性实施例中，热固化所述复合膜层的温度可以为150℃，热固化时间为10min。
根据再一实施例，分离的两个所述金属电极可以为源极和漏极，所述金属电极采用金材料、通过金属掩模板蒸镀形成，所述源极和所述漏极之间的分离区域形成沟道区域。
在示例性实施例中，所述源极和所述漏极的厚度范围可以为60-100nm；所述沟道区域的长度范围为80-100μm，宽度范围为700-900μm。
本公开的第二方面提供了一种薄膜晶体管，其采用上述的薄膜晶体管的制备方法形成。
本发明的第三方面提供了一种阵列基板，其可以包括上述的薄膜晶体管。
本公开的有益效果包括：该薄膜晶体管的制备方法，在对有机半导体层图案化的过程中，严格保证了有源层图案之间的成膜同步，消除或减小了基底上各个有机薄膜晶体管的有源层图案之间的成膜差异，从而保证了有机薄膜晶体管的器件性能。
附图说明
图1为根据本公开实施例的薄膜晶体管的制备方法的流程图；
图2为根据本公开实施例的在基底上方形成包括不同表面能的图案的示意图；
图3A、图3B为根据本公开实施例的形成复合膜层的示意图；
图4A、图4B为根据本公开实施例的去除对应着表面能相对较低的图案区域上方的复合膜层的示意图；
图5A、图5B为根据本公开实施例的通过有机溶剂蒸汽处理法使复合膜层分层的示意图；
图6为根据本公开实施例的在基底上方形成的有机薄膜晶体管的示意图；以及
图7为根据本公开实施例的单个有机薄膜晶体管的结构示意图。
图中：
1-基底；
2-图案化的自组装单分子层；
30-复合溶液；31-复合膜层；32-图案化的复合膜层；33-聚合物绝缘层；34-有机半导体层；
4-牺牲层；
5-胶带；
61-源极；62-漏极；
7-有机溶剂蒸汽环境。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开薄膜晶体管的制备方法及薄膜晶体管和阵列基板 作进一步详细描述。
本公开提供一种薄膜晶体管的制备方法以及采用该薄膜晶体管的制备方法相应形成的薄膜晶体管，该薄膜晶体管为有机薄膜晶体管。该薄膜晶体管的制备方法包括通过用带二氧化硅绝缘层的硅片作为基底，利用硅片作为有机薄膜晶体管器件的栅极，硅片的二氧化硅绝缘层与聚合物绝缘材料形成的聚合物绝缘层作为有机薄膜晶体管器件的栅绝缘层，有机半导体层作为有机薄膜晶体管器件的有源层，并且随后形成有机薄膜晶体管器件的源极和漏极。基底上的有机薄膜晶体管器件的有源层图案之间成膜同步，因此消除或减小了基底上各个有源层图案之间的成膜差异，从而保证了有机薄膜晶体管阵列的器件性能。
如图1所示，该制备方法具体包括以下步骤：
在步骤S1处，在基底上方形成包括不同表面能的图案。
如图2所示为在基底1上形成包括不同表面能的图案的示意图，其中的不同表面能由图案化的自组装单分子层2(Self-Assembled Monolayer，以下简称SAM层)决定。其中，基底1为表面具有二氧化硅绝缘层的n型掺磷基底(图2中未示出)，二氧化硅绝缘层的厚度范围为200-400nm。
在该步骤中，在基底1上方形成包括不同表面能的图案包括：
在步骤S11处，在基底1上方形成与基底1以共价键连接的自组装单分子层，其中的自组装单分子为带有疏水基团的单分子。自组装单分子为一种表面活性剂，对有机薄膜晶体管将在后续形成的有源层起到辅助形成的作用。
其中，形成自组装单分子层的方法包括：在无水的氩气(或氮气)环境下，将基底1浸泡在含有单分子材料的溶液中，使得单分子材料的疏水基团装配在二氧化硅绝缘层的表面。具体的，对基底1进行疏水基团装配的方法包括：采用包括八烷基三氯硅烷OTS的溶液对经过羟基化处理的洁净基底1进行浸泡，浸泡时间范围为1.5-2.5h；其中，溶解八烷基三氯硅烷的溶剂为甲苯，溶液浓度为10mg/ml。
在步骤S12处，对自组装单分子层进行图案化处理，在基底1上方形成不同表面能的格栅状结构的图案，也即图案化的自组装单分子层2。其中，对自组装单分子层进行图案化处理的方法包括金属掩模板的紫外臭氧清洗UV-OZONE法、有光刻胶保护的紫外臭氧清洗UV-OZONE法、有光刻胶保护的等离子体Plasma法或聚二甲基硅氧烷PDMS微接触法中的任 一种。根据工艺需要，图案化处理的方法可以选择上述方法中的任一种，这里不做限定。
在基底1上表面，由于SAM层为带有疏水基团的单分子层，因此导致基底1上有SAM层区域的表面能相对较低，而基底1上没有SAM层区域的表面能相对较高。也即，基底1装配自组装单分子层的区域表面能相对较低，亲水性弱，疏水性强，粘结力小；基底1上无自组装单分子层的区域表面能相对较高，亲水性强，疏水性弱，粘结力大。
这里应该理解的是，为了使得后续步骤中复合溶液能够在自组装单分子层上成膜，这里的自组装单分子层采用八烷基三氯硅烷而不推荐使用十八烷基三氯硅烷和全氟硅烷；同时，只要能够在基底1上得到表面能相对较高/表面能相对较低交错的微图案就可以，制备的方法不限于金属掩模板(mask)和UV-OZONE法，也可以采用光刻胶保护法、PDMS微接触法等方法，这里不做限定。
在步骤S2处，将含有有机半导体材料和聚合物绝缘材料的复合溶液30涂覆在基底1上方，并形成复合膜层31。
如图3A所示，在该步骤中，复合溶液30中的溶剂为能够同时溶解有机半导体材料和聚合物绝缘材料的溶剂，有机半导体材料包括TES-ADT、TIPS_PEN、BTBT、DATT或DNTT中的任一种，聚合物绝缘材料包括聚甲基丙烯酸甲酯PMMA或聚苯乙烯PS。根据工艺需要，有机半导体材料和聚合物绝缘材料可以选择上述材料中的任一种，或者选用与上述材料具有相同性质的其他材料，这里不做限定。
作为一个示例，这里的有机半导体材料例如为可以结晶的小分子半导体材料，如TES-ADT、TIPS_PEN、BTBT、DATT、DNTT等，TES-ADT、TIPS_PEN、BTBT、DATT、DNTT的名称以及结构简式详见以下的说明。
TES-ADT为5，11-Bis(triethylsilylethynyl)anthradithiophene，其结构简式如下所示：
Figure PCTCN2015089829-appb-000001
TIPS_PEN为6，13-Bis(triisopropylsilylethynyl)pentacene，中文名称为TIPS-并五苯，6，13-双(三异丙基甲硅烷基乙炔基)并五苯，其结构简式如下所示：
Figure PCTCN2015089829-appb-000002
BTBT为benzothienobenzothiophene，该分子的衍生物为BTBT类分子及其衍生物分子材料，其衍生物分子通式为Cn-BTBT，其中3≤n≤12。例如，C8-BTBT为其衍生物之一，名称为2，7-Dioctyl[1]benzothieno[3，2-b][1]benzothiophene，结构简式如下所示：
Figure PCTCN2015089829-appb-000003
DATT为dianthra[2，3-b：2′，3′-f]thieno[3，2-b]thiophene，结构简式如下所示：
Figure PCTCN2015089829-appb-000004
DNTT为Dinaphtho[2，3-b：2′，3′-f]thieno[3，2-b]thiophene，结构简式如下所示：
Figure PCTCN2015089829-appb-000005
DNTT的衍生物分子通式为Cn-DNTT，其中3≤n≤12。例如，C10-DNTT为其衍生物之一，名称为2，9-didecyldi-naphtho[2，3-b：2’，3’-f]thieno[3，2-b]thiophene(C10-DNTT)，结构简式如下所示：
Figure PCTCN2015089829-appb-000006
作为一个示例，聚合物绝缘材料可以使用传统的聚合物材料，例如摩尔质量为996kg/mol的聚甲基丙烯酸甲酯PMMA、摩尔质量为200kg/mol的聚苯乙烯PS等。
这里应该理解的是，关于复合溶液30中的有机半导体材料和聚合物绝缘材料的质量配比关系，希望使得聚合物绝缘材料过量，即有机半导体材料的质量配比小于等于聚合物绝缘材料的质量配比，以便实现在旋涂过程中聚合物绝缘材料对有机半导体材料小分子的包裹。在一个示例中，有机半导体材料与聚合物绝缘材料的质量配比为1∶99-1∶4，即1质量份有机半导体材料可以与4-99质量份聚合物绝缘材料相配。根据工艺需要，有机半导体材料和聚合物绝缘材料的质量配比可以选择上述质量配比中的 任一种，这里不做限定。有机半导体材料与聚合物绝缘材料的质量配比为1∶4时，复合溶液30的浓度为12.5mg/ml。
其中，复合溶液30通过旋涂方法形成复合膜层31，溶剂为沸点温度范围为60-250℃的有机溶剂，其中：
溶剂为沸点温度范围为60-150℃的低沸点有机溶剂，含有低沸点有机溶剂的复合溶液30的旋涂转速≥3500rpm，旋转时间范围为15-20s。其中，低沸点有机溶剂为氯仿、四氢呋喃、甲苯、邻二甲苯、对二甲苯、间二甲苯、氯苯的任一种或任意几种组合；
或者，溶剂为沸点温度范围为150-250℃的高沸点有机溶剂，含有高沸点有机溶剂的复合溶液30的旋涂转速≥5000rpm，旋转时间范围为15-20s。其中，高沸点有机溶剂为1，2二氯苯、1，2，4三氯苯、二甲基亚砜中的任一种或任意几种组合。
这里应该理解的是，溶剂可以是沸点较低、且能够溶解有机半导体材料和聚合物绝缘材料两组分材料的有机溶剂。在制备的转速选择上，可以考虑高转速，以使得复合溶液30能快速成膜形成复合膜层31，同时不给有机半导体材料和聚合物绝缘材料充分的相分离时间，阻断有机半导体材料和聚合物绝缘材料形成界面清晰的分层。
当选择沸点较高的溶剂时，混合溶液的旋转时间可以与选择沸点较低的溶剂的混合溶液的旋转时间相同，此时，由于其旋涂转速相对沸点较低的溶剂的混合溶液的旋涂转速高，混合溶液在旋涂过程中已经形成复合膜层并固化，也能阻断有机半导体材料和聚合物绝缘材料充分的相分离。
根据工艺需要，溶剂可以选择上述材料中的任一种，并选择相应的旋涂转速和旋转时间，以形成不同厚度的复合膜层31，这里不做限定。例如：当有机半导体材料与聚合物绝缘材料的质量配比为1∶4，复合溶液30的浓度为12.5mg/ml时，则制备得到的复合膜层31的厚度范围为50-100nm。
在上述旋涂工艺完成后，有机半导体材料即部分实现结晶，但有机半导体材料和聚合物绝缘材料之间并不存在清晰界面。
为了在后续步骤中能获得较佳的分层界面清晰的有机半导体层34和聚合物绝缘层33，在图案化处理复合膜层31之前，还包括热固化复合膜层31的步骤，热固化复合膜层31的温度范围为140-160℃，热固化时间范围为8-12min。
如图3A所示，将复合溶液30旋涂在已经预处理过的基底1和图案化的自组装单分子层2上方；如图3B所示，经过旋涂兼固化的过程后，复合溶液30形成复合膜层31。随后用150℃的热台热固化处理10min，加强复合膜层31与基底1的连接。
在步骤S3处，根据基底1上方不同表面能的图案，图案化处理复合膜层31，保留对应着表面能相对较高的图案区域的复合膜层31。
在该步骤中，图案化处理复合膜层31通过去除对应着表面能相对较低的图案区域上方的复合膜层31实现，在本实施例中可以用不同的物理剥离方式去除对应着表面能相对较低的图案区域上方的复合膜层31，保留对应着表面能相对较高的图案区域的复合膜层31，以形成图案化的复合膜层32。需要说明的是，表面能相对较高和相对较低的值可根据需要设置。
一种较为简单的去除方式是：在复合膜层31上方粘贴具有粘性的胶带，通过胶带物理剥离对应着表面能相对较低的图案区域上方的复合膜层31，形成图案化的复合膜层32。例如采用3M胶带完成物理剥离，由于复合膜层31与基底1上无SAM层的区域的粘结力很大(很强)，所以不容易被剥离；而复合膜层31与基底1上有SAM层的区域粘结力很小(很弱)，所以很容易被剥离，得到图案化的复合膜层32。在这种方式中，由于具有粘性的胶带通常含有聚合物，因此该聚合物可能会对复合膜层31中的有机半导体材料造成一定的影响。
另一种可替换的去除对应着表面能相对较低的图案区域上方的复合膜层31的方式是，在复合膜层31的上方形成一个牺牲层，然后再通过胶带同时去除该牺牲层以及对应着表面能相对较低的图案区域上方的复合膜层31。即，在去除对应着表面能相对较低的图案区域上方的复合膜层31之前，还包括：
在步骤S31处，在复合膜层31上方制备牺牲层4。
其中，牺牲层4通过对溶液进行旋涂的方式形成，溶液包括聚甲基丙烯酸甲酯PMMA和/或聚苯乙烯PS，溶解聚甲基丙烯酸甲酯PMMA和/或聚苯乙烯PS的溶剂为醋酸正丁酯。根据工艺需要，制备牺牲层4的溶液包括的物质可以选择上述材料中的任一种或两种均选，或者选用与上述材料具有相同性质的其他材料，这里不做限定。
其中的溶液可以包括摩尔质量为120kg/mol的聚甲基丙烯酸甲酯 PMMA或摩尔质量为200kg/mol的聚苯乙烯PS，也可以同时包括摩尔质量为120kg/mol的聚甲基丙烯酸甲酯PMMA或摩尔质量为200kg/mol的聚苯乙烯PS；其中的醋酸正丁酯溶剂不会对复合膜层31中的有机半导体材料造成影响，能减小在制备牺牲层4时溶剂对复合膜层31层的溶解，保证后续形成的有源层的性能。
在一个示例中，溶液的浓度范围为70-90mg/ml，旋涂转速范围为1800-2200rpm，旋转时间范围为50-70s，牺牲层4厚度范围为400-600nm。具体地，溶液的制备浓度可以为80mg/ml，旋涂转速为2000rpm，旋转时间为60s，制得的牺牲层4的厚度大约为500nm。
为了获得较佳的牺牲层4的品质，可以通过热固化使溶剂充分挥发，同时增强牺牲层4与复合膜层31之间的粘结性。即在形成牺牲层4后，还包括热固化牺牲层4的步骤，热固化牺牲层4的温度范围为70-90℃，热固化时间范围为20-40min。具体地，热固化温度可以为80℃，热固化处理时间为30min，促进牺牲层4的平整化以及与复合膜层的连接。
在步骤S32处，在牺牲层4上方粘贴具有粘性的胶带5，通过胶带5物理剥离牺牲层4以及同时剥离表面能相对较低的图案区域上方的复合膜层31。
例如采用3M胶带5完成物理剥离，由于复合膜层31与基底1上无SAM区域的粘结力很大(很强)，所以不容易被剥离；而复合膜层31与基底1上有SAM的区域粘结力很小(很弱)，所以很容易被剥离。如图4A所示，沿箭头方向撕开胶带5，复合膜层31便会沿着黑线的断面被剥离分开，得到如图4B中所示的图案化的复合膜层32。
这里值得注意的是，在去除对应着表面能相对较低的图案区域上方的复合膜层31的步骤中，由于此时的复合膜层31中有机半导体材料与聚合物绝缘材料这两组分的相分离是不彻底的，所以可以把复合膜层31视为一个整体，在剥离过程中，复合膜层31的两组分不会因此分离。
在步骤S4处，通过有机溶剂蒸汽处理法使复合膜层31分层。
在该步骤中，通过有机溶剂蒸汽处理法，使形成图案化的复合膜层32体系内部发生运动，使得有机半导体材料与聚合物绝缘材料形成有机半导体层34在上、聚合物绝缘层33在下的结构。
具体的，通过有机溶剂蒸汽处理法使图案化的复合膜层32分层包括：
在步骤S41处，将基底1置于含有机溶剂的密闭环境中。特别地，有 机溶剂为1，2-二氯乙烷、甲苯、氯苯、氯仿中的任一种。根据工艺需要，有机溶剂可以选择上述材料中的任一种，这里不做限定。
在该步骤中，将图4B所示的图案化的复合膜层32放入到一密闭环境中，并营造有机溶剂蒸汽环境7，如图5A所示。这里的密闭环境可以为可抽真空的玻璃容器，有机溶剂放入到玻璃容器内；有机溶剂需要满足可以同时溶解有机半导体材料和聚合物绝缘材料的要求，可选的有机溶剂为1，2-二氯乙烷，也可以采用常用的有机溶剂，如甲苯、氯苯、氯仿等。
在步骤S42处，对密闭环境抽真空，使得有机溶剂汽化，从而形成密闭的蒸汽环境。
在该步骤中，通过对密闭环境抽真空营造有机溶剂蒸汽环境7，即在真空环境中使有机溶剂汽化，从而在玻璃容器中提供一蒸汽氛围。这里提供的充满有机溶剂的密闭环境，使得有机溶剂可以浸入到图案化的复合膜层32中，完成蒸汽退火。
在步骤S43处，有机半导体材料缓慢移动到图案化的复合膜层32的上方并在向上移动的过程中结晶晶粒增大，聚合物绝缘材料移动到图案化的复合膜层32的下方。在这个过程中，有机半导体相与聚合物绝缘层相的相分离会比有机溶剂蒸汽处理前更加彻底。
在图4B形成图案化的复合膜层32的过程中，图案化的复合膜层32中有机半导体材料与聚合物绝缘材料的相分离是不彻底的；通过蒸汽退火的方式使有机溶剂的蒸汽浸入到图案化的复合膜层32中，使得有机半导体材料移动到图案化的复合膜层32的上方、聚合物绝缘材料移动到图案化的复合膜层32的下方，促进复合材料膜层的相分离，使得图案化的复合膜层32分层形成图5B中形成有机半导体层34在上、聚合物绝缘层33在下的结构；同时。有机半导体材料在向上移动的过程中迅速结晶，使晶粒尺寸变大，使得有机半导体层34在图案化的复合膜层32中的成膜性能更好。
通过以上步骤，即将物理剥离工艺和蒸汽退火工艺结合起来，先物理剥离出图案化的复合膜层32，再用蒸汽退火的方式促使图案化的复合膜层32进一步相分离，完成有机半导体层34在上部分、聚合物绝缘层33在下部分的双层结构。
在步骤S5处，在图案化的复合膜层32的相对两侧形成分离的两个金属电极。
在该步骤中，在分离的两个金属电极中，任一金属电极的一端位于有机半导体层34上方，另一端位于表面能相对较低的图案区域的上方。以上金属电极的位置仅作示例；根据薄膜晶体管的结构，金属电极的至少一端位于有机半导体层上方即可，而另一端可以位于表面能相对较低的图案区域的上方，或者可以位于对应着表面能相对较低的图案区域的其他层结构的上方，这里并不做限定，在实际制备过程中可根据薄膜晶体管结构的需要调节对应着表面能相对较低的图案区域的上方的层结构。
如图6所示，分离的两个金属电极为源极61和漏极62，源极61和漏极62均采用金材料、通过金属掩模板蒸镀形成，源极61和漏极62之间的分离区域形成沟道区域。在一个示例中，源极61和漏极62的厚度范围为60-100nm；沟道区域的长度范围为80-100μm，宽度范围为700-900μm。具体地，沟道宽度可以为800μm。
图7为采用上述薄膜晶体管的制备方法制备形成的单个有机薄膜晶体管的结构示意图，该薄膜晶体管采用带二氧化硅绝缘层的硅片作为基底1，由于硅片是可以导电的，则可以直接将硅片作为有机薄膜晶体管器件的栅极；采用图案化的自组装单分子层、物理剥离法以及有机溶剂蒸汽处理的方法完成有机半导体层34和聚合物绝缘层33的制备，此时，硅片的二氧化硅绝缘层与聚合物绝缘层33作为有机薄膜晶体管器件的栅绝缘层，有机半导体层34作为有机薄膜晶体管器件的有源层；随后在图案化的有机半导体层34和聚合物绝缘层33上方用金属掩模板蒸镀形成分离的两个金属电极并形成沟道，从而完成底栅顶接触(与有源层顶接触)的有机薄膜晶体管。
该有机薄膜晶体管的制备方法中，在形成有机半导体层在图案化过程中，严格保证了有源层图案之间成膜同步，消除或减小了基底上各个有机薄膜晶体管的有源层图案之间的成膜差异，从而保证了有机薄膜晶体管的器件性能。
本公开的实施例还提供了一种阵列基板，该阵列基板包括上述有机薄膜晶体管。
其中的阵列基板可以排列多个采用实施例1中的有机薄膜晶体管的制备方法制备形成的有机薄膜晶体管，多个有机薄膜晶体管成阵列排布，并进一步形成纵横交叉设置的栅线和数据线；然后，可以继续采用现有工艺制备形成像素电极等以形成液晶型阵列基板，或者，制备形成OLED 器件等形成OLED型阵列基板。
其中，在该阵列基板中形成多个有机薄膜晶体管时，图案化的自组装单分子层的图形与有机薄膜晶体管的栅极的图形形成互补。
该阵列基板可以制备形成OLED显示面板、TN型(Twisted Nematic，扭曲向列)液晶显示面板、VA型(Vertical Alignment，垂直取向)液晶显示面板、ADS型(ADvanced Super Dimension Switch，高级超维场转换技术)液晶显示面板中的阵列基板，这里不做限定。从而，进一步可形成液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在本公开提供的薄膜晶体管的制备方法中，通过将物理剥离工艺和蒸汽退火工艺结合起来的技术手段，达到使得有机半导体/聚合物绝缘复合材料图案化和相分离的技术效果，即：先物理剥离出图案化的复合膜层，再用蒸汽退火的方式促使复合膜层中有机半导体材料和聚合物绝缘材料的相分离，完成有机半导体层在上部分、聚合物绝缘层在下部分的双层结构，因而，在形成有机薄膜晶体管器件的结构的同时，还严格保证了图案化之后的有机薄膜晶体管阵列中，不同有机薄膜晶体管的有源层图案之间成膜同步，解决了有机半导体层图案同步化的技术问题。
基于该薄膜晶体管的制备方法制备形成的有机薄膜晶体管，具有更好的性能，从而使得包括该有机薄膜晶体管的阵列基板具有更好的显示性能。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (33)

  1. 一种薄膜晶体管的制备方法，包括步骤：
    在基底上方形成包括不同表面能的图案；
    将含有有机半导体材料和聚合物绝缘材料的复合溶液涂覆在所述基底上方，并形成复合膜层；
    根据所述基底上方不同表面能的图案，图案化处理所述复合膜层，保留对应着表面能相对较高的图案区域的所述复合膜层；
    通过有机溶剂蒸汽处理法使图案化的所述复合膜层分层；
    在图案化的所述复合膜层的相对两侧形成分离的两个金属电极。
  2. 根据权利要求1所述的制备方法，其中，通过有机溶剂蒸汽处理法使图案化的所述复合膜层分层为有机半导体层在上、聚合物绝缘层在下的结构；所述金属电极的至少一端位于所述有机半导体层上方。
  3. 根据权利要求1所述的制备方法，其中，所述基底为表面具有二氧化硅绝缘层的n型掺磷基底。
  4. 根据权利要求3所述的制备方法，其中，在所述基底上方形成包括不同表面能的图案包括：
    在所述基底上方形成与所述基底以共价键连接的自组装单分子层，其中的自组装单分子为带有疏水基团的单分子材料；
    对所述自组装单分子层进行图案化处理，在所述基底上方形成不同表面能的格栅状结构的图案。
  5. 根据权利要求4所述的制备方法，其中，形成所述自组装单分子层的方法包括：在无水的氩气或氮气环境下，将所述基底浸泡在含有单分子材料的溶液中，将所述单分子材料的疏水基团装配在所述二氧化硅绝缘层的表面。
  6. 根据权利要求5所述的制备方法，其中，对所述基底进行疏水基团装配的方法包括：采用包括八烷基三氯硅烷的溶液对所述基底进行浸泡，浸泡时间范围为1.5-2.5h；其中，溶解八烷基三氯硅烷的溶剂为甲苯，溶液浓度为10mg/ml。
  7. 根据权利要求4所述的制备方法，其中，对所述自组装单分子层进行图案化处理的方法包括金属掩模板的紫外臭氧清洗法、有光刻胶保护的紫外臭氧清洗法、有光刻胶保护的等离子体法或聚二甲基硅氧烷微接触 法中的任一种。
  8. 根据权利要求1所述的制备方法，其中，在所述复合溶液中，其中的溶剂为能够同时溶解所述有机半导体材料和所述聚合物绝缘材料的溶剂，所述有机半导体材料为可结晶的小分子半导体材料。
  9. 根据权利要求8所述的制备方法，其中，有机半导体材料包括TES-ADT、TIPS_PEN、BTBT、DATT或DNTT中的任一种，所述聚合物绝缘材料包括聚甲基丙烯酸甲酯或聚苯乙烯。
  10. 根据权利要求9所述的制备方法，其中，所述聚合物材料包括摩尔质量为996kg/mol的聚甲基丙烯酸甲酯或摩尔质量为200kg/mol的聚苯乙烯。
  11. 根据权利要求8所述的制备方法，其中，所述复合溶液通过旋涂方法形成所述复合膜层，并且其中：
    所述溶剂为沸点温度范围为60-150℃的低沸点有机溶剂，含有所述低沸点有机溶剂的所述复合溶液的旋涂转速≥3500rpm，旋转时间范围为15-20s；
    或者，所述溶剂为沸点温度范围为150-250℃的高沸点有机溶剂，含有所述高沸点有机溶剂的所述复合溶液的旋涂转速≥5000rpm，旋转时间范围为15-20s。
  12. 根据权利要求11所述的制备方法，其中，所述低沸点有机溶剂为氯仿、四氢呋喃、甲苯、邻二甲苯、对二甲苯、间二甲苯、氯苯的任一种或任意几种组合；
    所述高沸点有机溶剂为1，2二氯苯、1，2，4三氯苯、二甲基亚砜中的任一种或任意几种组合。
  13. 根据权利要求1所述的制备方法，其中，在所述复合溶液中，所述有机半导体材料的质量配比小于等于所述聚合物绝缘材料的质量配比。
  14. 根据权利要求13所述的制备方法，其中，所述有机半导体材料与所述聚合物绝缘材料的质量配比范围为1∶99-1∶4。
  15. 根据权利要求14所述的制备方法，其中，所述有机半导体材料与所述聚合物绝缘材料的质量配比为1∶4时，所述复合溶液的浓度为12.5mg/ml。
  16. 根据权利要求15所述的制备方法，其中，复合膜层的厚度范围为50-100nm。
  17. 根据权利要求1所述的制备方法，其中，图案化处理所述复合膜层通过去除对应着表面能相对较低的图案区域上方的所述复合膜层实现，包括：在所述复合膜层上方粘贴具有粘性的胶带，通过所述胶带物理剥离对应着表面能相对较低的图案区域上方的所述复合膜层。
  18. 根据权利要求1所述的制备方法，其中，在图案化处理所述复合膜层之前，还包括：
    在所述复合膜层上方制备牺牲层；
    在所述牺牲层上方粘贴具有粘性的胶带，通过所述胶带物理剥离所述牺牲层以及同时剥离表面能相对较低的图案区域上方的所述复合膜层。
  19. 根据权利要求18所述的制备方法，其中，所述牺牲层通过对溶液进行旋涂的方式形成，所述溶液包括聚甲基丙烯酸甲酯和/或聚苯乙烯，溶解聚甲基丙烯酸甲酯和/或聚苯乙烯的溶剂为醋酸正丁酯。
  20. 根据权利要求19所述的制备方法，其中，所述溶液包括摩尔质量为120kg/mol的聚甲基丙烯酸甲酯和/或摩尔质量为200kg/mol的聚苯乙烯。
  21. 根据权利要求19所述的制备方法，其中，所述溶液的浓度范围为70-90mg/ml，旋涂转速范围为1800-2200rpm，旋转时间范围为50-70s，所述牺牲层厚度范围为400-600nm。
  22. 根据权利要求21所述的制备方法，其中，所述溶液的浓度为80mg/ml，旋涂转速为2000rpm，旋转时间为60s，所述牺牲层厚度为500nm。
  23. 根据权利要求19所述的制备方法，其中，在形成所述牺牲层后，还包括热固化所述牺牲层的步骤，热固化所述牺牲层的温度范围为70-90℃，热固化时间范围为20-40min。
  24. 根据权利要求23所述的制备方法，其中，热固化所述牺牲层的温度为80℃，热固化时间为30min。
  25. 根据权利要求1所述的制备方法，其中，通过有机溶剂蒸汽处理法使图案化的所述复合膜层分层包括：
    将所述基底置于含有机溶剂的密闭环境中；
    对密闭环境抽真空，使得所述有机溶剂汽化，从而形成密闭的蒸汽环境；
    所述有机半导体材料移动到图案化的所述复合膜层的上方并在向上 移动的过程中结晶晶粒增大，所述聚合物绝缘材料移动到图案化的所述复合膜层的下方。
  26. 根据权利要求25所述的制备方法，其中，所述有机溶剂为1，2-二氯乙烷、甲苯、氯苯、氯仿中的任一种。
  27. 根据权利要求1所述的制备方法，其中，在图案化处理所述复合膜层之前，还包括热固化所述复合膜层的步骤，热固化所述复合膜层的温度范围为140-160℃，热固化时间范围为8-12min。
  28. 根据权利要求27所述的制备方法，其中，热固化所述复合膜层的温度为150℃，热固化时间为10min。
  29. 根据权利要求1所述的制备方法，其中，分离的两个所述金属电极为源极和漏极，所述金属电极采用金材料、通过金属掩模板蒸镀形成，所述源极和所述漏极之间的分离区域形成沟道区域。
  30. 根据权利要求29所述的制备方法，其中，所述源极和所述漏极的厚度范围为60-100nm；所述沟道区域的长度范围为80-100μm，宽度范围为700-900μm。
  31. 根据权利要求30所述的制备方法，其中，所述沟道宽度为800μm。
  32. 一种薄膜晶体管，采用权利要求1-31任一项所述的薄膜晶体管的制备方法形成。
  33. 一种阵列基板，包括权利要求32所述的薄膜晶体管。
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