WO2016119697A1 - 横向扩散金属氧化物半导体场效应管的制造方法 - Google Patents

横向扩散金属氧化物半导体场效应管的制造方法 Download PDF

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WO2016119697A1
WO2016119697A1 PCT/CN2016/072319 CN2016072319W WO2016119697A1 WO 2016119697 A1 WO2016119697 A1 WO 2016119697A1 CN 2016072319 W CN2016072319 W CN 2016072319W WO 2016119697 A1 WO2016119697 A1 WO 2016119697A1
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doping type
substrate
region
implantation
source region
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韩广涛
孙贵鹏
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Definitions

  • the present invention relates to semiconductor processes, and more particularly to a method of fabricating a laterally diffused metal oxide semiconductor field effect transistor.
  • LDMOS laterally diffused metal oxide semiconductor field effect transistors
  • lowering LDMOS Rdson's method is to continuously reduce the concentration of the drift region, and through the application of various surface electric field reduction (RESURF) theory, it can be completely depleted, thus obtaining low Rdson and maintaining a high off-BV.
  • Rdson and off-BV has approached the theoretical limit by this method.
  • a conventional method for shortening the channel length is to use a POLY self-aligned injection of P-type impurity ions to form a P-body after polysilicon (POLY) etching, and then Through a certain thermal process, the P-body is laterally expanded to form a channel region. Since the region of the POLY self-aligned implant is the region where the source end is located, this method can maximize the concentration of the channel region close to the source, thereby maintaining a higher pass-through voltage while obtaining a shorter channel length.
  • the specific formation process is: first using a lithographic plate etched by polysilicon to form a gate and a POLY field portion.
  • a P-body implanted lithographic plate is then used to form a P-body implant region.
  • NLMDOS is formed. Since this method uses POLY self-aligned implantation, limited by the thickness of POLY, the implantation energy cannot be too high, so it takes a long thermal process after P-body implantation to form the desired channel region.
  • LDMOS as the gate and not as the gate of the low-voltage MOS when preparing a wafer with both LDMOS and low-voltage MOSFETs integrated, because the Vt implant of the low-voltage device is not suitable for a long heat. process.
  • the P-body undergoes a long thermal process, and the P-type impurity after the lateral expansion also lowers the N-type impurity concentration in the drift region, and Rdson increases.
  • a method for fabricating a laterally diffused metal oxide semiconductor field effect transistor comprising the steps of: forming a first doping type drift region on a substrate; performing photolithography through a photolithography plate to form an implantation window; and injecting through the implantation window a second doping type ion forming body region, and implanting a first doping type ion forming source region, controlling an implantation angle and an implantation energy such that a junction depth of the body region is greater than a junction depth of the source region, and a width greater than a width of the source region; forming a gate oxide layer; depositing and etching polysilicon to form a gate; the first doping type and the second doping type being electrically opposite.
  • the P-type and N-type impurity implantation uses a photoresist remaining after the same photolithography as a barrier layer, and the trench length of the conductive channel is injected twice. The energy and angle are determined. Compared with the traditional source which requires further photolithography, it is not affected by the lithography alignment deviation, the groove length is more stable, and the threshold voltage (Vt), Rdson and other characteristics are more stable. The channel length is shorter, the channel resistance is reduced, and the overall size is smaller, making the total Rdson lower than conventional LDMOS. Rdson can be 10% to 30% lower. LDMOS and low-voltage MOS can share the same layer of polysilicon (POLY), the process is simpler, saving a lithography process and reducing costs.
  • POLY polysilicon
  • FIG. 1 is a flow chart showing a method of fabricating a laterally diffused metal oxide semiconductor field effect transistor in an embodiment
  • FIG. 2 is a schematic cross-sectional view of the device in step S130 when implanting a second doping type ion in an embodiment
  • step S130 is a schematic cross-sectional view of the device in step S130 when implanting the first doping type ions in an embodiment
  • step S150 is a cross-sectional view of the device after completion of step S150 in an embodiment
  • Figure 5 is a schematic illustration of an NLDMOS fabricated using a method of fabricating a laterally diffused metal oxide semiconductor field effect transistor in an embodiment.
  • a method for fabricating a laterally diffused metal oxide semiconductor field effect transistor of an embodiment includes the following steps:
  • NLDMOS is taken as an example. It can be understood that the method is also applicable to PLDMOS.
  • the first doping type refers to the N type
  • the second doping type refers to the P type.
  • a P-type substrate can be employed, and then an N well 20 is formed on the substrate as a drift region.
  • an isolation structure 40 such as a field oxide layer or a shallow trench isolation structure (STI), needs to be formed on the substrate.
  • the laterally diffused metal oxide semiconductor field effect transistor may also be field-free.
  • photolithography is performed by a lithographic plate of P-body implantation to form a photoresist 62. Both the ion implantation of the P-body and the N-type ion implantation of the source are performed through this implantation window.
  • a P-type injection is performed by a P-body, and a P-type injection of a large angle (the angle of the angle with the normal line, the same below) and a N-type injection of a small angle or a 0 degree angle are respectively performed.
  • a wider and deeper P-type region (as the P-type body region 30) and a relatively narrower and shallower N-type region (as the source) are respectively formed.
  • the arrow in FIG. 2 is the injection direction of the P-type ions
  • the arrow in FIG. 3 is the injection direction of the N-type ions. It can be understood that the P-type implantation should include injection in two directions, for example, the left and right sides of the injection in FIG.
  • the method of forming a source region by a large angle injection and a small angle injection to form a source region the body region completely forms a channel region by implantation, and the formation of the channel region does not need to undergo too many hot push-pull processes, and may even have no push-pull process at all.
  • the process is simpler and the POLY can act as the gate of the low voltage MOS.
  • the P-type impurity of the P-body is less laterally spread, and does not cause a decrease in the concentration of the N-type drift region, so that a lower on-resistance can be obtained.
  • the groove length of the conductive channel is completely determined by the energy and angle of the two injections, and the conventional Compared with the technique in which the source needs to perform photolithography again, the groove length is more stable, and the Vt (threshold voltage) and Rdson characteristics are more stable.
  • the P-type and N-type impurity implants may also be implanted using a small angle or a 0 degree angle. After the implantation is completed, only a short thermal process is required, and the diffusion of the P-type impurity and the N-type impurity is utilized. Different speed characteristics to obtain a wider, deeper area and a shallower, narrower area.
  • P-type impurities such as boron
  • N-type impurities such as phosphorus, arsenic, antimony, etc.
  • the thermal process can be placed before the gate oxide growth and the deposition of the POLY, so that it can be arranged before the corresponding ion implantation of the low voltage MOS without any influence on the Vt implantation of the low voltage MOS.
  • LDMOS can also share the same layer of POL with the low voltage MOS.
  • the process is simpler, saving a lithography process and reducing costs.
  • N-type impurities and slower P-type impurities such as phosphorus and indium, which are faster in diffusion, can also be respectively injected in step S130 to obtain desired body regions and sources.
  • a gate oxide layer (not shown) is formed by a conventional process.
  • the gate 70 (and the landing portion) is formed by etching.
  • the source electrode 54, the body region 56, and the drain electrode 58 are further formed on the basis of FIG.
  • the laterally diffused metal oxide semiconductor field effect transistor fabricated by the above-described lateral diffusion metal oxide semiconductor field effect transistor manufacturing method has a shorter channel length, a smaller channel resistance, and a smaller overall size, so that the total Rdson Lower. Especially effective for LDMOS with low operating voltage and small overall size, compared to traditional LDMOS Rdson can be 10% to 30% lower.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种横向扩散金属氧化物半导体场效应管的制作方法，包括步骤：在衬底上形成第一掺杂类型的漂移区（20）；通过光刻板进行光刻，形成注入窗口；通过注入窗口注入第二掺杂类型离子形成体区（30），及注入第一掺杂类型离子形成源极区（52），控制注入角度和注入能量使得体区的结深大于源极区的结深，宽度大于源极区的宽度；形成栅氧化层；淀积并蚀刻多晶硅，形成栅极（70）。

Description

横向扩散金属氧化物半导体场效应管的制造方法
【技术领域】
本发明涉及半导体工艺，特别是涉及一种横向扩散金属氧化物半导体场效应管的制造方法。
【背景技术】
随着横向扩散金属氧化物半导体场效应管（LDMOSFET）在集成电路中的应用越来越广泛，对于关态崩溃电压（off-BV）更高，导通电阻（Rdson）更小的LDMOS的需求越来越迫切。
通常来说，降低LDMOS Rdson的方法，就是在不断提高漂移区浓度的同时，通过各种降低表面电场（RESURF）理论的应用，使其能够完全耗尽，从而获得低Rdson，并维持很高的off-BV。目前通过此方法已经使Rdson与off-BV之间的关系接近了理论极限。
以N沟道LDMOS为例，一种传统的缩短沟道长度的方法是在多晶硅（POLY）刻蚀后，利用POLY自对准注入P型杂质离子形成P型体区（P-body），然后通过一定的热过程，使P-body横扩形成沟道区。由于POLY自对准注入的区域就是源极（source）端所在区域，此方法可以使靠近源极的沟道区浓度最高，从而在获得较短的沟道长度的同时，保持较高的穿通电压。具体的形成过程是：先使用多晶硅刻蚀的光刻版，形成栅极及POLY搭场部分。然后再使用P-body注入的光刻版，形成P-body注入区。最后经历较长时间热过程后形成NLMDOS。这种方法由于采用POLY自对准注入，受限于POLY厚度，注入能量不可能太高，因此在P-body注入后需要经历较长的热过程，才能形成所需的沟道区。这就使得在制备同时集成了LDMOS和低压MOSFET的晶圆时，此层POLY只能给LDMOS作为栅极，而不能作为低压MOS的栅极，因为低压器件的Vt注入不适合经历较长的热过程。此外，P-body经历较长的热过程，其横扩后的P型杂质也会使漂移区的N型杂质浓度降低，Rdson升高。
【发明内容】
基于此，有必要提供一种能够获得低导通电阻的横向扩散金属氧化物半导体场效应管的制造方法。
一种横向扩散金属氧化物半导体场效应管的制造方法，包括步骤：在衬底上形成第一掺杂类型的漂移区；通过光刻版进行光刻，形成注入窗口；通过所述注入窗口注入第二掺杂类型离子形成体区，及注入第一掺杂类型离子形成源极区，控制注入角度和注入能量使所述体区的结深大于所述源极区的结深，宽度大于所述源极区的宽度；形成栅氧化层；淀积并蚀刻多晶硅，形成栅极；所述第一掺杂类型和第二掺杂类型的电性相反。
上述横向扩散金属氧化物半导体场效应管的制造方法，P型和N型杂质注入使用的是同一次光刻后留下的光刻胶作为阻挡层，导电沟道的沟长由两次注入的能量和角度来决定，与传统的源极需要再进行一次光刻的技术相比，不受光刻对位偏差的影响，沟长更稳定，使阈值电压（Vt），Rdson等特性更加稳定。其沟道长度更短，沟道电阻减小的同时，总尺寸更小，使总的Rdson更低，比传统的LDMOS Rdson可以低10%至30%。LDMOS与低压MOS能够共用同一层多晶硅（POLY），工艺更加简单，节省一道光刻流程，能够降低成本。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一实施例中横向扩散金属氧化物半导体场效应管的制造方法的流程图；
图2是一实施例中步骤S130在注入第二掺杂类型离子时器件的剖面示意图；
图3是一实施例中步骤S130在注入第一掺杂类型离子时器件的剖面示意图；
图4是一实施例中步骤S150完成后器件的剖面示意图；
图5是一实施例中采用横向扩散金属氧化物半导体场效应管的制造方法制造的NLDMOS的示意图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
如图1所示，一实施例的横向扩散金属氧化物半导体场效应管的制造方法包括下列步骤：
S110，在衬底上形成第一掺杂类型的漂移区。
本实施例中以NLDMOS为例进行介绍，可以理解的，本方法同样适用于PLDMOS。对于NLDMOS来说，第一掺杂类型是指N型，第二掺杂类型是指P型。可以采用P型衬底，然后在衬底上形成N阱20作为漂移区。本实施例中还需要在衬底上形成隔离结构40，例如场氧层或浅沟槽隔离结构（STI），在其他实施例中，横向扩散金属氧化物半导体场效应管也可以为无场氧层或STI的结构。
S120，通过一光刻版进行光刻，形成注入窗口。
在本实施例中，是通过P-body注入的光刻版进行光刻，形成光刻胶62。P-body的离子注入和源极的N型离子注入都通过这个注入窗口来进行。
S130，通过注入窗口进行离子注入，形成体区和源极区，体区的结深和宽度大于源极区。
在本实施例中，是通过P-body注入的光刻版，分别进行大角度（指与法线的夹角的角度，下同）的P型注入和小角度或0度角的N型注入，如图2和图3所示。利用P型注入和N型注入的角度及能量差异，分别形成一个区域更宽更深的P型区域（作为P型体区30），和一个相对更窄、更浅的N型区域（作为源极52）。其中图2的箭头为P型离子的注入方向，图3的箭头为N型离子的注入方向。可以理解的，P型注入时应包括两个方向的注入，例如图2中的左、右两侧注入。
通过大角度注入形成体区、小角度注入形成源极的方法，体区完全通过注入形成沟道区，沟道区的形成不需要经历太多热推阱过程，甚至可以完全没有推阱过程，工艺过程更加简单，而且该POLY可以同时作为低压MOS的栅极。同时，P-body的P型杂质横扩较少，不会导致N型漂移区浓度降低，因此可以获得更低的导通电阻。另外，由于P型和N型杂质注入使用的是同一次光刻后留下的光刻胶62作为阻挡层，导电沟道的沟长完全由两次注入的能量和角度来决定，与传统的源极需要再进行一次光刻的技术相比，不受光刻对位偏差的影响，沟长更稳定，使Vt（阈值电压），Rdson等特性更加稳定。
在另一个实施例中，P型和N型杂质注入也可以都使用小角度或0度角注入，在注入完成后，只需经历较短的热过程，利用P型杂质和N型杂质的扩散速度不同的特点，来获得一个较宽、较深的区域和一个较浅、较窄的区域。P型杂质（如硼）扩散速度一般大于N型杂质（如磷、砷、锑等），因此热扩散后可形成区域更深更宽的P型区，以及区域相对较窄、较浅的N型区，从而同样可以在后续形成的多晶硅下方形成沟长非常稳定的P型沟道区。该方法虽然同样经历了一定的热过程，但该热过程可以放在栅氧生长以及淀积POLY前，因此可以安排在低压MOS相应的离子注入之前，不会对低压MOS的Vt注入产生任何影响，同样可以使LDMOS与低压MOS共用同一层POLY，工艺更加简单，节省一道光刻流程，能够降低成本。同理，对于PLDMOS的情况，同样可以在步骤S130中分别注入扩散速度较快的N型杂质和较慢的P型杂质，例如磷和铟，来获得所需的体区和源极。
S140，形成栅氧化层。
P型体区30和源极52形成完毕后，采用习知的工艺形成栅氧化层（图未示）。
S150，淀积并蚀刻多晶硅，形成栅极。
如图4所示，采用习知的工艺，光刻形成光刻胶64后，刻蚀形成栅极70（及搭场部分）。完成后如图5所示，在图4的基础上进一步形成源极54、体区56以及漏极58。
利用上述横向扩散金属氧化物半导体场效应管的制造方法制作的横向扩散金属氧化物半导体场效应管，其沟道长度更短，沟道电阻减小的同时，总尺寸更小，使总的Rdson更低。对于工作电压较低、总尺寸较小的LDMOS尤其有效，比传统的LDMOS Rdson可以低10%至30%。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (6)

  1. 一种横向扩散金属氧化物半导体场效应管的制造方法，包括步骤：
    在衬底上形成第一掺杂类型的漂移区；
    通过光刻版进行光刻，形成注入窗口；
    通过所述注入窗口注入第二掺杂类型离子在所述衬底内形成体区，及注入第一掺杂类型离子在所述衬底内形成源极区，控制注入角度和注入能量使所述体区的结深大于所述源极区的结深，宽度大于所述源极区的宽度；
    在所述衬底上形成栅氧化层；及
    在所述栅氧化层上淀积并蚀刻多晶硅，形成栅极；所述第一掺杂类型和第二掺杂类型的电性相反。
  2. 根据权利要求1所述的方法，其特征在于，通过所述注入窗口注入第二掺杂类型离子在所述衬底内形成体区，及注入第一掺杂类型离子在所述衬底内形成源极区，控制注入角度和注入能量使所述体区的结深大于所述源极区的结深，宽度大于所述源极区的宽度的步骤，是使得第二掺杂类型离子的注入方向与衬底法线间的夹角，大于所述第一掺杂类型离子的注入方向与衬底法线间的夹角，且所述第二掺杂类型离子的注入能量大于所述第一掺杂类型离子的注入能量。
  3. 根据权利要求1所述的方法，其特征在于，所述第一掺杂类型为N型，所述第二掺杂类型为P型，所述在衬底上形成栅氧化层的步骤之前还包括热扩散步骤。
  4. 根据权利要求1所述的方法，其特征在于，所述在栅氧化层上淀积并蚀刻多晶硅，形成栅极的步骤中，包括形成横向扩散金属氧化物半导体场效应管的栅极和低压金属氧化物半导体场效应管的栅极。
  5. 根据权利要求1所述的方法，其特征在于，通过所述光刻版进行光刻，形成注入窗口的步骤之前，还包括形成隔离结构的步骤。
  6. 根据权利要求1所述的方法，其特征在于，所述隔离结构为浅沟槽隔离结构或场氧层。
PCT/CN2016/072319 2015-01-30 2016-01-27 横向扩散金属氧化物半导体场效应管的制造方法 Ceased WO2016119697A1 (zh)

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