WO2016107093A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2016107093A1
WO2016107093A1 PCT/CN2015/081416 CN2015081416W WO2016107093A1 WO 2016107093 A1 WO2016107093 A1 WO 2016107093A1 CN 2015081416 W CN2015081416 W CN 2015081416W WO 2016107093 A1 WO2016107093 A1 WO 2016107093A1
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Prior art keywords
array substrate
display panel
substrate
disposed
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/081416
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English (en)
French (fr)
Inventor
贾纬华
江鹏
杨海鹏
金在光
尹傛俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Publication date
Application filed by BOE Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/906,095 priority Critical patent/US9933672B2/en
Publication of WO2016107093A1 publication Critical patent/WO2016107093A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/921—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133354—Arrangements for aligning or assembling substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/16—Materials and properties conductive
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/28—Adhesive materials or arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/607—Located on parts of packages, e.g. on encapsulations or on package substrates

Definitions

  • At least one embodiment of the present invention is directed to a display panel, a method of fabricating the same, and a display device.
  • the liquid crystal display device includes an array substrate and a counter substrate (for example, a color filter substrate) opposed to each other, and a liquid crystal layer disposed between the array substrate and the counter substrate.
  • the liquid crystal display device controls the deflection of the liquid crystal molecules by applying a voltage to the common electrode and the pixel electrode, thereby controlling the light.
  • liquid crystal display device Generally, during the manufacture, production, assembly, testing, storage or handling of a liquid crystal display device, static electricity is easily generated on the liquid crystal display device due to friction, or static electricity in the air, human body or other charged objects is transferred to the liquid crystal display device due to friction.
  • the substrate of the liquid crystal display device (for example, the counter substrate or the array substrate) is made of an insulating material such as glass, and the static elimination speed is very slow. Therefore, when static electricity accumulates on the surface of the substrate, static electricity is accumulated for a long time unless there is an appropriate release route. On the surface of the substrate.
  • the display module and the driver of the liquid crystal display device may cause electrostatic damage due to excessive electrical stress, such as generation of screen defects, melting or evaporation of metal lines, change in resistance of the element, and oxide layer. Destroyed or broken down, etc.
  • the static electricity may be attached to the liquid crystal display device by attaching a conductive tape around the liquid crystal display device. On the metal border.
  • At least one embodiment of the present invention provides a display panel, a method of fabricating the same, and a display device for enabling timely discharge of static electricity on a counter substrate in a display panel to avoid electrostatic damage and reduce cost.
  • At least one embodiment of the present invention provides a display panel including an array substrate and a counter substrate disposed opposite to each other; the array substrate includes a body region and a peripheral region, and the body region and the opposite substrate are in the An orthographic projection on the array substrate is coincident, and at least one dispensing region is disposed in the peripheral region or the body region, and the conductive adhesive is disposed in the dispensing region, and the conductive adhesive
  • the grounding member is electrically connected; the opposite substrate is provided with an electrostatic conducting structure, and the conductive adhesive is electrically connected to the electrostatic conducting structure.
  • At least one embodiment of the present invention also provides a display device including the above display panel.
  • At least one embodiment of the present invention further provides a method of fabricating a display panel, comprising: forming an opposite substrate, and providing an electrostatic conduction structure on the opposite substrate; forming an array substrate, the array substrate including a body region And a peripheral area, the main body area and the orthographic projection of the opposite substrate on the array substrate, the peripheral area or the main body area is provided with at least one dispensing area; the array substrate and the opposite substrate Forming the cartridge; and dropping a conductive paste into the dispensing region to electrically connect the conductive adhesive to the electrostatically conductive structure and the grounding member in the display panel.
  • FIG. 1a is a schematic top view of a display panel using a GOA mode according to an embodiment of the present invention
  • FIG. 1b is a schematic top view of a display panel adopting a COF mode according to an embodiment of the present invention
  • FIG. 2a is a partial cross-sectional view of a display panel according to an embodiment of the present invention.
  • 2b is a partial cross-sectional view showing another display panel according to an embodiment of the present invention.
  • 3a is a top plan view showing a conductive adhesive electrically connected to a printed circuit board through an electrostatic discharge line according to an embodiment of the present invention
  • 3b is a schematic structural view of a surface of a conductive adhesive contacting a metal frame according to an embodiment of the present invention
  • FIG. 4a is a cross-sectional view of an array substrate in a display panel according to an embodiment of the present invention.
  • 4b is a cross-sectional view of another array substrate in a display panel according to an embodiment of the present invention.
  • 4c is a cross-sectional view of still another array substrate in a display panel according to an embodiment of the invention.
  • FIG. 5 is a schematic structural diagram of a conductive adhesive device for dropping a conductive adhesive onto a registration mark according to an embodiment of the present invention
  • 6a is a schematic top view of an alignment mark according to an embodiment of the present invention.
  • FIG. 6b is a schematic top view of an alignment mark according to an embodiment of the present invention.
  • the inventors of the present application have noted that the manner in which the conductive tape is used to conduct static electricity to the metal frame is not suitable for a display device using a plastic frame, and the conductive tape material is costly and requires manual operation and cannot be automated. Moreover, there is currently no better way to derive the static electricity on the opposing substrate.
  • the embodiment of the invention provides a display panel, a manufacturing method thereof, and a display device.
  • the display panel includes an array substrate and a counter substrate disposed opposite to each other, and a grounding member.
  • the array substrate includes a main body region and a peripheral region, and the main body region and the opposite substrate.
  • the front projection on the array substrate overlaps, at least one dispensing area is disposed in the peripheral area or the main body area, the conductive glue is disposed in the dispensing area, the conductive adhesive is electrically connected to the grounding member, and the opposite substrate is provided with an electrostatic conducting structure.
  • the conductive paste is electrically connected to the electrostatic conduction structure.
  • Embodiments of the present invention provide a dispensing area in a peripheral area or a main body area of an array substrate a conductive adhesive is disposed in the dispensing region and electrically connected to the electrostatic conductive structure on the opposite substrate, so that static electricity on the opposite substrate can be led to the conductive adhesive in the dispensing region, and then exported to the grounding member. Therefore, the static electricity on the opposite substrate can be led out in time to avoid electrostatic damage.
  • the conductive adhesive by placing a dispensing area in the peripheral area of the array substrate, the conductive adhesive can be used to drop the conductive adhesive into the dispensing area.
  • the method of manually attaching conductive tape can reduce material and labor costs and increase production efficiency.
  • the conductive adhesive is an adhesive having certain conductive properties after curing or drying, and generally comprises a matrix resin, a conductive particle, a dispersing additive, an auxiliary agent, etc., and is electrically conductive.
  • the glue bonds the conductive particles together by the bonding of the matrix resin to form a conductive path to realize electrical connection of the material to be bonded.
  • the embodiment of the present invention does not limit the position and the connection relationship between the grounding member and the array substrate or the opposite substrate, as long as the components in the display panel that can discharge the static electricity on the conductive adhesive from the conductive adhesive can be used in the embodiment of the present invention. Grounding parts.
  • the embodiments of the present invention are applicable to various display panels such as a liquid crystal display panel and an OLED (Organic Light Emitting Diode) display panel.
  • OLED Organic Light Emitting Diode
  • the following embodiments mainly describe a liquid crystal display panel.
  • the packaging method of the liquid crystal display panel may include COG (chip on glass, connecting the chip and the glass substrate by a conductor), COB (chip on board, directly connecting the bare chip to the printed circuit board with a wire), COF (chip on
  • the film driving method of the liquid crystal display device may be a GOA (gate driver on array) or the like.
  • FIG. 1 is a top plan view of a display panel adopting a GOA mode according to an embodiment of the present invention
  • FIG. 1b is a schematic top view of a display panel adopting a COF mode according to an embodiment of the present invention
  • FIG. 1a and FIG. The display panel shown is an example.
  • At least one embodiment of the present invention provides a display panel including an array substrate 100 and a counter substrate 200 disposed opposite to each other, and a grounding member (eg, printed circuit board 60) as shown in FIGS. 1a and 1b.
  • the array substrate 100 includes a body region 11 and a peripheral region 12.
  • the body region 11 and the orthographic substrate 200 are orthogonally projected on the array substrate 100. Therefore, the peripheral region 12 is beyond the opposite substrate 200 of the array substrate 100 in the plane direction thereof.
  • At least one dispensing region 30 is disposed in the peripheral region 12 (FIG. 1a and FIG.
  • the dispensing region 30 is provided with a conductive adhesive 90, a conductive adhesive 90 and a grounding member (for example, , The printed circuit board 60) is electrically connected.
  • the counter substrate 200 is provided with an electrostatic conduction structure (for example, the first trace 202 in FIG. 1b), and the conductive paste 90 is electrically connected to the electrostatic conduction structure.
  • the opposite substrate 200 may be a color filter substrate provided with a black matrix, a color filter layer or the like, and the color filter layer generally includes a plurality of red sub-pixels R, a plurality of green sub-pixels G, and more. Blue subpixel B. Partial sub-pixels of the opposite substrate are shown in Figures 1a and 1b.
  • the liquid crystal display panel can be classified into a vertical electric field type, such as a twisted nematic (TN, Twisted Nematic) type, and a horizontal electric field type, such as an In Plane Switching (IPS) type and an advanced type.
  • IPS In Plane Switching
  • ADS Advanced Super Dimension Switch
  • an electrostatic conductive structure is disposed on the opposite substrate, and the conductive adhesive is electrically connected to the electrostatic conductive structure by adjusting the amount of the conductive adhesive dropped into the dispensing region. Therefore, the static electricity on the opposite substrate is led to the conductive paste.
  • the common electrode and the pixel electrode which supply voltage to drive the liquid crystal deflection are disposed in the array substrate, so no electrode is disposed on the opposite substrate to protect the liquid crystal molecules when charged
  • an object such as a human body
  • static electricity on the charged object is transferred to the liquid crystal display panel, which affects the deflection of the liquid crystal molecules, thereby affecting the display effect of the screen.
  • a transparent conductive layer is disposed on a side of the substrate remote from the array substrate, and the transparent conductive layer is grounded to shield external signals, thereby ensuring uniform electric field in the liquid crystal cell, ensuring product quality and reliability.
  • the static electricity on the opposite substrate can be led to the conductive paste by using the transparent conductive layer on the opposite side of the array substrate, that is, the electrostatic conduction structure in the above embodiment of the present invention.
  • It may be a transparent conductive layer 201 on the side of the opposite substrate 200 remote from the array substrate 100, as shown in FIG. 2a.
  • the transparent conductive layer 201 can be made of a transparent metal oxide such as indium zinc oxide, indium tin oxide or indium gallium zinc oxide.
  • the electrostatic conduction structure can be designed as a trace provided on the periphery of the opposite substrate.
  • the electrostatic conduction structure on the opposite substrate 200 is a first trace 202 surrounding the periphery of the opposite substrate 200 .
  • the first trace 202 may be located in the display area 110 .
  • the first trace 202 may be located on a side of the opposite substrate 200 facing the array substrate 100 (as shown in FIG. 1 b ) or on a side of the opposite substrate 200 away from the array substrate 100 .
  • first trace surrounding (or disposed on) the periphery of the opposite substrate means that the first trace may be disposed in a region where at least one side of the opposite substrate is located.
  • FIG. 1b is only described by taking the first trace in the region where the three sides of the opposite substrate are located; the embodiment of the present invention includes, but is not limited to, the same.
  • the dispensing region may be disposed in the body region of the array substrate.
  • the conductive paste may be manually disposed in the dispensing area so that the conductive paste is electrically connected to the first trace.
  • the first traces may be disposed in the same layer as the electrodes on the opposing substrate to simultaneously form the first traces and electrodes in the same patterning process, thereby reducing the process flow.
  • the counter substrate 200 is provided with a common electrode 204 and a first trace 202 on a side thereof facing the array substrate 100, and thus, a common electrode can be formed.
  • the common electrode 204 and the first trace 202 are simultaneously formed.
  • a touch electrode for example, a touch sensing electrode
  • an On cell touch display panel is disposed on the opposite substrate away from the array substrate.
  • a touch electrode is disposed on one side of the touch panel, and an in-cell touch display panel is provided with a touch electrode on a side of the opposite substrate facing the array substrate. Therefore, the touch electrode can be formed first. Traces.
  • the material of the first trace 202 formed simultaneously with the electrodes is also a transparent conductive material such as indium zinc oxide, indium tin oxide, indium gallium zinc oxide or the like. Metal oxide.
  • the first trace 202 may not be formed simultaneously with the transparent electrode on the opposite substrate. In this case, the first trace 202 may also be made of a metal material.
  • FIG. 2b does not show a structure such as a color filter layer, a flat layer, or the like on the opposite substrate 200.
  • the display panel provided by the embodiment of the present invention can also be exported to the grounding component by introducing a part of the static electricity on the array substrate to the grounding member 90 to a certain extent.
  • Electrostatic discharge on the array substrate For example, a signal line such as a gate signal line or a data signal line located in the main body area 11 may be electrically connected to the conductive paste 90 by means of an electrostatic ring or the like commonly used by those skilled in the art.
  • the array substrate 100 may also be provided with a second trace 15 around its periphery, and the second trace 15 may be electrically connected to the conductive paste or electrically connected to the printed circuit board 60 through the electrode legs.
  • the second trace 15 is located outside the display area 110, and the leading end and the trailing end of the second trace 15 are both located in the dispensing region 30 to be electrically connected to the conductive paste 90.
  • the second trace 15 can be formed simultaneously with the gate signal line in the body region of the array substrate to save process flow.
  • the second trace is electrically connected to the grounding member through the conductive paste or the electrode leg, which is more advantageous for deriving the static electricity on the array substrate.
  • FIG. 1a illustrates the use of the GOA mode as an example.
  • the second trace on the array substrate can also use the trace on the COF (flexible circuit film) to cross the COF region.
  • the array substrate may be provided with a second trace around its periphery, which means that the second trace may be disposed in an area where at least one side of the array substrate is located.
  • FIG. 1a is only an example in which the second trace is disposed in a region where the three sides of the array substrate are located; the embodiment of the present invention includes, but is not limited to, the same.
  • the conductive paste 90 can be electrically connected to the grounding member through the electrostatic discharge line 40.
  • the electrostatic discharge wire 40 can include a portion 41 located in the dispensing region 30 and electrically connected to the conductive paste 90, and located at A portion 42 outside the dispensing region 30 and electrically connected to the grounding member.
  • the data signal input side of the array substrate 100 is provided with a printed circuit board 60, and the end of the signal line provided on the array substrate 100 is connected to the printed circuit board 60 through the electrode pins 20. It should be noted that the connection relationship between the signal lines and the electrode pins is not shown in FIG. 1a and FIG. 1b.
  • the grounding member can be the printed circuit board 60, ie, in this case, the conductive paste 90 can be electrically connected to the printed circuit board 60 via the electrostatic discharge line 40,
  • the electrostatic discharge line 40 includes a portion 41 located in the dispensing region 30 and electrically connected to the conductive paste 90, and a portion 42 located outside the dispensing region 30 and electrically connected to the grounding member (printed circuit board 60).
  • the conductive paste 90 can be dropped into the dispensing region 30 by an automated dispensing device. Due to the surface tension, the conductive paste 90 is formed into an elliptical shape and is infiltrated into the dispensing region 30 of the electrostatic discharge line 40. In the portion 41, the conductive paste 90 is electrically connected to the portion 41 of the electrostatic discharge line 40 located in the dispensing region 30, so that static electricity on the conductive paste 90 can be led out to the printed circuit board 60 through the electrostatic discharge line 40.
  • FIG. 3a is a schematic structural view of a conductive adhesive electrically connected to a printed circuit board through an electrostatic discharge line according to an embodiment of the present invention; and FIG. 3a illustrates a COF mode of the display panel as an example.
  • a flexible circuit film 61 is disposed between the electrode leg 20 and the printed circuit board 60.
  • the flexible circuit film 61 uses a flexible circuit board as a carrier for packaging the chip to bond the chip to the flexible circuit board.
  • the flexible circuit film 61 is bent, so that the printed circuit board 60 is located on the side of the array substrate away from the opposite substrate, and then the opposite substrate and the array are formed by using a package frame (for example, a metal frame or a plastic frame).
  • the substrate is fixed.
  • the conductive paste 90 is electrically connected to the printed circuit board 60 through the electrostatic discharge line 40, even in the case where the liquid crystal display panel is packaged with a plastic frame, the static electricity in the liquid crystal display panel can be obtained through the printed circuit board. freed.
  • FIG. 3b is a schematic structural view of a conductive adhesive in contact with a surface of a metal frame according to an embodiment of the present invention.
  • the counter substrate 200 and the array substrate 100 are fixed to the cartridge through the bracket 500 and the metal frame 50, and by controlling the amount of the conductive glue dropped into the dispensing region of the array substrate 100, the conductive paste 90 can be disposed.
  • the surface of the metal frame 50 is brought into contact to realize electrical connection between the conductive paste 90 and the metal frame 50, so that static electricity on the conductive paste 90 can be led out to the metal frame 50.
  • a backlight 400 may be further disposed on a side of the array substrate 100 remote from the opposite substrate 200 to provide backlight for the liquid crystal display panel.
  • the number of peripheral regions included in the array substrate is different according to different packaging modes or driving modes of the liquid crystal display panel.
  • the display panel shown in FIG. 1a adopts a GOA mode, and one cutting line of the array substrate 100 exceeds the cutting line of the opposite substrate 200 corresponding to the cutting line, that is, the array substrate 100 includes a peripheral region 12.
  • the array substrate 100 may also include a plurality of peripheral regions.
  • the display panel shown in FIG. 1b adopts a COF mode, and the array substrate 100 is driven by a double gate, so the array substrate 100 includes three peripheral regions 12, 13, and 14.
  • the dispensing zone 30 can be located in a combination of at least one or several of the three peripheral zones.
  • the dispensing region 30 can be disposed on the side of the array substrate 100 on which the printed circuit board 60 is disposed along its plane, i.e., the side on which the peripheral region 12 is located as in Figures 1a and 1b.
  • the dispensing area 30 is disposed on the side where the printed circuit board is located, and the length of the electrostatic lead-out line can be reduced compared to the other side disposed on the array substrate, thereby reducing the resistance of the electrostatic lead-out line.
  • the dispensing region 30 is disposed in the peripheral region 12, the electrostatic discharge line passes only through the peripheral region 12, and the dispensing region is disposed in the peripheral region 13 or 14 to pass through the peripheral region 13 or 14 and the peripheral region 12.
  • the length of the electrostatic discharge line can be effectively shortened.
  • the dispensing region 30 is disposed on a side of the array substrate on which the printed circuit board 60 is disposed, so that the array substrate provided with the glued region can adopt GOA (as shown in FIG. 1a) and COF (as shown in FIG. 1). 1b) and other modes, so that it has better versatility.
  • a Pad region that is, a plurality of signal lines of the array substrate and leads of an external driving circuit board are further disposed.
  • the UV region 21 i.e., ultraviolet curable glue
  • the UV glue 21 covers the signal line and the electrode leg 20.
  • the UV adhesive 21 may also cover the portion 42 of the electrostatic discharge line 40 outside the dispensing region 30, as shown in FIG. 1a and FIG. 1b to prevent it from being corroded or scratched by moisture. If the dispensing area is located in the middle of the peripheral area 12, the automated dispensing device needs to lift the probe and interrupt the coating during the application of the UV glue to prevent the UV glue from covering the dispensing area, which results in the UV coating not being continuously coated. Thereby reducing the coating efficiency of the UV glue.
  • the dispensing area 30 can be located in the array. At the top corner of the substrate 100, that is, the dispensing region 30 is disposed at the end of the peripheral region 12. 1a and 1b are each illustrated as an example in which the two dispensing regions 30 are respectively disposed at positions where the vertex angles ⁇ and ⁇ of the array substrate 100 are located.
  • the electrostatic discharge line 40 in the embodiment of the present invention will be described in detail below with reference to FIGS. 4a, 4b, and 4c and taking a liquid crystal display panel as an example.
  • the gate substrate 71 of the thin film transistor 70, the gate insulating layer 77, the active layer 72, and the source/drain electrodes 73, 74 may be sequentially disposed on the substrate of the array substrate 100.
  • the passivation layer 78, the pixel electrode 75, and the pixel electrode 75 are electrically connected to the drain 74 of the thin film transistor through a via hole in the passivation layer 78.
  • the electrostatic discharge line 40 In the direction along the plane of the array substrate, the electrostatic discharge line 40 includes a portion 41 located in the dispensing region 30 and a portion 42 located outside the dispensing region 30, as shown in FIGS. 1a and 1b; perpendicular to the array substrate 100
  • the electrostatic discharge line 40 includes a first conductive portion 410, as shown in FIGS. 4a, 4b, and 4c.
  • the first conductive portion 410 may be disposed in the same layer as the electrodes in the array substrate.
  • the first conductive portion 410 of the electrostatic discharge line 40 can be formed while forming the electrodes in the display region of the array substrate by one patterning process, thereby eliminating the patterning process required for separately forming the electrostatic discharge lines, thereby reducing the process flow.
  • a thin film transistor 70 is disposed in the body region of the array substrate, and the thin film transistor 70 includes a gate electrode 71, an active layer 72, a source electrode 73, and a drain electrode 74. Since the gate electrode 71 and the source/drain electrodes 73, 74 are made of metal, such as A metal such as aluminum, copper or molybdenum has a small electrical resistance. Therefore, in at least one embodiment, the first conductive portion 410 of the electrostatic discharge line 40 can be disposed in the same layer as the gate 71, as shown in FIGS. 4a and 4c. Alternatively, the first conductive portion 410 may be disposed in the same layer as the source/drain electrodes 73, 74, as shown in FIG. 4b, that is, the electrodes in the array substrate are gates or source/drain electrodes.
  • the thin film transistor 70 can be divided into a top gate type (ie, the gate 71 is located on the side of the active layer 72 away from the substrate 10) and a bottom gate type (ie, the gate 71 is located).
  • a top gate type ie, the gate 71 is located on the side of the active layer 72 away from the substrate 10
  • a bottom gate type ie, the gate 71 is located.
  • the thin film transistor 70 can be divided into a top contact according to the manner in which the source/drain electrodes 73, 74 are in contact with the active layer 72.
  • Type ie, source/drain 73, 74 is located on the side of active layer 72 remote from substrate substrate 10, as shown in Figures 4a, 4b and 4c
  • bottom contact type i.e.
  • the first conductive portion 410 of the electrostatic discharge line 40 may be disposed close to the base substrate 10. Therefore, the preferred embodiment of the present invention is a thin film.
  • the transistor is of a bottom gate type and/or a bottom contact type.
  • the gate signal line in the array substrate is connected to the gate, and the data signal line is connected to the source/drain. Therefore, the first conductive portion 410, the gate 71, and the gate signal line may be formed in the same patterning process, or The first conductive portion 410, the source/drain electrodes 73, 74, and the data signal line may be formed in the same patterning process.
  • the electrostatic discharge line 40 may further include an insulating layer 430 covering the first conductive portion 410.
  • the electrostatic discharge line 40 may further include a second conductive portion 420 passing through the plurality of via holes 43 in the insulating layer 430 (ie, through the plurality of insulating layers 430) The via 43) is electrically connected to the first conductive portion 410.
  • the second conductive portion 420 may be made of a transparent conductive material such as indium tin oxide, indium zinc oxide or indium gallium zinc oxide, so as to prevent oxidation of the first conductive portion 410, and a plurality of via holes 43 are used.
  • the contact area between the first conductive portion 410 and the second conductive portion 420 may be increased, thereby reducing the electrical resistance of the entire electrostatic discharge line 40. It will be understood by those skilled in the art that the greater the number of vias 43 in the insulating layer 430, the larger the contact area between the first conductive portion 410 and the second conductive portion 420, and the smaller the resistance of the entire electrostatic discharge line 40.
  • the insulating layer 430 can utilize the gate insulating layer 77 and the blunt body in the body region.
  • the material of the layer 78 is formed or the like. For example, as shown in FIG. 4c, after the first conductive portion 410 of the electrostatic discharge line 40 is formed by the gate metal layer forming the gate electrode 71, in the process of forming the gate insulating layer 77, the gate insulating layer material is simultaneously covered first.
  • Conductive portion 410 in the process of forming the active layer 72 on the gate insulating layer 77, the active layer material on the first conductive portion 410 on which the gate insulating layer material is formed is etched away; a source is formed on the active layer 72 During the process of the /drain electrodes 73, 74, the source/drain metal layer formed on the first conductive portion 410 is etched away; during the formation of the passivation layer 78 and the passivation layer via holes on the source/drain, The passivation layer material is simultaneously covered with the first conductive portion 410 formed with the gate insulating layer material and the via hole 43 is formed, thereby forming the insulating layer 430 of the electrostatic discharge line 40 and the via hole 43 in the insulating layer 430.
  • the via 43 penetrates the gate insulating layer material and the passivation layer material to expose a partial region of the first conductive portion 410 such that the second conductive portion 420 formed thereon may be electrically connected to the first conductive portion 410
  • the insulating layer 430 is not limited to being formed using the material of the gate insulating layer 77 and the passivation layer 78 in the body region.
  • the insulating layer 430 may also utilize only the body region.
  • the material of the passivation layer 78 is formed.
  • the first conductive portion 410 of the electrostatic discharge line 40 is disposed in the same layer as the source/drain electrodes 73, 74, and thus the insulating layer 430 is formed between the first conductive portion 410 and the second conductive portion 420.
  • the material may not include the material of the gate insulating layer 77.
  • the second conductive portion 420 of the electrostatic discharge line 40 can be disposed in the same layer as the pixel electrode 75 in the array substrate body region, as shown in Figure 4c.
  • the pixel electrode 75 and the second conductive portion 420 can be simultaneously formed by one patterning process.
  • a common electrode 76 may also be disposed in the array substrate as shown in FIGS. 4a and 4b.
  • the second conductive portion 420 can also be disposed in the same layer as the common electrode 76.
  • FIG. 4a and 4b illustrate the example in which the pixel electrode 75 is located between the common electrode 76 and the base substrate 10.
  • the peripheral region of the pixel electrode material can be retained. a portion of the pixel electrode material is electrically connected to the first conductive portion 410 through the via hole 43; in the process of forming the insulating layer 79 between the pixel electrode 75 and the common electrode 76, the insulating layer 79 corresponds to an insulating layer
  • a portion of the via 43 in the 430 is subjected to a via process to expose a portion of the pixel electrode material electrically connected to the first conductive portion 410; in the process of forming the common electrode 76 over the insulating layer 79, the common electrode 76 and the second conductive portion 420 may be simultaneously formed by one patterning process, thereby making the second conductive
  • the portion 420 is electrically connected to the first conductive portion 410 through a pixel electrode material located in the via 43.
  • the portion of the pixel electrode material located in the peripheral region may also be etched away.
  • the second conductive portion 420 and the first conductive portion are formed in the electrostatic discharge line 40 formed.
  • the portion 410 is directly electrically connected.
  • the pixel electrode 75 and the common electrode 76 are transparent electrodes, and are usually made of a transparent metal oxide such as ITO (Indium Tin Oxide).
  • the embodiment of the present invention does not limit the positional relationship between the pixel electrode 75 and the common electrode 76 in the array substrate.
  • the pixel electrode 75 may be located on the side of the common electrode 76 facing the substrate 10 as shown in FIGS. 4a and 4b; for example, the pixel electrode 75 may also be located on the side of the common electrode 76 remote from the substrate 10.
  • FIG. 4a and FIG. 4b are only described by taking the second conductive portion 420 and the common electrode in the same layer as an example.
  • the second conductive portion 420 of the electrostatic discharge line 40 may be formed by any one of the pixel electrode 75 and the common electrode 76 according to actual conditions.
  • the structure in which the second conductive portion 420 of the electrostatic discharge line 40 is electrically connected to the first conductive portion 410 through the plurality of via holes 43 in the insulating layer 430 may be located on the electrostatic discharge line 40.
  • the insulating layer via and the second conductive portion may not be disposed on the portion 42 of the electrostatic discharge line 40 outside the dispensing region 30.
  • the first conductive portion of the electrostatic discharge line may also be formed simultaneously with the gate or the source/drain of the thin film transistor included in the array substrate (ie, disposed in the same layer), and the insulating layer covering the first conductive portion is also It can be formed using a gate insulating layer and a passivation layer of a thin film transistor.
  • the first conductive portion and the insulating layer covering the first conductive portion may also be formed by using other conductive structures or insulating layers on the array substrate in the OLED display panel; accordingly, the second conductive portion may also be displayed by using the OLED A transparent conductive layer on the array substrate in the panel is formed.
  • the embodiments of the present invention are not described herein.
  • a registration mark can be formed in the dispensing area. Since the portion 41 of the electrostatic discharge line 40 located in the dispensing region 30 is formed simultaneously with the gate or the source/drain, that is, formed of the same metal (e.g., magnesium, aluminum, copper, titanium, etc.), the metal is generally opaque and easily identifiable. Therefore, the alignment mark can be formed using the first conductive portion 410 of the electrostatic discharge line 40.
  • FIG. 5 is a schematic structural diagram of a conductive adhesive device for dropping a conductive adhesive into a registration mark according to an embodiment of the present invention.
  • the conical probe 01 of the dispensing device is provided with a conductive paste.
  • the detecting device 02 of the dispensing device can read the alignment mark 46 in the dispensing region 30. Since the second conductive portion 420 and the insulating layer 430 of the electrostatic discharge line 40 are made of a transparent material, the pattern of the alignment mark formed by the first conductive portion 410 is clearly visible under the irradiation of strong light, and therefore, the dispensing device can be smoothly performed. Read and use the pattern of the alignment mark to implement feedback calibration, coarse alignment and fine alignment.
  • FIG. 5 shows that the first conductive portion 410 of the electrostatic discharge line 40 forms a "mountain" shaped alignment mark.
  • the bottom gate type thin film transistor is formed in the array substrate, and the pattern of the alignment mark is formed by forming the gate electrode and forming the electrostatic discharge line 40 by using the gate metal layer to make the corresponding point of the static electricity discharge line 40.
  • the pattern of the first conductive portion 410 of the portion 41 in the glue region 30 is a "mountain" shape.
  • FIG. 5 is only described by taking the “mountain” shape as an example.
  • FIG. 6a is an example of a combination of “ ⁇ ” and “ ⁇ ”
  • FIG. 6b is described by taking “ ⁇ ” as an example.
  • the embodiment of the present invention is not limited thereto.
  • the pattern of the alignment mark may include at least one of a “mountain”, a “field”, a “back”, a “mouth” shape, and a “ ⁇ ” “ ⁇ ” shape. Combination of species or several. As long as the alignment mark can be smoothly read by the detecting device of the dispensing device, the dispensing device can realize the feedback calibration, the coarse alignment and the fine alignment function by using the pattern of the alignment mark.
  • a sealant 300 is disposed between the opposite substrate 200 and the array substrate 100, and the dispensing region 30 is disposed on the outer side of the sealant 300 (ie, the sealant 300 in FIGS. 2a and 2b). On the left side).
  • the end of the black matrix 203 in the opposite substrate 200 located inside the sealant 300 may be located in the sealant 300 (as shown in FIGS. 2a and 2b) or on the inside of the sealant 300.
  • the end of the signal line 80 (for example, the gate signal line, the data signal line) in the array substrate 100 inside the sealant 300 may be located in the sealant 300 or on the inside of the sealant 300.
  • the embodiment of the present invention compresses the black matrix layer included in the opposite substrate of the display device into the sealant 300 or the inside of the sealant 300, thereby avoiding the black caused by the black matrix layer contacting the conductive adhesive 90.
  • the static accumulation of the matrix layer which in turn affects the pixel liquid crystal deflection of the entire display screen; in the embodiment of the invention, the signal line in the array substrate is compressed into the sealant 300 or the inside of the sealant 300, thereby avoiding the signal line being
  • the conductive adhesive 90 is not covered by UV glue and is directly exposed to be corroded by water vapor.
  • At least one embodiment of the present invention also provides a display device comprising the display panel of any of the above embodiments.
  • the display device is a liquid crystal display device, which may further include a backlight for providing a light source to the display panel, and a polarizer on both sides of the display panel.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a touch panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., having any display function.
  • a liquid crystal panel an electronic paper
  • an OLED panel an organic light-emitting diode
  • a touch panel a mobile phone
  • a tablet computer a television
  • a display a notebook computer
  • a digital photo frame a navigator, etc.
  • At least one embodiment of the present invention further provides a method of fabricating a display panel, the method comprising: forming an opposite substrate, wherein the opposite substrate is provided with an electrostatic conduction structure; forming an array substrate, the array substrate comprising a body region and a peripheral region, The front surface of the main body and the opposite substrate on the array substrate coincides with at least one dispensing area in the peripheral area or the main body area; the array substrate and the opposite substrate are formed into a box; and the conductive adhesive is dropped into the dispensing area.
  • the conductive adhesive is electrically connected to the electrostatic conduction structure and the grounding member.
  • the embodiment of the invention does not limit the manner in which the conductive adhesive is dropped into the dispensing area.
  • the conductive adhesive may be manually dropped into the dispensing area, or may be dropped into the dispensing area by an automated device.
  • the grounding member may be a printed circuit board disposed on the array substrate, in which case the step of forming the array substrate includes forming an electrostatic discharge line in a peripheral region of the array substrate, such that the electrostatic discharge line is included a portion of the dispensing region and a portion outside the dispensing region and electrically connected to the printed circuit board; the step of dropping the conductive paste into the dispensing region includes electrically electrifying the portion of the conductive paste and the electrostatic discharge line located in the dispensing region The connection is made to electrically connect the conductive adhesive to the printed circuit board through the electrostatic discharge line.
  • the grounding member may also be a metal frame.
  • the step of forming the array substrate and the opposite substrate into the box includes fixing the array substrate and the opposite substrate by using a metal frame, in the dispensing area.
  • the step of dropping the conductive paste includes contacting the conductive paste with the surface of the metal frame.
  • the step of forming the opposite substrate and the step of forming the array substrate are not limited, and the opposite substrate may be formed after the array substrate is formed first, or the array substrate may be formed after the opposite substrate is formed first. .
  • the electrostatic conduction structure may be located on a side of the opposite substrate away from the array substrate Transparent conductive layer.
  • the electrostatic conduction structure may surround the opposite substrate.
  • a first trace of the periphery ie, disposed in a region where at least one side of the opposite substrate is located
  • the first trace is located on a side of the opposite substrate facing the array substrate or a side of the opposite substrate away from the array substrate
  • the first trace may be formed in the same patterning process as the common electrode or the touch electrode on the opposite substrate.
  • the touch electrode may be located on a side of the opposite substrate facing the opposite substrate or on a side of the opposite substrate away from the array substrate.
  • the electrostatic discharge line includes a first conductive portion in a direction perpendicular to a plane of the array substrate, the first conductive portion being formed in the same patterning process as the gate or source/drain in the array substrate.
  • the electrostatic discharge line may further include an insulating layer and a second conductive portion on a side of the first conductive portion away from the array substrate, and the second conductive portion passes through the plurality of via holes in the insulating layer and the first conductive portion Electrical connection.
  • the second conductive portion may be formed in the same patterning process as the pixel electrode or the common electrode in the array substrate. The embodiment of the invention does not limit the positional relationship between the pixel electrode and the common electrode in the array substrate.
  • the display panel, the manufacturing method thereof and the display device provided by the embodiments of the present invention have at least one of the following advantages.
  • a conductive paste is disposed in the dispensing region and electrically connected to the electrostatic conducting structure on the opposite substrate, so that the opposing substrate is
  • the static electricity can be exported to the conductive adhesive in the dispensing area, and then exported to the grounding component, so that the static electricity in the array substrate and the opposite substrate can be led out in time to avoid electrostatic damage.
  • the embodiment of the present invention can be automated compared to the manner in which the conductive tape is manually attached.
  • the dispensing device drops the conductive adhesive into the dispensing area, thereby saving labor costs and material costs and improving production efficiency.
  • the conductive adhesive is electrically connected to the transparent conductive layer on the side of the opposite substrate away from the array substrate, and the external signal can be shielded while ensuring the uniformity of the electric field in the liquid crystal cell to ensure the product quality. And trustworthiness.
  • the dispensing area is disposed on the data signal input side of the array substrate, which can improve the versatility of the array substrate, and is suitable for various modes such as COF and GOA; and the dispensing area is disposed at the top corner of the array substrate.
  • the UV glue can be continuously coated in the pad area.
  • a printed circuit board is used as the grounding member, so that the embodiment of the present invention can be applied to a display device using a plastic bezel.
  • the electrostatic discharge can be reduced by providing the insulating layer covering the first conductive portion and the second conductive portion electrically connected to the first conductive portion through the plurality of via holes in the insulating layer
  • the overall resistance of the wire prevents oxidation of the electrostatic discharge wire or corrosion by moisture; moreover, the corresponding portions of the layer structure of the electrostatic discharge line are formed while fabricating the respective film structures in the array substrate, which can reduce the process flow.
  • the dispensing device can smoothly read and utilize the pattern of the alignment mark to realize feedback calibration, coarse alignment and fine alignment function.
  • the end of the signal line in the array substrate is disposed in the sealant or the inside of the sealant, which can prevent the conductive adhesive from directly contacting the signal line, and prevent the signal line from being exposed and being corroded by water vapor.

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Abstract

一种显示面板及其制作方法、显示装置，该显示面板包括阵列基板（100）和对置基板（200），阵列基板（100）包括主体区域和周边区域，主体区域和对置基板（200）在阵列基板（100）上的正投影重合，周边区域和主体区域中设置有静电导出线（40）和至少一个点胶区域（30），点胶区域（30）中设置有导电胶（90），导电胶（90）与接地部件（50，60）电连接，对置基板（200）上设置有静电传导结构（201，202），导电胶（90）与静电传导结构（201，202）电连接。

Description

显示面板及其制作方法、显示装置 技术领域
本发明的至少一个实施例涉及一种显示面板及其制作方法、显示装置。
背景技术
液晶显示装置包括相互对置的阵列基板和对置基板(例如彩膜基板)，以及设置于阵列基板和对置基板之间的液晶层。液晶显示装置通过对公共电极和像素电极施加电压以控制液晶分子的偏转，进而控制光线。
通常，在液晶显示装置的制造、生产、组装、测试、存放或搬运过程中，由于摩擦容易在液晶显示装置上产生静电，或由于电连接，空气、人体或其他带电物体中的静电会转移至液晶显示装置。液晶显示装置的基板(例如对置基板、阵列基板)采用玻璃等绝缘材料制作，静电消除速度非常缓慢，因此，当基板表面有静电累积时，除非有适当的释放途径，否则静电会长时间累积在基板的表面。当大量积聚的静电发生静电放电时，液晶显示装置的显示模块和驱动器等会由于过度的电应力而产生静电破坏，如产生屏幕缺陷、金属线路被熔解或蒸发、元件电阻值发生改变、氧化层被破坏或击穿等。
为了将液晶显示装置的基板表面的静电及时导出、避免静电在液晶显示装置的基板表面积累而造成静电损坏，可以采用在液晶显示装置的四周贴附导电胶带的方式将静电导出至液晶显示装置的金属边框上。
发明内容
本发明的至少一个实施例提供了一种显示面板及其制作方法、显示装置，以实现将显示面板中对置基板上的静电及时导出以避免静电损坏并降低成本。
本发明的至少一个实施例提供了一种显示面板，其包括相对设置的阵列基板和对置基板；所述阵列基板包括主体区域和周边区域，所述主体区域与所述对置基板在所述阵列基板上的正投影重合，所述周边区域或所述主体区域中设置有至少一个点胶区域，所述点胶区域中设置有导电胶，所述导电胶 与接地部件电连接；所述对置基板上设置有静电传导结构，所述导电胶与所述静电传导结构电连接。
本发明的至少一个实施例还提供了一种显示装置，其包括上述显示面板。
本发明的至少一个实施例还提供了一种显示面板的制作方法，其包括：形成对置基板，并在所述对置基板上设置静电传导结构；形成阵列基板，所述阵列基板包括主体区域和周边区域，所述主体区域与所述对置基板在所述阵列基板上的正投影重合，所述周边区域或所述主体区域中设置有至少一个点胶区域；将阵列基板与对置基板对盒成型；以及在所述点胶区域中滴入导电胶，使所述导电胶电连接所述静电传导结构以及所述显示面板中的接地部件。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1a为本发明实施例提供的一种采用GOA模式的显示面板的俯视示意图；
图1b为本发明实施例提供的一种采用COF模式的显示面板的俯视示意图；
图2a为本发明实施例提供的一种显示面板的局部剖视示意图；
图2b为本发明实施例提供的另一种显示面板的局部剖视示意图；
图3a为本发明实施例提供的一种导电胶通过静电导出线与印刷电路板电连接的俯视示意图；
图3b为本发明实施例提供的一种导电胶与金属边框的表面接触的结构示意图；
图4a为本发明实施例提供的显示面板中一种阵列基板的剖视示意图；
图4b为本发明实施例提供的显示面板中另一种阵列基板的剖视示意图；
图4c为本发明实施例提供的显示面板中再一种阵列基板的剖视示意图；
图5为本发明实施例提供的一种采用自动化点胶设备将导电胶滴到对位标记上的结构示意图；
图6a为本发明实施例提供的一种对位标记的俯视示意图；
图6b为本发明实施例提供的一种对位标记的俯视示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在研究中，本申请的发明人注意到，采用导电胶带将静电导出至金属边框的方式不适用于采用塑料边框的显示装置，并且导电胶带材料成本高且需要人工操作，无法实现自动化。而且，对于如何将对置基板上的静电导出，目前没有更好的方式。
本发明实施例提供一种显示面板及其制作方法、显示装置，该显示面板包括相对设置的阵列基板和对置基板、以及接地部件，阵列基板包括主体区域和周边区域，主体区域与对置基板在阵列基板上的正投影重合，周边区域或主体区域中设置有至少一个点胶区域，点胶区域中设置有导电胶，导电胶与接地部件电连接；对置基板上设置有静电传导结构，导电胶与静电传导结构电连接。本发明实施例通过在阵列基板的周边区域或主体区域设置点胶区 域，在点胶区域中设置导电胶并使其与对置基板上的静电传导结构电连接，使得对置基板上的静电可以导出至点胶区域内的导电胶上，之后导出至接地部件，从而可以将对置基板上的静电及时导出，避免静电损坏；本发明实施例通过在阵列基板的周边区域设置点胶区域，可以实现采用自动化点胶设备在点胶区域中滴入导电胶，相对于人工贴附导电胶带的方式，可以减少材料和人力成本，提高生产效率。
需要说明的是，在本发明实施例中，导电胶是一种固化或干燥后具有一定导电性能的胶黏剂，通常其组成成分主要包括基体树脂、导电粒子和分散添加剂、助剂等，导电胶通过基体树脂的粘接作用把导电粒子结合在一起，形成导电通路，实现被粘材料的电连接。此外，本发明实施例不限定接地部件与阵列基板或对置基板的位置和连接关系，只要是显示面板中可以使导电胶上的静电从导电胶上导出的部件都可作为本发明实施例中的接地部件。
本发明实施例适用于液晶显示面板、OLED(Organic Light Emitting Diode)显示面板等多种显示面板，以下实施例主要以液晶显示面板为例进行说明。
液晶显示面板的封装方式可包括COG(chip on glass，用导体使芯片与玻璃基板相互连接)、COB(chip on board，用导线将裸露的芯片直接连接到印刷电路板上)、COF(chip on film，芯片安装在薄膜上)等方式，液晶显示装置的栅极驱动方式可采用GOA(gate driver on array，阵列基板行驱动)等方式。
图1a为本发明实施例提供的一种采用GOA模式的显示面板的俯视示意图，图1b为本发明实施例提供的一种采用COF模式的显示面板的俯视示意图；下面以图1a和图1b所示的显示面板为例进行说明。
本发明的至少一个实施例提供了一种显示面板，如图1a和图1b所示，该显示面板包括相对设置的阵列基板100和对置基板200、以及接地部件(例如，印刷电路板60)。阵列基板100包括主体区域11和周边区域12，主体区域11与对置基板200在阵列基板100上的正投影重合，因此，周边区域12为阵列基板100的沿其所在平面方向超出对置基板200的区域。周边区域12中设置有至少一个点胶区域30(图1a和图1b分别以两个点胶区域为例进行说明)，点胶区域30中设置有导电胶90，导电胶90与接地部件(例如， 印刷电路板60)电连接。对置基板200上设置有静电传导结构(例如，图1b中的第一走线202)，导电胶90与静电传导结构电连接。
例如，对置基板200可以为彩膜基板，彩膜基板上设置有黑矩阵、彩色滤光层等膜层，彩色滤光层通常包括多个红色子像素R、多个绿色子像素G和多个蓝色子像素B。图1a和图1b中示出了对置基板的部分子像素。根据驱动液晶的电场方向的不同，液晶显示面板可以分为垂直电场型，例如扭曲向列(TN，Twisted Nematic)型等，和水平电场型，例如平面转换(IPS，In Plane Switching)型和高级超维场开关(ADS，AdvancedSuper Dimension Switch)型等。在垂直电场型液晶显示面板中，像素电极和公共电极分别形成在阵列基板中和对置基板中；在水平电场型液晶显示面板中，像素电极和公共电极同时形成在阵列基板中。
为了将对置基板上的静电引至导电胶上，对置基板上需设置静电传导结构，通过调整导电胶滴入点胶区域中的滴入量，可以使导电胶与该静电传导结构电连接，从而将对置基板上的静电引至导电胶上。
在采用水平电场控制模式的液晶显示面板中，提供电压以驱动液晶偏转的公共电极和像素电极都设置在阵列基板中，因此在对置基板上没有设置电极以对液晶分子起保护作用，当带电物体(例如人体)从对置基板所在侧接触液晶显示面板时，带电物体上的静电会转移到液晶显示面板上，影响液晶分子的偏转，从而影响画面显示效果，此时，可以通过在对置基板的远离阵列基板的一侧设置一层透明导电层并将该透明导电层接地的方式，以屏蔽外界信号，从而保证液晶盒内电场均匀，确保产品品质和信赖性。因此，对于水平电场型液晶显示面板，可以利用对置基板远离阵列基板一侧透明导电层将对置基板上的静电引至导电胶上，也就是说，本发明上述实施例中的静电传导结构可以为位于对置基板200的远离阵列基板100一侧的透明导电层201，如图2a所示。例如，透明导电层201可以采用氧化铟锌、氧化铟锡、氧化铟镓锌等透明的金属氧化物制作。
对于对置基板的远离阵列基板一侧没有设置透明导电层的显示面板，例如垂直电场型液晶显示面板，可以将静电传导结构设计为设置于对置基板周边的走线。例如，如图1b所示，对置基板200上的静电传导结构为环绕对置基板200周边的第一走线202，例如，第一走线202可以位于显示区域110 外，且第一走线202可以位于对置基板200的面向阵列基板100的一侧(如图1b所示)或者位于对置基板200的远离阵列基板100的一侧。
需要说明的是，环绕(或设置于)对置基板周边的第一走线是指第一走线可以设置在对置基板的至少一条边所在的区域中。图1b仅以第一走线设置于对置基板的三条边所在的区域中为例进行说明；本发明实施例包括、但不限于此。
例如，第一走线设置于对置基板的面向阵列基板一侧时，点胶区域可以设置于阵列基板的主体区域内。在这种情况下，可以采用人工方式在点胶区域中设置导电胶，以便导电胶与第一走线电连接。
在至少一个实施例中，第一走线可以与对置基板上的电极同层设置，以在同一构图工艺中同时形成第一走线和电极，进而减少工艺流程。例如，在垂直电场型液晶显示面板中，如图2b所示，对置基板200在其面向阵列基板100的一侧设置有公共电极204和第一走线202，因此，可以在形成公共电极的同时形成公共电极204和第一走线202。例如，对于嵌入式触控显示面板，通常在对置基板上设置有触控电极(例如触控感应电极)，例如，覆盖表面式(On cell)触控显示面板在对置基板的远离阵列基板的一侧设置有触控电极，内嵌式(In cell)触控显示面板在对置基板的面向阵列基板的一侧设置有触控电极，因此，可以在形成触控电极的同时形成第一走线。
由于对置基板上的电极通常采用透明导电材料制作，因此，与电极同时形成的第一走线202的材料也为透明导电材料，例如氧化铟锌、氧化铟锡、氧化铟镓锌等透明的金属氧化物。当然，第一走线202也可以不与对置基板上的透明电极同时形成，在这种情况下，第一走线202也可以采用金属材料制作。
需要说明的是，为了更清楚地说明本发明实施例，图2b未示出对置基板200上的例如彩色滤光层、平坦层等结构。
在将对置基板200上的静电导出的同时，本发明实施例提供的显示面板还可以通过将阵列基板上的部分静电引至导电胶90上之后导出至接地部件的方式，在一定程度上将阵列基板上的静电导出。例如，可以将位于主体区域11中的栅极信号线、数据信号线等信号线通过本领域技术人员常用的静电环等方式与导电胶90电连接。例如，在至少一个实施例中，如图1a所示， 阵列基板100上还可以设置有环绕其周边的第二走线15，第二走线15可以与导电胶电连接或通过电极脚与印刷电路板60电连接。例如，在图1a中，第二走线15位于显示区域110外，第二走线15的首端和尾端均位于点胶区域30中以与导电胶90电连接。例如，第二走线15可以与阵列基板主体区域中的栅极信号线同时形成以节省工艺流程。本发明实施例通过使第二走线通过导电胶或电极脚与接地部件电连接，更有利于将阵列基板上的静电导出。
需要说明的是，图1a以采用GOA模式为例进行说明，当采用COF模式时，阵列基板上的第二走线还可以利用COF(柔性电路薄膜)上的走线跨过COF区域。此外，阵列基板上可以设置有环绕其周边的第二走线是指第二走线可以设置在阵列基板的至少一个边所在的区域中。图1a仅以第二走线设置于阵列基板的三条边所在的区域中为例进行说明；本发明实施例包括、但不限于此。
在至少一个实施例中，导电胶90可以通过静电导出线40与接地部件电连接，此时，静电导出线40可以包括位于点胶区域30中且与导电胶90电连接的部分41，以及位于点胶区域30外且与接地部件电连接的部分42。如图1a和图1b所示，阵列基板100的数据信号输入侧设置有印刷电路板60，阵列基板100上设置的信号线的末端通过电极脚20连接到该印刷电路板60。需要说明的是，图1a和图1b中未示出信号线与电极脚的连接关系。由于印刷电路板60接地设置，因而，在至少一个实施例中，接地部件可以为印刷电路板60，即在这种情况下，导电胶90可以通过静电导出线40与印刷电路板60电连接，静电导出线40包括位于点胶区域30中且与导电胶90电连接的部分41，以及位于点胶区域30外且与接地部件(印刷电路板60)电连接的部分42。
在本发明实施例中，导电胶90可以通过自动化点胶设备滴入点胶区域30中，由于表面张力作用，导电胶90形成椭圆形并浸润到静电导出线40的位于点胶区域30中的部分41上，实现导电胶90与静电导出线40的位于点胶区域30中的部分41电连接，从而导电胶90上的静电可以通过静电导出线40导出到印刷电路板60上。
图3a为本发明实施例提供的一种导电胶通过静电导出线与印刷电路板电连接的结构示意图；并且，图3a以显示面板采用COF方式为例进行说明。 如图3a所示，在电极脚20与印刷电路板60之间设置有柔性电路薄膜61，该柔性电路薄膜61运用软性电路板作封装芯片的载体，将芯片与软性电路板接合。在封装过程中，将柔性电路薄膜61进行弯折，可以使印刷电路板60位于阵列基板的远离对置基板的一侧，之后采用封装边框(例如金属边框或塑料边框)将对置基板和阵列基板固定。在本发明实施例中，由于导电胶90通过静电导出线40与印刷电路板60电连接，即使在液晶显示面板采用塑料边框封装的情况下，液晶显示面板中的静电也可以通过印刷电路板得到释放。
此外，当液晶显示面板采用金属边框时，接地部件也可以为金属边框。图3b为本发明实施例提供的一种导电胶与金属边框的表面接触的结构示意图。如图3b所示，对置基板200和阵列基板100对盒后通过支架500和金属边框50进行固定，通过控制导电胶滴入阵列基板100的点胶区域中的量，可以使位于导电胶90与金属边框50的表面接触以实现导电胶90与金属边框50之间的电连接，从而导电胶90上的静电可以导出至金属边框50上。在图3b中，在阵列基板100的远离对置基板200的一侧还可以设置背光源400，以便为液晶显示面板提供背光。
需要说明的是，在本发明实施例中，根据液晶显示面板的封装方式或驱动方式的不同，阵列基板包括的周边区域的数量也不相同。例如，图1a所示的显示面板采用GOA模式，其阵列基板100的一条切割线超出该切割线对应的对置基板200的切割线，即阵列基板100包括一个周边区域12。当然，阵列基板100也可以包括多个周边区域。例如，图1b所示的显示面板采用COF模式，其阵列基板100采用双边栅极驱动，因此阵列基板100包括三个周边区域12、13和14。点胶区域30可以位于这三个周边区域中的至少一个或几个的组合中。
在至少一个实施例中，可以将点胶区域30设置于阵列基板100沿其所在平面方向设置有印刷电路板60的一侧，即如图1a和图1b中的周边区域12所在的一侧。点胶区域30设置于印刷电路板所在的一侧，相比设置于阵列基板的其他侧，可以减小静电导出线的长度，从而减小静电导出线的电阻。例如，在图1b中，点胶区域30设置于周边区域12中，静电导出线只经过周边区域12，与点胶区域设置在周边区域13或14中需经过周边区域13或14以及周边区域12的情形相比，这样可以有效地缩短静电导出线的长度。此外， 在本发明实施例中，将点胶区域30设置于阵列基板设置有印刷电路板60的一侧，使得设置有点胶区域的阵列基板可以采用GOA(如图1a所示)、COF(如图1b所示)等多种模式，从而具有较好的通用性。
如图1a和图1b所示，在阵列基板100的数据信号输入侧(即周边区域12所在的一侧)还设置有Pad区域，即阵列基板的多种信号线与外部的驱动电路板的引线进行压接的区域。为了防止信号线和电极脚20被水汽腐蚀，通常在Pad区域中涂有UV胶21(即紫外光固化胶)，UV胶21覆盖信号线和电极脚20。在本发明实施例中，当导电胶90通过静电导出线40与印刷电路板电连接时，UV胶21还可以覆盖静电导出线40的位于点胶区域30外的部分42，如图1a和图1b所示，以防止其被水汽腐蚀或被划伤。如果点胶区域位于周边区域12的中部，自动化点胶设备在涂覆UV胶的过程中需将探头抬起并中断涂胶以避免UV胶覆盖点胶区域，这导致UV胶不能连续涂覆，进而降低UV胶的涂覆效率。为了保证点胶区域30不对UV胶的涂覆造成影响，保证UV胶能够连续涂覆，从而节省自动化点胶设备涂覆UV胶的时间，在至少一个实施例中，点胶区域30可以位于阵列基板100的顶角处，也就是说，将点胶区域30设置于周边区域12的端部。图1a和图1b均以两个点胶区域30分别设置于阵列基板100的顶角α和β所在的位置为例进行说明。
下面结合图4a、图4b和图4c并以液晶显示面板为例对本发明实施例中静电导出线40进行详细说明。
如图4a、图4b和图4c所示，阵列基板100的衬底基板上可以依次设置有薄膜晶体管70的栅极71、栅绝缘层77、有源层72以及源/漏极73、74，钝化层78、像素电极75，像素电极75通过钝化层78中的过孔与薄膜晶体管的漏极74电连接。
沿阵列基板所在平面的方向上，静电导出线40包括位于点胶区域30中的部分41和位于点胶区域30外的部分42，如图1a和图1b所示；沿垂直于阵列基板100所在平面的方向上，静电导出线40包括第一导电部410，如图4a、图4b和图4c所示，例如，第一导电部410可以与阵列基板中的电极同层设置。这样可以通过一次构图工艺在形成阵列基板显示区域中的电极的同时形成静电导出线40的第一导电部410，以省去单独形成静电导出线所需的构图工艺，从而减少工艺流程。
阵列基板的主体区域中设置有薄膜晶体管70，薄膜晶体管70包括栅极71、有源层72、源极73和漏极74，由于栅极71和源/漏极73、74采用金属制作，如铝、铜、钼等金属，金属的电阻较小，因此，在至少一个实施例中，静电导出线40的第一导电部410可以与栅极71同层设置，如图4a和图4c所示；或者，第一导电部410可以与源/漏极73、74同层设置，如图4b所示，也就是说，上述阵列基板中的电极为栅极或者源/漏极。
需要说明的是，根据栅极的位置，薄膜晶体管70可以分为顶栅型(即栅极71位于有源层72的远离衬底基板10的一侧)和底栅型(即栅极71位于有源层72的面向衬底基板10的一侧，如图4a、4b和4c所示)；根据源/漏极73、74与有源层72的接触方式，薄膜晶体管70可以分为顶接触型(即源/漏极73、74位于有源层72的远离衬底基板10的一侧，如图4a、4b和4c所示)和底接触型(即源/漏极73、74位于有源层72的面向衬底基板10的一侧)。在本发明实施例中，为了避免静电导出线40的第一导电部410发生断线，可以将静电导出线40的第一导电部410靠近衬底基板10设置，因此，本发明实施例优选薄膜晶体管为底栅型和/或底接触型。
此外，阵列基板中的栅极信号线与栅极连接，数据信号线与源/漏极连接，因此，第一导电部410、栅极71以及栅极信号线可以在同一构图工艺中形成，或者，第一导电部410、源/漏极73、74和数据信号线可以在同一构图工艺中形成。
为了避免静电导出线40被水汽腐蚀，如图4c所示，静电导出线40还可以包括覆盖第一导电部410的绝缘层430。此外，为了进一步保护第一导电部410，静电导出线40还可以包括第二导电部420，第二导电部420通过绝缘层430中的多个过孔43(即穿过绝缘层430的多个过孔43)与第一导电部410电连接。例如，第二导电部420可以采用氧化铟锡、氧化铟锌、氧化铟镓锌等透明导电材料制作，这样可以起到防止第一导电部410氧化的作用，而且，采用多个过孔43还可以增大第一导电部410与第二导电部420之间的接触面积，从而减小整个静电导出线40的电阻。本领域技术人员可以理解，绝缘层430中的过孔43的数量越多，第一导电部410与第二导电部420之间的接触面积越大，整个静电导出线40的电阻越小。
在本发明实施例中，绝缘层430可以利用主体区域中的栅绝缘层77和钝 化层78的材料等形成。例如，如图4c所示，在利用形成栅极71的栅金属层形成静电导出线40的第一导电部410后，在形成栅绝缘层77的过程中，使栅绝缘层材料同时覆盖第一导电部410；在栅绝缘层77上形成有源层72的过程中，将形成有栅绝缘层材料的第一导电部410上的有源层材料刻蚀掉；在有源层72上形成源/漏极73、74的过程中，将形成在第一导电部410上的源/漏金属层刻蚀掉；在源/漏极上形成钝化层78以及钝化层过孔的过程中，使钝化层材料同时覆盖形成有栅绝缘层材料的第一导电部410并形成过孔43，由此形成了静电导出线40的绝缘层430和绝缘层430中的过孔43，此时，该过孔43贯穿栅绝缘层材料和钝化层材料以暴露出第一导电部410的部分区域，从而使在其上形成的第二导电部420可以与第一导电部410电连接。
需要注意的是，根据实际情况，绝缘层430并不限于利用主体区域中的栅绝缘层77和钝化层78的材料形成。
例如，当图4c中的第一导电部410与源/漏极73、74同层设置时，即第一导电部410设置在栅绝缘层77上时，绝缘层430也可以仅利用主体区域中的钝化层78的材料形成。
例如，如图4b所示，静电导出线40的第一导电部410与源/漏极73、74同层设置，因而形成于第一导电部410与第二导电部420之间的绝缘层430的材料可以不包括栅绝缘层77的材料。
在至少一个实施例中，静电导出线40的第二导电部420可以与阵列基板主体区域中的像素电极75同层设置，如图4c所示。这样，在钝化层78上形成像素电极75的过程中，可以采用一次构图工艺同时形成像素电极75和第二导电部420。
此外，对于采用水平电场模式的显示面板，阵列基板中还可以设置有公共电极76，如图4a和4b所示。因此，在至少一个实施例中，第二导电部420也可以与公共电极76同层设置。
图4a和图4b以像素电极75位于公共电极76与衬底基板10之间为例进行说明，此时，在钝化层上形成像素电极75的过程中，可以保留像素电极材料的位于周边区域中的部分并使该部分像素电极材料通过过孔43与第一导电部410电连接；在形成像素电极75和公共电极76之间的绝缘层79的过程中，对该绝缘层79对应绝缘层430中的过孔43的部分进行过孔工艺以暴露 出像素电极材料的与第一导电部410电连接的部分；在绝缘层79上方形成公共电极76的过程中，可以采用一次构图工艺同时形成公共电极76和第二导电部420，从而第二导电部420通过位于过孔43中的像素电极材料与第一导电部410电连接。当然，在形成像素电极75的过程中，也可以刻蚀掉像素电极材料的位于周边区域中的部分，在这种情况下所形成的静电导出线40中，第二导电部420与第一导电部410直接电连接。
在本发明的上述实施例中，像素电极75和公共电极76为透明电极，通常采用透明金属氧化物制作，如ITO(氧化铟锡)等。
需要说明的是，本发明实施例不限定像素电极75和公共电极76在阵列基板中的位置关系。例如，像素电极75可以位于公共电极76的面向衬底基板10的一侧，如图4a和图4b所示；例如，像素电极75也可以位于公共电极76的远离衬底基板10的一侧。
对于同时包括像素电极75和公共电极76的阵列基板，图4a和图4b仅以第二导电部420与公共电极同层设置为例进行说明。根据实际情况，可以利用像素电极75和公共电极76中的任一个形成静电导出线40的第二导电部420。
图4a、图4b和图4c仅示例性地示出了导电胶90滴入过孔43中后与静电导出线40电连接的情形，其形状等并不反映真实形状。
在本发明实施例中，静电导出线40的第二导电部420通过绝缘层430中的多个过孔43与第一导电部410电连接的结构可以是主要针对静电导出线40的位于点胶区域30中的部分41而言，在静电导出线40的位于点胶区域30外的部分42上可以不设置绝缘层过孔和第二导电部。
此外，对于OLED显示面板，静电导出线的第一导电部也可以与阵列基板包括的薄膜晶体管的栅极或源/漏极同时形成(即同层设置)，覆盖第一导电部的绝缘层也可以利用薄膜晶体管的栅绝缘层和钝化层形成。当然，根据实际情况，第一导电部和覆盖第一导电部的绝缘层也可以利用OLED显示面板中阵列基板上的其他导电结构或绝缘层形成；相应地，第二导电部也可以利用OLED显示面板中阵列基板上的透明导电层形成。本发明实施例不做赘述。
为了使自动化点胶设备在点胶区域中滴入导电胶时获得更好的对位精 度，在至少一个实施例中，可以在点胶区域中形成对位标记。由于静电导出线40位于点胶区域30中的部分41与栅极或源/漏极同时形成，即采用相同的金属(例如镁、铝、铜、钛等)材料形成，金属通常不透明，易于识别，因此，可以利用静电导出线40的第一导电部410形成对位标记。
图5为本发明实施例提供的一种采用自动化点胶设备将导电胶滴到对位标记中的结构示意图。在图5中，点胶设备的锥形探头01内装有导电胶，在点胶过程中，点胶设备的探测装置02能够读取点胶区域30中的对位标记46。由于静电导出线40的第二导电部420和绝缘层430采用透明材料制作时，在强光的照射下，第一导电部410形成的对位标记的图案清晰可见，因此，点胶设备能够顺利读取并利用对位标记的图案实现反馈校准、粗对位及精对位功能。
图5示出了静电导出线40的第一导电部410形成“山”字形的对位标记。以在阵列基板中形成底栅型薄膜晶体管为例，对位标记的图案的制作过程例如为：在形成栅极的同时利用栅极金属层形成静电导出线40，使静电导出线40的对应点胶区域30中的部分41的第一导电部410的图案为“山”字形。
图5仅以“山”字形为例进行说明，图6a以“田”字和“口”字的组合为例进行说明，图6b以“田”字为例进行说明。但本发明实施例并不限于此，在至少一个实施例中，对位标记的图案可以包括“山”“田”“回”“口”字形，及“◆”“●”形中的至少一种或几种的组合。只要该对位标记能够被点胶设备的探测装置顺利读取，使点胶设备利用对位标记的图案能够实现反馈校准、粗对位及精对位功能即可。
如图2a和图2b所示，对置基板200与阵列基板100之间设置有封框胶300，点胶区域30设置于封框胶300的外侧(即图2a和图2b中封框胶300的左侧)。在至少一个实施例中，位于封框胶300内侧的对置基板200中的黑矩阵203的末端可以位于封框胶300中(如图2a和图2b所示)或位于封框胶300的内侧；和/或，位于封框胶300内侧的阵列基板100中的信号线80(例如栅极信号线、数据信号线)的末端可以位于封框胶300中或位于封框胶300的内侧。
由于涂覆到点胶区域中的导电胶的液滴成不规则形状，其外侧面由于表面张力接近椭圆型，并且由于导电胶在凝固之前的浸润作用，导电胶90容易 侵入到信号线80上及对置基板200上的黑矩阵203所在的层上，这可能造成信号线与静电串扰及黑矩阵层电荷累积。鉴于此，本发明实施例将显示装置内部的对置基板包括的黑矩阵层压缩到封框胶300中或封框胶300的内侧，可以避免出现由于黑矩阵层接触导电胶90而造成的黑矩阵层静电累积，进而影响到整个显示屏的像素液晶偏转的情形；本发明实施例将阵列基板中的信号线压缩到封框胶300中或封框胶300的内侧，可以避免信号线由于在导电胶90处没有UV胶覆盖、直接暴露出来而被水汽腐蚀。
本发明的至少一个实施例还提供了一种显示装置，其包括上述任一实施例所述的显示面板。例如，该显示装置为液晶显示装置，其还可以包括用于给显示面板提供光源的背光源，以及位于显示面板两侧的偏光片。
例如，本发明实施例提供的显示装置可以为：液晶面板、电子纸、OLED面板、触控面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明的至少一个实施例还提供了一种显示面板的制作方法，该方法包括：形成对置基板，对置基板上设置有静电传导结构；形成阵列基板，阵列基板包括主体区域和周边区域，主体区域与对置基板在阵列基板上的正投影重合，周边区域或主体区域中设置有至少一个点胶区域；将阵列基板与对置基板对盒成型；以及在点胶区域中滴入导电胶，使导电胶电连接静电传导结构和接地部件。
本发明实施例不限定在点胶区域中滴入导电胶的方式，导电胶可以人工方式滴入点胶区域中，也可以通过自动化设备滴入点胶区域中。
在至少一个实施例中，接地部件可以为阵列基板上设置的印刷电路板，在这种情况下，形成阵列基板的步骤包括在阵列基板的周边区域中形成静电导出线，使静电导出线包括位于点胶区域中的部分以及位于点胶区域外且与印刷电路板电连接的部分；在点胶区域中滴入导电胶的步骤包括使导电胶与静电导出线的位于点胶区域中的部分电连接，以实现导电胶通过静电导出线与印刷电路板电连接。
在至少一个实施例中，接地部件也可以为金属边框，在这种情况下，将阵列基板与对置基板对盒成型的步骤包括采用金属边框固定阵列基板和对置基板，在点胶区域中滴入导电胶的步骤包括使导电胶与金属边框的表面接触。
需要说明的是，本发明实施例中，形成对置基板的步骤与形成阵列基板的步骤的顺序不限，可以先形成阵列基板之后形成对置基板，也可以先形成对置基板之后形成阵列基板。
对于对置基板的远离阵列基板一侧设置有透明导电层的显示面板，例如水平电场型液晶显示面板，在至少一个实施例中，静电传导结构可以为位于对置基板的远离阵列基板的一侧的透明导电层。
对于对置基板的远离阵列基板一侧没有设置透明导电层的显示面板，例如垂直电场型液晶显示面板、OLED显示面板等，在至少一个实施例中，静电传导结构可以为环绕所述对置基板周边(即，设置于对置基板的至少一条边所在的区域中)的第一走线，第一走线位于对置基板的面向阵列基板的一侧或者对置基板的远离所述阵列基板的一侧。例如，第一走线可以与对置基板上的公共电极或触控电极在同一构图工艺中形成。触控电极可以位于对置基板的面向对置基板的一侧，或位于对置基板的远离阵列基板的一侧。
在至少一个实施例中，静电导出线沿垂直于阵列基板所在平面的方向包括第一导电部，第一导电部与阵列基板中的栅极或源/漏极在同一构图工艺中形成。
在至少一个实施例中，静电导出线还可以包括位于第一导电部远离阵列基板一侧的绝缘层和第二导电部，第二导电部通过绝缘层中的多个过孔与第一导电部电连接。例如，第二导电部可以与阵列基板中的像素电极或公共电极在同一构图工艺中形成。本发明实施例不限定像素电极和公共电极在阵列基板中的位置关系。
本发明实施例提供的显示面板的制作方法的实施可以参考上述显示面板的实施例，重复之处不再赘述。
综上所述，本发明实施例提供的显示面板及其制作方法、显示装置，至少具有如下优点之一。
(1)本发明实施例通过在阵列基板的周边区域或主体区域中设置点胶区域，在点胶区域中设置导电胶并使其与对置基板上的静电传导结构电连接，使得对置基板上的静电可以导出至点胶区域内的导电胶上，之后导出至接地部件，从而可以及时将阵列基板和对置基板中的静电导出，避免静电损坏。
(2)与人工贴附导电胶带的方式相比，本发明实施例可以采用自动化的 点胶设备将导电胶滴入点胶区域，从而节省人力成本和材料成本，提高生产效率。
(3)导电胶与对置基板远离阵列基板一侧的透明导电层电连接，在实现将对置基板上的静电导出的同时，还能够屏蔽外界信号，保证液晶盒内电场均匀，确保产品品质和信赖性。
(4)将点胶区域设置于阵列基板的数据信号输入侧，可以提高阵列基板的通用性，使其适用于COF、GOA等多种模式；将点胶区域设置于阵列基板的顶角处，使得UV胶可以连续涂覆在pad区域中。
(5)采用印刷电路板作为接地部件，使得本发明实施例可以应用于采用塑料边框的显示装置中。
(6)在静电导出线的层结构中，通过设置覆盖第一导电部的绝缘层以及通过绝缘层中的多个过孔与第一导电部电连接的第二导电部，可以减小静电导出线的整体电阻，防止静电导出线氧化或被水汽腐蚀；而且，在制作阵列基板中的各膜结构的同时形成静电导出线的层结构中相应的部分，可以减少工艺流程。
(7)通过在点胶区域中设置对位标记，使点胶设备能够顺利读取并利用对位标记的图案实现反馈校准、粗对位及精对位功能。
(8)将对置基板中的黑矩阵的末端压缩到封框胶中或封框胶内侧，可以避免黑矩阵层因与导电胶接触后累积静电而造成的液晶偏转异常。
(9)将阵列基板中的信号线的末端设置于封框胶中或封框胶内侧，可以避免导电胶与信号线直接接触，防止信号线暴露出来而被水汽腐蚀。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年12月31日递交的中国专利申请第201410850811.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (22)

  1. 一种显示面板，包括相对设置的阵列基板和对置基板，其中，
    所述阵列基板包括主体区域和周边区域，所述主体区域与所述对置基板在所述阵列基板上的正投影重合，所述周边区域或所述主体区域中设置有至少一个点胶区域，所述点胶区域中设置有导电胶，所述导电胶与接地部件电连接；
    所述对置基板上设置有静电传导结构，所述导电胶与所述静电传导结构电连接。
  2. 如权利要求1所述的显示面板，其中，所述静电传导结构为位于所述对置基板的远离所述阵列基板的一侧的透明导电层。
  3. 如权利要求1所述的显示面板，其中，所述静电传导结构为设置于所述对置基板周边的第一走线，所述第一走线位于所述对置基板的面向所述阵列基板的一侧或者所述对置基板的远离所述阵列基板的一侧。
  4. 如权利要求3所述的显示面板，其中，所述第一走线与所述对置基板上的电极同层设置。
  5. 如权利要求1-4任一项所述的显示面板，还包括金属边框，其中，所述接地部件为所述金属边框，所述导电胶与所述金属边框的表面接触。
  6. 如权利要求1-4任一项所述的显示面板，其中，所述导电胶通过静电导出线与所述接地部件电连接，所述静电导出线包括位于所述点胶区域中且与所述导电胶电连接的部分，以及位于所述点胶区域外且与所述接地部件电连接的部分。
  7. 如权利要求6所述的显示面板，其中，所述阵列基板包括印刷电路板，所述接地部件为所述印刷电路板。
  8. 如权利要求7所述的显示面板，其中，所述点胶区域设置于所述阵列基板沿其所在平面的方向设置有所述印刷电路板的一侧。
  9. 如权利要求1-6任一项所述的显示面板，其中，所述阵列基板包括印刷电路板，所述点胶区域设置于所述阵列基板沿其所在平面的方向设置有所述印刷电路板的一侧。
  10. 如权利要求1-9任一项所述的显示面板，其中，所述点胶区域位于 所述阵列基板的顶角处。
  11. 如权利要求1-10任一所述的显示面板，其中，所述静电导出线沿垂直于所述阵列基板所在平面的方向包括第一导电部，所述阵列基板的所述主体区域中设置有薄膜晶体管，所述薄膜晶体管包括栅极和源/漏极，所述第一导电部与所述栅极或者所述源/漏极同层设置。
  12. 如权利要求11所述的显示面板，其中，所述静电导出线还包括绝缘层，所述绝缘层覆盖所述第一导电部。
  13. 如权利要求12所述的显示面板，其中，所述静电导出线还包括第二导电部，所述第二导电部通过所述绝缘层中的多个过孔与所述第一导电部电连接。
  14. 如权利要求13所述的显示面板，其中，
    所述阵列基板还包括像素电极，所述第二导电部与所述像素电极同层设置；或者
    所述阵列基板还包括像素电极和公共电极，所述第二导电部与所述像素电极或所述公共电极同层设置。
  15. 如权利要求11-14任一项所述的显示面板，其中，所述点胶区域中设置有对位标记。
  16. 如权利要求15所述的显示面板，其中，所述对位标记由所述第一导电部形成。
  17. 如权利要求1-10任一项所述的显示面板，其中，所述点胶区域中设置有对位标记。
  18. 如权利要求15-16任一项所述的显示面板，其中，所述对位标记的图案包括“山”“田”“回”和“口”字形以及“●”和“◆”中的至少一种或几种的组合。
  19. 如权利要求1-18任一项所述的显示面板，还包括位于所述对置基板与所述阵列基板之间的封框胶，其中，
    所述点胶区域设置于所述封框胶的外侧；并且
    所述对置基板包括黑矩阵，所述黑矩阵位于所述封框胶内侧，且所述黑矩阵的末端位于所述封框胶中或位于所述封框胶的内侧；和/或
    所述阵列基板还包括信号线，所述信号线的末端位于所述封框胶中或位 于所述封框胶的内侧。
  20. 如权利要求1-19任一项所述的显示面板，其中，所述阵列基板还包括设置于所述阵列基板周边的第二走线，所述第二走线与所述导电胶或所述接地部件电连接。
  21. 一种显示装置，包括如权利要求1-20任一项所述的显示面板。
  22. 一种显示面板的制作方法，包括：
    形成对置基板，其中，所述对置基板上设置有静电传导结构；
    形成阵列基板，其中，所述阵列基板包括主体区域和周边区域，所述主体区域与所述对置基板在所述阵列基板上的正投影重合，所述周边区域或所述主体区域中设置有至少一个点胶区域；
    将阵列基板与对置基板对盒成型；以及
    在所述点胶区域中滴入导电胶，使所述导电胶电连接所述静电传导结构以及所述显示面板中的接地部件。
PCT/CN2015/081416 2014-12-31 2015-06-15 显示面板及其制作方法、显示装置 Ceased WO2016107093A1 (zh)

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