Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/02—Transmitters
  • H04B1/03—Constructional details, e.g. casings, housings
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/0237—Materials
  • H01L21/02373—Group 14 semiconducting materials
  • H01L21/02378—Silicon carbide
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/0237—Materials
  • H01L21/02373—Group 14 semiconducting materials
  • H01L21/02381—Silicon, silicon germanium, germanium
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02524—Group 14 semiconducting materials
  • H01L21/02529—Silicon carbide
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  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02524—Group 14 semiconducting materials
  • H01L21/02532—Silicon, silicon germanium, germanium
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02612—Formation types
  • H01L21/02617—Deposition types
  • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
  • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
  • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
  • H01M4/00—Electrodes
  • H01M4/02—Electrodes composed of, or comprising, active material
  • H01M4/64—Carriers or collectors
  • H01M4/66—Selection of materials
  • H01M4/663—Selection of materials containing carbon or carbonaceous materials as conductive part, e.g. graphite, carbon fibres
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
  • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/031—Manufacture or treatment of data-storage electrodes
  • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/80—Constructional details
  • H10N30/87—Electrodes or interconnections, e.g. leads or terminals
  • H10N30/877—Conductive materials
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
  • Y02E60/10—Energy storage using batteries

Definitions

• the present invention relates to the field of integrated radio frequency devices.
• Integrated devices are usually developed on platelet-shaped substrates, which serve primarily as a support for their manufacture.
• the increase in the degree of integration and the expected performance of these devices leads to an increasingly important coupling between their performance and the characteristics of the substrate on which they are formed. This is particularly the case of radio frequency (RF) devices, processing signals whose frequency is between about 3kHz and 300GHz, which find particular application in the field of telecommunications (cellular telephony, Wi-Fi, Bluetooth ...) .
• RF radio frequency
• the electromagnetic fields originating from the high frequency signals propagating in the devices, penetrate the depth of the substrate and interact with the possible charge carriers therein. This results in problems of nonlinear distortion of the signal (harmonics), unnecessary consumption of a part of the signal energy by loss of insertion and possible influences between components.
• RF devices have characteristics governed both by their architectures and production processes and by the capacity of the substrate on which they are manufactured to limit insertion losses, crosstalk between neighboring devices, and nonlinear distortion phenomena generating harmonics.
• Radio frequency devices such as antenna switches and adapters as well as power amplifiers, can be developed on different types of substrates.
• silicon substrates on sapphire commonly known as SOS (for "silicon on sapphire” according to the English name) are known to provide components developed using microelectronic technologies in the surface layer of silicon.
• the antenna switches and power amplifiers manufactured on this type of substrate have very good merit factors but are mainly used for niche applications because of the overall cost of the solution.
• High-resistivity silicon substrates comprising a support substrate, a trapping layer disposed on the support substrate, a dielectric layer disposed on the trapping layer, and a semiconductor layer disposed on the dielectric layer.
• the support substrate usually has a resistivity greater than 1 kOhm.cm.
• the trapping layer may comprise undoped polycrystalline silicon.
• An object of the invention is therefore to provide a structure adapted for radio frequency applications, overcoming the drawbacks of the prior art.
• An object of the invention is to provide an integrated structure ensuring radio frequency performance, especially in the range of operating temperatures.
• the invention relates to a structure for radiofrequency applications comprising: A semiconductor support substrate;
• a trapping layer disposed on the support substrate.
• the trapping layer is remarkable in that it comprises a defect density greater than a predetermined defect density;
• the predetermined density of defects is the density of defects for which the electrical resistivity of the trapping layer is greater than or equal to 10 k ⁇ hm over a temperature range [-20 ° C .; + 120 ° C].
• the structure for radio frequency applications according to the invention thus has temperature-stable electrical properties, ensuring a good stability and repeatability of the RF performances in the temperature range of use.
• the trapping layer has a resistivity, at 20
• the difference in coefficient of thermal expansion of the trapping layer and the support substrate is less than 5 ppm / K between 100 ° C. and 1200 ° C .;
• the trapping layer comprises microstructures of size less than 20 nm, preferably less than 10 nm;
• the trapping layer comprises a porous or polycrystalline material
• the trapping layer comprises polycrystalline silicon comprising 1 to 20% of carbon
• the thickness of the trapping layer is between 10 and 50 ⁇ m, preferably between 20 and 30 ⁇ m;
• the support substrate comprises at least one of the materials selected from the following group: silicon, silicon germanium, silicon carbide;
• the resistivity of the support substrate is between 10 and 2000 Ohm. cm.
• an active layer is placed on the trapping layer
• the active layer is transferred to the trapping layer by direct bonding
• the active layer is formed from a semiconductor material
• the active layer is formed from a piezoelectric material
• the thickness of the active layer is between 10 nm and 50 ⁇ m;
• a dielectric layer is disposed between the trapping layer and the active layer
• the dielectric layer is transferred to the trapping layer by direct bonding
• the dielectric layer is between 10 nm and 6 ⁇ m.
• At least one microelectronic device is present on or in the active layer:
• the microelectronic device is a switching circuit or an antenna adaptation circuit or a radio frequency power amplification circuit; the microelectronic device comprises a plurality of active components and a plurality of passive components;
• the microelectronic device comprises at least one control element and a MEMS switching element consisting of an ohmic contact microswitch or a capacitive microswitch;
• the microelectronic device is a radiofrequency filter operating by propagation of acoustic waves of volume or of surface.
• FIG. 1 represents a structure for radiofrequency applications according to the invention, comprising a substrate and a trapping layer;
• FIG. 2 presents comparative curves of the resistivity of structures according to the state of the art and of a structure according to the invention
• FIGS. 3a and 3b respectively represent a structure for radiofrequency applications in accordance with the invention, further comprising an active layer; - Figures 4a and 4b respectively show a structure for radio frequency applications according to the invention, further comprising a microelectronic device.
• the structure 1,1 ', 11 for radio frequency applications comprises a support substrate 2 semiconductor.
• the support substrate 2 may be made of materials commonly used in the microelectronics, optics, opto-electronics and photovoltaic industries.
• the support substrate 2 may comprise at least one material selected from the following group: silicon, silicon germanium, silicon carbide, etc.
• the resistivity of the support substrate may be between 1 and 100OOohm.cm; it is advantageously between 10 and 2000ohm.cm.
• the structure 1,1 ', 11 for radio frequency applications also comprises a trapping layer 3 disposed on the support substrate 2, as shown in FIGS. 1,3 and 4.
• the trapping layer 3 comprises a density of defects greater than a density predetermined defects; the predetermined defect density is the defect density for which the electrical resistivity of the trapping layer is greater than or equal to 10 k ⁇ / cm over the temperature range [-20 ° C; + 120 ° C].
• the determination of the number of defects or of the density of defects can be carried out by various techniques, including transmission electron microscopy (TEM in the English terminology).
• the known density of defects, the electrical resistivity of the trapping layer 3 can be measured at different temperatures.
• the predetermined density of defects may be between 10 19 and 10 21 cm -3 (for example, in the case of a polycrystalline silicon trapping layer).
• defect means grain boundaries in the polycrystalline materials, vacuum zones in the porous materials, interstices, inclusions, etc.
• the trapping layer 3 comprises microstructures smaller than 20 nm; preferably, the microstructures are even smaller than 10 nm.
• microstructures is meant crystallites, especially for polycrystalline materials, also called grains.
• the trapping layer 3 also has a resistivity greater than 10 kOhm.cm at room temperature; preferably, it has a resistivity greater than 50kohm.cm.
• the aforementioned physical (microstructure) and electrical (resistivity) characteristics of the trapping layer 3 make it possible to provide a jump-through conductivity mechanism therein, which has a low dependence as a function of temperature; the resistivity of the trapping layer 3 similarly has a low dependence on temperature, compared to layers of the state of the art, making it possible to maintain a level greater than 10 k ohm cm over the entire range of temperatures .
• the thickness of the trapping layer 3 may be between 10 and 50 mm; preferably, it is between 20 and 30mm. The thickness of the trapping layer 3 is such that the RF signals from the components manufactured on the structure 1.1 'penetrate and propagate mainly in the trapping layer 3, without reaching the underlying support substrate 2.
• the electrical properties of the substrate substrate assembly 2 and trapping layer 3 are thus essentially dictated by the properties of the trapping layer 3.
• the requirements on the resistivity of the support substrate 2 are therefore lower.
• the cost and availability of substrates whose resistivity is in the range 10-1000ohm. cm are more favorable than those of substrates with very high resistivity (> 1000ohm.cm and up to 20kohm.cm).
• the trapping layer 3 also has a small difference in coefficient of thermal expansion with the support substrate 2 between 100 ° C. and 1200 ° C., advantageously less than 5 ppm / K. Indeed, the subsequent manufacture of RF components above the trapping layer 3 generally requires heat treatment steps at temperatures above 850 ° C or even above 1100 ° C, for example 1200 ° C. At such temperatures, and for trapping layer thicknesses 3 of the order of a few tens of microns, a difference in coefficient of excessive thermal expansion between the trapping layer 3 and the support substrate 2 may cause incompatible deformations. with subsequent manufacturing processes, even likely to break the substrate. A difference in coefficient of thermal expansion between the trapping layer 3 and the support substrate 2 less than 5ppm / K prevents the risk of breakage of the structure.
• the trapping layer 3 is advantageously made of porous or polycrystalline material.
• the support substrate 2 is a silicon substrate and the trapping layer 3 is a porous silicon layer comprising microstructures less than 20 nm in size, having a porosity greater than 50% and a thickness of 30 mm.
• the formation of the porous silicon layer advantageously comprises the following steps:
• a p-doped silicon layer (boron for example) by epitaxy on the support substrate, said formation being carried out by a vapor deposition technique, at a temperature of between 900 ° C. and 1200 ° C., with precursors of trichlorosilane and diborane (B 2 H 6 );
• the size of the microstructures confers on the trapping layer 3 a resistivity greater than 10kohm.cm, stable over the entire temperature range [-20 ° C; 120 ° C].
• the pores of the trapping layer 3 are not affected during a high temperature heat treatment step (typically up to 1100 ° C.): the size of the grains of the layer 3 governing the resistivity of said layer 3, its electrical properties remain unchanged after heat treatments of component development.
• the support substrate 2 is a silicon substrate and the trapping layer 3 is a polycrystalline silicon layer comprising grains of size less than 20 nm, preferably less than 10 nm and having a thickness of between 10 and 50 ⁇ m, for example 30 ⁇ m.
• the difference in coefficient of thermal expansion between the support substrate 2 and the trapping layer 3 is less than 5 ppm / K, and prevents any excessive deformation of the substrate that may cause it to break.
• the layer of trapping 3 also has a resistivity greater than 50kOhm.cm at room temperature.
• the polycrystalline silicon layer advantageously comprises carbon at a higher temperature. content between 1 and 20%, for example 5%.
• the realization of such a trapping layer 3 requires the use of chemical vapor deposition techniques.
• the formation temperature of the layer must then be greater than 700 ° C., preferably greater than 900 ° C., even more preferentially between 1100 and 1200 ° C.
• the precursors of carbon (C) can comprise at least one of the elements chosen from: methylsilane (SiH3CH3), methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H10), and methyltrichlorosilane (SiCH3C13).
• the precursors of silicon (Si) may comprise at least one of the elements chosen from: silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), trichlorosilane (SiHC13), tetrachlorosilane (SiCl4).
• a carbon doping of the poly-silicon layer makes it possible to stabilize the size of the grains during a thermal anneal comprising a rise in temperature higher than 850 ° C., for example 1200 ° C. Indeed, without this carbon doping, the grains of the trapping layer 3 poly-silicon reorganize and increase their size; this has the effect of drastically reducing the resistivity of the trapping layer 3, and degrade its electrical characteristics.
• FIG. 2 represents the resistivity of the trapping layer 3 according to the invention (curve C) simulated over the temperature range [20 ° C. to 140 ° C.]: it can be noted that the resistivity of said layer 3 is greater than 10kohm .cm, at least up to 120 ° C, which corresponds to the upper limit of the target temperature range.
• the simulated resistivity of state-of-the-art structures (curves A and B) has values well below 10kohm.cm at 120 ° C, which does not allow sufficient RF performance to meet specifications. demanding LTE (Long Term Evolution) standards for mobile telephony.
• a structure 1,1 ', 11 for RF applications according to the invention may in turn ensure a stable performance, not sensitive to temperature variations in the range of use.
• the structure 1 for radiofrequency applications may take the form of a wafer of dimensions compatible with microelectronic processes, for example with a diameter of 200 mm or
• the structure 1 for radio frequency applications may take the form of a wafer and may further comprise an active layer 5, arranged on the trapping layer 3, in and on which RF components can be developed.
• the active layer 5 can advantageously be made of semiconductor materials and / or piezoelectric materials.
• the active layer 5 comprises at least one of: silicon, silicon carbide, silicon germanium, lithium niobate, lithium tantalate, quartz, aluminum nitride.
• the thickness of the active layer 5 may vary from a few nanometers (for example 10 nm) to several tens of microns (for example 50 mm) depending on the components to be manufactured.
• the active layer 5 is transferred to a support substrate 2 comprising the trapping layer 3 by one of the thin-film transfer methods well known to those skilled in the art, among which:
• the Smart Cut TM process based on an implantation of light ions of hydrogen and / or helium in a donor substrate and a bonding for example by molecular adhesion of this donor substrate to the trapping layer 3, itself arranged on the support substrate 2; a detachment step then makes it possible to separate a thin surface layer of the donor substrate (the active layer), at the level of the weakening plane defined by the implantation depth of the ions. Finishing steps that can include heat treatments at high temperature finally provide the crystalline and surface quality required for the active layer 5.
• This process is particularly suitable for the manufacture of thin active layers, of thickness ranging from a few nanometers to about 1 , 5mm for example for silicon layers.
• the structure 1 for radio frequency applications may also include a dielectric layer 4, arranged between the active layer 5 and the trapping layer 3.
• the dielectric layer 4 will comprise at least one of: silicon dioxide, silicon nitride, aluminum oxide ... Its thickness may vary between 10 nm and 6 mm.
• the dielectric layer 4 is obtained by thermal oxidation or by LPCVD or PECVD or HDP deposition, on the trapping layer 3 or on the donor substrate prior to the transfer of the active layer 5 to the trapping layer 3.
• the structure 11 for radiofrequency applications can also comprise or consist of a microelectronic device 6 on or in the active layer 5, which is arranged on a dielectric layer 4 or directly on the layer 3.
• the microelectronic device 6 may be a switching circuit (called a "switch” according to the English terminology), an adaptation or tuning circuit (called a “tuner”), or a power amplification circuit (called “power amplifier”), developed according to silicon microelectronic technologies.
• the active silicon layer 5 typically has a thickness of between 50 nm and 180 nm, for example 145 nm, and the underlying dielectric layer 4 has a thickness of between 50 nm and 400 nm, for example 200 nm; the trapping layer 3 is disposed between the dielectric layer 4 and the support substrate 2.
• the microelectronic device 6 developed in and on the active layer 5 comprises a plurality of active components (MOS type, bipolar, ...) and a plurality passive components (capacitors, inductors, resistors, resonators, filters, ).
• the manufacture of microelectronic components requires the realization of several steps, including heat treatments at high temperatures, typically at 950-1100 ° C, or even beyond.
• the trapping layers 3 described in the first and second examples cited above retain their physical and electrical properties after such heat treatments.
• the microelectronic device 6 can first be produced on a substrate of the SOI type (for "silicon on insulator” according to the English terminology), then reported by a known layer transfer technique. of a person skilled in the art, on a structure 1 according to the invention comprising the trapping layer 3 disposed on the support substrate 2. In this case, as represented in FIG.
• the structure 11 comprises the support substrate 2 on which is disposed the trapping layer 3; above this, there is the layer of components of the microelectronic device 6: the so-called “back end” portion of layers of metal interconnections and dielectrics is disposed above the trapping layer 3, the so-called part " front end "(silicon), developed partly in the active layer, being itself above the "back-end” part. Finally, there is still above the active layer 5 and optionally a dielectric layer 4 '.
• the structure 11 for radiofrequency applications may comprise or consist of a microelectronic device 6 comprising at least one control element and a MEMS switching element (microelectromechanical systems) according to the English name. Saxon) consisting of an ohmic contact microswitch or a capacitive microswitch.
• the manufacture of MEMS can be facilitated by the presence of a dielectric layer 4 under a silicon active layer 5.
• the structure 11 according to the invention may therefore comprise, by way of example, an active silicon layer 5 having a thickness of between 20 nm and 2000 nm, advantageously 145 nm, and an underlying dielectric layer 4 having a thickness of between 20 nm and 1000 nm, advantageously 400 nm; the trapping layer 3 is disposed between the dielectric layer 4 and the support substrate 2.
• the manufacture of the MEMS part is then based on surface micromachining techniques, in particular allowing the release of beams or mobile membranes in the active layer 5 of silicon.
• the MEMS portion may be prepared directly on the trapping layer 3, by successive deposition of a plurality of layers (including an electrode, a dielectric, a sacrificial layer, a active layer) and by making patterns on these different layers.
• CMOS control element or elements
• the microelectronic processes for manufacturing the control element or elements usually performed before the MEMS part, require, as in the previous embodiment, the application of heat treatments at high temperatures.
• the fact that the trapping layer 3 according to the invention does not undergo physical and electrical modifications during this type of treatment is therefore very advantageous.
• the structure 11 for radio frequency applications may comprise or consist of a microelectronic device 6 comprising a radiofrequency filter operating by acoustic wave propagation volume (called "BAW" for "Bulk Acoustic Wave” according to the English name).
• the manufacture of a BAW filter type FBAR requires an active layer 5 consisting of a piezoelectric material, in which the wave will be confined. acoustic, between the two electrodes that surround it.
• the structure 11 according to the invention may therefore comprise, by way of example, an active layer 5 of aluminum nitride with a thickness of between 50 nm and 1 mm, advantageously 100 nm, and a dielectric layer 4 (for example silicon oxide) whose thickness is between 1 and 6 mm; the trapping layer 3 is disposed between the dielectric layer 4 and the support substrate 2. Insulation cavities are provided under the active zones of the filter, that is to say the zones in which the acoustic waves will be brought into contact. spread.
• the manufacture of the BAW filter also requires electrode deposition steps at which the RF signal will be applied.
• the structure according to the invention makes it possible, on the one hand, to limit the depth of the insulating cavities whose insulation function with respect to the substrate is made less critical by the resistivity greater than 10kohm.cm of the trapping layer 3, on the entire temperature range targeted; it is an advantage in terms of simplification, flexibility and robustness of manufacturing process of these devices.
• the structure 11 according to the invention makes it possible to obtain better performance of the filters over the entire temperature range targeted for use of the device 6, in particular in terms of linearity.
• the microelectronic device 6 comprises a radiofrequency filter operating by surface acoustic wave propagation (called “SAW” for “Surface Acoustic Wave” according to the Anglo-Saxon name).
• SAW surface acoustic wave propagation
• the manufacture of a SAW filter requires an active layer 5 made of a piezoelectric material, on the surface of which will be developed a comb of electrodes: the acoustic wave is intended to propagate between these electrodes.
• the structure 11 according to the invention may therefore comprise, by way of example, an active layer 5 of lithium tantalate with a thickness of between 200 nm and 20 mm, advantageously 0.6 mm; the trapping layer 3 is disposed between the active layer 5 and the support substrate 2.
• a dielectric layer 4 may optionally be added between the active layer 5 and the trapping layer 3.
• the structure 11 according to the invention makes it possible to obtain better filter performances over the entire temperature range targeted for use of the device 6, in particular in terms of insertion losses and linearity.
• the structures 1,1 ', 11 for radio frequency applications according to the invention are not limited to the embodiments mentioned above. They are suitable for any application for which high frequency signals propagate and are liable to suffer unwanted losses or disturbances in a support substrate 2, because the physical and electrical characteristics of the trapping layer 3 disposed on the support substrate 2 give the structure 1,1 ', 11 good RF properties (limiting losses, nonlinearities and other disturbances), stable over a range of operating temperatures, ie [-20 ° C; 120 ° C].

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• 2014
  • 2014-12-04 FR FR1402801A patent/FR3029682B1/fr active Active
• 2015
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