JP6612872B2 - 高周波用途のための構造 - Google Patents

高周波用途のための構造 Download PDF

Info

Publication number
JP6612872B2
JP6612872B2 JP2017529767A JP2017529767A JP6612872B2 JP 6612872 B2 JP6612872 B2 JP 6612872B2 JP 2017529767 A JP2017529767 A JP 2017529767A JP 2017529767 A JP2017529767 A JP 2017529767A JP 6612872 B2 JP6612872 B2 JP 6612872B2
Authority
JP
Japan
Prior art keywords
high frequency
frequency applications
layer
trapping layer
active layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017529767A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018501651A (ja
JP2018501651A5 (enExample
Inventor
コノンチュク オレグ
ランドリュ ディディエ
フィゲ クリストフ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of JP2018501651A publication Critical patent/JP2018501651A/ja
Publication of JP2018501651A5 publication Critical patent/JP2018501651A5/ja
Application granted granted Critical
Publication of JP6612872B2 publication Critical patent/JP6612872B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/03—Constructional details, e.g. casings, housings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M4/00—Electrodes
    • H01M4/02—Electrodes composed of, or comprising, active material
    • H01M4/64—Carriers or collectors
    • H01M4/66—Selection of materials
    • H01M4/663—Selection of materials containing carbon or carbonaceous materials as conductive part, e.g. graphite, carbon fibres
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/87—Electrodes or interconnections, e.g. leads or terminals
    • H10N30/877—Conductive materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Electrochemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
  • Micromachines (AREA)
JP2017529767A 2014-12-04 2015-09-17 高周波用途のための構造 Active JP6612872B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR1402801 2014-12-04
FR1402801A FR3029682B1 (fr) 2014-12-04 2014-12-04 Substrat semi-conducteur haute resistivite et son procede de fabrication
PCT/FR2015/052494 WO2016087728A1 (fr) 2014-12-04 2015-09-17 Structure pour applications radiofréquences

Publications (3)

Publication Number Publication Date
JP2018501651A JP2018501651A (ja) 2018-01-18
JP2018501651A5 JP2018501651A5 (enExample) 2018-09-06
JP6612872B2 true JP6612872B2 (ja) 2019-11-27

Family

ID=53039463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017529767A Active JP6612872B2 (ja) 2014-12-04 2015-09-17 高周波用途のための構造

Country Status (8)

Country Link
US (1) US10250282B2 (enExample)
EP (2) EP3872839A1 (enExample)
JP (1) JP6612872B2 (enExample)
KR (1) KR102395398B1 (enExample)
CN (1) CN107004572B (enExample)
FR (1) FR3029682B1 (enExample)
SG (1) SG11201704516QA (enExample)
WO (1) WO2016087728A1 (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3037438B1 (fr) 2015-06-09 2017-06-16 Soitec Silicon On Insulator Procede de fabrication d'un element semi-conducteur comprenant une couche de piegeage de charges
US10541667B2 (en) * 2015-08-25 2020-01-21 Avago Technologies International Sales Pte. Limited Surface acoustic wave (SAW) resonator having trap-rich region
US10523178B2 (en) 2015-08-25 2019-12-31 Avago Technologies International Sales Pte. Limited Surface acoustic wave (SAW) resonator
US10530327B2 (en) * 2015-08-25 2020-01-07 Avago Technologies International Sales Pte. Limited Surface acoustic wave (SAW) resonator
US10181428B2 (en) * 2015-08-28 2019-01-15 Skyworks Solutions, Inc. Silicon on porous silicon
EP3144958B1 (en) 2015-09-17 2021-03-17 Soitec Structure for radiofrequency applications and process for manufacturing such a structure
CN108605422B (zh) * 2016-02-25 2019-12-17 日本瑞翁株式会社 导热片及其制造方法、以及散热装置
FR3053532B1 (fr) * 2016-06-30 2018-11-16 Soitec Structure hybride pour dispositif a ondes acoustiques de surface
FR3058561B1 (fr) 2016-11-04 2018-11-02 Soitec Procede de fabrication d'un element semi-conducteur comprenant un substrat hautement resistif
FR3062238A1 (fr) 2017-01-26 2018-07-27 Soitec Support pour une structure semi-conductrice
FR3062517B1 (fr) * 2017-02-02 2019-03-15 Soitec Structure pour application radiofrequence
US10784348B2 (en) 2017-03-23 2020-09-22 Qualcomm Incorporated Porous semiconductor handle substrate
US11063117B2 (en) * 2017-04-20 2021-07-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure having carrier-trapping layers with different grain sizes
FR3067517B1 (fr) 2017-06-13 2019-07-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives Substrat soi compatible avec les technologies rfsoi et fdsoi
FR3079662B1 (fr) * 2018-03-30 2020-02-28 Soitec Substrat pour applications radiofrequences et procede de fabrication associe
JP6827442B2 (ja) * 2018-06-14 2021-02-10 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法及び貼り合わせｓｏｉウェーハ
EP4557350A3 (fr) * 2018-07-05 2025-08-20 Soitec Substrat pour un dispositif intégré radiofréquence et son procédé de fabrication
FR3098642B1 (fr) * 2019-07-12 2021-06-11 Soitec Silicon On Insulator procédé de fabrication d'une structure comprenant une couche mince reportée sur un support muni d’une couche de piégeage de charges
JP2022541172A (ja) * 2019-07-19 2022-09-22 アイキューイー ピーエルシー 調整可能な誘電率及び調整可能な熱伝導率を有する半導体材料
CN113629182A (zh) * 2020-05-08 2021-11-09 济南晶正电子科技有限公司 一种tc-saw复合衬底及其制备方法
CN111884616B (zh) * 2020-07-23 2021-04-13 中国科学院上海微系统与信息技术研究所 一种衬底基板/压电材料薄膜结构及其制备方法和应用
US20220116014A1 (en) * 2020-10-13 2022-04-14 RF360 Europe GmbH Surface acoustic wave (saw) device with high permittivity dielectric for intermodulation distortion improvement
CN112260660B (zh) * 2020-10-21 2023-03-03 济南晶正电子科技有限公司 一种复合基底、复合薄膜及其制备方法
FR3117668B1 (fr) * 2020-12-16 2022-12-23 Commissariat Energie Atomique Structure amelioree de substrat rf et procede de realisation
CN112750686B (zh) * 2020-12-30 2021-12-07 济南晶正电子科技有限公司 一种多层衬底、电子元器件及多层衬底制备方法
JP2023054965A (ja) * 2021-10-05 2023-04-17 信越半導体株式会社 シリコンウエーハ及びｓｏｉウエーハ並びにそれらの製造方法
WO2023232562A1 (fr) * 2022-06-02 2023-12-07 Soitec Procédé de fabrication d'un dispositif à ondes élastiques de surface
FR3136325B1 (fr) * 2022-06-02 2025-10-03 Soitec Silicon On Insulator Dispositif a ondes elastiques de surface

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5637883A (en) * 1995-02-27 1997-06-10 The United States Of America As Represented By The Secretary Of The Navy Optically addressed spatial light modulator using an intrinsic semiconductor active material and high resistivity cladding layers
CN1856873A (zh) * 2003-09-26 2006-11-01 卢万天主教大学 制造具有降低的欧姆损耗的多层半导体结构的方法
JP4983010B2 (ja) * 2005-11-30 2012-07-25 富士通株式会社 圧電素子及びその製造方法
JP2009231376A (ja) * 2008-03-19 2009-10-08 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハ及び半導体デバイスならびにｓｏｉウェーハの製造方法
US8536021B2 (en) * 2010-12-24 2013-09-17 Io Semiconductor, Inc. Trap rich layer formation techniques for semiconductor devices
CN103348473B (zh) * 2010-12-24 2016-04-06 斯兰纳半导体美国股份有限公司 用于半导体装置的富陷阱层
FR2973158B1 (fr) * 2011-03-22 2014-02-28 Soitec Silicon On Insulator Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences
KR101876579B1 (ko) * 2012-09-13 2018-07-10 매그나칩 반도체 유한회사 전력용 반도체 소자 및 그 소자의 제조 방법

Also Published As

Publication number Publication date
EP3227905B1 (fr) 2021-08-18
SG11201704516QA (en) 2017-07-28
EP3872839A1 (fr) 2021-09-01
EP3227905A1 (fr) 2017-10-11
US10250282B2 (en) 2019-04-02
WO2016087728A1 (fr) 2016-06-09
CN107004572B (zh) 2020-05-22
JP2018501651A (ja) 2018-01-18
FR3029682B1 (fr) 2017-12-29
US20170331501A1 (en) 2017-11-16
KR102395398B1 (ko) 2022-05-10
KR20170091627A (ko) 2017-08-09
FR3029682A1 (fr) 2016-06-10
CN107004572A (zh) 2017-08-01

Similar Documents

Publication Publication Date Title
JP6612872B2 (ja) 高周波用途のための構造
JP2018501651A5 (enExample)
CN106575637B (zh) 用于射频应用的结构
TWI849089B (zh) 供無線射頻應用之包含埋置多孔層之半導體結構
JP7053502B2 (ja) 無線周波数用途のための構造
KR102520751B1 (ko) 무선 주파수 응용들을 위한 구조
CN112236853B (zh) 用于集成射频器件的衬底及其制造方法
WO2023162448A1 (ja) 高周波デバイス用基板、及びその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180725

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180725

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190514

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190521

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190821

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20191001

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20191031

R150 Certificate of patent or registration of utility model

Ref document number: 6612872

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250