WO2016061893A1 - Tft中mis结构设计的控制方法及系统 - Google Patents

Tft中mis结构设计的控制方法及系统 Download PDF

Info

Publication number
WO2016061893A1
WO2016061893A1 PCT/CN2014/095343 CN2014095343W WO2016061893A1 WO 2016061893 A1 WO2016061893 A1 WO 2016061893A1 CN 2014095343 W CN2014095343 W CN 2014095343W WO 2016061893 A1 WO2016061893 A1 WO 2016061893A1
Authority
WO
WIPO (PCT)
Prior art keywords
mis structure
voltage
silicon nitride
capacitance
dielectric constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/095343
Other languages
English (en)
French (fr)
Inventor
阙祥灯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to GB1705786.0A priority Critical patent/GB2547134A/en
Priority to US14/416,809 priority patent/US9857655B2/en
Priority to JP2017520949A priority patent/JP6502490B2/ja
Priority to RU2017117490A priority patent/RU2665263C1/ru
Priority to KR1020177013414A priority patent/KR101947931B1/ko
Priority to DE112014006986.8T priority patent/DE112014006986T5/de
Publication of WO2016061893A1 publication Critical patent/WO2016061893A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/045—Manufacture or treatment of capacitors having potential barriers, e.g. varactors
    • H10D1/047—Manufacture or treatment of capacitors having potential barriers, e.g. varactors of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0604—Process monitoring, e.g. flow or thickness monitoring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing

Definitions

  • One of the technical problems to be solved by the present invention is to provide a control method for MIS structure design in a TFT, which can effectively obtain a required MIS structure when designing the MIS structure. Also available A control system for MIS structure design in a TFT.
  • the method further comprises: obtaining the MIS by the high frequency capacitor voltage test The capacitance voltage characteristic curve of the structure; the film thickness value of the silicon nitride in the MIS structure is detected; the maximum capacitance value in the capacitance voltage characteristic curve of the MIS structure and the film thickness value of the silicon nitride in the MIS structure are calculated The dielectric constant of silicon nitride in the MIS structure.
  • the dielectric constant ⁇ i of the silicon nitride in the MIS structure is obtained by the following expression:
  • the step of obtaining a capacitance voltage characteristic curve of the MIS structure by a high frequency capacitor voltage test further:
  • the MIS structure applies a high-frequency voltage signal, and adjusts the high-frequency voltage signal from the first voltage to the second voltage according to the set voltage interval, thereby obtaining capacitance-voltage values of the respective intervals, thereby depicting the capacitance-voltage values of the respective intervals.
  • a capacitance voltage characteristic curve of the MIS structure is a capacitance voltage characteristic curve of the MIS structure.
  • a control system for designing an MIS structure in a TFT comprising: a computing device configured to calculate a dielectric constant of silicon nitride in the designed MIS structure; And determining whether the dielectric constant of the silicon nitride reaches a set value in the TFT process, wherein if the determination result is no, adjusting parameters of the MIS structure to make silicon nitride in the adjusted MIS structure The dielectric constant reaches the set value in the TFT process.
  • the invention tests the characteristics of the dielectric layer in the preliminary designed MIS structure, thereby obtaining the dielectric constant of the silicon nitride, and then judging the current position by judging whether the dielectric constant of the silicon nitride reaches the specification in the TFT process. Whether the designed MIS structure conforms to the required structure. When not met, the parameters of the MIS structure are adjusted to obtain the required MIS structure. Therefore, the present invention can effectively control the MIS structure design and improve the performance and stability of the TFT-LCD product.
  • FIG. 2 is a flow chart showing a method of measuring a dielectric constant of silicon nitride in an MIS structure according to an embodiment of the invention
  • Figure 3 is a schematic diagram of the MIS structure
  • FIG. 4 is an equivalent circuit diagram of the MIS
  • FIG. 5 is a diagram showing an example of design of a preliminary design of a MIS capacitor
  • FIG. 7 is a schematic structural diagram of a control system for designing an MIS structure in a TFT according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural view of a high frequency capacitance-voltage characteristic testing device 710;
  • FIG. 9 is a CV graph obtained by testing with the high frequency capacitance-voltage characteristic testing device 710.
  • the gate dielectric layer directly affects the reliability of the TFT product.
  • it is generally expected to obtain a silicon nitride having a high dielectric constant, and at the same time, it is desirable to minimize the ion contamination of the silicon nitride. And the effect of the interface defect trap of the silicon nitride and the semiconductor layer is less. Because of this, it is possible to obtain TFT products with excellent properties and excellent reliability.
  • the embodiment of the present invention mainly tests the dielectric constant of the silicon nitride dielectric layer in the designed MIS structure, so that the process can be optimized by the dielectric constant to obtain the desired MIS structure with large dielectric constant of silicon nitride. .
  • FIG. 1 is a flow chart showing a control method for designing an MIS structure in a TFT according to an embodiment of the invention. The various steps of the method are described in detail below with reference to FIG.
  • step S110 the dielectric constant of silicon nitride in the designed MIS structure is calculated.
  • FIG. 2 is a schematic flow chart of each substep in step S110 according to the first embodiment of the present invention.
  • a steady-state capacitor voltage characteristic curve (which may be referred to as a CV curve) regarding the MIS structure to be tested is obtained by a high-frequency capacitor voltage test. Specifically, a high frequency voltage signal is applied to the MIS structure, and the high frequency voltage signal is adjusted from the first voltage to the second voltage according to the set voltage interval, thereby obtaining capacitance-voltage values of the respective intervals, and then the capacitance-voltage of each interval is further obtained. The value is depicted as a steady state capacitance voltage characteristic of the MIS structure.
  • step S1102 the film thickness value of the silicon nitride to be tested for the MIS structure is detected.
  • step S1103 the dielectric constant of the silicon nitride of the MIS structure to be tested is calculated based on the maximum capacitance value of the steady-state capacitor voltage characteristic curve of the MIS structure to be tested and the film thickness value of the silicon nitride to be tested.
  • step S1103 the dielectric constant ⁇ i of the silicon nitride in the MIS structure is obtained by the following expression:
  • Cmax represents the maximum capacitance value of the MIS structure
  • di represents the film thickness value of silicon nitride in the MIS structure
  • A represents the electrode area
  • ⁇ 0 represents the vacuum dielectric constant.
  • Step S120 determining whether the dielectric constant of the silicon nitride reaches a set value in the TFT process, wherein if the determination result is no, adjusting the parameters of the MIS structure to make the dielectric of the silicon nitride in the adjusted MIS structure The constant reaches the set value in the TFT process.
  • the MIS structure is similar to a plate capacitor formed of metal and dielectric, as shown in FIG. However, since the charge density in the semiconductor is much smaller than in the metal, the charge charge is formed to a certain thickness (generally on the order of micrometers) in the space charge region formed on the surface of the semiconductor (the amorphous silicon 50 shown in the drawing). Unlike in metals, it is concentrated in only one thin layer (about 0.1 nm). 4 is an equivalent circuit diagram of the MIS. The thickness of the space charge region of the semiconductor surface changes with the bias voltage V G , so the MIS capacitor is a differential capacitor, as shown in the following equation (1):
  • Q G is the charge surface density on the metal electrode and A is the electrode area.
  • the work function difference between metal and semiconductor is zero (ie, n+ layer 40 achieves an ideal ohmic contact in the figure);
  • gate silicon nitride insulating layer ( Hereinafter, there may be no charge in the SiN x insulating layer or SiN x ) 60;
  • a part of the bias voltage V G- acts on SiN x , denoted as V i
  • the other part acts on the space charge region of the semiconductor surface, denoted as V S , ie V G satisfies the following formula:
  • V G V i +V S (2)
  • V S is also called surface potential.
  • Q SC is the space charge region charge areal density of the semiconductor surface.
  • the MIS capacitor is composed of C i and C S in series, and its equivalent circuit is shown in FIG. 4 .
  • C i is the capacitance of the silicon nitride dielectric layer with SiN x as the medium, and its value does not change with V G ;
  • C S is the capacitance of the surface space region of the semiconductor (amorphous silicon 50), and its value varies with V G . therefore:
  • FIG. 5 is a top view of a structure designed by a current product.
  • the design is a circular shape with a diameter of 500 um. It is easy to understand. The diameter is only an example, and the present invention is not limited, and those skilled in the art can design according to the requirements.
  • the circular cross-sectional structure is as shown in FIG. 6, and the first layer metal (gate metal layer) 10, the gate silicon nitride insulating layer 60, the semiconductor amorphous silicon layer 50, n+ are sequentially in order from the bottom to the top of the glass substrate 70.
  • Layer 40, a second layer of metal (source metal layer) 20, and a silicon nitride passivation protective layer 30 are sequentially in order from the bottom to the top of the glass substrate 70.
  • the first metal (gate metal layer) 10, the semiconductor amorphous silicon layer 50, the n+ layer 40, and the second metal (source metal layer) 20 form a circular pattern as shown in FIG. Moreover, the first layer of metal 10 and the second layer of metal 20 each draw a rectangular pad (Pad) having a size of 200 um * 300 um for contacting the test pin during the test.
  • the thickness of each of the above layers is determined by the TFT process technology and is produced as the TFT is fabricated. Of course, the above dimensions are examples, and other sizes are not excluded.
  • the maximum value of the MIS structure capacitance C is obtained according to the CV curve. According to the expression (6), the maximum value is approximately equal to the capacitance of the silicon nitride of the MIS structure.
  • the film thickness value of silicon nitride is measured by the film thickness measuring instrument or the scanning electron microscope (SEM), and the silicon nitride to be tested is calculated according to the film thickness value, the electrode area, the vacuum dielectric constant and the capacitance relationship. Dielectric constant. The higher the dielectric constant, the better the silicon nitride insulation performance.
  • the invention tests the characteristics of the dielectric layer in the preliminary designed MIS structure, thereby obtaining the dielectric constant of the silicon nitride, and then judging the current position by judging whether the dielectric constant of the silicon nitride reaches the specification in the TFT process. Whether the designed MIS structure conforms to the required structure. When not met, the parameters of the MIS structure are adjusted to obtain the required MIS structure. Therefore, the present invention can effectively control the MIS structure design and improve the performance and stability of the TFT-LCD product.
  • FIG. 7 is a schematic structural diagram of a control system for designing an MIS structure in a TFT according to an embodiment of the present invention.
  • the respective constituent structures and functions of the present invention will be described in detail below with reference to FIG.
  • control system includes a computing device 700 and a determining device 800 coupled thereto.
  • a computing device 700 is configured to calculate the dielectric constant of silicon nitride in the designed MIS structure.
  • the determining device 800 is configured to determine whether the dielectric constant of the silicon nitride reaches a set value in the TFT process, wherein if the determination result is no, the parameters of the MIS structure are adjusted to cause nitridation in the adjusted MIS structure.
  • the dielectric constant of silicon reaches a set value in the TFT process.
  • the computing device 700 further includes:
  • a high frequency capacitor-voltage characteristic test device (abbreviated as a high frequency CV test device) 710 is configured to obtain a steady state capacitor voltage characteristic curve with respect to the MIS structure by a high frequency capacitor voltage test.
  • FIG. 8 is a schematic structural view of a high frequency capacitance-voltage characteristic testing device 710.
  • the high-frequency capacitance-voltage characteristic testing device 710 includes a high-frequency capacitance-voltage characteristic tester (high-frequency CV tester shown in the drawing) 711, which is configured to give a MIS disposed on the sample stage 713.
  • the structure (“sample” shown in the figure) applies a high frequency voltage signal, and The high frequency voltage signal is adjusted from the first voltage to the second voltage according to the set voltage interval, and the capacitance-voltage value of each interval is obtained.
  • the XY function recorder 712 is coupled to the high frequency capacitance-voltage characteristic tester 711, and is configured to describe the capacitance-voltage values of the respective intervals output by the high-frequency capacitance-voltage characteristic test 711 to the steady state of the MIS structure. Capacitance voltage characteristic curve.
  • the high frequency capacitance-voltage characteristic testing device 710 further includes a heating device 714, a temperature control device 715, and a water cooling device 716, by which the performance of the designed MIS structure can be detected.
  • a heating device 714 a temperature control device 715
  • a water cooling device 716 by which the performance of the designed MIS structure can be detected.
  • the CV curve after the recovery of the MIS structure is compared with the unbiased CV curve (steady-state capacitor voltage characteristic curve), and the voltage bias of the curve is The smaller the shift, the better the silicon nitride performance and the stronger the TFT reliability.
  • the film thickness measuring instrument 720 is configured to detect the film thickness value of silicon nitride in the MIS structure.
  • a calculator 730 configured to calculate a dielectric constant of silicon nitride in the MIS structure based on a maximum capacitance value in a steady-state capacitance-voltage characteristic curve of the MIS structure and a film thickness value of silicon nitride in the MIS structure .
  • the calculator 730 uses the following expression to obtain the dielectric constant ⁇ i of silicon nitride in the MIS structure:
  • Cmax represents the maximum capacitance value of the MIS structure
  • di represents the film thickness value of silicon nitride in the MIS structure
  • A represents the electrode area
  • ⁇ 0 represents the vacuum dielectric constant.
  • test steps for testing using the above apparatus include:
  • the zero point and the range of the X-Y function recorder 712 are determined. And, the corresponding capacitance range of the high-frequency C-V characteristic tester 711 is selected based on the maximum capacitance value of the sample to be measured (estimated by the known electrode area and oxide thickness), and the selected capacitance range is corrected.
  • the high frequency C-V characteristic tester 711 outputs a capacitance-voltage value based on the minority lifetime of the sample, and the X-Y function recorder 712 determines the bias C-V curve based on the output value, but the bias C-V curve at this time is not what we need.
  • the initial rate test of 100mV per second is used. If the deep depletion curve is still obtained, the rate should be slowed down again until a steady state C-V curve is obtained.
  • the calculator 730 obtains the value of the maximum capacitance Cmax at room temperature based on the steady state C-V curve.
  • the thickness of the silicon nitride film is measured by a film thickness meter 720 or a scanning electron microscope.
  • the calculator 730 calculates the silicon nitride dielectric constant based on the maximum capacitance value and the silicon nitride film thickness value.
  • the dielectric constant of the gate silicon nitride is 6.18, and the specified range in the design rule is 5.8 to 6.3.
  • the dielectric constant conforms to the set range and is high, so the product can be mass-produced as a final product.
  • the invention tests the characteristics of the dielectric layer in the preliminary designed MIS structure, thereby obtaining the dielectric constant of the silicon nitride, and then judging the current position by judging whether the dielectric constant of the silicon nitride reaches the specification in the TFT process. Whether the designed MIS structure conforms to the required structure. When not met, the parameters of the MIS structure are adjusted to obtain the required MIS structure. Therefore, the present invention can effectively control the MIS structure design and improve the performance and stability of the TFT-LCD product.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Liquid Crystal (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

一种TFT中MIS结构设计的控制方法及系统，该方法包括：计算得到所设计的MIS结构中氮化硅的介电常数；判断氮化硅的介电常数是否达到TFT制程中的设定值，其中，若判断结果为否，则调整该MIS结构的参数，使得调整后的MIS结构中氮化硅的介电常数达到TFT制程中的设定值。该方法及系统能够有效地对MIS结构设计进行控制，提高TFT-LCD产品性能与稳定性。

Description

TFT中MIS结构设计的控制方法及系统
相关申请的交叉引用
本申请要求享有2014年10月24日提交的名称为“TFT中MIS结构设计的控制方法及系统”的中国专利申请CN201410579313.7的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种TFT中MIS结构设计的控制方法及系统。
背景技术
近年来，随着薄型化的显示趋势，液晶显示器(Liquid Crystal Display，简称LCD)已广泛使用在各种电子产品的应用中，例如手机、笔记本计算机以及彩色电视机等。
TFT-LCD的制作工艺按照加工的先后顺序分为阵列工艺、成盒工艺和模块工艺。其中，阵列工艺类似于半导体工艺，其是在玻璃基板上有规则地做成TFT器件、像素等图案的过程。
与半导体工艺不同的是，在制作TFT的工艺中，金属-绝缘体-半导体(Metal-Insulator-Semiconductor，简称MIS)结构基本采用等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)生长的氮化硅作为栅极以开启绝缘层，而不是在Si基板上直接氧化生长的性质优良SiO2。因此氮化硅的性质对TFT特性影响十分关键。
然而，在本领域中还未有一种有效的方法来对TFT中的MIS结构的设计进行控制，进而确定TFT中的MIS结构，因此，亟需一种方法来解决上述问题。
发明内容
本发明所要解决的技术问题之一是需要提供一种TFT中MIS结构设计的控制方法，该控制方法能够在对MIS结构进行设计时有效地获得所需要的MIS结构。另外，还提供 了一种TFT中MIS结构设计的控制系统。
1)本发明提供了一种TFT中MIS结构设计的控制方法，包括：计算得到所设计的MIS结构中氮化硅的介电常数；判断所述氮化硅的介电常数是否达到TFT制程中的设定值，其中，若判断结果为否，则调整该MIS结构的参数，使得调整后的MIS结构中氮化硅的介电常数达到所述TFT制程中的设定值。
2)在本发明的第1)项的一个优选实施方式中，在计算得到所设计的MIS结构中氮化硅的介电常数的步骤中，进一步包括：通过高频电容电压测试得到关于该MIS结构的电容电压特性曲线；检测出该MIS结构中氮化硅的膜厚数值；基于该MIS结构的电容电压特性曲线中的最大电容值和该MIS结构中氮化硅的膜厚数值，计算得到该MIS结构中氮化硅的介电常数。
3)在本发明的第1)项或第2)项中的一个优选实施方式中，利用如下表达式来得到该MIS结构中氮化硅的介电常数εi：
Figure PCTCN2014095343-appb-000001
式中，Cmax表示MIS结构的最大电容值，di表示MIS结构中氮化硅的膜厚数值，A表示电极面积，ε0表示真空介电常数。
4)在本发明的第1)项-第3)项中任一项的一个优选实施方式中，在通过高频电容电压测试得到关于该MIS结构的电容电压特性曲线的步骤中，进一步：给所述MIS结构施加高频电压讯号，并将高频电压讯号按照设定电压间隔从第一电压调整到第二电压，得到各个间隔的电容-电压值，进而将各个间隔的电容-电压值描绘成所述MIS结构的电容电压特性曲线。
5)根据本发明的另一方面，还提供了一种TFT中MIS结构设计的控制系统，包括：计算装置，其构成以计算得到所设计的MIS结构中氮化硅的介电常数；判断装置，其构成以判断所述氮化硅的介电常数是否达到TFT制程中的设定值，其中，若判断结果为否，则调整该MIS结构的参数，使得调整后的MIS结构中氮化硅的介电常数达到所述TFT制程中的设定值。
6)在本发明的第5)项的一个优选实施方式中，所述计算装置进一步包括：高频电容-电压特性测试装置，其构成以通过高频电容电压测试得到关于该MIS结构的电容电压特性曲线；膜厚测量仪，其构成以检测出该MIS结构中氮化硅的膜厚数值；计算器，其构成以基于该MIS结构的电容电压特性曲线中的最大电容值和该MIS结构中氮化硅的膜 厚数值，计算得到该MIS结构中氮化硅的介电常数。
7)在本发明的第5)项或第6)项中的一个优选实施方式中，所述计算器利用如下表达式来得到所述MIS结构中氮化硅的介电常数εi：
Figure PCTCN2014095343-appb-000002
式中，Cmax表示MIS结构的最大电容值，di表示MIS结构中氮化硅的膜厚数值，A表示电极面积，ε0表示真空介电常数。
8)在本发明的第5)项-第7)项中任一项的一个优选实施方式中，高频电容-电压特性测试装置包括：高频电容-电压特性测试仪，其构成以给所述MIS结构施加高频电压讯号，并将高频电压讯号按照设定电压间隔从第一电压调整到第二电压，得到各个间隔的电容-电压值；X-Y函数记录仪，其耦接于高频电容-电压特性测试仪，并且其构成以将所述高频电容-电压特性测试仪输出的各个间隔的电容-电压值描绘成所述MIS结构的电容电压特性曲线。
与现有技术相比，本发明的一个或多个实施例可以具有如下优点：
本发明通过对初步设计的MIS结构中介质层的特性进行测试，进而得到氮化硅的介电常数，然后，通过判断氮化硅的介电常数是否达到TFT制程中的规定，进而判断当前所设计的MIS结构是否符合所需的结构。在不符合时，通过对MIS结构的参数进行调整以得到所需要的MIS结构。因此，本发明能够有效地对MIS结构设计进行控制，提高TFT-LCD产品性能与稳定性。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1是根据本发明一实施例的TFT中MIS结构设计的控制方法的流程示意图；
图2是根据本发明一实施例的测量MIS结构中氮化硅的介电常数的方法的流程示意图；
图3是MIS结构示意图；
图4是MIS的等效电路图；
图5是一初步设计的MIS电容的设计示例图；
图6是图5所示的MIS电容的截面示意图；
图7是根据本发明一实施例的TFT中MIS结构设计的控制系统的结构示意图；
图8是高频电容-电压特性测试装置710的结构示意图；
图9是利用高频电容-电压特性测试装置710测试得到的CV曲线图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。
在TFT制作工艺中，栅极介质层直接影响到TFT产品的信赖性，在该制作工艺中，一般期待能够得到高介电常数的氮化硅，同时希望氮化硅所受的离子沾污最小，以及氮化硅与半导体层的界面缺陷陷阱较少的效果。因为这样才可能得到性质优良、信赖性优异的TFT产品。本发明的实施例主要通过测试所设计的MIS结构中氮化硅介质层的介电常数，致使制程可以通过此介电常数进行优化设计，得到所需要的氮化硅介电常数大的MIS结构。
(第一实施例)
图1是根据本发明一实施例的TFT中MIS结构设计的控制方法的流程示意图。下面参考图1来详细说明该方法的各个步骤。
步骤S110，计算得到所设计的MIS结构中氮化硅的介电常数。
以下即列举一例来说明如何计算MIS结构中氮化硅的介电常数。图2是根据本发明第一实施例中步骤S110中各子步骤流程示意图。
请参考图2，首先，在步骤S1101中，通过高频电容电压测试得到关于待测MIS结构的稳态电容电压特性曲线(可简称CV曲线)。具体地，给MIS结构施加高频电压讯号，并将高频电压讯号按照设定电压间隔从第一电压调整到第二电压，得到各个间隔的电容-电压值，进而将各个间隔的电容-电压值描绘成MIS结构的稳态电容电压特性曲线。
接着，如步骤S1102所示，检测出待测MIS结构氮化硅的膜厚数值。最后，在步骤S1103中，基于待测MIS结构的稳态电容电压特性曲线的最大电容值和待测MIS结构氮化硅的膜厚数值计算得到待测MIS结构氮化硅的介电常数。
在步骤S1103中，利用如下表达式来得到该MIS结构中氮化硅的介电常数εi：
Figure PCTCN2014095343-appb-000003
式中，Cmax表示MIS结构的最大电容值，di表示MIS结构中氮化硅的膜厚数值，A表示电极面积，ε0表示真空介电常数。
步骤S120，判断氮化硅的介电常数是否达到TFT制程中的设定值，其中，若判断结果为否，则调整该MIS结构的参数，使得调整后的MIS结构中氮化硅的介电常数达到TFT制程中的设定值。
本申请的申请人通过大量研究了解到以下内容。
MIS结构类似于金属和介质形成的平板电容器，如图3所示。但是，由于半导体中的电荷密度比金属中的小得多，所以充电电荷在半导体(图中所示非晶硅50)表面形成的空间电荷区有一定的厚度(一般为微米量级)，而不像金属中那样，只集中在一薄层(约为0.1nm)内。图4是MIS的等效电路图，半导体表面的空间电荷区的厚度随偏压VG而改变，所以MIS电容是微分电容，具体如下式(1)所示：
Figure PCTCN2014095343-appb-000004
式中，QG是金属电极上的电荷面密度，A是电极面积。
考虑到理想MIS结构需要满足以下条件：(1)金属与半导体之间的功函数差为零(即图中n+层40实现了理想的欧姆接触)；(2)栅极氮化硅绝缘层(以下可称为SiNx绝缘层或SiNx)60内没有电荷；(3)SiNx绝缘层60与半导体界面处不存在界面态。偏压VG-的一部分作用在SiNx上，记作Vi，另一部分作用在半导体表面空间电荷区上，记作VS，即VG满足下式：
VG＝Vi+VS  (2)
其中，VS又称为表面势。
考虑到半导体表面的空间电荷区电荷和金属电极上的电荷数量相等、符号相反，则存在下式(3)：
|QSC|＝|QG|  (3)
式中，QSC是半导体表面的空间电荷区电荷面密度。
因此将式(2)、(3)代入式(1)得到：
Figure PCTCN2014095343-appb-000005
从上式(4)可以看出MIS电容由Ci和CS串联构成，其等效电路如图4所示。其中Ci是以SiNx为介质的氮化硅介质层的电容，它的数值不随VG而改变；CS是半导体(非晶硅50)表面空间区的电容，其数值随VG改变，因此：
Figure PCTCN2014095343-appb-000006
Figure PCTCN2014095343-appb-000007
式中，εi表示SiNx的相对介电常数，di表示SiNx的介质层厚度，ε0表示真空介电常数。由式(4)、(5)可得MIS结构的最大电容如下式表示：
Figure PCTCN2014095343-appb-000008
因此，可知MIS结构氮化硅的介电常数计算式为
Figure PCTCN2014095343-appb-000009
为了进一步说明本发明方法，下面列举一示例来进行进一步说明。
示例
假设，MIS电容设计结构如图5所示，其截面如图6所示。
图5为目前某产品所设计的结构俯视图，其设计为直径500um的圆形，容易理解，该直径大小仅为一示例，不限定本发明，本领域技术人员可以根据所需进行设计。其圆形截面结构如图6，以玻璃基板70为基准从下至上依次为：第一层金属(栅极金属层)10、栅极氮化硅绝缘层60、半导体非晶硅层50、n+层40、第二层金属(源极金属层)20以及氮化硅钝化保护层30。
其中第一层金属(栅极金属层)10、半导体非晶硅层50、n+层40、第二层金属(源极金属层)20形成了图5所示的圆形图案。而且第一层金属10与第二层金属20各自引出了尺寸为200um*300um的长方形焊盘(Pad)，用以在测试过程中接触测试针。以上各层厚度是由TFT制程工艺决定的，并随着TFT制作而产生。当然，以上尺寸为实例，不排除其他尺寸的设计。
通过给以上两层金属接触的焊盘(pad)施加以1MHz的高频电压讯号，并将电压讯号调整范围从-20V增大到20V，在常温下每隔50mV或100mV记录一组电容电压数值， 然后得到对应的CV曲线，最后，根据CV曲线得到MIS结构电容C的最大值，根据表达式(6)可知，该最大值约等于为MIS结构氮化硅的电容。
同时，通过制程上膜厚测量仪或者扫描电镜(简称SEM)测量出氮化硅的膜厚数值，根据膜厚数值、电极面积、真空介电常数和电容关系，计算待测MIS结构氮化硅的介电常数。介电常数越高则表明氮化硅绝缘性能越出色。
最后，判断得到的MIS结构氮化硅的介电常数是否达到制程所规定的设定值，若未达到，则说明当前设计的MIS结构还不符合所需要的设计。需要对其参数进行调整。
另外，还可以对设计好的MIS进行测试得到其性能的好坏。具体地，在不同环境(如MIS电压偏置、环境温湿度)下，将MIS结构恢复后的C-V曲线与未受偏置的C-V曲线比较，其曲线之电压偏移(shift)越小，则证明氮化硅性能越佳，TFT信赖性越强。
本发明通过对初步设计的MIS结构中介质层的特性进行测试，进而得到氮化硅的介电常数，然后，通过判断氮化硅的介电常数是否达到TFT制程中的规定，进而判断当前所设计的MIS结构是否符合所需的结构。在不符合时，通过对MIS结构的参数进行调整以得到所需要的MIS结构。因此，本发明能够有效地对MIS结构设计进行控制，提高TFT-LCD产品性能与稳定性。
(第二实施例)
图7是根据本发明一实施例的TFT中MIS结构设计的控制系统的结构示意图。下面参考图7来详细说明本发明的各个组成结构和功能。
如图7所示，该控制系统包括：计算装置700和与之耦接的判断装置800。
计算装置700，其构成以计算得到所设计的MIS结构中氮化硅的介电常数。
判断装置800，其构成以判断氮化硅的介电常数是否达到TFT制程中的设定值，其中，若判断结果为否，则调整该MIS结构的参数，使得调整后的MIS结构中氮化硅的介电常数达到所述TFT制程中的设定值。
在计算装置700进一步包括：
高频电容-电压特性测试装置(简称高频CV测试装置)710，其构成以通过高频电容电压测试得到关于该MIS结构的稳态电容电压特性曲线。
图8是高频电容-电压特性测试装置710的结构示意图。如图8所示，该高频电容-电压特性测试装置710包括高频电容-电压特性测试仪(图中所示高频C-V测试仪)711，其构成以给设置在样品台713上的MIS结构(图中所示“样品”)施加高频电压讯号，并 将高频电压讯号按照设定电压间隔从第一电压调整到第二电压，得到各个间隔的电容-电压值。
X-Y函数记录仪712，其耦接于高频电容-电压特性测试仪711，并且其构成以将高频电容-电压特性测试711仪输出的各个间隔的电容-电压值描绘成MIS结构的稳态电容电压特性曲线。
另外，高频电容-电压特性测试装置710还包括加热装置714、控温装置715和水冷装置716，通过对这些装置进行设置能够检测设计好的MIS结构的性能。具体地，在不同环境(如MIS电压偏置、环境温湿度)下，将MIS结构恢复后的C-V曲线与未受偏置的C-V曲线(稳态电容电压特性曲线)比较，其曲线的电压偏移(shift)越小，则证明氮化硅性能越佳，TFT信赖性越强。
膜厚测量仪720，其构成以检测出该MIS结构中氮化硅的膜厚数值。
计算器730，其构成以基于该MIS结构的稳态电容-电压特性曲线中的最大电容值和该MIS结构中氮化硅的膜厚数值，计算得到该MIS结构中氮化硅的介电常数。
具体地，计算器730利用如下表达式来得到MIS结构中氮化硅的介电常数εi：
Figure PCTCN2014095343-appb-000010
式中，Cmax表示MIS结构的最大电容值，di表示MIS结构中氮化硅的膜厚数值，A表示电极面积，δ0表示真空介电常数。
利用上述装置进行测试的测试步骤包括：
首先，打开上述各仪器的电源，预热10分钟。然后，确定X-Y函数记录仪712的零点和量程。并且，根据被测量样品的最大电容数值(用已知的电极面积和氧化层厚度进行估算)选择高频C-V特性测试仪711相应的电容量程，并对所选择的电容量程进行校正。高频C-V特性测试仪711根据样品的少子寿命来输出电容-电压值，X-Y函数记录仪712根据输出的值确定偏压C-V曲线，但是此时的偏压C-V曲线不是我们所需要的。随后，使用1MHz的高频频率电压讯号，初步选用每秒100mV的速率测试，如果仍得到深耗尽的曲线，则应将速率再放慢，直至得到稳态C-V曲线。
计算器730根据稳态C-V曲线得到室温下最大电容Cmax的数值。
膜厚测量仪720或扫描电镜测量得到氮化硅膜厚数值。最后计算器730基于最大电容值和氮化硅膜厚数值计算得到氮化硅介电常数。
利用上述仪器对某产品的设计进行测试，其量测的C-V曲线图如图9所示， Cmax＝3.212E-11F，A＝πr2＝3.14×(258×10-6)2＝2.09×10-7(m2)，ε0＝8.85×10-12F/m
经过SEM和Nano技术量测氮化硅膜厚：di＝3562A＝3.562×10-7m
因此：
Figure PCTCN2014095343-appb-000011
此时栅极氮化硅的介电常数为6.18，设计规则里规定范围为5.8～6.3，该介电常数符合设定范围且较高，因此该产品可作为最终产品进行批量生产。
本发明通过对初步设计的MIS结构中介质层的特性进行测试，进而得到氮化硅的介电常数，然后，通过判断氮化硅的介电常数是否达到TFT制程中的规定，进而判断当前所设计的MIS结构是否符合所需的结构。在不符合时，通过对MIS结构的参数进行调整以得到所需要的MIS结构。因此，本发明能够有效地对MIS结构设计进行控制，提高TFT-LCD产品性能与稳定性。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉该技术的人员在本发明所揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (9)

  1. 一种TFT中MIS结构设计的控制方法，包括：
    计算得到所设计的MIS结构中氮化硅的介电常数；
    判断所述氮化硅的介电常数是否达到TFT制程中的设定值，其中，
    若判断结果为否，则调整该MIS结构的参数，使得调整后的MIS结构中氮化硅的介电常数达到所述TFT制程中的设定值。
  2. 根据权利要求1所述的控制方法，其中，在计算得到所设计的MIS结构中氮化硅的介电常数的步骤中，进一步包括：
    通过高频电容电压测试得到关于该MIS结构的电容电压特性曲线；
    检测出该MIS结构中氮化硅的膜厚数值；
    基于该MIS结构的电容电压特性曲线中的最大电容值和该MIS结构中氮化硅的膜厚数值，计算得到该MIS结构中氮化硅的介电常数。
  3. 根据权利要求2所述的控制方法，其中，
    利用如下表达式来得到该MIS结构中氮化硅的介电常数εi：
    Figure PCTCN2014095343-appb-100001
    式中，Cmax表示MIS结构的最大电容值，di表示MIS结构中氮化硅的膜厚数值，A表示电极面积，ε0表示真空介电常数。
  4. 根据权利要求2所述的控制方法，其中，在通过高频电容电压测试得到关于该MIS结构的电容电压特性曲线的步骤中，进一步：
    给所述MIS结构施加高频电压讯号，并将高频电压讯号按照设定电压间隔从第一电压调整到第二电压，得到各个间隔的电容-电压值，进而将各个间隔的电容-电压值描绘成所述MIS结构的电容电压特性曲线。
  5. 根据权利要求3所述的控制方法，其中，在通过高频电容电压测试得到关于该MIS结构的电容电压特性曲线的步骤中，进一步：
    给所述MIS结构施加高频电压讯号，并将高频电压讯号按照设定电压间隔从第一电压调整到第二电压，得到各个间隔的电容-电压值，进而将各个间隔的电容-电压值描绘成 所述MIS结构的电容电压特性曲线。
  6. 一种TFT中MIS结构设计的控制系统，包括：
    计算装置，其构成以计算得到所设计的MIS结构中氮化硅的介电常数；
    判断装置，其构成以判断所述氮化硅的介电常数是否达到TFT制程中的设定值，其中，
    若判断结果为否，则调整该MIS结构的参数，使得调整后的MIS结构中氮化硅的介电常数达到所述TFT制程中的设定值。
  7. 根据权利要求6所述的控制系统，其中，所述计算装置进一步包括：
    高频电容-电压特性测试装置，其构成以通过高频电容电压测试得到关于该MIS结构的电容电压特性曲线；
    膜厚测量仪，其构成以检测出该MIS结构中氮化硅的膜厚数值；
    计算器，其构成以基于该MIS结构的电容电压特性曲线中的最大电容值和该MIS结构中氮化硅的膜厚数值，计算得到该MIS结构中氮化硅的介电常数。
  8. 根据权利要求7所述的控制系统，其中，
    所述计算器利用如下表达式来得到所述MIS结构中氮化硅的介电常数εi：
    Figure PCTCN2014095343-appb-100002
    式中，Cmax表示MIS结构的最大电容值，di表示MIS结构中氮化硅的膜厚数值，A表示电极面积，ε0表示真空介电常数。
  9. 根据权利要求7所述的介电常数测量方法，其中，高频电容-电压特性测试装置包括：
    高频电容-电压特性测试仪，其构成以给所述MIS结构施加高频电压讯号，并将高频电压讯号按照设定电压间隔从第一电压调整到第二电压，得到各个间隔的电容-电压值；
    X-Y函数记录仪，其耦接于高频电容-电压特性测试仪，并且其构成以将所述高频电容-电压特性测试仪输出的各个间隔的电容-电压值描绘成所述MIS结构的电容电压特性曲线。
PCT/CN2014/095343 2014-10-24 2014-12-29 Tft中mis结构设计的控制方法及系统 Ceased WO2016061893A1 (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
GB1705786.0A GB2547134A (en) 2014-10-24 2014-12-29 Method and system for controlling mis structure design in TFT
US14/416,809 US9857655B2 (en) 2014-10-24 2014-12-29 Method for controlling MIS structure design in TFT and system thereof
JP2017520949A JP6502490B2 (ja) 2014-10-24 2014-12-29 Ｔｆｔにおけるｍｉｓ構造設計の制御方法及び制御システム
RU2017117490A RU2665263C1 (ru) 2014-10-24 2014-12-29 Способ контроля конструкции с мдп-структурой в тонкопленочных транзисторах и система для осуществления контроля
KR1020177013414A KR101947931B1 (ko) 2014-10-24 2014-12-29 Tft 중의 mis 구조 디자인의 제어방법 및 시스템
DE112014006986.8T DE112014006986T5 (de) 2014-10-24 2014-12-29 Verfahren zum Steuern eines MIS-Strukturentwurfs in einem TFT und System zur Durchführung des Verfahrens

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410579313.7 2014-10-24
CN201410579313.7A CN104282250B (zh) 2014-10-24 2014-10-24 Tft 中mis 结构设计的控制方法及系统

Publications (1)

Publication Number Publication Date
WO2016061893A1 true WO2016061893A1 (zh) 2016-04-28

Family

ID=52257086

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/095343 Ceased WO2016061893A1 (zh) 2014-10-24 2014-12-29 Tft中mis结构设计的控制方法及系统

Country Status (8)

Country Link
US (1) US9857655B2 (zh)
JP (1) JP6502490B2 (zh)
KR (1) KR101947931B1 (zh)
CN (1) CN104282250B (zh)
DE (1) DE112014006986T5 (zh)
GB (1) GB2547134A (zh)
RU (1) RU2665263C1 (zh)
WO (1) WO2016061893A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109696583B (zh) * 2019-02-26 2021-07-13 航天材料及工艺研究所 用于介电性能测试的氮化硅纤维试样、制样方法及测试方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020070731A1 (en) * 2000-12-12 2002-06-13 Nobuyuki Ohminami Apparatus and method for analyzing capacitance of insulator
TW200708748A (en) * 2005-08-31 2007-03-01 Solid State Measurements Inc Method and system for automatically determining electrical properties of a semiconductor wafer or sample
CN101017153A (zh) * 2006-03-13 2007-08-15 信息产业部电子第五研究所 一种评估和监测介质层质量和可靠性的方法
CN102346232A (zh) * 2010-07-30 2012-02-08 中国科学院微电子研究所 一种通过肖特基测试图形检测GaN基HEMT可靠性的方法
CN102520020A (zh) * 2011-12-12 2012-06-27 复旦大学 寄生效应对电导法表征Ge衬底界面态所产生的干扰的修正方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5650361A (en) * 1995-11-21 1997-07-22 The Aerospace Corporation Low temperature photolytic deposition of aluminum nitride thin films
KR100205318B1 (ko) * 1996-10-11 1999-07-01 구본준 자유전율의 절연막 제조방법
DE69937485T2 (de) * 1998-01-28 2008-08-21 Thin Film Electronics Asa Methode zur herstellung zwei- oder dreidimensionaler elektrisch leitender oder halbleitender strukturen, eine löschmethode derselben und ein generator/modulator eines elektrischen feldes zum gebrauch in der herstellungsmethode
KR100396879B1 (ko) * 2000-08-11 2003-09-02 삼성전자주식회사 동일 물질로 이루어진 이중막을 포함하는 다중막으로캡슐화된 캐패시터를 구비한 반도체 메모리 소자 및 그의제조 방법
US6642131B2 (en) * 2001-06-21 2003-11-04 Matsushita Electric Industrial Co., Ltd. Method of forming a silicon-containing metal-oxide gate dielectric by depositing a high dielectric constant film on a silicon substrate and diffusing silicon from the substrate into the high dielectric constant film
JP3909712B2 (ja) * 2003-10-10 2007-04-25 セイコーエプソン株式会社 静電容量検出装置
US7688569B2 (en) * 2004-03-16 2010-03-30 E. I. Du Pont De Nemours And Company Thick-film dielectric and conductive compositions
US20050204864A1 (en) * 2004-03-16 2005-09-22 Borland William J Thick-film dielectric and conductive compositions
JP4441927B2 (ja) * 2004-10-12 2010-03-31 セイコーエプソン株式会社 静電容量検出装置
US20080248596A1 (en) * 2007-04-04 2008-10-09 Endicott Interconnect Technologies, Inc. Method of making a circuitized substrate having at least one capacitor therein
JP2006269734A (ja) * 2005-03-24 2006-10-05 Seiko Epson Corp 半導体素子を評価する方法および装置、半導体素子を製造する方法、ならびにプログラム
US7521946B1 (en) * 2005-04-06 2009-04-21 Kla-Tencor Technologies Corporation Electrical measurements on semiconductors using corona and microwave techniques
US7712373B2 (en) * 2006-03-03 2010-05-11 Nagle H Troy Sensor device for real-time monitoring or relative movement using capacitive fabric sensors
JP2009170439A (ja) * 2008-01-10 2009-07-30 Panasonic Corp ゲート絶縁膜の形成方法
JP5172567B2 (ja) * 2008-09-25 2013-03-27 株式会社東芝 膜形成用組成物、絶縁膜、半導体装置およびその製造方法
US8106455B2 (en) * 2009-04-30 2012-01-31 International Business Machines Corporation Threshold voltage adjustment through gate dielectric stack modification
CN101655526B (zh) * 2009-09-10 2012-05-30 复旦大学 一种快速电压扫描测量铁电薄膜微分电容的方法
JP5521726B2 (ja) * 2010-04-16 2014-06-18 富士通セミコンダクター株式会社 半導体装置及びその製造方法
CN102110601B (zh) * 2010-12-03 2012-12-12 复旦大学 制备可测量mos电容器低频cv曲线的器件结构的方法
CN102176421A (zh) * 2011-03-15 2011-09-07 上海宏力半导体制造有限公司 Mos管栅极氧化层累积厚度的测量方法
US8871425B2 (en) * 2012-02-09 2014-10-28 Az Electronic Materials (Luxembourg) S.A.R.L. Low dielectric photoimageable compositions and electronic devices made therefrom
JP2013175593A (ja) * 2012-02-24 2013-09-05 Rohm Co Ltd 半導体装置およびその製造方法
TWI511257B (zh) * 2013-07-30 2015-12-01 國立交通大學 半導體元件之內連接結構
US9082729B2 (en) * 2013-11-20 2015-07-14 Intermolecular, Inc. Combinatorial method for solid source doping process development
CN105336680B (zh) * 2014-08-13 2020-02-11 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置
US10332684B2 (en) * 2015-07-19 2019-06-25 Vq Research, Inc. Methods and systems for material cladding of multilayer ceramic capacitors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020070731A1 (en) * 2000-12-12 2002-06-13 Nobuyuki Ohminami Apparatus and method for analyzing capacitance of insulator
TW200708748A (en) * 2005-08-31 2007-03-01 Solid State Measurements Inc Method and system for automatically determining electrical properties of a semiconductor wafer or sample
CN101017153A (zh) * 2006-03-13 2007-08-15 信息产业部电子第五研究所 一种评估和监测介质层质量和可靠性的方法
CN102346232A (zh) * 2010-07-30 2012-02-08 中国科学院微电子研究所 一种通过肖特基测试图形检测GaN基HEMT可靠性的方法
CN102520020A (zh) * 2011-12-12 2012-06-27 复旦大学 寄生效应对电导法表征Ge衬底界面态所产生的干扰的修正方法

Also Published As

Publication number Publication date
JP6502490B2 (ja) 2019-04-17
US20160252765A1 (en) 2016-09-01
CN104282250A (zh) 2015-01-14
GB2547134A (en) 2017-08-09
CN104282250B (zh) 2016-08-31
KR101947931B1 (ko) 2019-02-13
US9857655B2 (en) 2018-01-02
KR20170073636A (ko) 2017-06-28
RU2665263C1 (ru) 2018-08-28
GB201705786D0 (en) 2017-05-24
JP2018503240A (ja) 2018-02-01
DE112014006986T5 (de) 2017-06-22

Similar Documents

Publication Publication Date Title
US10684175B2 (en) Substrate and display device
CN104596683A (zh) 基于层状材料的压力传感器及压电效应测量系统
CN104716065B (zh) 金属氧化物半导体场效应晶体管电容‑电压特性修正方法
US10008421B2 (en) Capacitance monitoring using x-ray diffraction
CN102495295B (zh) 一种半导体薄膜材料电容特性的测量方法及装置
WO2016061893A1 (zh) Tft中mis结构设计的控制方法及系统
JP5343693B2 (ja) ドーパント濃度測定方法
US20070018674A1 (en) Apparatus and method for testing semiconductor device
TWI800932B (zh) 介電質薄片之等效物理厚度取得方法
WO2016106850A1 (zh) 一种用于获取阵列基板中电容容值的结构体及方法
US7521946B1 (en) Electrical measurements on semiconductors using corona and microwave techniques
US20080290889A1 (en) Method of destructive testing the dielectric layer of a semiconductor wafer or sample
WO2017101205A1 (zh) 阵列基板的esd检测方法
JP3871131B2 (ja) 空乏層容量測定方法
JP5018053B2 (ja) 半導体ウエーハの評価方法
TWI676025B (zh) 熱膨脹係數檢測系統及方法
CN104698279A (zh) 场效应管电容-电压特性测试电路的串联电阻测定方法
Chung Study of electrochemical etch-stop for high-precision thickness control of single-crystal Si in aqueous TMAH: IPA: pyrazine solutions
JP2977172B2 (ja) 半導体の特性測定方法
Yuan et al. P‐11.9: Study on process conditions of planarization layer in FFS mode using a‐IGZO TFTs
JP2016076662A (ja) シリコン単結晶ウェーハの評価方法
CN118706305A (zh) 一种lpcvd薄膜应力计算方法及系统
EP1550876A1 (en) Apparatus and methods for measuring permittivity in semiconductor wafers
Kamiński et al. Characterization thin films TiO2 obtained in the magnetron sputtering process
Allen et al. Sheet and line resistance of patterned SOI surface film CD reference materials as a function of substrate bias

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14416809

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14904328

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 201705786

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20141229

ENP Entry into the national phase

Ref document number: 2017520949

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 112014006986

Country of ref document: DE

ENP Entry into the national phase

Ref document number: 20177013414

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2017117490

Country of ref document: RU

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 14904328

Country of ref document: EP

Kind code of ref document: A1