WO2016045290A1 - 一种栅极驱动器、显示装置及栅极驱动方法 - Google Patents

一种栅极驱动器、显示装置及栅极驱动方法 Download PDF

Info

Publication number
WO2016045290A1
WO2016045290A1 PCT/CN2015/071918 CN2015071918W WO2016045290A1 WO 2016045290 A1 WO2016045290 A1 WO 2016045290A1 CN 2015071918 W CN2015071918 W CN 2015071918W WO 2016045290 A1 WO2016045290 A1 WO 2016045290A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
row
logic circuit
shift register
Prior art date
Application number
PCT/CN2015/071918
Other languages
English (en)
French (fr)
Inventor
王俪蓉
段立业
吴仲远
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP15750618.9A priority Critical patent/EP3200179B1/en
Priority to US14/770,364 priority patent/US9799271B2/en
Priority to KR1020157023231A priority patent/KR101718272B1/ko
Priority to JP2017535948A priority patent/JP6755250B2/ja
Publication of WO2016045290A1 publication Critical patent/WO2016045290A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a gate driver, a display device, and a gate driving method.
  • an active matrix organic light emitting diode display Active Matrix OLED
  • a scan line of each row and a data line of each column intersect to form an active matrix.
  • the method of progressive scanning is adopted, and the gate tubes of each row are sequentially turned on, and the voltage on the data line is transmitted to the pixel driving tube, and converted into a current-driven organic light emitting diode (OLED) light-emitting display.
  • OLED organic light emitting diode
  • the driving circuit of the scan line is implemented by a shift register.
  • the shift register can be classified into a dynamic shift register and a static shift register according to the type.
  • the structure of the dynamic shift register is relatively simple and requires a small number of Thin film transistor (TFT), but it consumes a lot of power and has limited operating frequency bandwidth.
  • Static shift registers require more TFT devices, but have a larger operating bandwidth and lower power consumption.
  • the row scan driving circuit is usually implemented by amorphous silicon (a-Si) or polycrystalline silicon (p-Si) TFT transistors and directly fabricated on the panel, which can reduce the peripheral driving circuit. Interconnection, reducing size and cost.
  • the line scan driving circuit based on the panel design does not require high speed, but needs to be compact and occupy a small area, so the dynamic shift register is often used.
  • traditional shift registers designed with P-channel metal oxide semiconductor (PMOS) and N-Mental-Oxide-Semiconductor (NMOS) transistors are compared in process implementation. Complex, costly (usually 7 to 9 masks are required), and transient currents are large, so panel-based designs use only NMOS or PMOS dynamic circuits.
  • PMOS P-channel metal oxide semiconductor
  • NMOS N-Mental-Oxide-Semiconductor
  • the gate driver (GOA) of the existing array substrate is a logic circuit for generating a single pulse waveform. As shown in FIG. 2, in order to prevent panel display unevenness caused by Vth drift, the OLED pixel structure mostly has internal threshold voltage compensation. Functional pixel circuit. When the existing GOA circuit inputs a double pulse, a simulation result as shown in FIG. 3 appears.
  • Embodiments of the present invention provide a gate driver, a display device, and a gate driving method for implementing a function of a gate driver outputting a multi-pulse waveform.
  • a gate driver provided by an embodiment of the present invention includes: a plurality of groups of driving units, each group of driving units including N rows of shift registers and logic circuits, N being an integer greater than 1, and an output terminal of each row of shift registers Line logic circuits are connected;
  • the output end of the mth row logic circuit is connected to the gate scan line of the mth row pixel, and is connected to the trigger signal input end of the m+1th row shift register, and the value range of m is [1, M-1] , M is the total number of rows of pixels;
  • the output of the kth row logic circuit is connected to the reset terminal of the k-th (N-1)th row shift register, and the value range of k is [N, M];
  • All logic circuits in multiple sets of drive units share a single logic circuit clock signal.
  • each row shift register multiplexes N different timing shift register clock signals
  • each row logic circuit outputs logic circuit output signals each including a plurality of pulses at different timings, the plurality of The pulse width of each pulse in the pulse is equal to the pulse width of the logic circuit clock signal.
  • a plurality of clock signals of different timings are multiplexed by the shift register in the gate driver and output to a corresponding logic circuit, and the corresponding logic circuit selects and outputs clock signals of different timings.
  • the mth row logic circuit includes: a first thin film transistor, a second thin film transistor, and an inverter connected between a gate of the first thin film transistor and a gate of the second thin film transistor;
  • the drain of the first thin film transistor is connected to the drain of the second thin film transistor and serves as an output end of the logic circuit; the source of the first thin film transistor serves as an input end of the logic circuit clock signal; the gate of the first thin film transistor The pole serves as an input connected to the output of the mth row shift register; the source of the second thin film transistor serves as an input of the low level signal.
  • the pulse width of the logic circuit clock signal is a first pulse width, and the pulse period is a first pulse period;
  • the pulse width of the shift register clock signal is a second pulse width
  • the pulse period is a second pulse period
  • the second pulse width is greater than the first pulse width
  • the second pulse period is greater than the first pulse period One pulse period.
  • the second pulse width is 2*(N-1) times the first pulse width, and the second pulse period is N times the first pulse period;
  • each row of logic circuit outputs includes N-1 pulse widths as described a logic circuit output signal of a pulse of a first pulse width, a timing of an output signal of the n+1th row logic circuit being later than an output signal of the nth row logic circuit by the first pulse period, wherein a range of n is [1, N-1].
  • each row includes a shift register and a logic circuit.
  • the mth row shift register comprises: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first capacitor, a second capacitor, and a resistor;
  • the gate of the first thin film transistor is shorted to the source, and when m is 1, as the input end of the initial trigger signal, when m is greater than 1, the trigger signal input terminal and the m-1 are used as the shift register.
  • the line The outputs of the logic circuits are connected;
  • the first thin film transistor is connected in series with the second thin film transistor, and a connection point of the first thin film transistor and the second thin film transistor is connected to one end of the first capacitor and a gate of the third thin film transistor, and the third thin film transistor is connected in series with the fourth thin film transistor.
  • a connection point of the third thin film transistor and the fourth thin film transistor is connected to the other end of the first capacitor and one end of the resistor, and serves as an output end of the shift register, and a source of the third thin film transistor serves as an input end of the clock signal,
  • the gate of the second thin film transistor and the gate of the fourth thin film transistor both serve as reset ends of the shift register, and the other end of the resistor is connected to one end of the second capacitor, and the other end of the second capacitor and the drain of the second thin film transistor And the drain of the fourth thin film transistor is used as an input terminal of the low level signal.
  • a display device includes the gate driver according to any one of the embodiments of the present invention.
  • FIG. 1 is a schematic diagram of an active matrix in the prior art
  • FIG. 2 is a schematic diagram of a circuit structure of a conventional GOA
  • FIG. 3 is a schematic diagram showing simulation results of an output signal of a conventional GOA circuit when a double pulse is input;
  • FIG. 4 is a schematic structural diagram of a circuit of a gate driver according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing a timing relationship between a clock signal multiplexed by every 8 rows of shift registers, a clock signal shared by all logic circuits, and an initial trigger signal STV input by the shift register of the 1st row, according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of a circuit of a shift register according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a circuit of a logic circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of an equivalent circuit of the logic circuit shown in FIG. 7 according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of simulation results of a gate driver according to an embodiment of the present invention.
  • FIG. 10 is a flowchart of a gate driving method using a gate driver according to an embodiment of the present invention.
  • Embodiments of the present invention provide a gate driver, a display device, and a gate driving method for implementing a function of a gate driver outputting a multi-pulse waveform.
  • the shift register shares a set of clock signals every N (N is an integer greater than 1), and the output signal of each shift register is input to the corresponding logic circuit, and the shift register is The output signal is processed by the logic circuit, and the clock signal is selectively outputted, and finally the multi-pulse shift signal is output and transmitted to the Gate end of the gate scan line of each row of pixels to realize multi-line scanning. Therefore, the function of the gate driver to output the multi-pulse waveform is realized, and the shift register with the threshold voltage compensation function is prepared, so that the multi-line scan shift register becomes possible on the display panel, and the technology for solving the multi-line scan on the glass panel is solved. problem.
  • N is equal to 8.
  • N may take other values, for example, may be 9, and the specific value of N depends on the time required to scan a row of pixels.
  • the OLED display Due to the threshold voltage (Vth) drift of the thin film transistor (TFT), the OLED display is uneven. In order to eliminate this non-uniformity, many OLED pixel circuit structures have internal threshold voltage compensation, and the working process generally includes pre-processing. The charging, compensating, writing, and illuminating stages are different from the existing liquid crystal display (GATE Driving) scanning waveforms, and the OLED gate driving (GATE Driver) is more complicated.
  • the GOA output provided by the embodiment of the present invention has The multi-pulse waveform function prepares in advance for a pixel circuit with a threshold voltage compensation function waveform.
  • a gate driver includes: a plurality of groups of driving units, each group of driving units including N rows of shift registers and logic circuits.
  • ON1 represents the first row shift The output of the register
  • ON2 represents the output of the shift register of the 2nd row
  • ON3 represents the output of the shift register of the 3rd row
  • ON16 represents the output of the shift register of the 16th row;
  • the output of the mth row logic circuit is coupled to the gate scan line of the mth row of pixels to provide a gate drive signal for the mth row of pixels.
  • the output of the mth row logic circuit is also connected to the input terminal IN of the m+1th row shift register, the value range of m is [1, M-1], and M is the total number of rows of pixels. That is, as shown in FIG. 4, the output terminal of the first row logic circuit is connected to the input terminal IN of the second row shift register, and the output terminal of the second row logic circuit is connected to the input terminal IN of the third row shift register, the third row.
  • the output of the logic circuit is connected to the input IN of the shift register of the 4th row, and so on, and the output of the logic circuit of the 15th line is connected to the input IN of the shift register of the 16th row.
  • Output 1 represents the output of the first row of logic
  • Output 2 represents the output of the second row of logic
  • Output 3 represents the output of the third row of logic, and so on
  • Output 16 represents the 16th row.
  • the output of the logic circuit; the shift register 1 represents the 1st row shift register, the shift register 2 represents the 2nd row shift register, the shift register 3 represents the 3rd row shift register, and so on, the shift register 16 Indicates the 16th row shift register; logic circuit 1 represents the 1st row logic circuit, logic circuit 2 represents the 2nd row logic circuit, logic circuit 3 represents the 3rd row logic circuit, and so on, and logic circuit 16 represents the 16th line logic Circuit.
  • the output of the kth row logic circuit is connected to the reset end of the k-(N-1)th row shift register, and the value range of k is [N, M].
  • k is taken from 8
  • the value, that is, the output of the 8th line logic circuit is connected to the reset end of the 1st row shift register, the output of the 9th line logic circuit is connected to the reset end of the 2nd row shift register, and the output of the 10th line logic circuit is connected.
  • All logic circuits share a clock signal having a pulse width of a first pulse width and a pulse period of a first pulse period (in FIG. 4, all of which are denoted by CLK);
  • each group of drive units when each row of shift registers is multiplexed with N different timings a clock signal, wherein a pulse width of each clock signal is a second pulse width, a pulse period is a second pulse period, and the second pulse width is 2*(N-1) times the first pulse width, The second pulse period is N times of the first pulse period; the nth row shift register inputs an nth clock signal, and the timing of the n+1th clock signal is later than the nth clock signal by the first pulse period Each row of logic circuit outputs a signal including N-1 pulses having a pulse width of the first pulse width, and an output signal of the n+1th row logic circuit is later than an output signal of the nth row logic circuit The first pulse period, where n has a value range of [1, N-1].
  • N 8.
  • eight clock signals with different timings multiplexed every 8 rows of shift registers are CLK 1, CLK 2, ... CLK 8.
  • the CLK 1 signal is input to the 1st row shift register
  • the CLK 2 signal is input to the 2nd row shift register
  • the CLK 8 signal is input to the 8th row shift register.
  • the mth row shift register includes: a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a first capacitor C1, a second capacitor C2, and a resistor R1;
  • the gate of the first thin film transistor M1 is short-circuited with the source.
  • m 1
  • the trigger signal input terminal of the shift register is connected to the mth. -1 line logic circuit output Output(m-1);
  • the first thin film transistor M1 is connected in series with the second thin film transistor M2, and the connection point of the first thin film transistor M1 and the second thin film transistor M2 is connected to one end of the first capacitor C1 and the gate of the third thin film transistor M3, and the third thin film transistor M3 is
  • the fourth thin film transistor M4 is connected in series, and the connection point of the third thin film transistor M3 and the fourth thin film transistor M4 is connected to the other end of the first capacitor C1 and one end of the resistor R1, and serves as an output terminal of the shift register ON(m),
  • the source of the three thin film transistor M3 serves as an input terminal of the clock signal CLK(n), and the gate of the second thin film transistor M2 and the gate of the fourth thin film transistor M4 serve as the shift
  • the reset end of the bit register is reset, the other end of the resistor R1 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2, the drain of the second thin film transistor M2, and the drain of the fourth thin film transistor M4
  • the logic circuit in the mth row includes: a first thin film transistor T1, a second thin film transistor T2, and a gate connected to the gate of the first thin film transistor T1 and the second thin film transistor T2.
  • the drain of the first thin film transistor T1 is connected to the drain of the second thin film transistor T2 and serves as the output terminal Output(m) of the logic circuit; the source of the first thin film transistor T1 serves as a clock signal CLK shared by the logic circuit.
  • the input terminal; the gate of the first thin film transistor T1 serves as an input terminal connected to the output terminal ON(m) of the shift register in the mth row; the source of the second thin film transistor T2 serves as an input of the low level signal VSS end.
  • Fig. 8 shows an equivalent circuit of the logic circuit shown in Fig. 7, in which OP(m) represents an inverted signal of an ON (m) output signal. That is, the logic circuit provided in this embodiment is equivalent to an inverter, two AND gates, and an OR gate.
  • the clock signal for the shift register includes eight different timing clock signals CLK 1, CLK 2, ... CLK 8, and the shift register complexes the eight clock signals.
  • the wide pulse width of the one clock signal is 14 times the narrow pulse width of the clock signal CLK of the source input of the thin film transistor T1 in the logic circuit, that is, a pulse corresponding logic of the clock signal of the shift register.
  • the seven pulses of the clock signal of the circuit, the two clock signals are logically ANDed, ORed, and the multi-pulse output Outputn with 7 pulses is selected.
  • the shift register generates the waveforms of the ON1 to ON8 output signals after multiplexing the clock signals CLK 1, CLK 2, ... CLK 8 in this simulation.
  • the pulse width of the ON output signal is 14 times the narrow pulse width of the selected clock signal CLK.
  • the ON is input to the thin film transistor T2 of FIG. 7 as a logic or circuit standby through the logic non-operation input, and the ON output signal and the clock CLK signal pass.
  • the logical AND operation is selected, and then the logic signal is finally processed into the output Output with 7 pulses, thereby realizing the function of the gate driver to output the multi-pulse waveform.
  • the shift register with threshold voltage compensation function is prepared, so that the multi-line scan shift register becomes possible on the display panel, solving the technical problem of multi-line scanning on the glass panel.
  • a display device includes the above-described gate driver (GOA) according to the embodiment of the present invention, and the display device may be, for example, an OLED display.
  • GOA gate driver
  • a gate driving method using the gate driver according to an embodiment of the present invention includes:
  • a shift register clock signal of a different timing is input to each row of shift registers
  • a logic circuit clock signal is input to each row of logic circuits such that by shifting the shift register output signals received by each row of logic circuits with the logic circuit clock signals, respectively, outputting different timings each including a plurality of pulses The signal, the pulse width of each of the plurality of pulses is equal to the pulse width of the logic circuit clock signal.
  • the pulse width of the logic circuit clock signal is a first pulse width
  • the pulse period is a first pulse period
  • a pulse width of each shift register clock signal is a second pulse width
  • a pulse period is a second pulse period
  • the second pulse width is greater than the first pulse width
  • the first The two pulse period is greater than the first pulse period.
  • the second pulse width is 2*(N-1) times the first pulse width
  • the second pulse period is N times the first pulse period
  • each group of driving units the timing of the n+1th shift register clock signal is later than the nth shift register clock signal by one of the first pulse periods; each row of logic circuit outputs includes N-1 pulse widths as described The output signal of the pulse of the first pulse width, the timing of the output signal of the n+1th row logic circuit is later than the output signal of the nth row logic circuit by the first pulse period, wherein the value range of n is [1] , N-1].

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种栅极驱动器、显示装置及栅极驱动方法。栅极驱动器包括：多组驱动单元，每组驱动单元包括N行移位寄存器和逻辑电路，N为大于1的整数，每行移位寄存器的输出端与该行逻辑电路相连；移位寄存器对多个不同时序的时钟信号进行复用，输出至逻辑电路，采用逻辑电路对时钟信号进行选择输出，从而实现栅极驱动器输出多脉冲波形的功能，为带有阈值电压补偿功能波形的移位寄存器做准备，从而使多行扫描移位寄存器在显示面板上成为可能。

Description

一种栅极驱动器、显示装置及栅极驱动方法 技术领域
本发明涉及显示器技术领域，尤其涉及一种栅极驱动器、显示装置及栅极驱动方法。
背景技术
如图1所示，在有源矩阵有机发光二极管显示(Active Matrix OLED)中，各行的扫描线(scan line)和各列的数据线(data line)交叉构成了一个有源矩阵。一般采用逐行扫描的方法，依次打开各行的门管，将数据线上的电压传入像素驱动管，并转化为电流驱动有机发光二极管(OLED)发光显示。
通常扫描线的驱动电路由移位寄存器(shift register)来实现，移位寄存器按照类型可分为动态移位寄存器和静态移位寄存器，通常动态移位寄存器的结构相对简单，需要较少数量的薄膜晶体管(TFT)，但是它的功耗较大，且工作频率带宽有限。静态移位寄存器需要较多的TFT器件，但是工作带宽大，功耗较低。随着显示面板尺寸的增大，行扫描驱动电路通常采用非晶硅(a-Si)或多晶硅(p-Si)的TFT晶体管实现并直接制作在面板之上，这样可以减少和外围驱动电路之间的互联，减小尺寸和成本。基于面板设计的行扫描驱动电路对速度要求不高，但是需要结构紧凑，占用面积小，因此多用动态移位寄存器来实现。此外传统的采用P沟道金属氧化物半导体(Positive channel Metal Oxide Semiconductor，PMOS)和N型金属氧化物半导体(N-Mental-Oxide-Semiconductor，NMOS)晶体管设计的移位寄存器，在工艺实现上比较复杂，成本很高(通常需要7～9层掩模板)，并且瞬态电流较大，因此基于面板的设计多仅使用NMOS或PMOS的动态电路。在考量移位寄存器的性能时，要综合考虑工作电压、功耗、可靠性和面积的因素，但是随着面板尺寸的逐渐增大，功耗和可靠性已成为更为重要的性能参数指标。通常，由于材料和膜厚的原因，基于非晶硅和低温多晶硅工艺的薄膜晶体管的阈值电压 Vth(绝对值)都比较大，这使得移位寄存器的工作电压和功耗都比较大。
现有的阵列基板的栅极驱动器(GOA)都是产生单脉冲波形的逻辑电路，如图2所示，为了防止Vth漂移造成面板显示不均匀性，OLED像素结构大多是带有内部阈值电压补偿功能的像素电路。现有的GOA电路在输入双脉冲时，会出现如图3所示的仿真结果。
从图3的仿真结果看，现有的GOA输入双脉冲波形，无法输出双脉冲波形，Q点的波形在第二个脉冲过来的时候，无法被拉上去，从而使Q点工作不正常，GOA电路无法完成输出多脉冲波形的功能。
发明内容
本发明实施例提供了一种栅极驱动器、显示装置及栅极驱动方法，用以实现栅极驱动器输出多脉冲波形的功能。
本发明实施例提供的一种栅极驱动器，包括：多组驱动单元，每组驱动单元包括N行移位寄存器和逻辑电路，N为大于1的整数，每行移位寄存器的输出端与该行逻辑电路相连；
第m行逻辑电路的输出端与第m行像素的栅极扫描线相连，并与第m+1行移位寄存器的触发信号输入端连接，m的取值范围为[1，M-1]，M为像素的总行数；
第k行逻辑电路的输出端与第k-(N-1)行移位寄存器的复位端相连，k的取值范围为[N，M]；
多组驱动单元中的所有逻辑电路共用一个逻辑电路时钟信号。
较佳地，在每组驱动单元中：各行移位寄存器复用N个不同时序的移位寄存器时钟信号，各行逻辑电路输出不同时序的各自包括多个脉冲的逻辑电路输出信号，所述多个脉冲中每个脉冲的脉冲宽度等于所述逻辑电路时钟信号的脉冲宽度。
因此，通过该栅极驱动器中的移位寄存器对多个不同时序的时钟信号进行复用并输出至对应逻辑电路，对应逻辑电路对不同时序的时钟信号进行选择输出， 来实现栅极驱动器输出多脉冲波形的功能，为带有阈值电压补偿功能移位寄存器做准备，从而使多行扫描移位寄存器在显示面板上成为可能，解决玻璃面板上多行扫描的技术问题。
较佳地，第m行逻辑电路包括：第一薄膜晶体管、第二薄膜晶体管，以及连接在所述第一薄膜晶体管的栅极和所述第二薄膜晶体管的栅极之间的反相器；
其中，第一薄膜晶体管的漏极与第二薄膜晶体管的漏极相连，并作为该逻辑电路的输出端；第一薄膜晶体管的源极作为逻辑电路时钟信号的输入端；第一薄膜晶体管的栅极作为与第m行移位寄存器的输出端相连的输入端；第二薄膜晶体管的源极作为低电平信号的输入端。
较佳地，逻辑电路时钟信号的脉冲宽度为第一脉冲宽度、脉冲周期为第一脉冲周期；
所述移位寄存器时钟信号的脉冲宽度均为第二脉冲宽度、脉冲周期均为第二脉冲周期，所述第二脉冲宽度大于所述第一脉冲宽度，所述第二脉冲周期大于所述第一脉冲周期。
较佳地，所述第二脉冲宽度是所述第一脉冲宽度的2*(N-1)倍，所述第二脉冲周期是所述第一脉冲周期的N倍；
在每组驱动单元中：第n+1移位寄存器时钟信号的时序晚于第n移位寄存器时钟信号一个所述第一脉冲周期；每行逻辑电路输出包括N-1个脉冲宽度为所述第一脉冲宽度的脉冲的逻辑电路输出信号，第n+1行逻辑电路的输出信号的时序晚于第n行逻辑电路的输出信号一个所述第一脉冲周期，其中，n的取值范围为[1，N-1]。
较佳地，每行包括一个移位寄存器和一个逻辑电路。
较佳地，第m行移位寄存器包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容、第二电容和电阻；
其中，第一薄膜晶体管的栅极与源极短接，当m为1时，作为初始触发信号的输入端，当m大于1时，作为该移位寄存器的触发信号输入端与第m-1行中的 逻辑电路的输出端相连；
第一薄膜晶体管与第二薄膜晶体管串联，第一薄膜晶体管与第二薄膜晶体管的连接点与第一电容的一端以及第三薄膜晶体管的栅极相连，第三薄膜晶体管与第四薄膜晶体管串联，第三薄膜晶体管与第四薄膜晶体管的连接点与第一电容的另一端以及电阻的一端相连，并作为该移位寄存器的输出端，第三薄膜晶体管的源极作为时钟信号的输入端，第二薄膜晶体管的栅极和第四薄膜晶体管的栅极均作为该移位寄存器的复位端，电阻的另一端与第二电容的一端相连，第二电容的另一端、第二薄膜晶体管的漏极以及第四薄膜晶体管的漏极均作为低电平信号的输入端。
本发明实施例提供的一种显示装置，包括本发明实施例任一所述的栅极驱动器。
本发明实施例提供的采用上述任一栅极驱动器的栅极驱动方法，包括：
在每组驱动单元中：
向每一行移位寄存器输入不同时序的移位寄存器时钟信号；
向每一行逻辑电路输入逻辑电路时钟信号，使得通过将每一行逻辑电路接收的移位寄存器输出信号分别与所述逻辑电路时钟信号进行逻辑运算，输出不同时序的各自包括多个脉冲的逻辑电路输出信号，所述多个脉冲中的每个脉冲的脉冲宽度等于为所述逻辑电路时钟信号的脉冲宽度。
附图说明
图1为现有技术中的有源矩阵示意图；
图2为现有GOA的电路结构示意图；
图3为现有的GOA电路在输入双脉冲时的输出信号的仿真结果示意图；
图4为本发明实施例提供的栅极驱动器的电路结构示意图；
图5为本发明实施例提供的每8行移位寄存器复用的时钟信号，与所有逻辑电路共用的时钟信号，以及第1行移位寄存器输入的初始触发信号STV之间的时序关系示意图；
图6为本发明实施例提供的移位寄存器的电路结构示意图；
图7为本发明实施例提供的逻辑电路的电路结构示意图；
图8为本发明实施例提供的图7所示的逻辑电路的等效电路结构示意图；
图9为本发明实施例提供的栅极驱动器的仿真结果示意图；以及
图10为本发明实施例提供的采用栅极驱动器的栅极驱动方法的流程图。
具体实施方式
本发明实施例提供了一种栅极驱动器、显示装置及栅极驱动方法，用以实现栅极驱动器输出多脉冲波形的功能。
本发明实施例提供的栅极驱动器中，移位寄存器每N(N为大于1的整数)行共用一组时钟信号，每个移位寄存器的输出信号输入给对应的逻辑电路，移位寄存器的输出信号经过逻辑电路的处理，对时钟信号进行选择输出，最终输出多脉冲的移位信号，并传送给每一行像素的栅极扫描线的Gate端，实现多行扫描。从而，实现栅极驱动器输出多脉冲波形的功能，为带有阈值电压补偿功能移位寄存器做准备，从而使多行扫描移位寄存器在显示面板上成为可能，解决玻璃面板上多行扫描的技术问题。
以下本发明实施例中以N等于8为例进行说明，当然N也可以取其他值，例如可以为9，N的具体取值取决于扫描一行像素所需的时间。
由于薄膜晶体管(TFT)的阈值电压(Vth)漂移会使OLED显示产生不均匀性，为了消除这种不均匀性，很多OLED像素电路结构都具有内部阈值电压补偿的作用，工作过程一般会包含预充、补偿、写数据以及发光阶段，与现有的液晶显示器栅极驱动(LCD GATE Driving)扫描波形不同，OLED栅极驱动(GATE Driver)会更复杂些，本发明实施例提供的GOA输出具有多脉冲波形的功能，可以提前为具有带阈值电压补偿功能波形的像素电路做准备。
参见图4，本发明实施例提供的栅极驱动器包括：多组驱动单元，每组驱动单元包括N行移位寄存器和逻辑电路，本实施例中，每行包括一个移位寄存器和 一个逻辑电路，对应一行像素，N为大于1的整数，本实施例中，N＝8，每行移位寄存器的输出端与该行逻辑电路相连；图4中，ON1表示第1行移位寄存器的输出端，ON2表示第2行移位寄存器的输出端，ON3表示第3行移位寄存器的输出端，以此类推，ON16表示第16行移位寄存器的输出端；
第m行逻辑电路的输出端与第m行像素的栅极扫描线相连，为第m行像素提供栅极驱动信号。第m行逻辑电路的输出端还连接第m+1行移位寄存器的输入端IN，m的取值范围为[1，M-1]，M为像素的总行数。即如图4所示，第1行逻辑电路的输出端连接第2行移位寄存器的输入端IN，第2行逻辑电路的输出端连接第3行移位寄存器的输入端IN，第3行逻辑电路的输出端连接第4行移位寄存器的输入端IN，以此类推，第15行逻辑电路的输出端连接第16行移位寄存器的输入端IN。
图4中，Output 1表示第1行逻辑电路的输出端，Output 2表示第2行逻辑电路的输出端，Output 3表示第3行逻辑电路的输出端，以此类推，Output 16表示第16行逻辑电路的输出端；移位寄存器1表示第1行移位寄存器，移位寄存器2表示第2行移位寄存器，移位寄存器3表示第3行移位寄存器，以此类推，移位寄存器16表示第16行移位寄存器；逻辑电路1表示第1行逻辑电路，逻辑电路2表示第2行逻辑电路，逻辑电路3表示第3行逻辑电路，以此类推，逻辑电路16表示第16行逻辑电路。
第k行逻辑电路的输出端连接第k-(N-1)行移位寄存器的复位端(reset)，k的取值范围为[N，M].本实施例中，k从8开始取值，即第8行逻辑电路的输出端连接第1行移位寄存器的复位端，第9行逻辑电路的输出端连接第2行移位寄存器的复位端，第10行逻辑电路的输出端连接第3行移位寄存器的复位端，以此类推。
所有逻辑电路共用一个脉冲宽度为第一脉冲宽度、脉冲周期为第一脉冲周期的时钟信号(图4中，以下均用CLK表示)；
在每组驱动单元中(即每8行中)：各行移位寄存器复用N个不同时序的时 钟信号，其中每一个时钟信号的脉冲宽度均为第二脉冲宽度、脉冲周期均为第二脉冲周期，所述第二脉冲宽度是所述第一脉冲宽度的2*(N-1)倍，所述第二脉冲周期是所述第一脉冲周期的N倍；第n行移位寄存器输入第n时钟信号，第n+1时钟信号的时序晚于第n时钟信号一个所述第一脉冲周期，每行逻辑电路输出包括N-1个脉冲宽度为所述第一脉冲宽度的脉冲的信号，第n+1行逻辑电路的输出信号的时序晚于第n行逻辑电路的输出信号一个所述第一脉冲周期，其中，n的取值范围为[1，N-1]。
本实施例中，N＝8，如图4所示，每8行移位寄存器复用的8个时序不同的时钟信号分别为CLK 1、CLK 2......CLK 8。在每组驱动单元中：向第1行移位寄存器输入CLK 1信号，向第2行移位寄存器输入CLK 2信号，以此类推，向第8行移位寄存器输入CLK 8信号。
每8行移位寄存器复用的8个时序不同的时钟信号CLK 1、CLK 2......CLK 8，与所有逻辑电路共用的时钟信号CLK，以及第1行移位寄存器输入的初始触发信号STV之间的时序关系，如图5所示。
参见图6，第m行移位寄存器包括：第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第一电容C1、第二电容C2和电阻R1；
其中，第一薄膜晶体管M1的栅极与源极短接，当m为1时，作为初始触发信号STV的输入端，当m大于1时，作为该移位寄存器的触发信号输入端连接第m-1行逻辑电路的输出端Output(m-1)；
第一薄膜晶体管M1与第二薄膜晶体管M2串联，第一薄膜晶体管M1与第二薄膜晶体管M2的连接点连接第一电容C1的一端以及第三薄膜晶体管M3的栅极，第三薄膜晶体管M3与第四薄膜晶体管M4串联，第三薄膜晶体管M3与第四薄膜晶体管M4的连接点连接第一电容C1的另一端以及电阻R1的一端，并作为该移位寄存器的输出端ON(m)，第三薄膜晶体管M3的源极作为时钟信号CLK(n)的输入端，第二薄膜晶体管M2的栅极和第四薄膜晶体管M4的栅极均作为该移 位寄存器的复位端reset，电阻R1的另一端与第二电容C2的一端相连，第二电容C2的另一端、第二薄膜晶体管M2的漏极以及第四薄膜晶体管M4的漏极均作为低电平信号VSS的输入端。本发明不对GOA具体电路做限定。
参见图7，第m行中的逻辑电路包括：第一薄膜晶体管T1、第二薄膜晶体管T2，以及连接在所述第一薄膜晶体管T1的栅极和所述第二薄膜晶体管T2的栅极之间的反相器P1；
其中，第一薄膜晶体管T1的漏极与第二薄膜晶体管T2的漏极相连，并作为该逻辑电路的输出端Output(m)；第一薄膜晶体管T1的源极作为逻辑电路共用的时钟信号CLK的输入端；第一薄膜晶体管T1的栅极作为与第m行中的移位寄存器的输出端ON(m)相连的输入端；第二薄膜晶体管T2的源极作为低电平信号VSS的输入端。
图8示出了图7所示的逻辑电路的等效电路，其中的OP(m)表示ON(m)输出信号的反向信号。即本实施例中提供的逻辑电路，相当于由一个反相器、两个与门以及一个或门组成。
参见图9，本实施例中，用于移位寄存器的时钟信号包括8个不同时序的时钟信号CLK 1、CLK 2......CLK 8，移位寄存器对这八个时钟信号进行复用，生成一个时钟信号，该一个时钟信号的宽脉冲宽度是逻辑电路中薄膜晶体管T1的源极输入的时钟信号CLK的窄脉冲宽度的14倍，即移位寄存器的时钟信号的一个脉冲对应逻辑电路的时钟信号的7个脉冲，这两个时钟信号经过逻辑与、非、或的运算，选择出具有7个脉冲的多脉冲输出Outputn.
从图9所示的仿真结果可以看出，移位寄存器在复用了时钟信号CLK 1、CLK 2......CLK 8之后，产生了ON1～ON8输出信号的波形，在本仿真中，ON输出信号的脉冲宽度是被选择的时钟信号CLK的窄脉冲宽度的14倍，ON经过逻辑非运算输入给图7中的薄膜晶体管T2作为逻辑或电路备用，ON输出信号与时钟CLK信号通过逻辑与运算进行选择，再通过逻辑或运算最终将CLK信号处理成具有7个脉冲的输出Outputn，从而实现栅极驱动器输出多脉冲波形的功能，为 带有阈值电压补偿功能移位寄存器做准备，从而使多行扫描移位寄存器在显示面板上成为可能，解决玻璃面板上多行扫描的技术问题。
本发明实施例提供的一种显示装置，包括上述本发明实施例所述的栅极驱动器(GOA)，该显示装置，例如可以是OLED显示器。
参照图10，本发明实施例提供的一种采用所述栅极驱动器的栅极驱动方法，包括：
在每组驱动单元中：
在操作1001处，向每一行移位寄存器输入不同时序的移位寄存器时钟信号；
在操作1002处，向每一行逻辑电路输入逻辑电路时钟信号，使得通过将每一行逻辑电路接收的移位寄存器输出信号分别与逻辑电路时钟信号进行逻辑运算，输出不同时序的各自包括多个脉冲的信号，多个脉冲中每个脉冲的脉冲宽度等于逻辑电路时钟信号的脉冲宽度。
较佳地，逻辑电路时钟信号的脉冲宽度为第一脉冲宽度、脉冲周期为第一脉冲周期。
在每组驱动单元中：每一移位寄存器时钟信号的脉冲宽度均为第二脉冲宽度、脉冲周期均为第二脉冲周期，所述第二脉冲宽度大于所述第一脉冲宽度，所述第二脉冲周期大于所述第一脉冲周期。
较佳地，所述第二脉冲宽度是所述第一脉冲宽度的2*(N-1)倍，所述第二脉冲周期是所述第一脉冲周期的N倍。
在每组驱动单元中：第n+1移位寄存器时钟信号的时序晚于第n移位寄存器时钟信号一个所述第一脉冲周期；每行逻辑电路输出包括N-1个脉冲宽度为所述第一脉冲宽度的脉冲的输出信号，第n+1行逻辑电路的输出信号的时序晚于第n行逻辑电路的输出信号一个所述第一脉冲周期，其中，n的取值范围为[1，N-1]。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (9)

  1. 一种栅极驱动器，包括：多组驱动单元，每组驱动单元包括N行移位寄存器和逻辑电路，N为大于1的整数，每行移位寄存器的输出端与该行逻辑电路相连，
    其中，第m行逻辑电路的输出端与第m行像素的栅极扫描线相连，并与第m+1行移位寄存器的触发信号输入端相连，m的取值范围为[1，M-1]，M为像素的总行数；
    第k行逻辑电路的输出端与第k-(N-1)行移位寄存器的复位端相连，k的取值范围为[N，M]；并且
    多组驱动单元中的所有逻辑电路共用一个逻辑电路时钟信号。
  2. 根据权利要求1所述的栅极驱动器，其中，在每组驱动单元中：各行移位寄存器复用N个不同时序的移位寄存器时钟信号，各行逻辑电路输出不同时序的各自包括多个脉冲的输出信号，所述多个脉冲中每个脉冲的脉冲宽度等于所述逻辑电路时钟信号的脉冲宽度。
  3. 根据权利要求1所述的栅极驱动器，其中，第m行逻辑电路包括：第一薄膜晶体管、第二薄膜晶体管，以及连接在所述第一薄膜晶体管的栅极和所述第二薄膜晶体管的栅极之间的反相器；
    其中，第一薄膜晶体管的漏极与第二薄膜晶体管的漏极相连，并作为该逻辑电路的输出端；第一薄膜晶体管的源极作为逻辑电路时钟信号的输入端；第一薄膜晶体管的栅极作为与第m行移位寄存器的输出端相连的输入端；第二薄膜晶体管的源极作为低电平信号的输入端。
  4. 根据权利要求2所述的栅极驱动器，其中，所述逻辑电路时钟信号的脉冲宽度为第一脉冲宽度、脉冲周期为第一脉冲周期；
    所述移位寄存器时钟信号的脉冲宽度均为第二脉冲宽度、脉冲周期均为第二脉冲周期，并且所述第二脉冲宽度大于所述第一脉冲宽度，所述第二脉冲周期大于所述第一脉冲周期。
  5. 根据权利要求4所述的栅极驱动器，其中，所述第二脉冲宽度是所述第一脉 冲宽度的2*(N-1)倍，所述第二脉冲周期是所述第一脉冲周期的N倍；
    在每组驱动单元中：第n+l移位寄存器时钟信号的时序晚于第n移位寄存器时钟信号一个所述第一脉冲周期；每行逻辑电路输出包括N-1个脉冲宽度为所述第一脉冲宽度的脉冲的输出信号，第n+1行逻辑电路的输出信号的时序晚于第n行逻辑电路的输出信号一个所述第一脉冲周期，其中，n的取值范围为[1，N-1]。
  6. 根据权利要求5所述的栅极驱动器，其中，每行包括一个移位寄存器和一个逻辑电路。
  7. 根据权利要求5所述的栅极驱动器，其中，第m行移位寄存器包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容、第二电容和电阻；
    其中，第一薄膜晶体管的栅极与源极短接，当m为1时，作为初始触发信号的输入端，当m大于1时，作为该移位寄存器的触发信号输入端与第m-1行逻辑电路的输出端相连；
    第一薄膜晶体管与第二薄膜晶体管串联，第一薄膜晶体管与第二薄膜晶体管的连接点与第一电容的一端以及第三薄膜晶体管的栅极相连，第三薄膜晶体管与第四薄膜晶体管串联，第三薄膜晶体管与第四薄膜晶体管的连接点与第一电容的另一端以及电阻的一端相连，并作为该移位寄存器的输出端，第三薄膜晶体管的源极作为时钟信号的输入端，第二薄膜晶体管的栅极和第四薄膜晶体管的栅极均作为该移位寄存器的复位端，电阻的另一端与第二电容的一端相连，第二电容的另一端、第二薄膜晶体管的漏极以及第四薄膜晶体管的漏极均作为低电平信号的输入端。
  8. 一种显示装置，包括权利要求1-7任一权项所述的栅极驱动器。
  9. 一种采用权利要求1-7任一项所述的栅极驱动器的栅极驱动方法，包括：
    在每组驱动单元中：
    向每一行移位寄存器输入不同时序的移位寄存器时钟信号；并且
    向每一行逻辑电路输入逻辑电路时钟信号，使得通过将每一行逻辑电路接收的移位寄存器输出信号分别与所述逻辑电路时钟信号进行逻辑运算，输出不同时序的 各自包括多个脉冲的输出信号，所述多个脉冲中的每个脉冲的脉冲宽度等于所述逻辑电路时钟信号的脉冲宽度。
PCT/CN2015/071918 2014-09-28 2015-01-30 一种栅极驱动器、显示装置及栅极驱动方法 WO2016045290A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP15750618.9A EP3200179B1 (en) 2014-09-28 2015-01-30 Gate driver, display device, and gate driving method
US14/770,364 US9799271B2 (en) 2014-09-28 2015-01-30 Gate driver, display apparatus and gate driving method of outputting a multi-pulse waveform
KR1020157023231A KR101718272B1 (ko) 2014-09-28 2015-01-30 게이트 구동기, 디스플레이 장치 및 게이트 구동 방법
JP2017535948A JP6755250B2 (ja) 2014-09-28 2015-01-30 ゲートドライバ、表示装置及びゲート駆動方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410510753.7 2014-09-28
CN201410510753.7A CN104269134B (zh) 2014-09-28 2014-09-28 一种栅极驱动器、显示装置及栅极驱动方法

Publications (1)

Publication Number Publication Date
WO2016045290A1 true WO2016045290A1 (zh) 2016-03-31

Family

ID=52160650

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/071918 WO2016045290A1 (zh) 2014-09-28 2015-01-30 一种栅极驱动器、显示装置及栅极驱动方法

Country Status (6)

Country Link
US (1) US9799271B2 (zh)
EP (1) EP3200179B1 (zh)
JP (1) JP6755250B2 (zh)
KR (1) KR101718272B1 (zh)
CN (1) CN104269134B (zh)
WO (1) WO2016045290A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104269134B (zh) * 2014-09-28 2016-05-04 京东方科技集团股份有限公司 一种栅极驱动器、显示装置及栅极驱动方法
CN104537977B (zh) 2015-01-20 2017-08-11 京东方科技集团股份有限公司 一种goa单元及驱动方法、goa电路和显示装置
CN104575396B (zh) * 2015-02-05 2017-07-18 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极扫描电路
CN104766587B (zh) * 2015-04-30 2016-03-02 京东方科技集团股份有限公司 扫描驱动电路及其驱动方法、阵列基板、显示装置
CN105206225B (zh) * 2015-10-12 2017-09-01 深圳市华星光电技术有限公司 Oled栅极驱动电路架构
CN106057150A (zh) * 2016-07-14 2016-10-26 江苏万邦微电子有限公司 高精度栅极驱动电路
CN106023940B (zh) * 2016-07-29 2018-07-17 武汉华星光电技术有限公司 一种两级单mos管goa扫描驱动电路及显示面板
CN107452316A (zh) * 2017-08-22 2017-12-08 京东方科技集团股份有限公司 一种选择输出电路及显示装置
CN107622755B (zh) * 2017-10-30 2023-09-12 北京小米移动软件有限公司 栅极驱动电路及其驱动方法、电子设备
CN108230981B (zh) * 2018-01-19 2021-06-01 厦门天马微电子有限公司 一种显示面板和显示装置
CN108182905B (zh) * 2018-03-27 2021-03-30 京东方科技集团股份有限公司 开关电路、控制单元、显示装置、栅极驱动电路及方法
CN108766357B (zh) * 2018-05-31 2020-04-03 京东方科技集团股份有限公司 信号合并电路、栅极驱动单元、栅极驱动电路和显示装置
CN108538257B (zh) 2018-07-13 2020-07-24 京东方科技集团股份有限公司 栅极驱动单元及其驱动方法、栅极驱动电路和显示基板
CN109686296B (zh) * 2019-03-05 2022-05-20 合肥鑫晟光电科技有限公司 移位寄存器模块及驱动方法、栅极驱动电路
CN109767716B (zh) * 2019-03-12 2022-09-06 京东方科技集团股份有限公司 一种阵列基板、显示装置及驱动方法
CN110827778B (zh) * 2019-10-25 2021-10-08 深圳市华星光电半导体显示技术有限公司 栅极扫描驱动电路及显示面板
CN113037260B (zh) * 2019-12-09 2022-10-14 圣邦微电子（北京）股份有限公司 一种信号开关管的驱动电路以及信号传输电路
JP2022099473A (ja) 2020-12-23 2022-07-05 武漢天馬微電子有限公司 表示装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1486482A (zh) * 2001-10-17 2004-03-31 ���ṫ˾ 显示装置
US20060284820A1 (en) * 2005-06-20 2006-12-21 Lg Philips Lcd Co., Ltd. Driving circuit, liquid crystal display device and method of driving the same
CN101233556A (zh) * 2005-08-01 2008-07-30 夏普株式会社 显示装置及其驱动电路与驱动方法
CN101266769A (zh) * 2008-04-21 2008-09-17 昆山龙腾光电有限公司 时序控制器、液晶显示装置及液晶显示装置的驱动方法
CN101281719A (zh) * 2007-04-06 2008-10-08 三星Sdi株式会社 有机发光显示器
CN101630475A (zh) * 2008-07-14 2010-01-20 索尼株式会社 扫描驱动电路和包括该扫描驱动电路的显示设备
CN101783117A (zh) * 2009-01-20 2010-07-21 联咏科技股份有限公司 栅极驱动器及应用其的显示驱动器
CN102103294A (zh) * 2009-12-17 2011-06-22 联咏科技股份有限公司 栅极驱动电路及相关液晶显示器
CN104269134A (zh) * 2014-09-28 2015-01-07 京东方科技集团股份有限公司 一种栅极驱动器、显示装置及栅极驱动方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5692026A (en) * 1996-05-31 1997-11-25 Hewlett-Packard Company Apparatus for reducing capacitive loading of clock and shift signals by shifting register-based devices
GB2323957A (en) * 1997-04-04 1998-10-07 Sharp Kk Active matrix drive circuits
KR101019416B1 (ko) * 2004-06-29 2011-03-07 엘지디스플레이 주식회사 쉬프트레지스터 및 이를 포함하는 평판표시장치
US7586476B2 (en) * 2005-06-15 2009-09-08 Lg. Display Co., Ltd. Apparatus and method for driving liquid crystal display device
JP4912023B2 (ja) * 2006-04-25 2012-04-04 三菱電機株式会社 シフトレジスタ回路
JP2008020675A (ja) * 2006-07-13 2008-01-31 Mitsubishi Electric Corp 画像表示装置
JP4816686B2 (ja) * 2008-06-06 2011-11-16 ソニー株式会社 走査駆動回路
WO2010041649A1 (ja) * 2008-10-10 2010-04-15 シャープ株式会社 表示装置及びその駆動方法
KR101573460B1 (ko) * 2009-04-30 2015-12-02 삼성디스플레이 주식회사 게이트 구동회로
KR101481675B1 (ko) * 2011-10-04 2015-01-22 엘지디스플레이 주식회사 양 방향 쉬프트 레지스터
CN102654975B (zh) * 2011-11-01 2014-08-20 京东方科技集团股份有限公司 Amoled驱动补偿电路、方法及其显示装置
US9711238B2 (en) * 2011-12-16 2017-07-18 Sharp Kabushiki Kaisha Shift register, scan signal line driver circuit, display panel and display device
CN103578433B (zh) * 2012-07-24 2015-10-07 北京京东方光电科技有限公司 一种栅极驱动电路、方法及液晶显示器

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1486482A (zh) * 2001-10-17 2004-03-31 ���ṫ˾ 显示装置
US20060284820A1 (en) * 2005-06-20 2006-12-21 Lg Philips Lcd Co., Ltd. Driving circuit, liquid crystal display device and method of driving the same
CN101233556A (zh) * 2005-08-01 2008-07-30 夏普株式会社 显示装置及其驱动电路与驱动方法
CN101281719A (zh) * 2007-04-06 2008-10-08 三星Sdi株式会社 有机发光显示器
CN101266769A (zh) * 2008-04-21 2008-09-17 昆山龙腾光电有限公司 时序控制器、液晶显示装置及液晶显示装置的驱动方法
CN101630475A (zh) * 2008-07-14 2010-01-20 索尼株式会社 扫描驱动电路和包括该扫描驱动电路的显示设备
CN101783117A (zh) * 2009-01-20 2010-07-21 联咏科技股份有限公司 栅极驱动器及应用其的显示驱动器
CN102103294A (zh) * 2009-12-17 2011-06-22 联咏科技股份有限公司 栅极驱动电路及相关液晶显示器
CN104269134A (zh) * 2014-09-28 2015-01-07 京东方科技集团股份有限公司 一种栅极驱动器、显示装置及栅极驱动方法

Also Published As

Publication number Publication date
US20160372046A1 (en) 2016-12-22
JP2017533474A (ja) 2017-11-09
KR20160052461A (ko) 2016-05-12
KR101718272B1 (ko) 2017-03-20
CN104269134A (zh) 2015-01-07
CN104269134B (zh) 2016-05-04
JP6755250B2 (ja) 2020-09-16
EP3200179A1 (en) 2017-08-02
EP3200179B1 (en) 2020-10-28
EP3200179A4 (en) 2018-04-25
US9799271B2 (en) 2017-10-24

Similar Documents

Publication Publication Date Title
WO2016045290A1 (zh) 一种栅极驱动器、显示装置及栅极驱动方法
US10950321B2 (en) Shift register, gate driving circuit, display panel and display device
US9437325B2 (en) TFT array substrate, display panel and display device
US7817771B2 (en) Shift register
US9653179B2 (en) Shift register, driving method and gate driving circuit
KR101486175B1 (ko) 어레이 기판 행 구동 유닛, 어레이 기판 행 구동 회로 및 디스플레이 장치
US8605029B2 (en) Shift register, display device provided with same, and method of driving shift register
US10146362B2 (en) Shift register unit, a shift register, a driving method, and an array substrate
EP3232430B1 (en) Shift register and drive method therefor, shift scanning circuit and display device
US10658060B2 (en) Shift register circuit and shift register unit
KR100826997B1 (ko) 평판표시장치의 게이트 드라이버용 쉬프트 레지스터
WO2016161727A1 (zh) 移位寄存器单元及其驱动方法、阵列基板栅极驱动装置、以及显示面板
US10923064B2 (en) Scanning signal line drive circuit and display device equipped with same
US11107381B2 (en) Shift register and method for driving the same, gate driving circuit and display device
CN114220400A (zh) 具有栅极驱动器的显示装置
WO2010116778A1 (ja) シフトレジスタおよびそれを備えた表示装置、ならびにシフトレジスタの駆動方法
CN113178221A (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN113192551A (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
US10937380B2 (en) Shift register and driving method therefor, gate driving circuit and display apparatus
EP4131228A1 (en) Gate drive circuit, driving method therefor, and display panel
CN110956915B (zh) 栅极驱动单元电路、栅极驱动电路、显示装置和驱动方法
WO2022170567A1 (zh) 像素电路及其驱动方法、显示装置
KR101914546B1 (ko) 게이트 구동 회로 및 그 구동 방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14770364

Country of ref document: US

ENP Entry into the national phase

Ref document number: 20157023231

Country of ref document: KR

Kind code of ref document: A

REEP Request for entry into the european phase

Ref document number: 2015750618

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2015750618

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2017535948

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15750618

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE