US9799271B2 - Gate driver, display apparatus and gate driving method of outputting a multi-pulse waveform - Google Patents

Gate driver, display apparatus and gate driving method of outputting a multi-pulse waveform Download PDF

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US9799271B2
US9799271B2 US14/770,364 US201514770364A US9799271B2 US 9799271 B2 US9799271 B2 US 9799271B2 US 201514770364 A US201514770364 A US 201514770364A US 9799271 B2 US9799271 B2 US 9799271B2
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thin film
film transistor
logic circuit
shift register
output
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US20160372046A1 (en
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Lirong Wang
Liye DUAN
Zhongyuan Wu
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BOE Technology Group Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation

Definitions

  • the present disclosure relates to the technical field of displays, and in particular, to a gate driver, a display apparatus, and a gate driving method.
  • OLED Organic Light Emitting Diode
  • various rows of scan lines and various columns of data lines intersect to form an active matrix.
  • various rows of gating diodes are opened in turn by using a progressive scanning method to apply voltage on the data lines to pixel driving diodes, which convert the voltage into current to drive the OLED to emit light for display.
  • a driving circuit for the scan lines is typically implemented by using shift registers.
  • the shift registers may be divided into dynamic shift registers and static shift registers in terms of categories.
  • the dynamic shift registers generally have a relatively simple structure, and need a few of Thin Film Transistors (TFTs), but consume large power and operate at a limited frequency bandwidth.
  • the static shift registers need more TFT devices, but operate at a larger bandwidth and consumes less power.
  • a row scan driving circuit is generally implemented by using TFT transistors made of amorphous silicon (a-Si) or polycrystalline Si (p-Si), and is directly manufactured on the panel. This may eliminate interconnection with a peripheral driving circuit, and reduce the size and cost.
  • the row scan driving circuit which is designed based on a panel has low requirements for the speed, but needs a compact structure and a small occupation area. As a result, the row scan driving circuit is often implemented by using dynamic shift registers.
  • the conventional shift register which is designed by using a Positive channel Metal Oxide Semiconductor (PMOS) transistor and an N-Mental-Oxide-Semiconductor (NMOS) transistor is relatively complex in terms of process realization, and leads to a high cost (the shift register generally needs to include 7-9 mask plate layers) and large transient current. Therefore, the panel based design typically utilizes a dynamic circuit which merely uses an NMOS or a PMOS.
  • the embodiments of the present disclosure provide a gate driver, a display apparatus and a gate driving method, to achieve a function of outputting a multi-pulse waveform by the gate driver.
  • a gate driver comprises: multiple groups of driving units, each group of driving units comprising N driving units each of which comprises a shift register and a logic circuit, wherein N is an integer larger than 1, and an output of a shift register is connected to a logic circuit in each driving unit,
  • an output of a logic circuit in an m th driving unit is connected to a gate scan line of an m th row of pixels, and is connected to an input for a trigger signal of a shift register in an m+1 th driving unit, wherein m is in a range of [1, M ⁇ 1], and M is a total number of rows of pixels;
  • an output of a logic circuit in a k th driving unit is connected to a reset of a k ⁇ (N ⁇ 1) th of a shift register, wherein k is in a range of [N, M];
  • shift registers in various driving units multiplex N shift register clock signals with different timings, and logic circuits in various driving units output output signals with different timings which have multiple pulses respectively, each of the multiple pulses having a pulse width equal to that of the logic circuit clock signal.
  • the shift registers in the gate driver multiplex multiple clock signals with different timings.
  • Each of the shift registers outputs an output signal to a corresponding logic circuit.
  • a part of a clock signal is selected by the corresponding logic circuit using the output signal from the shift register for output.
  • a function of outputting a multi-pulse waveform by the gate driver is achieved, which prepares for a shift register having a function of threshold voltage compensation, to make a shift register capable of multi-row scanning become feasible on a display panel, which solves the technical problem of multi-row scanning on a glass panel.
  • the logic circuit in the m th driving unit comprises a first thin film transistor, a second thin film transistor, and an inverter connected between a gate of the first thin film transistor and a gate of the second thin film transistor,
  • a drain of the first thin film transistor is connected to a drain of the second thin film transistor, and acts as an output of the logic circuit; a source of the first thin film transistor acts as an input for the logic circuit clock signal; the gate of the first thin film transistor acts as an input connected to an output of a shift register in the m th driving unit; and a source of the second thin film transistor acts as an input for a low level signal.
  • the logic circuit clock signal has a pulse width equal to a first pulse width and a pulse period equal to a first pulse period;
  • the second pulse width is 2*(N ⁇ 1) times the first pulse width
  • the second pulse period is N times the first pulse period
  • a timing of an n+1 th shift register clock signal is the first pulse period later than an n th shift register clock signal; and a logic circuit in each driving unit outputs an output signal having N ⁇ 1 pulses with a pulse width equal to the first pulse width, and a timing of an output signal of a logic circuit in an n+1 th driving unit is the first pulse period later than that of an output signal of a logic circuit in an n th driving unit, wherein n is in a range of [1, N ⁇ 1].
  • each driving unit comprises a shift register and a logic circuit.
  • a shift register in an m th driving unit comprises a first thin film register, a second thin film register, a third thin film register, a fourth thin film register, a first capacitor, a second capacitor, and a resistor,
  • a gate of the first thin film transistor is shorted to a source of the first thin film transistor, and when m is equal to 1, the gate acts as an input for an initial trigger signal, and when m is larger than 1, the gate is connected to an output of a logic circuit in an m ⁇ 1 th driving unit as an input for a trigger signal of the shift register;
  • the first thin film transistor is connected to the second thin film transistor in series, a connection point between the first thin film transistor and the second thin film transistor is connected to one end of the first capacitor and a gate of the third thin film transistor, the third thin film transistor is connected to the fourth thin film transistor in series, a connection point between the third thin film transistor and the fourth thin film transistor is connected to the other end of the first capacitor and one end of the resistor, and acts as an output of the shift register, a source of the third thin film transistor acts as an input for a clock signal, both a gate of the second thin film transistor and a gate of the fourth thin film transistor act as a reset of the shift register, the other end of the resistor is connected to one end of the second capacitor, and the other end of the second capacitor, a drain of the second thin film transistor, and a drain of the fourth thin film transistor act as an input for a low level signal.
  • a display apparatus comprises the gate driver according to any of the embodiments of the present disclosure.
  • the logic circuits in various driving units output output signals with different timings which have multiple pulses respectively, each of the multiple pulses having a pulse width equal to that of the logic circuit clock signal.
  • FIG. 1 is a diagram of an active matrix in the related art
  • FIG. 2 is a structural diagram of an existing GOA circuit
  • FIG. 3 is a diagram of a simulation result of an output signal when dual pulses are input into an existing GOA circuit
  • FIG. 4 is a structural diagram of a gate driver circuit according to an embodiment of the present disclosure.
  • FIG. 5 is diagram of a timing relationship among clock signals multiplexed by shift registers in every 8 driving units, a common clock signal used by all logic circuits, and an initial trigger signal STV input into a shift register in a 1 st driving unit according to an embodiment of the present disclosure
  • FIG. 6 is a structural diagram of a shift register circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a structural diagram of a logic circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a structural diagram of an equivalent circuit of the logic circuit illustrated in FIG. 7 according to an embodiment of the present disclosure.
  • FIG. 9 is a diagram of a simulation result of a gate driver according to an embodiment of the present disclosure.
  • FIG. 10 is a flowchart of a gate driving method using a gate driver according to an embodiment of the present disclosure.
  • the embodiments of the present disclosure provide a gate driver, a display apparatus, and a gate driving method, to achieve a function of outputting a multi-pulse waveform by the gate driver.
  • shift registers in every N (N is an integer larger than 1) driving units use a common group of clock signals.
  • An output signal of each shift register is input into a corresponding logic circuit.
  • the logic circuit processes the output signal of the shift register, and selects a part of a clock signal thereof to finally output a multi-pulse shift signal, and transmits the multi-pulse shift signal to a gate end of a gate scan line of a corresponding row of pixels, so as to implement multi-row scanning.
  • N is equal to 8 as an example.
  • N may be equal to another value, for example, 9.
  • a specific value of N depends on the time required for scanning a row of pixels.
  • a threshold voltage (Vth) of a TFT may result in non-uniformity in the display of the OLED
  • many OLED pixel circuit structures have a function of internal threshold voltage compensation, and the operation process of the OLED pixel circuits may generally include a pre-charging phase, a compensation phase, a data writing phase, and a light emitting phase.
  • a scan waveform of the OLED gate driver may be more complex.
  • the GOA according to the embodiment of the present disclosure has a function of outputting a multi-pulse waveform, which may prepare for the pixel circuit having a function of threshold voltage compensation in advance.
  • a gate driver comprises multiple groups of driving units, each group of driving units comprising N driving units, each of which comprises a shift register and a logic circuit.
  • each driving unit comprises a shift register and a logic circuit, and corresponds to a row of pixels, and N is an integer larger than 1.
  • N 8 and an output of a shift register is connected to a logic circuit in each driving unit.
  • ON 1 represents an output of a shift register in a 1 st driving unit
  • ON 2 represents an output of a shift register in a 2 nd driving unit
  • ON 3 represents an output of a shift register in a 3 rd driving unit
  • ON 16 represents an output of a shift register in a 16 th driving unit.
  • An output of a logic circuit in an m th driving unit is connected to a gate scan line of an m th row of pixels, to provide a gate drive signal to the m th row of pixels.
  • the output of the logic circuit in the m th driving unit is also connected to an input IN of a shift register in an m+1 th driving unit, wherein m is in a range of [1, M ⁇ 1], and M is a total number of rows of pixels. That is, as shown in FIG.
  • an output of a logic circuit in a 1 st driving unit is connected to an input IN of a shift register in the 2 nd driving unit
  • an output of a logic circuit in a 2 nd driving unit is connected to an input IN of a shift register in the 3 rd driving unit
  • an output of a logic circuit in a 3 rd driving unit is connected to an input IN of a shift register in a 4 th driving unit
  • so on until an output of a logic circuit in a 15 th driving unit is connected to an input IN of a shift register in the 16 th driving unit.
  • Output 1 represents the output of a logic circuit in the 1 st driving unit
  • Output 2 represents the output of a logic circuit in the 2 nd driving unit
  • Output 3 represents the output of a logic circuit in the 3 rd driving unit, and so on, until Output 16 represents an output of a logic circuit in a 16 th driving unit
  • Shift register 1 represents a shift register in the 1 st driving unit
  • Shift register 2 represents a shift register in the 2 nd driving unit
  • Shift register 3 represents a shift register in the 3 rd driving unit, and so on, until Shift register 16 represents a shift register in the 16 th driving unit
  • Logic circuit 1 represents a logic circuit in the 1 st driving unit
  • Logic circuit 2 represents a logic circuit in the 2 nd driving unit
  • Logic circuit 3 represents a logic circuit in the 3 rd driving unit, and so on, until Logic circuit 16 represents a logic circuit in the 16 th driving unit.
  • An output of a logic circuit in a k th driving unit is connected to a reset of a shift register in a k ⁇ (N ⁇ 1) th driving unit, wherein k is in a range of [N, M].
  • k starts from 8. That is, an output of a logic circuit in a 8 th driving unit is connected to a reset of a shift register in the 1 st driving unit, an output of a logic circuit in a 9 th driving unit is connected to a reset of a shift register in the 2 nd driving unit, an output of a logic circuit in a 10 th driving unit is connected to a reset of a shift register in the 3 rd driving unit, and so on.
  • All logic circuits use a common clock signal (which is represented by CLK below as in FIG. 4 ) with a pulse width equal to a first pulse width and a pulse period equal to a first pulse period.
  • CLK common clock signal
  • shift registers in various driving units multiplex N clock signals with different timings.
  • Each of the clock signals has a pulse width equal to a second pulse width and a pulse period equal to a second pulse period.
  • the second pulse width is 2(N ⁇ 1) times the first pulse width
  • the second pulse period is N times the first pulse period.
  • An n th clock signal is input into a shift register in an n th driving unit, a timing of an n+1 th clock signal is the first pulse period later than that of the n th clock signal.
  • a logic circuit in each driving unit outputs a signal having N ⁇ 1 pulses with a pulse width equal to the first pulse width.
  • a timing of an output signal of a logic circuit in an n+1 th driving unit is the first pulse period later than that of an output signal of a logic circuit in an n th driving unit, wherein n is in a range of [1, N ⁇ 1].
  • N 8.
  • 8 clock signals with different timings which are multiplexed by shift registers in every 8 driving units are CLK 1 , CLK 2 . . . CLK 8 respectively.
  • the signal CLK 1 is input into a shift register in the 1 st driving unit
  • the signal CLK 2 is input into a shift register in the 2 nd driving unit
  • so on until the signal CLK 8 is input into a shift register in a 8 th driving unit.
  • FIG. 5 A timing relationship among the 8 clock signals CLK 1 , CLK 2 . . . CLK 8 with different timings which are multiplexed by shift registers in every 8 driving units, the common clock signal CLK used by all logic circuits, and an initial trigger signal STV input into a shift register in the 1 st driving unit is shown in FIG. 5 .
  • a shift register in an m th driving unit comprises a first thin film transistor M 1 , a second thin film transistor M 2 , a third thin film transistor M 3 , a fourth thin film transistor M 4 , a first capacitor C 1 , a second capacitor C 2 , and a resistor R 1 .
  • a gate of the first thin film transistor M 1 is shorted to a source of the first thin film transistor M 1 .
  • the gate acts as an input for an initial trigger signal STV, and when m is larger than 1, the gate is connected to an output Output(m ⁇ 1) of a logic circuit in an m ⁇ 1 th driving unit as an input for a trigger signal of the shift register.
  • the first thin film transistor M 1 is connected to the second thin film transistor M 2 in series, and a connection point between the first thin film transistor M 1 and the second thin film transistor M 2 is connected to one end of the first capacitor C 1 and a gate of the third thin film transistor M 3 .
  • the third thin film transistor M 3 is connected to the fourth thin film transistor M 4 in series, and a connection point between the third thin film transistor M 3 and the fourth thin film transistor M 4 is connected to the other end of the first capacitor C 1 and one end of the resistor R 1 , and acts as an output ON(m) of the shift register.
  • a source of the third thin film transistor M 3 acts as an input for a clock signal CLK(n).
  • Both a gate of the second thin film transistor M 2 and a gate of the fourth thin film transistor M 4 act as a reset of the shift register.
  • the other end of the resistor R 1 is connected to one end of the second capacitor C 2 , and the other end of the second capacitor C 2 , a drain of the second thin film transistor M 2 , and a drain of the fourth thin film transistor M 4 act as an input for a low level signal VSS.
  • the specific GOA circuit is not limited in the present disclosure.
  • a logic circuit in an m th driving unit comprises a first thin film transistor T 1 , a second thin film transistor T 2 , and an inverter P 1 connected between a gate of the first thin film transistor T 1 and a gate of the second thin film transistor T 2 .
  • a drain of the first thin film transistor T 1 is connected to a drain of the second thin film transistor T 2 , and acts as an output Output(m) of the logic circuit.
  • a source of the first thin film transistor T 1 acts as an input for the common clock signal CLK used by the logic circuits.
  • the gate of the first thin film transistor T 1 acts as an input connected to an output ON(m) of a shift register in the m th driving unit.
  • a source of the second thin film transistor T 2 acts as an input for a low level signal VSS.
  • FIG. 8 illustrates an equivalent circuit of the logic circuit illustrated in FIG. 7 , wherein OP(m) represents an inverse signal of an output signal of ON(m). That is, the logic circuit according to the present embodiment is equivalent to being comprised of an inverter, two AND gates, and an OR gate.
  • each of the generated clock signals has a wide pulse width which is 14 times a narrow pulse width of a clock signal CLK input into a source of a thin film transistor T 1 of a logic circuit. That is, a pulse of the clock signal generated by the shift register corresponds to 7 pulses of the clock signal of the logic circuit.
  • a multi-pulse output signal Outputn with 7 pulses is obtained by implementing logic AND, NOT and OR operations on the two clock signals for selection.
  • a display apparatus comprises the above gate driver (GOA) according to the embodiment of the present disclosure.
  • the display apparatus may be an OLED display for example.
  • a gate driving method using the gate driver according to the embodiment of the present disclosure comprises:
  • in operation 1002 inputting a logic circuit clock signal to logic circuits in various driving units, so that after logic operations are implemented on an output signal of a shift register received by a logic circuit in each driving unit and the logic circuit clock signal, the logic circuits in the various driving units output signals with different timings which have multiple pulses respectively, each of the multiple pulses having a pulse width equal to that of the logic circuit clock signal.
  • the logic circuit clock signal has a pulse width equal to a first pulse width and a pulse period equal to a first pulse period.
  • each shift register clock signal has a pulse width equal to a second pulse width and a pulse period equal to a second pulse period, wherein the second pulse width is larger than the first pulse width, and the second pulse period is larger than the first pulse period.
  • the second pulse width is 2*(N ⁇ 1) times the first pulse width
  • the second pulse period is N times the first pulse period
  • a timing of an n+1 th shift register clock signal is the first pulse period later than an n th shift register clock signal; and a logic circuit in each driving unit outputs an output signal having N ⁇ 1 pulses with a pulse width equal to the first pulse width, and a timing of an output signal of a logic circuit in an n+1 th driving unit is the first pulse period later than that of an output signal of a logic circuit in an n th driving unit, wherein n is in a range of [1, N ⁇ 1].

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