WO2016029564A1 - 阵列基板及其制备方法、显示面板和显示装置 - Google Patents

阵列基板及其制备方法、显示面板和显示装置 Download PDF

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WO2016029564A1
WO2016029564A1 PCT/CN2014/091555 CN2014091555W WO2016029564A1 WO 2016029564 A1 WO2016029564 A1 WO 2016029564A1 CN 2014091555 W CN2014091555 W CN 2014091555W WO 2016029564 A1 WO2016029564 A1 WO 2016029564A1
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Prior art keywords
electrode
layer
common electrode
source
forming
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PCT/CN2014/091555
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English (en)
French (fr)
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占红明
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to EP14891131.6A priority Critical patent/EP3188235B1/en
Priority to US14/771,094 priority patent/US9893091B2/en
Publication of WO2016029564A1 publication Critical patent/WO2016029564A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same, a display panel, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • HADS Advanced-Super Dimensional Switching
  • the array substrate of the prior art HADS technology includes a base substrate 1a, a gate electrode 2a, a common electrode line 3a, a gate insulating layer 4a, an active layer 5a, a pixel electrode 6a, a drain electrode 8a, and a source.
  • the common electrode 11a is electrically connected to the common electrode line 3a via the hole 20a.
  • the via hole 20a is a via hole penetrating the gate insulating layer 4a and the passivation layer 10a.
  • the passivation layer 10a In the design of the array substrate, in order to reduce the coupling capacitance between the common electrode 11a and the data line 9a, the passivation layer 10a needs to be made thicker. Therefore, in order to ensure the effectiveness of the via hole 20a, the hole depth of the via hole 20a is sufficient. Deep and large through hole size. However, the larger pore depth and size of the via holes 20a make the coating process of the subsequent preparation process difficult to control, and the coating film layer is easily corrugated, thereby affecting the yield of the array substrate.
  • an array substrate includes a base substrate, a gate metal layer, a gate insulating layer, an active layer, a source/drain metal layer, a passivation layer, and a common electrode layer sequentially formed on the base substrate, and a pixel electrode layer between the active layer and the source/drain metal layer or between the source/drain metal layer and the passivation layer; the gate metal layer includes a gate electrode and a common electrode line.
  • the pixel electrode layer or the source/drain metal layer includes a connection electrode electrically connected to the common electrode line through a first via hole in the gate insulating layer,
  • the connection electrode is electrically connected to a common electrode of the common electrode layer through a second via hole in the passivation layer.
  • connection electrode is in direct contact with the gate insulating layer and the passivation layer.
  • vertical projections of the first via and the second via on the substrate are offset from each other, and the first via corresponds to a position of the common electrode line, and the second via Corresponding to the position of the common electrode, a vertical projection of the first via hole and the second via hole on the substrate substrate falls within a range of vertical projection of the connection electrode on the substrate substrate Inside.
  • connection electrode is located in the pixel electrode layer, and the connection electrode and the pixel electrode of the pixel electrode layer are insulated from each other.
  • connection electrode is located in the source/drain metal layer, and the connection electrode and the source electrode, the drain electrode, and the data line of the source/drain metal layer are insulated from each other.
  • a display panel includes the array substrate as described above.
  • a display device includes a display panel as described above.
  • a method of fabricating an array substrate includes sequentially forming a gate metal layer, a gate insulating layer, an active layer, a source/drain metal layer, a passivation layer, and a common electrode layer on the base substrate, and the active layer and the source/drain metal layer A pixel electrode layer is formed between or between the source drain metal layer and the passivation layer, the gate metal layer including a gate electrode and a common electrode line.
  • the method further includes forming a connection electrode in the pixel electrode layer or the source/drain metal layer, forming a first via hole in the gate insulating layer, and forming a second via hole in the passivation layer, wherein the connection electrode passes through the gate insulating layer
  • the first via is electrically connected to the common electrode line
  • the connection electrode is electrically connected to the common electrode of the common electrode layer through the second via in the passivation layer.
  • the method for preparing the array substrate includes:
  • the gate metal layer including a gate electrode and a common electrode line
  • a pixel electrode layer including a pixel electrode and a connection electrode on the base substrate, the connection The electrode is electrically connected to the common electrode line through the first via hole;
  • a source/drain metal layer including a source electrode, a drain electrode, and a data line on the base substrate
  • the passivation layer including a second via corresponding to the connection electrode
  • a common electrode layer including a common electrode is formed on the base substrate, and the common electrode is electrically connected to the connection electrode through the second via hole.
  • the method for preparing the array substrate includes:
  • the gate metal layer including a gate electrode and a common electrode line
  • a source/drain metal layer including a source electrode, a drain electrode, a data line, and a connection electrode on the base substrate, the connection electrode being electrically connected to the common electrode line through the first via hole;
  • the passivation layer including a second via corresponding to the connection electrode
  • a common electrode layer including a common electrode is formed on the base substrate, and the common electrode is electrically connected to the connection electrode through the second via hole.
  • the method for preparing the array substrate includes:
  • the gate metal layer including a gate electrode and a common electrode line
  • a source/drain metal layer including a source electrode, a drain electrode, a data line, and a connection electrode on the base substrate, the connection electrode being electrically connected to the common electrode line through the first via hole;
  • the passivation layer including a second via corresponding to the connection electrode
  • a common electrode layer including a common electrode is formed on the base substrate, and the common electrode is electrically connected to the connection electrode through the second via hole.
  • the method for preparing the array substrate includes:
  • the gate metal layer including a gate electrode and a common electrode line
  • a gate insulating layer, an active layer, and a source/drain metal layer including a source electrode, a drain electrode, and a data line over the gate metal layer;
  • a pixel electrode layer including a pixel electrode and a connection electrode, wherein the connection electrode is electrically connected to the common electrode line through the first via hole;
  • the passivation layer including a second via corresponding to the connection electrode
  • a common electrode layer including a common electrode is formed on the base substrate, and the common electrode is electrically connected to the connection electrode through the second via hole.
  • connection electrode and the pixel electrode are insulated from each other.
  • connection electrode and the source electrode, the drain electrode, and the data line are insulated from each other.
  • vertical projections of the first via and the second via on the substrate are offset from each other, and vertical of the first via and the second via on the substrate The projection falls within a range of vertical projection of the connection electrode on the substrate.
  • FIG. 1 is a schematic structural view of a prior art HADS array substrate
  • FIG. 2 is a schematic structural diagram of a first array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a second array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a third array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a fourth array substrate according to an embodiment of the present invention.
  • Embodiments of the present invention provide an array substrate including a base substrate, a gate metal layer, a gate insulating layer, an active layer, a source/drain metal layer, a passivation layer, and a common electrode layer sequentially formed on the base substrate. And a pixel electrode layer between the active layer and the source/drain metal layer or between the source/drain metal layer and the passivation layer; the gate metal layer includes a gate electrode and a common electrode line;
  • the pixel electrode layer or the source/drain metal layer includes a connection electrode electrically connected to the common electrode line through the first via hole in the gate insulating layer, and the connection electrode passes through the second via hole in the passivation layer and the common electrode layer The common electrode is electrically connected.
  • connection electrode on the pixel electrode layer or the source/drain metal layer
  • the connection electrode is electrically connected to the common electrode line through the first via hole
  • the common electrode of the common electrode layer is electrically connected to the connection electrode through the second via hole and the connection electrode.
  • the connection electrode Since the first via and the second via are electrically connected through the connection electrode, the depth and size of the first via and the second via are continuous compared to the two layers directly penetrating the gate insulating layer and the passivation layer The hole depth and size of the via hole are reduced, and the influence of the coating film layer in the subsequent preparation process is reduced to avoid the occurrence of coating film layer corrugation.
  • connection electrode is in direct contact with the gate insulating layer and the passivation layer, and passes through the first via in the gate insulating layer and the second via in the passivation layer, respectively, and the common electrode line and the common
  • the electrodes are electrically connected.
  • the vertical projections of the first via holes and the second via holes on the substrate substrate are offset from each other, the first via holes correspond to the positions of the common electrode lines, and the second via holes correspond to the positions of the common electrodes, the first via holes and
  • the vertical projection of the second via on the substrate substrate falls within the range of the vertical projection of the connection electrode on the substrate. Since the vertical projections of the first via and the second via are not the same position, they do not affect each other.
  • connection electrode is located at the pixel electrode layer, and the connection electrode and the pixel electrode of the pixel electrode layer are insulated from each other.
  • connection electrode is located in the source/drain metal layer, and the source electrode, the drain electrode, and the data line of the connection electrode and the source/drain metal layer are insulated from each other.
  • an array substrate provided by an embodiment of the present invention includes a base substrate 1, a gate metal layer, a gate insulating layer 4, an active layer 5, a pixel electrode layer, and a source and drain electrode sequentially formed on the base substrate 1.
  • the gate metal layer includes a gate electrode 2 and a common electrode line 3
  • the pixel electrode layer includes a pixel electrode 6, and the source and drain metal layers include a source electrode 7, a drain electrode 8, and a data line 9.
  • the common electrode layer includes a common electrode 11, and the source electrode 7, the drain electrode 8, the gate electrode 2, and the active layer 5 constitute a Thin Film Transistor (TFT).
  • TFT Thin Film Transistor
  • the pixel electrode layer further includes a connection electrode 12 electrically connected to the common electrode line 3 through a first via 13 in the gate insulating layer, and the connection electrode 12 passes through the second via 14 and the common electrode layer in the passivation layer
  • the common electrode 11 is electrically connected.
  • the connection electrode 12 is disposed in the same layer as the pixel electrode 6.
  • connection electrode 12 is in direct contact with the gate insulating layer 4 and the passivation layer 10, and is disposed outside the regions of the active layer 5 and the pixel electrode 6.
  • the vertical projections (not shown) of the first via holes 13 and the second via holes 14 on the base substrate 1 are shifted from each other, the first via holes 13 correspond to the positions of the common electrode lines 3, and the second via holes 14 and the common electrodes Corresponding to the position of 11, the vertical projection (not shown) of the first via 13 and the second via 14 on the base substrate 1 falls on the vertical projection (not shown) of the connection electrode 12 on the base substrate 1.
  • FIG. 2 intuitively shows the positional relationship of the first via 13, the second via 14, and the connection electrode 12. Since the vertical projections of the first via 13 and the second via 14 are not in the same position, they do not affect each other.
  • connection electrode 12 and the pixel electrode 6 are insulated from each other.
  • connection electrode 12 in a pixel electrode layer, the connection electrode 12 is electrically connected to the common electrode line 3 through the first via hole 13, and the common electrode 11 of the common electrode layer passes through
  • the second via hole 14 is electrically connected to the connection electrode 12 to realize electrical connection between the common electrode 11 and the common electrode line 3. Since the first via hole 13 and the second via hole 14 are electrically connected by the connection electrode 12, the hole depth and the size of the first via hole 13 and the second via hole 14 are directly penetrated.
  • the continuous vias of the two layers of the gate insulating layer 4 and the passivation layer 10 (the vias 20 shown in FIG. 1) have a reduced hole depth and size, and are coated for the film layer in the subsequent preparation process. The effect is reduced, and the coating film layer corrugation is avoided, thereby improving the yield of the array substrate.
  • an array substrate provided by an embodiment of the present invention includes a base substrate 1, a gate metal layer, a gate insulating layer 4, an active layer 5, a pixel electrode layer, and a source and drain electrode sequentially formed on the base substrate 1.
  • Gold a gate layer, a passivation layer 10 and a common electrode layer; the gate metal layer includes a gate electrode 2 and a common electrode line 3, the pixel electrode layer includes a pixel electrode 6, and the source and drain metal layers include a source electrode 7, a drain electrode 8, and a data line 9.
  • the common electrode layer includes a common electrode 11, and the source electrode 7, the drain electrode 8, the gate electrode 2, and the active layer 5 constitute a TFT.
  • the source and drain metal layers further include a connection electrode 12 electrically connected to the common electrode line 3 through a first via 13 in the gate insulating layer, and the connection electrode 12 passes through the second via 14 in the passivation layer and the common The common electrode 11 of the electrode layer is electrically connected.
  • the connection electrode 12 is disposed in the same layer as the source electrode 7, the drain electrode 8, and the data line 9.
  • connection electrode 12 is in direct contact with the gate insulating layer 4 and the passivation layer 10, and is disposed outside the regions of the active layer 5 and the pixel electrode 6.
  • FIG. 3 intuitively shows the positional relationship of the first via 13, the second via 14, and the connection electrode 12. Since the vertical projections of the first via 13 and the second via 14 are not in the same position, they do not affect each other.
  • connection electrode 12 is insulated from the source electrode 7, the drain electrode 8, and the data line 9 from each other.
  • connection electrode 12 in a source/drain metal layer, the connection electrode 12 is electrically connected to the common electrode line 3 through the first via 13, and the common electrode 11 of the common electrode layer
  • the electrical connection between the common electrode 11 and the common electrode line 3 is achieved by the second via 14 being electrically connected to the connection electrode 12. Since the first via hole 13 and the second via hole 14 are electrically connected by the connection electrode 12, the hole depth and the size of the first via hole 13 and the second via hole 14 are directly penetrated.
  • the continuous vias of the two layers of the gate insulating layer 4 and the passivation layer 10 (the vias 20 shown in FIG. 1) have a reduced hole depth and size, and are coated for the film layer in the subsequent preparation process. The effect is reduced, and the coating film layer corrugation is avoided, thereby improving the yield of the array substrate.
  • an array substrate provided by an embodiment of the present invention includes a base substrate 1, a gate metal layer, a gate insulating layer 4, an active layer 5, a source/drain metal layer, and a pixel sequentially formed on the base substrate 1.
  • the gate metal layer includes a gate electrode 2 and a common electrode line 3,
  • the source and drain metal layers include a source electrode 7, a drain electrode 8, and a data line 9, and the pixel electrode layer includes a pixel electrode 6.
  • the common electrode layer includes a common electrode 11, and the source electrode 7, the drain electrode 8, the gate electrode 2, and the active layer 5 constitute a TFT.
  • the source and drain metal layers further include a connection electrode 12 electrically connected to the common electrode line 3 through a first via 13 in the gate insulating layer, and the connection electrode 12 passes through the second via 14 in the passivation layer and the common The common electrode 11 of the electrode layer is electrically connected.
  • the connection electrode 12 is disposed in the same layer as the source electrode 7, the drain electrode 8, and the data line 9.
  • connection electrode 12 is in direct contact with the gate insulating layer 4 and the passivation layer 10, and is disposed outside the regions of the active layer 5 and the pixel electrode 6.
  • FIG. 3 intuitively shows the positional relationship of the first via 13, the second via 14, and the connection electrode 12. Since the vertical projections of the first via 13 and the second via 14 are not in the same position, they do not affect each other.
  • connection electrode 12 is insulated from the source electrode 7, the drain electrode 8, and the data line 9 from each other.
  • connection electrode 12 in a source/drain metal layer, the connection electrode 12 is electrically connected to the common electrode line 3 through the first via hole 13, and the common electrode 11 of the common electrode layer
  • the electrical connection between the common electrode 11 and the common electrode line 3 is achieved by the second via 14 being electrically connected to the connection electrode 12. Since the first via hole 13 and the second via hole 14 are electrically connected by the connection electrode 12, the hole depth and the size of the first via hole 13 and the second via hole 14 are directly penetrated.
  • the continuous vias of the two layers of the gate insulating layer 4 and the passivation layer 10 (the vias 20 shown in FIG. 1) have a reduced hole depth and size, and are coated for the film layer in the subsequent preparation process. The effect is reduced, and the coating film layer corrugation is avoided, thereby improving the yield of the array substrate.
  • an array substrate provided by an embodiment of the present invention includes a base substrate 1, a gate metal layer, a gate insulating layer 4, an active layer 5, a source/drain metal layer, and a pixel sequentially formed on the base substrate 1.
  • the gate metal layer includes a gate electrode 2 and a common electrode line 3,
  • the source and drain metal layers include a source electrode 7, a drain electrode 8, and a data line 9, and the pixel electrode layer includes a pixel electrode 6.
  • the common electrode layer includes a common electrode 11, and the source electrode 7, the drain electrode 8, the gate electrode 2, and the active layer 5 constitute a Thin Film Transistor (TFT).
  • TFT Thin Film Transistor
  • the pixel electrode layer further includes a connection electrode 12 electrically connected to the common electrode line 3 through a first via 13 in the gate insulating layer, and the connection electrode 12 passes through the second via 14 and the common electrode layer in the passivation layer
  • the common electrode 11 is electrically connected.
  • the connection electrode 12 is disposed in the same layer as the pixel electrode 6.
  • connection electrode 12 is in direct contact with the gate insulating layer 4 and the passivation layer 10, and is disposed outside the regions of the active layer 5 and the pixel electrode 6.
  • the vertical projections (not shown) of the first via holes 13 and the second via holes 14 on the base substrate 1 are shifted from each other, the first via holes 13 correspond to the positions of the common electrode lines 3, and the second via holes 14 and the common electrodes Corresponding to the position of 11, the vertical projection (not shown) of the first via 13 and the second via 14 on the base substrate 1 falls on the vertical projection (not shown) of the connection electrode 12 on the base substrate 1.
  • the positional relationship of the first via 13, the second via 14, and the connection electrode 12 is visually shown in FIG. Since the vertical projections of the first via 13 and the second via 14 are not in the same position, they do not affect each other.
  • connection electrode 12 and the pixel electrode 6 are insulated from each other.
  • connection electrode 12 in a pixel electrode layer, the connection electrode 12 is electrically connected to the common electrode line 3 through the first via hole 13, and the common electrode 11 of the common electrode layer passes through
  • the second via hole 14 is electrically connected to the connection electrode 12 to realize electrical connection between the common electrode 11 and the common electrode line 3. Since the first via hole 13 and the second via hole 14 are electrically connected by the connection electrode 12, the hole depth and the size of the first via hole 13 and the second via hole 14 are directly penetrated.
  • the continuous vias of the two layers of the gate insulating layer 4 and the passivation layer 10 (the vias 20 shown in FIG. 1) have a reduced hole depth and size, and are coated for the film layer in the subsequent preparation process. The effect is reduced, and the coating film layer corrugation is avoided, thereby improving the yield of the array substrate.
  • the embodiment of the invention further provides a display panel comprising the array substrate of the above embodiment.
  • the display panel of the embodiment of the present invention may further include a color film substrate, a liquid crystal, other common accessories, and the like, and details are not described herein again.
  • the pixel electrode layer or the source/drain metal layer is provided with a connection electrode
  • the connection electrode is electrically connected to the common electrode line through the first via hole
  • the common electrode is electrically connected to the connection electrode through the second via hole and the connection electrode Connected to achieve electrical connection between the common electrode and the common electrode line. Since the first via and the second via are respectively disposed in different layers and are electrically connected through the connection electrodes, the hole depth and the size are compared to the holes of the continuous via which directly penetrate the two layers of the gate insulating layer and the passivation layer Deep and size reduction Small, the influence of the coating film layer in the subsequent preparation process is reduced, and the coating film layer corrugation is avoided, thereby improving the yield of the array substrate.
  • the embodiment of the invention further provides a display device comprising the display panel of the above embodiment.
  • the display device according to the embodiment of the present invention may further include a backlight module, a frame, a base, and the like, and details are not described herein.
  • a connection electrode is disposed between the gate insulating layer and the passivation layer of the array substrate, the connection electrode is electrically connected to the common electrode line through the first via hole, and the common electrode passes through the second via hole Electrical connection with the connection electrode to achieve electrical connection between the common electrode and the common electrode line. Since the first via and the second via are respectively disposed in different layers and are electrically connected through the connection electrodes, the hole depth and the size are compared to the holes of the continuous via which directly penetrate the two layers of the gate insulating layer and the passivation layer The depth and size are reduced, and the influence of the coating film layer in the subsequent preparation process is reduced, and the coating film layer corrugation is avoided, thereby improving the yield of the array substrate.
  • the embodiment of the invention further provides a method for preparing an array substrate, which comprises sequentially forming a gate metal layer, a gate insulating layer, an active layer, a source/drain metal layer, a passivation layer and a common electrode on the substrate. And forming a pixel electrode layer between the active layer and the source/drain metal layer or between the source/drain metal layer and the passivation layer, wherein the gate metal layer includes a gate electrode and a common electrode line.
  • the method includes forming a connection electrode in the pixel electrode layer or the source/drain metal layer, forming a first via hole in the gate insulating layer, and forming a second via hole in the passivation layer, wherein the connection electrode passes through the gate electrode
  • the first via in the insulating layer is electrically connected to the common electrode line
  • the connection electrode is electrically connected to the common electrode of the common electrode layer through the second via in the passivation layer.
  • the method for preparing an array substrate includes the following steps:
  • a gate metal layer is sequentially formed on the base substrate, and the gate metal layer includes a gate electrode and a common electrode line.
  • a pixel electrode layer including a pixel electrode and a connection electrode on the base substrate that completes the above steps, and the connection electrode is electrically connected to the common electrode line through the first via hole.
  • connection electrode and the pixel electrode are insulated from each other.
  • Source drain metal layer forming a source electrode, a drain electrode, and a data line on the base substrate that completes the above steps Source drain metal layer.
  • the vertical projections of the second via and the first via on the substrate are offset from one another and fall within the vertical projection of the connection electrode on the substrate.
  • the structure of the array substrate prepared from step 601 to step 607 is as shown in FIG. 2.
  • connection electrode in the pixel electrode layer, the connection electrode is electrically connected to the common electrode line through the first via hole, and the common electrode of the common electrode layer passes through the second via hole and The connection electrode is electrically connected to realize electrical connection between the common electrode and the common electrode line. Since the first via hole and the second via hole are electrically connected through the connection electrode, the hole depth and the size of the first via hole and the second via hole are opposite.
  • connection electrode is formed in the same layer as the pixel electrode and formed simultaneously, thereby reducing the preparation process and material consumption.
  • the method for preparing an array substrate includes the following steps:
  • a gate metal layer is sequentially formed on the base substrate, and the gate metal layer includes a gate electrode and a common electrode line.
  • connection electrode is insulated from the source electrode, the drain electrode, and the data line.
  • the vertical projections of the second via and the first via on the substrate are offset from one another and fall within the vertical projection of the connection electrode on the substrate.
  • connection electrode in the source/drain metal layer, the connection electrode is electrically connected to the common electrode line through the first via hole, and the common electrode of the common electrode layer passes through the second pass.
  • the hole is electrically connected to the connection electrode to realize electrical connection between the common electrode and the common electrode line.
  • the depth and size of the first via and the second via are continuous compared to the two layers directly penetrating the gate insulating layer and the passivation layer
  • the hole depth and size of the via hole are reduced, and the influence of the coating film layer in the subsequent preparation process is reduced, thereby avoiding the coating film layer corrugation, thereby improving the yield of the array substrate; further, connecting the electrode and the source electrode, and leakage
  • the pole and the data line are formed in the same layer and simultaneously, reducing the preparation process and material consumption.
  • the structure of the array substrate prepared by steps 701 to 707 is as shown in FIG.
  • the method for preparing an array substrate includes the following steps:
  • a gate metal layer is sequentially formed on the base substrate, and the gate metal layer includes a gate electrode and a common electrode line.
  • a source/drain metal layer including a source electrode, a drain electrode, a data line, and a connection electrode on the base substrate that completes the above steps, and the connection electrode is electrically connected to the common electrode line through the first via hole.
  • connection electrode is insulated from the source electrode, the drain electrode, and the data line.
  • the vertical projections of the second via and the first via on the substrate are offset from one another and fall within the vertical projection of the connection electrode on the substrate.
  • connection electrode in the source/drain metal layer, the connection electrode is electrically connected to the common electrode line through the first via hole, and the common electrode of the common electrode layer passes through the second pass.
  • the hole is electrically connected to the connection electrode to realize the electricity of the common electrode and the common electrode line connection.
  • the depth and size of the first via and the second via are continuous compared to the two layers directly penetrating the gate insulating layer and the passivation layer
  • the hole depth and size of the via hole are reduced, and the influence of the coating film layer in the subsequent preparation process is reduced, thereby avoiding the coating film layer corrugation, thereby improving the yield of the array substrate; further, connecting the electrode and the source electrode, and leakage
  • the pole and the data line are formed in the same layer and simultaneously, reducing the preparation process and material consumption.
  • the structure of the array substrate prepared by steps 801 to 806 is as shown in FIG.
  • the method for preparing an array substrate includes the following steps:
  • a gate metal layer is sequentially formed on the base substrate, and the gate metal layer includes a gate electrode and a common electrode line.
  • the position of the first via corresponds to the position of the common electrode line.
  • a pixel electrode layer including a pixel electrode and a connection electrode on the base substrate that completes the above steps, and the connection electrode is electrically connected to the common electrode line through the first via hole.
  • connection electrode and the pixel electrode are insulated from each other.
  • the vertical projections of the second via and the first via on the substrate are offset from one another and fall within the vertical projection of the connection electrode on the substrate.
  • connection electrode in the pixel electrode layer
  • the connection electrode is electrically connected to the common electrode line through the first via hole
  • the common electrode of the common electrode layer passes through the second via hole and
  • the connection electrodes are electrically connected to realize electrical connection between the common electrode and the common electrode line. Since the first via hole and the second via hole are electrically connected through the connection electrode, the hole depth and size of the first via hole and the second via hole are compared to directly penetrating through the two layers of the gate insulating layer and the passivation layer.
  • the hole depth and size of the continuous via are reduced, and the influence of the coating film layer in the subsequent preparation process is reduced, thereby avoiding the coating film layer corrugation, thereby improving the yield of the array substrate; further, the connecting electrode is the same as the pixel electrode Layers are formed simultaneously, reducing manufacturing processes and material consumption.
  • the structure of the array substrate prepared by steps 901 to 906 is as shown in FIG.
  • the gate insulating layer and the first via hole therein, the passivation layer and the second via hole thereof may be coated, etched, etc.
  • the gate metal layer and the source/drain metal layer may be formed by sputtering, etching, or the like.
  • the active layer, the pixel electrode layer, and the common electrode layer may be coated, etched, or the like, and will not be described herein.

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Abstract

一种阵列基板及其制备方法、显示面板和显示装置。阵列基板包括衬底基板（1），依次形成于衬底基板上的栅极金属层（2、3）、栅极绝缘（4）、有源层（5）、源漏极金属层（7、8）、钝化层（10）和公共电极层（11），及位于有源层和源漏极金属层之间或者源漏极金属层和钝化层之间的像素电极层（6）；栅极金属层包括栅电极（2）和公共电极线（3）；像素电极层或源漏极金属层包括连接电极（12），连接电极通过栅极绝缘层上的第一过孔（13）与公共电极线电连接，连接电极通过钝化层上的第二过孔（14）与公共电极层的公共电极（11）电连接。

Description

阵列基板及其制备方法、显示面板和显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制备方法、显示面板和显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)由于具有体积小、功耗低、无辐射等优点，是较为理想的显示设备。近年来，TFT-LCD在显示领域的应用范围逐步扩大，相关的技术也发展迅速。其中，高开口率高级超维场开关(High aperture ratio Advanced-Super Dimensional Switching，HADS)模式的显示器由于具有宽的视角和低的色偏等诸多优点，已广泛应用在各种显示产品中。
如图1所示，现有技术的HADS技术的阵列基板包括衬底基板1a、栅电极2a、公共电极线3a、栅极绝缘层4a、有源层5a、像素电极6a、漏电极8a、源电极7a、数据线9a、钝化层10a、公共电极11a。其中，公共电极11a经过孔20a与公共电极线3a电连接。由图1可知，过孔20a是贯穿栅极绝缘层4a和钝化层10a的过孔。在阵列基板设计时，为了减少公共电极11a和数据线9a之间的耦合电容，钝化层10a需要做得比较厚，因此，为了保证过孔20a的有效性，过孔20a的孔深要足够深且过孔尺寸较大。但是，过孔20a的较大的孔深和尺寸使后续制备过程的涂布工艺很难控制，容易使涂布膜层形成波纹，从而影响制备阵列基板的良率。
发明内容
根据本发明的实施例，提供一种阵列基板。该阵列基板包括衬底基板，依次形成于所述衬底基板上的栅极金属层、栅极绝缘层、有源层、源漏极金属层、钝化层和公共电极层，及位于所述有源层和所述源漏极金属层之间或者所述源漏极金属层和所述钝化层之间的像素电极层；所述栅极金属层包括栅电极和公共电极线。所述像素电极层或所述源漏极金属层包括连接电极，所述连接电极通过所述栅极绝缘层中的第一过孔与所述公共电极线电连接， 所述连接电极通过所述钝化层中的第二过孔与所述公共电极层的公共电极电连接。
例如，所述连接电极与所述栅极绝缘层和所述钝化层直接接触。
例如，所述第一过孔和所述第二过孔在所述衬底基板上的垂直投影相互错开，所述第一过孔与所述公共电极线的位置对应，所述第二过孔与所述公共电极的位置对应，所述第一过孔和所述第二过孔在所述衬底基板上的垂直投影落于所述连接电极在所述衬底基板上的垂直投影的范围内。
例如，所述连接电极位于所述像素电极层，所述连接电极与所述像素电极层的像素电极彼此绝缘。
例如，所述连接电极位于所述源漏极金属层，所述连接电极与所述源漏极金属层的源电极、漏电极和数据线彼此绝缘。
根据本发明的实施例，提供一种显示面板。该显示面板包括如上所述的阵列基板。
根据本发明的实施例，提供一种显示装置。该显示装置包括如上所述的显示面板。
根据本发明的实施例，提供一种阵列基板的制备方法。该方法包括：在衬底基板上依次形成栅极金属层、栅极绝缘层、有源层、源漏极金属层、钝化层和公共电极层，并在有源层和源漏极金属层之间或者源漏极金属层和钝化层之间形成像素电极层，所述栅极金属层包括栅电极和公共电极线。该方法还包括在像素电极层或源漏极金属层中形成连接电极，在栅极绝缘层中形成第一过孔，在钝化层中形成第二过孔，其中连接电极通过栅极绝缘层中的第一过孔与公共电极线电连接，连接电极通过钝化层中的第二过孔与公共电极层的公共电极电连接。
例如，所述阵列基板的制备方法包括：
在衬底基板上依次形成栅极金属层，所述栅极金属层包括栅电极和公共电极线；
在所述栅极金属层之上依次形成所述栅极绝缘层和有源层；
在所述栅极绝缘层的、所述有源层之外的区域中形成第一过孔，所述第一过孔的位置与所述公共电极线的位置对应；
在所述衬底基板上形成包括像素电极和连接电极的像素电极层，所述连 接电极通过所述第一过孔与所述公共电极线电连接；
在所述衬底基板上形成包括源电极、漏电极和数据线的源漏极金属层；
在所述衬底基板上形成钝化层，所述钝化层包括与所述连接电极相对应的第二过孔；
在所述衬底基板上形成包括公共电极的公共电极层，所述公共电极通过所述第二过孔与所述连接电极电连接。
例如，所述阵列基板的制备方法包括：
在衬底基板上依次形成栅极金属层，所述栅极金属层包括栅电极和公共电极线；
在所述栅极金属层之上形成所述栅极绝缘层和有源层；
在所述栅极绝缘层的、所述有源层之外的区域中形成第一过孔，所述第一过孔的位置与所述公共电极线的位置对应；
在所述衬底基板上形成包括源电极、漏电极、数据线和连接电极的源漏极金属层，所述连接电极通过所述第一过孔与所述公共电极线电连接；
在所述衬底基板形成包括像素电极的像素电极层；
在所述衬底基板上形成钝化层，所述钝化层包括与所述连接电极相对应的第二过孔；
在所述衬底基板上形成包括公共电极的公共电极层，所述公共电极通过所述第二过孔与所述连接电极电连接。
例如，所述阵列基板的制备方法包括：
在衬底基板上依次形成栅极金属层，所述栅极金属层包括栅电极和公共电极线；
在所述栅极金属层之上形成所述栅极绝缘层、有源层及包括像素电极的像素电极层；
在所述栅极绝缘层的、所述有源层和所述像素电极之外的区域中形成第一过孔，所述第一过孔的位置与所述公共电极线的位置对应；
在所述衬底基板上形成包括源电极、漏电极、数据线和连接电极的源漏极金属层，所述连接电极通过所述第一过孔与所述公共电极线电连接；
在所述衬底基板上形成钝化层，所述钝化层包括与所述连接电极相对应的第二过孔；
在所述衬底基板上形成包括公共电极的公共电极层，所述公共电极通过所述第二过孔与所述连接电极电连接。
例如，所述阵列基板的制备方法包括：
在衬底基板上依次形成栅极金属层，所述栅极金属层包括栅电极和公共电极线；
在所述栅极金属层之上形成栅极绝缘层、有源层及包括源电极、漏电极和数据线的源漏极金属层；
在所述栅极绝缘层的、所述有源层和所述数据线之外的区域中形成第一过孔，所述第一过孔的位置与所述公共电极线的位置对应；
在所述衬底基板上形成包括像素电极和连接电极的像素电极层，所述连接电极通过所述第一过孔与所述公共电极线电连接；
在所述衬底基板上形成钝化层，所述钝化层包括与所述连接电极相对应的第二过孔；
在所述衬底基板上形成包括公共电极的公共电极层，所述公共电极通过所述第二过孔与所述连接电极电连接。
例如，所述连接电极和所述像素电极彼此绝缘。
例如，所述连接电极与所述源电极、所述漏电极和所述数据线彼此绝缘。
例如，所述第一过孔和所述第二过孔在所述衬底基板上的垂直投影相互错开，所述第一过孔和所述第二过孔在所述衬底基板上的垂直投影落于所述连接电极在所述衬底基板上的垂直投影的范围内。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为现有技术HADS阵列基板的结构示意图；
图2为本发明实施例提供的第一种阵列基板的结构示意图；
图3为本发明实施例提供的第二种阵列基板的结构示意图；
图4为本发明实施例提供的第三种阵列基板的结构示意图；
图5为本发明实施例提供的第四种阵列基板的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种阵列基板，包括衬底基板，依次形成于衬底基板上的栅极金属层、栅极绝缘层、有源层、源漏极金属层、钝化层和公共电极层，及位于有源层和源漏极金属层之间或者源漏极金属层和钝化层之间的像素电极层；栅极金属层包括栅电极和公共电极线；
像素电极层或源漏极金属层包括连接电极，连接电极通过栅极绝缘层中的第一过孔与公共电极线电连接，连接电极通过钝化层中的第二过孔与公共电极层的公共电极电连接。
本发明实施例中，通过在像素电极层或源漏极金属层设置连接电极，连接电极通过第一过孔与公共电极线电连接，公共电极层的公共电极通过第二过孔与连接电极电连接，实现公共电极与公共电极线的电连接。由于第一过孔和第二过孔通过连接电极实现电连接，因此第一过孔和第二过孔的孔深和尺寸相比于直接贯穿栅极绝缘层和钝化层这两层的连续过孔的孔深和尺寸减小，对后续制备过程中涂布膜层的影响减小，避免产生涂布膜层波纹。
本实施例中，连接电极与栅极绝缘层和钝化层是直接接触，并通过栅极绝缘层中的第一过孔和钝化层中的第二过孔，分别与公共电极线和公共电极实现电连接。例如，第一过孔和第二过孔在衬底基板上的垂直投影相互错开，第一过孔与公共电极线的位置对应，第二过孔与公共电极的位置对应，第一过孔和第二过孔在衬底基板上的垂直投影落于连接电极在衬底基板上的垂直投影的范围内。由于第一过孔和第二过孔的垂直投影非同一位置，彼此互不影响。
例如，连接电极位于像素电极层，连接电极与像素电极层的像素电极彼此绝缘。或者，连接电极位于源漏极金属层，连接电极与源漏极金属层的源电极、漏电极和数据线彼此绝缘。
下面，将参考附图对根据本发明实施例的阵列基板进行更加详细的说明。
参见图2，本发明实施例提供的阵列基板包括衬底基板1，依次形成于衬底基板1上的栅极金属层、栅极绝缘层4、有源层5、像素电极层、源漏极金属层、钝化层10和公共电极层；栅极金属层包括栅电极2和公共电极线3，像素电极层包括像素电极6，源漏极金属层包括源电极7、漏电极8和数据线9，公共电极层包括公共电极11，源电极7、漏电极8、栅电极2和有源层5构成薄膜晶体管(Thin Film Transistor，TFT)。
像素电极层还包括连接电极12，连接电极12通过栅极绝缘层中的第一过孔13与公共电极线3电连接，连接电极12通过钝化层中的第二过孔14与公共电极层的公共电极11电连接。本实施例中，连接电极12与像素电极6同层设置。
根据图2，连接电极12与栅极绝缘层4和钝化层10直接接触，设置于有源层5和像素电极6区域之外。
第一过孔13和第二过孔14在衬底基板1上的垂直投影(未示出)相互错开，第一过孔13与公共电极线3的位置对应，第二过孔14与公共电极11的位置对应，第一过孔13和第二过孔14在衬底基板1上的垂直投影(未示出)落于连接电极12在衬底基板1上的垂直投影(未示出)的范围内，虽然本实施例中未示出各上述的各投影，但是图2直观的示出了第一过孔13、第二过孔14和连接电极12的位置关系。由于第一过孔13和第二过孔14的垂直投影非同一位置，彼此互不影响。
连接电极12与像素电极6彼此绝缘。
在图2中，通过在像素电极层中设置连接电极12，所述连接电极12通过所述第一过孔13与所述公共电极线3电连接，所述公共电极层的公共电极11通过所述第二过孔14与所述连接电极12电连接，实现所述公共电极11与所述公共电极线3的电连接。由于所述第一过孔13和所述第二过孔14通过连接电极12实现电连接，因此所述第一过孔13和所述第二过孔14的孔深和尺寸相比于直接贯穿所述栅极绝缘层4和所述钝化层10这两层的连续过孔(如图1所示的过孔20)的孔深和尺寸减小，对后续制备过程中涂布膜层的影响减小，避免产生涂布膜层波纹，从而提高阵列基板的良率。
参见图3，本发明实施例提供的阵列基板包括衬底基板1，依次形成于衬底基板1上的栅极金属层、栅极绝缘层4、有源层5、像素电极层、源漏极金 属层、钝化层10和公共电极层；栅极金属层包括栅电极2和公共电极线3，像素电极层包括像素电极6，源漏极金属层包括源电极7、漏电极8和数据线9，公共电极层包括公共电极11，源电极7、漏电极8、栅电极2和有源层5构成TFT。
源漏极金属层还包括连接电极12，连接电极12通过栅极绝缘层中的第一过孔13与公共电极线3电连接，连接电极12通过钝化层中的第二过孔14与公共电极层的公共电极11电连接。本实施例中，连接电极12与源电极7、漏电极8和数据线9同层设置。
根据图3，连接电极12与栅极绝缘层4和钝化层10直接接触，设置于有源层5和像素电极6区域之外。
第一过孔13和第二过孔14在衬底基板1上的垂直投影(未示出)相互错开，第一过孔13与公共电极线3的位置对应，第二过孔14与公共电极11的位置对应，第一过孔13和第二过孔14在衬底基板1上的垂直投影(未示出)落于连接电极12在衬底基板1上的垂直投影(未示出)的范围内，虽然本实施例中未示出各上述的各投影，但是图3直观的示出了第一过孔13、第二过孔14和连接电极12的位置关系。由于第一过孔13和第二过孔14的垂直投影非同一位置，彼此互不影响。
连接电极12与源电极7、漏电极8和数据线9彼此绝缘。
在图3中，通过在源漏极金属层中设置连接电极12，所述连接电极12通过所述第一过孔13与所述公共电极线3电连接，所述公共电极层的公共电极11通过所述第二过孔14与所述连接电极12电连接，实现所述公共电极11与所述公共电极线3的电连接。由于所述第一过孔13和所述第二过孔14通过连接电极12实现电连接，因此所述第一过孔13和所述第二过孔14的孔深和尺寸相比于直接贯穿所述栅极绝缘层4和所述钝化层10这两层的连续过孔(如图1所示的过孔20)的孔深和尺寸减小，对后续制备过程中涂布膜层的影响减小，避免产生涂布膜层波纹，从而提高阵列基板的良率。
参见图4，本发明实施例提供的阵列基板包括衬底基板1，依次形成于衬底基板1上的栅极金属层、栅极绝缘层4、有源层5、源漏极金属层、像素电极层、钝化层10和公共电极层；栅极金属层包括栅电极2和公共电极线3，源漏极金属层包括源电极7、漏电极8和数据线9，像素电极层包括像素电极 6，公共电极层包括公共电极11，源电极7、漏电极8、栅电极2和有源层5构成TFT。
源漏极金属层还包括连接电极12，连接电极12通过栅极绝缘层中的第一过孔13与公共电极线3电连接，连接电极12通过钝化层中的第二过孔14与公共电极层的公共电极11电连接。本实施例中，连接电极12与源电极7、漏电极8和数据线9同层设置。
根据图4，连接电极12与栅极绝缘层4和钝化层10直接接触，设置于有源层5和像素电极6区域之外。
第一过孔13和第二过孔14在衬底基板1上的垂直投影(未示出)相互错开，第一过孔13与公共电极线3的位置对应，第二过孔14与公共电极11的位置对应，第一过孔13和第二过孔14在衬底基板1上的垂直投影(未示出)落于连接电极12在衬底基板1上的垂直投影(未示出)的范围内，虽然本实施例中未示出各上述的各投影，但是图3直观的示出了第一过孔13、第二过孔14和连接电极12的位置关系。由于第一过孔13和第二过孔14的垂直投影非同一位置，彼此互不影响。
连接电极12与源电极7、漏电极8和数据线9彼此绝缘。
在图4中，通过在源漏极金属层中设置连接电极12，所述连接电极12通过所述第一过孔13与所述公共电极线3电连接，所述公共电极层的公共电极11通过所述第二过孔14与所述连接电极12电连接，实现所述公共电极11与所述公共电极线3的电连接。由于所述第一过孔13和所述第二过孔14通过连接电极12实现电连接，因此所述第一过孔13和所述第二过孔14的孔深和尺寸相比于直接贯穿所述栅极绝缘层4和所述钝化层10这两层的连续过孔(如图1所示的过孔20)的孔深和尺寸减小，对后续制备过程中涂布膜层的影响减小，避免产生涂布膜层波纹，从而提高阵列基板的良率。
参见图5，本发明实施例提供的阵列基板包括衬底基板1，依次形成于衬底基板1上的栅极金属层、栅极绝缘层4、有源层5、源漏极金属层、像素电极层、钝化层10和公共电极层；栅极金属层包括栅电极2和公共电极线3，源漏极金属层包括源电极7、漏电极8和数据线9，像素电极层包括像素电极6，公共电极层包括公共电极11，源电极7、漏电极8、栅电极2和有源层5构成薄膜晶体管(Thin Film Transistor，TFT)。
像素电极层还包括连接电极12，连接电极12通过栅极绝缘层中的第一过孔13与公共电极线3电连接，连接电极12通过钝化层中的第二过孔14与公共电极层的公共电极11电连接。本实施例中，连接电极12与像素电极6同层设置。
根据图5，连接电极12与栅极绝缘层4和钝化层10直接接触，设置于有源层5和像素电极6区域之外。
第一过孔13和第二过孔14在衬底基板1上的垂直投影(未示出)相互错开，第一过孔13与公共电极线3的位置对应，第二过孔14与公共电极11的位置对应，第一过孔13和第二过孔14在衬底基板1上的垂直投影(未示出)落于连接电极12在衬底基板1上的垂直投影(未示出)的范围内，虽然本实施例中未示出各上述的各投影，但是图2直观的示出的第一过孔13、第二过孔14和连接电极12的位置关系。由于第一过孔13和第二过孔14的垂直投影非同一位置，彼此互不影响。
连接电极12与像素电极6彼此绝缘。
在图5中，通过在像素电极层中设置连接电极12，所述连接电极12通过所述第一过孔13与所述公共电极线3电连接，所述公共电极层的公共电极11通过所述第二过孔14与所述连接电极12电连接，实现所述公共电极11与所述公共电极线3的电连接。由于所述第一过孔13和所述第二过孔14通过连接电极12实现电连接，因此所述第一过孔13和所述第二过孔14的孔深和尺寸相比于直接贯穿所述栅极绝缘层4和所述钝化层10这两层的连续过孔(如图1所示的过孔20)的孔深和尺寸减小，对后续制备过程中涂布膜层的影响减小，避免产生涂布膜层波纹，从而提高阵列基板的良率。
本发明实施例还提供一种显示面板，包括如上实施例的阵列基板。当然，本发明实施例的显示面板还可以包括彩膜基板、液晶、其他常用配件等，在此不再赘述。
在根据本发明实施例的显示面板中：像素电极层或源漏极金属层设置有连接电极，连接电极通过第一过孔与公共电极线电连接，公共电极通过第二过孔与连接电极电连接，实现公共电极与公共电极线的电连接。由于第一过孔和第二过孔分别设置于不同层且通过连接电极实现电连接，因此孔深和尺寸相比于直接贯穿栅极绝缘层和钝化层这两层的连续过孔的孔深和尺寸减 小，对后续制备过程中涂布膜层的影响减小，避免产生涂布膜层波纹，从而提高阵列基板的良率。
本发明实施例还提供一种显示装置，包括如上实施例的显示面板。根据本发明实施例的显示装置还可以包括背光模组、边框和底座等，在此不再赘述。
在根据本发明实施例的显示装置中，阵列基板的栅极绝缘层和钝化层之间设置有连接电极，连接电极通过第一过孔与公共电极线电连接，公共电极通过第二过孔与连接电极电连接，实现公共电极与公共电极线的电连接。由于第一过孔和第二过孔分别设置于不同层且通过连接电极实现电连接，因此孔深和尺寸相比于直接贯穿栅极绝缘层和钝化层这两层的连续过孔的孔深和尺寸减小，对后续制备过程中涂布膜层的影响减小，避免产生涂布膜层波纹，从而提高阵列基板的良率。
本发明实施例还提供一种阵列基板的制备方法，该方法包括在衬底基板上依次形成栅极金属层、栅极绝缘层、有源层、源漏极金属层、钝化层和公共电极层，并在有源层和源漏极金属层之间或者源漏极金属层和钝化层之间形成像素电极层，其中栅极金属层包括栅电极和公共电极线。
进一步地，该方法包括在像素电极层或源漏极金属层中形成连接电极，在栅极绝缘层中形成第一过孔，在钝化层中形成第二过孔，其中连接电极通过栅极绝缘层中的第一过孔与公共电极线电连接，连接电极通过钝化层中的第二过孔与公共电极层的公共电极电连接。
例如，本发明实施例提供的阵列基板的制备方法包括以下步骤：
601，在衬底基板上依次形成栅极金属层，栅极金属层包括栅电极和公共电极线。
602，在栅极金属层之上形成栅极绝缘层和有源层。
603，在栅极绝缘层的、有源层之外的区域中形成第一过孔，第一过孔的位置与公共电极线的位置对应。
604，在完成上述步骤的衬底基板上形成包括像素电极和连接电极的像素电极层，连接电极通过第一过孔与公共电极线电连接。
连接电极和像素电极彼此绝缘。
605，在完成上述步骤的衬底基板上形成包括源电极、漏电极和数据线的 源漏极金属层。
606，在完成上述步骤的衬底基板上形成钝化层，钝化层包括与连接电极相对应的第二过孔。
第二过孔和第一过孔在衬底基板上的垂直投影相互错开、且落于连接电极在衬底基板上的垂直投影的范围内。
607，在完成上述步骤的衬底基板上形成包括公共电极的公共电极层，公共电极通过第二过孔与连接电极电连接。
由步骤601至步骤607制备的阵列基板的结构如图2所示。
在根据本发明实施例的阵列基板的制备方法中，通过在像素电极层中设置连接电极，连接电极通过第一过孔与公共电极线电连接，公共电极层的公共电极通过第二过孔与连接电极电连接，实现公共电极与公共电极线的电连接，由于第一过孔和第二过孔是通过连接电极实现电连接，因此第一过孔和第二过孔的孔深和尺寸相比于直接贯穿栅极绝缘层和钝化层这两层的连续过孔的孔深和尺寸减小，对后续制备过程中涂布膜层的影响减小，避免产生涂布膜层波纹，从而提高阵列基板的良率；进一步的，连接电极与像素电极同层且同步形成，减少制备工序和材料消耗。
例如，本发明实施例提供的阵列基板的制备方法包括以下步骤：
701，在衬底基板上依次形成栅极金属层，栅极金属层包括栅电极和公共电极线。
702，在栅极金属层之上形成栅极绝缘层和有源层。
703，在栅极绝缘层的、有源层之外的区域中形成第一过孔，第一过孔的位置与公共电极线的位置对应。
704，在完成上述步骤的衬底基板上形成包括源电极、漏电极、数据线和连接电极的源漏极金属层，连接电极通过第一过孔与公共电极线电连接。
连接电极与源电极、漏电极和数据线彼此绝缘。
705，在完成上述步骤的衬底基板形成包括像素电极的像素电极层。
706，在完成上述步骤的衬底基板上形成钝化层，钝化层包括与连接电极相对应的第二过孔。
第二过孔和第一过孔在衬底基板上的垂直投影相互错开、且落于连接电极在衬底基板上的垂直投影的范围内。
707，在完成上述步骤的衬底基板上形成包括公共电极的公共电极层，公共电极通过第二过孔与连接电极电连接。
在根据本发明实施例的阵列基板的制备方法中，通过在源漏极金属层中设置连接电极，连接电极通过第一过孔与公共电极线电连接，公共电极层的公共电极通过第二过孔与连接电极电连接，实现公共电极与公共电极线的电连接。由于第一过孔和第二过孔通过连接电极实现电连接，因此第一过孔和第二过孔的孔深和尺寸相比于直接贯穿栅极绝缘层和钝化层这两层的连续过孔的孔深和尺寸减小，对后续制备过程中涂布膜层的影响减小，避免产生涂布膜层波纹，从而提高阵列基板的良率；进一步的，连接电极与源电极、漏电极和数据线同层且同步形成，减少制备工序和材料消耗。
由步骤701至步骤707制备的阵列基板的结构如图4所示。
例如，本发明实施例提供的阵列基板的制备方法包括以下步骤：
801，在衬底基板上依次形成栅极金属层，栅极金属层包括栅电极和公共电极线。
802，在栅极金属层之上形成栅极绝缘层、有源层及包括像素电极的像素电极层。
803，在栅极绝缘层的、有源层和像素电极之外的区域中形成第一过孔，第一过孔的位置与公共电极线的位置对应。
804，在完成上述步骤的衬底基板上形成包括源电极、漏电极、数据线和连接电极的源漏极金属层，连接电极通过第一过孔与公共电极线电连接。
连接电极与源电极、漏电极和数据线彼此绝缘。
805，在完成上述步骤的衬底基板上形成钝化层，钝化层包括与连接电极相对应的第二过孔。
第二过孔和第一过孔在衬底基板上的垂直投影相互错开、且落于连接电极在衬底基板上的垂直投影的范围内。
806，在完成上述步骤的衬底基板上形成包括公共电极的公共电极层，公共电极通过第二过孔与连接电极电连接。
在根据本发明实施例的阵列基板的制备方法中，通过在源漏极金属层中设置连接电极，连接电极通过第一过孔与公共电极线电连接，公共电极层的公共电极通过第二过孔与连接电极电连接，实现公共电极与公共电极线的电 连接。由于第一过孔和第二过孔通过连接电极实现电连接，因此第一过孔和第二过孔的孔深和尺寸相比于直接贯穿栅极绝缘层和钝化层这两层的连续过孔的孔深和尺寸减小，对后续制备过程中涂布膜层的影响减小，避免产生涂布膜层波纹，从而提高阵列基板的良率；进一步的，连接电极与源电极、漏电极和数据线同层且同步形成，减少制备工序和材料消耗。
由步骤801至步骤806制备的阵列基板的结构如图3所示。
例如，本发明实施例提供的阵列基板的制备方法包括以下步骤：
901，在衬底基板上依次形成栅极金属层，栅极金属层包括栅电极和公共电极线。
902，在栅极金属层之上形成栅极绝缘层、有源层及包括源电极、漏电极和数据线的源漏极金属层。
903，在栅极绝缘层的、有源层和数据线之外的区域中形成第一过孔。
第一过孔的位置与公共电极线的位置对应。
904，在完成上述步骤的衬底基板上形成包括像素电极和连接电极的像素电极层，连接电极通过第一过孔与公共电极线电连接。
连接电极与像素电极彼此绝缘。
905，在完成上述步骤的衬底基板上形成钝化层，钝化层包括与连接电极相对应的第二过孔。
第二过孔和第一过孔在衬底基板上的垂直投影相互错开、且落于连接电极在衬底基板上的垂直投影的范围内。
906，在完成上述步骤的衬底基板上形成包括公共电极的公共电极层，公共电极通过第二过孔与连接电极电连接。
在根据本发明实施例的阵列基板的制备方法中，通过在像素电极层中设置连接电极，连接电极通过第一过孔与公共电极线电连接，公共电极层的公共电极通过第二过孔与连接电极电连接，实现公共电极与公共电极线的电连接。由于第一过孔和第二过孔是通过连接电极实现电连接，因此第一过孔和第二过孔的孔深和尺寸相比于直接贯穿栅极绝缘层和钝化层这两层的连续过孔的孔深和尺寸减小，对后续制备过程中涂布膜层的影响减小，避免产生涂布膜层波纹，从而提高阵列基板的良率；进一步的，连接电极与像素电极同层且同步形成，减少制备工序和材料消耗。
由步骤901至步骤906制备的阵列基板的结构如图5所示。
需要说明的，在根据本发明实施例的阵列基板的制备方法中，形成栅极绝缘层及其中的第一过孔、钝化层及其中的第二过孔可以采用涂覆、刻蚀等工艺，形成栅极金属层和源漏极金属层可以采用溅射、刻蚀等工艺，形成有源层、像素电极层、公共电极层可以采用涂覆、刻蚀等工艺，在此不再赘述。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年8月29日递交的第201410438637.9号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种阵列基板，包括衬底基板，依次形成于所述衬底基板上的栅极金属层、栅极绝缘层、有源层、源漏极金属层、钝化层和公共电极层，及位于所述有源层和所述源漏极金属层之间或者所述源漏极金属层和所述钝化层之间的像素电极层；所述栅极金属层包括栅电极和公共电极线；其中
    所述像素电极层或所述源漏极金属层包括连接电极，所述连接电极通过所述栅极绝缘层中的第一过孔与所述公共电极线电连接，所述连接电极通过所述钝化层中的第二过孔与所述公共电极层的公共电极电连接。
  2. 如权利要求1所述的阵列基板，其中所述连接电极与所述栅极绝缘层和所述钝化层直接接触。
  3. 如权利要求1或2所述的阵列基板，其中所述第一过孔和所述第二过孔在所述衬底基板上的垂直投影相互错开，所述第一过孔与所述公共电极线的位置对应，所述第二过孔与所述公共电极的位置对应，所述第一过孔和所述第二过孔在所述衬底基板上的垂直投影落于所述连接电极在所述衬底基板上的垂直投影的范围内。
  4. 如权利要求1至3任一项所述的阵列基板，其中所述连接电极位于所述像素电极层，所述连接电极与所述像素电极层的像素电极彼此绝缘。
  5. 如权利要求1至3任一项所述的阵列基板，其中所述连接电极位于所述源漏极金属层，所述连接电极与所述源漏极金属层的源电极、漏电极和数据线彼此绝缘。
  6. 一种显示面板，包括如权利要求1至5任一项所述的阵列基板。
  7. 一种显示装置，包括如权利要求6所述的显示面板。
  8. 一种阵列基板的制备方法，包括：在衬底基板上依次形成栅极金属层、栅极绝缘层、有源层、源漏极金属层、钝化层和公共电极层，并在有源层和源漏极金属层之间或者源漏极金属层和钝化层之间形成像素电极层，所述栅极金属层包括栅电极和公共电极线，其中
    该方法还包括在像素电极层或源漏极金属层中形成连接电极，在栅极绝缘层中形成第一过孔，在钝化层中形成第二过孔，其中连接电极通过栅极绝缘层中的第一过孔与公共电极线电连接，连接电极通过钝化层中的第二过孔与公共电极层的公共电极电连接。
  9. 如权利要求8所述的阵列基板的制备方法，包括：
    在衬底基板上依次形成栅极金属层，所述栅极金属层包括栅电极和公共电极线；
    在所述栅极金属层之上依次形成所述栅极绝缘层和有源层；
    在所述栅极绝缘层的、所述有源层之外的区域中形成第一过孔，所述第一过孔的位置与所述公共电极线的位置对应；
    在所述衬底基板上形成包括像素电极和连接电极的像素电极层，所述连接电极通过所述第一过孔与所述公共电极线电连接；
    在所述衬底基板上形成包括源电极、漏电极和数据线的源漏极金属层；
    在所述衬底基板上形成钝化层，所述钝化层包括与所述连接电极相对应的第二过孔；
    在所述衬底基板上形成包括公共电极的公共电极层，所述公共电极通过所述第二过孔与所述连接电极电连接。
  10. 如权利要求8所述的阵列基板的制备方法，包括：
    在衬底基板上依次形成栅极金属层，所述栅极金属层包括栅电极和公共电极线；
    在所述栅极金属层之上形成所述栅极绝缘层和有源层；
    在所述栅极绝缘层的、所述有源层之外的区域中形成第一过孔，所述第一过孔的位置与所述公共电极线的位置对应；
    在所述衬底基板上形成包括源电极、漏电极、数据线和连接电极的源漏极金属层，所述连接电极通过所述第一过孔与所述公共电极线电连接；
    在所述衬底基板形成包括像素电极的像素电极层；
    在所述衬底基板上形成钝化层，所述钝化层包括与所述连接电极相对应的第二过孔；
    在所述衬底基板上形成包括公共电极的公共电极层，所述公共电极通过所述第二过孔与所述连接电极电连接。
  11. 如权利要求8所述的阵列基板的制备方法，包括：
    在衬底基板上依次形成栅极金属层，所述栅极金属层包括栅电极和公共电极线；
    在所述栅极金属层之上形成所述栅极绝缘层、有源层及包括像素电极的 像素电极层；
    在所述栅极绝缘层的、所述有源层和所述像素电极之外的区域中形成第一过孔，所述第一过孔的位置与所述公共电极线的位置对应；
    在所述衬底基板上形成包括源电极、漏电极、数据线和连接电极的源漏极金属层，所述连接电极通过所述第一过孔与所述公共电极线电连接；
    在所述衬底基板上形成钝化层，所述钝化层包括与所述连接电极相对应的第二过孔；
    在所述衬底基板上形成包括公共电极的公共电极层，所述公共电极通过所述第二过孔与所述连接电极电连接。
  12. 如权利要求8所述的阵列基板的制备方法，包括：
    在衬底基板上依次形成栅极金属层，所述栅极金属层包括栅电极和公共电极线；
    在所述栅极金属层之上形成栅极绝缘层、有源层及包括源电极、漏电极和数据线的源漏极金属层；
    在所述栅极绝缘层的、所述有源层和所述数据线之外的区域中形成第一过孔，所述第一过孔的位置与所述公共电极线的位置对应；
    在所述衬底基板上形成包括像素电极和连接电极的像素电极层，所述连接电极通过所述第一过孔与所述公共电极线电连接；
    在所述衬底基板上形成钝化层，所述钝化层包括与所述连接电极相对应的第二过孔；
    在所述衬底基板上形成包括公共电极的公共电极层，所述公共电极通过所述第二过孔与所述连接电极电连接。
  13. 如权利要求9或12所述的阵列基板的制备方法，其中所述连接电极和所述像素电极彼此绝缘。
  14. 如权利要求10或11所述的阵列基板的制备方法，其中所述连接电极与所述源电极、所述漏电极和所述数据线彼此绝缘。
  15. 如权利要求8-14任一项所述的阵列基板的制备方法，其中所述第一过孔和所述第二过孔在所述衬底基板上的垂直投影相互错开，所述第一过孔和所述第二过孔在所述衬底基板上的垂直投影落于所述连接电极在所述衬底基板上的垂直投影的范围内。
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