WO2016008183A1 - 用于制作hva像素电极的方法及阵列基板 - Google Patents

用于制作hva像素电极的方法及阵列基板 Download PDF

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Publication number
WO2016008183A1
WO2016008183A1 PCT/CN2014/083744 CN2014083744W WO2016008183A1 WO 2016008183 A1 WO2016008183 A1 WO 2016008183A1 CN 2014083744 W CN2014083744 W CN 2014083744W WO 2016008183 A1 WO2016008183 A1 WO 2016008183A1
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Prior art keywords
pixel electrode
conductive layer
array substrate
mask
insulating
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PCT/CN2014/083744
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English (en)
French (fr)
Inventor
施明宏
姜佳丽
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深圳市华星光电技术有限公司
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Priority to US14/416,858 priority Critical patent/US9891477B2/en
Publication of WO2016008183A1 publication Critical patent/WO2016008183A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133742—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers for homeotropic alignment
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a method for fabricating an HVA (High Vertical Alignment) pixel electrode and an array substrate.
  • HVA High Vertical Alignment
  • HVA pixel electrodes have a Fine Slit (modified slit) structure.
  • the Fine Slut structure does not have a pixel electrode in the slit portion. Therefore, the slit portion has a poor control effect on the electric field, and thus the control force on the liquid crystal molecules is inferior.
  • dark lines appear in the area corresponding to the slit portion. This loses the light transmittance of the liquid crystal to some extent, and thus the transmittance of the liquid crystal panel is lost.
  • the present invention provides a method of fabricating an HVA pixel electrode capable of improving the transmittance of a liquid crystal panel and a corresponding array substrate.
  • a method for fabricating an HVA pixel electrode comprising the steps of:
  • a transparent conductive material is entirely coated on the surface of the insulating structure and other exposed layers, and a transparent conductive layer is formed by etching through a fifth mask.
  • the insulating structure is a m-shaped structure.
  • the m-shaped structure includes horizontally intersecting horizontal trunks and vertical masters, and thousands of branches extending from the horizontal main thousand and the vertical main thousand S sides at a certain angle, respectively.
  • Each of the branch portions and the trunk portion has a convex strip shape with a groove shape between the branches.
  • the light transmissive area on the fourth photomask corresponds to a recess forming an insulating structure on the array substrate.
  • a transparent conductive layer formed by etching through the fifth mask covers the surface of the ridge and the surface of the recess to form a pixel electrode.
  • an array substrate having a pixel electrode fabricated by the above method comprising:
  • the pixel unit comprising:
  • a pixel electrode disposed in the open area, the pixel electrode being disposed on the insulating structure, wherein the insulating structure includes ridges and grooves arranged in phase.
  • the insulating structure is a m-shaped structure.
  • the m-shaped structure includes horizontally intersecting horizontal trunks and vertical trunks, and a plurality of branches extending from the middle to the sides at a certain angle, each of the branch portions and the trunk portion having a convex strip shape , has a groove shape between the branches.
  • the widths of the ridges and the grooves are set to be equal.
  • the widths of the ridges and the grooves are set to be unequal, wherein adjacent ribs have the same width and adjacent grooves have the same width.
  • the steps of etching the contact hole and etching the insulating structure are combined into one step, which saves a mask process, saves cost, shortens the fabrication time of the array substrate, and improves the time. Capacity. Same When the pixel electrode is completely covered in the open area, the control power of the liquid crystal molecules by the pixel electrode is improved, and the transmittance of the liquid crystal raft is improved.
  • Figure 2 is a schematic view of the A-A side of Figure 1;
  • Figure 3 is a schematic diagram of a method of an embodiment of the present invention.
  • FIG. 4 is a plan view showing an embodiment of an array substrate having pixel electrodes fabricated in accordance with the method of the present invention
  • Figure 5 is a cross-sectional view taken along line B-B of Figure 4.
  • the steps illustrated in the flowchart of the Pf diagram may be performed in a computer system such as a set of computer executable instructions, and although the logical order is illustrated in the flowchart, in some cases, The steps shown or described are performed differently than the order herein.
  • an array substrate of a conventional HVA pixel electrode having a Fine Slit form is shown.
  • the array substrate includes a substrate 1 and a pixel unit.
  • the pixel unit includes a gate line 2, a data line 3, a TFT 4, a pixel electrode 5, and a common electrode line 6 which are disposed on the substrate 1.
  • the line 2 is arranged in parallel with the common electrode line 6. Both the outline 2 and the common electrode 6 are disposed perpendicular to the data line 3.
  • TFT4 is disposed on the machine line 2, and its emitter, source and drain are respectively associated with «line 2, data
  • the line 3 and the pixel electrode 5 are electrically connected.
  • the TFT 4 is connected to the pixel electrode 5 through the contact hole 7.
  • a slit 5a is disposed on the pixel unit, and a transparent conductive material is not disposed on the slit 5a to form a pixel electrode.
  • Figure 2 is a cross-sectional view of Figure 1 taken along the line A-A.
  • the substrate 1 is covered with a gate insulating layer 8.
  • a deposition passivation layer 9 is overlaid on the data line 3 and the gate insulating layer 8.
  • a pixel electrode 5 is provided on the deposition purification layer 9.
  • a slit 5a is provided between the pixel electrodes 5, and a portion of the slit 5a is not provided with a conductive material. Since the portion of the slit 5a is not provided with a conductive material, the control force of the portion to the electric field is poor, which in turn causes the control force of the portion to the liquid crystal molecules to be poor.
  • FIG. 3 is a diagram showing the steps of a method for fabricating a new pixel electrode in accordance with the principles of the present invention.
  • step S001 a first metal village material is deposited on the selected substrate, and the first metal material is etched through the first mask to be patterned to form a first metal conductive layer.
  • the first metal conductive layer at this point corresponds to the «polar metal layer.
  • a metal layer is first formed on the substrate by sputtering.
  • a layer of positive PR (photoresist) is then applied over the metal layer.
  • the exposure process is then performed using the corresponding mask. Thereafter, development treatment, wet etching treatment, and PR dissection treatment are carried out to obtain a desired electrode metal layer.
  • a first insulating material is first deposited on the first layer of metal conductive layer to form a gate insulating layer.
  • a semiconductor material is then deposited over the gate insulating layer and the semiconductor material is etched through a second mask to form a silicon island pattern.
  • a layer of positive PR (photoresist) is then applied over the exposed outline insulating layer and the etched semiconductor material. Then, the corresponding mask is used for exposure processing. Thereafter, development treatment, wet etching treatment, and PR. dissection treatment are carried out to obtain a desired intermediate layer.
  • a second layer of metal material is first deposited on the intermediate layer and a second metal conductive layer is formed through the third mask.
  • the second metal conductive layer there includes a data line, a source and a drain of the TFT.
  • a metal layer is first formed on the intermediate layer by sputtering.
  • a layer of positive PR (photoresist) is then applied over the metal layer.
  • the corresponding mask is used for exposure processing. Thereafter, development treatment, wet etching treatment, and PR dissection treatment are performed to obtain a desired second metal conductive layer.
  • step S004 a purification layer is first deposited on the exposed intermediate layer and the second metal conductive layer, and then etched on the deposition passivation layer by using a corresponding fourth mask to simultaneously form the contact hole and the insulating structure.
  • a passivation layer is first deposited for insulating protection of the exposed intermediate layer and the second metal conductive layer, and then etching is performed on the deposited passivation layer.
  • the light transmissive region on the fourth reticle employed herein is provided in two portions under the condition of a positive PR (photoresist). Part of the light-transmitting area corresponding array A contact hole portion on the substrate, the light-transmitting region correspondingly forming a contact hole reaching the second metal conductive layer. Another portion of the light-transmissive region corresponds to a portion of the pixel unit opening region on the array substrate, and the insulating material on the array substrate corresponding to the light-transmitting region is I*-etched into a groove.
  • the pixel unit opening area on the corresponding array substrate of the fourth reticle is further provided with an opaque area, and the insulating material on the array substrate corresponding to the opaque area is not etched to form a ridge on the substrate.
  • the grooves and ridges on the array substrate form an insulating structure having a three-dimensional shape.
  • the etching of the insulating material on the contact hole and the array substrate is performed by two turns, that is, a mask is used to etch the insulating material on the array substrate to form a contact hole, and then another mask is used to etch the insulation on the array substrate. Material to form ribs and grooves.
  • the fourth light mask is used to simultaneously etch the contact holes, the ridges and the grooves. The manufacturing method saves a mask and a process, saves costs, and shortens the production of the array substrate, thereby increasing the production capacity.
  • step S005 the transparent conductive village material is completely coated on the surface of the insulating structure and the other exposed layers, and a transparent conductive layer, that is, a pixel electrode, is formed through the fifth mask.
  • the pixel electrode covers the ridges and the grooves of the entire insulating structure, and since the insulating structure is located at the opening area of the pixel unit, the pixel electrode covers the opening area of the entire pixel unit.
  • the control power of the pixel electrode to the electric field is increased, thereby improving the control of the liquid crystal molecules.
  • the increase in the control of the liquid crystal molecules reduces the appearance of dark lines, thereby increasing the transmittance of the liquid crystal and thereby increasing the transmittance of the liquid crystal raft.
  • the array substrate includes a substrate and a pixel unit.
  • the pixel unit includes a machine line 2, a data line 3, a TFT 4, a pixel electrode 5, and a common electrode line 6 which are disposed on the substrate 1.
  • the machine line 2 is disposed in parallel with the common electrode line 6.
  • the number line 2 and the common electrode line 6 are both arranged perpendicular to the line 3.
  • the TFT 4 is disposed on the 'line 2, and its pole, source and drain are electrically connected to the gate line 2, the data line 3 and the pixel electrode 5, respectively.
  • the drain of the TFT 4 is connected to the pixel electrode 5 through the contact hole 7.
  • the rib 5b and the groove 5c are arranged to form an insulating structure.
  • the pixel electrode 5 covers the insulating structure.
  • the insulating structure has a m-shaped structure.
  • the m-shaped structure includes horizontally intersecting horizontal trunks and vertical trunks, and thousands of branches extending from the center to the sides at a certain angle. The angle between each branch and the trunk leading out is set to 30° ⁇ 60.
  • Each of the branch portions and the trunk portion has a convex strip shape with a groove shape between the branches.
  • the ribs and the grooves are arranged in phase.
  • the width of the ridges and grooves can be set equal, as shown in FIG. In another embodiment of the invention, the width of the ridges and grooves may also be set to be unequal.
  • Figure 5 is a cross-sectional view of Figure 4 taken along the line B-B.
  • the substrate 1 is covered with a gate insulating layer 8.
  • a deposition passivation layer 9 is covered on the data line 3 and the insulator insulating layer 8.
  • An insulating structure is formed between the pixel electrode 5 and the substrate 1.
  • the absolute The edge structure includes ridges and grooves.
  • the transparent conductive material is covered on the ridge and the groove to form the pixel electrode, thereby increasing the coverage area of the pixel electrode of the liquid crystal panel, thereby improving the control of the liquid crystal molecules by the pixel electrode.
  • the improvement of the control of the liquid crystal molecules will reduce the appearance of dark lines, which will increase the transmittance of the liquid crystal, thereby increasing the transmittance of the liquid crystal panel.

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Abstract

一种用于制作HVA像素电极的方法及对应的阵列基板，应用于液晶显示技术领域，该方法包括：在基底（1）上沉积第一金属材料经蚀刻形成第一金属导电层（S001）；在第一金属导电层上沉积第一绝缘材料和半导体材料经蚀刻形成中间层（S002）；在中间层上沉积第二金属材料经蚀刻形成第二金属导电层（S003）；在第二金属导电层以及裸露的中间层上涂敷第二绝缘材料经蚀刻同时形成接触孔及三维结构的绝缘结构体（S004）；在绝缘结构体表面以及裸露出的其它层上全面涂敷透明导电材料，并通过第五道光罩蚀刻形成透明导电层（S005），同时还包括采用以上方法制成的阵列基板。由于节省了一道光罩过程，节约了成本，缩短了阵列基板的制作时间，提高了产能，同时提高了液晶面板的穿透率。

Description

用于制作 HVA像素电极的方法及阵列基板 相关申请的交叉引用
本申请要求享有 2014年 7 .月 18日提交的名称为 "用于制作 HVA像素电极的方法及 阵列基板"的中国专利申请 CN201410344992.X的优先权， 该申请的全部内容通过引用并 入本文中。 技术领域
本发明涉及液晶显示技术领域， 具体地说， 涉及一种用于制作 HVA (High Vertical Alignment, 高垂直排列） 像素电极的方法及阵列基板„ 背景技术
一般而言， HVA像素电极具有 Fine Slit (改进的狭缝） 结构样式。 Fine Slut结构在狭 缝部分不设置像素电极。因此狭缝部分对电场的控刺力较差，进而对液晶分子的控制力较 差。在显示的^候， 该狭缝部分对应的区域会出现暗纹。这在一定程度上损失了液晶的透 光效率， 进而损失了液晶面板的穿透率。
基于上述情况， 亟需一种能够提高液晶面板穿透率的 HVA像素电极的制作方法及对 应的阵列基板。 发明内容
为解决上述问题， 本发明提供了一种能够提高液晶面板穿透率的 HVA像素电极的制 作方法及对应的阵列基板。
根据本发明的一个方面， 提供了一种用于制作 HVA像素电极的方法， 其包括以下步 骤：
在一基底上沉积第一金属材料，并采用第一道光罩对所述第一金属材料进行蚀刻以图 案化形成第一金属导电层；
在所述第一金属导电层上沉积第一绝缘材料和半导体材料,并采用第二道光罩对所述 半导体材料进行蚀刻以图案化形成硅岛图案，裸露的第一绝缘材料和饨刻后的半导体材料 形成中间层； 在所述中间层上沉积第二金属村料，并采用第三道光罩对所述第二金属材料进行蚀刻 以图案化形成第二金属导电层；
在图案化的第二金属导电层以及裸露的中间层上涂敷第二绝缘材料，并通过第四道光 罩对所述第二绝缘材料进行蚀刻， 以形成至少到达所述第二金属导电层的接触孔， 其中， 所述第四道光罩设计成还能蚀刻出具有三维结构的绝缘结构体；
在所述绝缘结构体表面以及裸露出的其它层上全面涂敷透明导电材料,并通过第五道 光罩蚀刻形成透明导电层。
根据本发明的一个实施例， 所述绝缘结构体为米字形结构。
根据本发明的一个实施例，所述米字形结构包括垂直相交的水平主干和竖直主千， 以 及分别从水平主千和竖直主千向 S侧以一定夹角延伸出的若千分支，各个分支部分和主干 部分具有凸条形状， 在分支之间具有凹槽形状。
根据本发明的一个实施例，所述第四道光罩上的透光区域对应形成阵列基板上的绝缘 结构体的凹槽。
根据本发明的一个实施例，经所述第五道光罩蚀刻后形成的透明导电层覆盖于所述凸 条的表靣和所述凹槽的表面， 从而形成像素电极。
根据本发明的另一方面，还提供了一种具有以上方法制作的像素电极的阵列基板，其 包括；
基底；
在基底上形成的多个像素单元， 所述像素单元包括：
设置在开口区的像素电极， 所述像素电极设置于绝缘结构体上， 其中， 所述绝缘结构 体包括相间排列的凸条和凹槽。
根据本发明的一个实施例， 所述绝缘结构体为米字形结构。
根据本发明的一个实施例，所述米字形结构包括垂直相交的水平主干和竖直主干， 以 及分别从中向两侧以一定夹角延伸出的若干分支， 各个分支部分和主干部分具有凸条形 状， 在分支之间具有凹槽形状。
根据本发明的一个实施例， 所述凸条和所述凹槽的宽度设置为相等。
根据本发明的一个实施例， 所述凸条和所述凹槽的宽度设置为不等， 其中， 相邻凸条 的宽度相等， 相邻凹槽的宽度相等。
本发明带来了以下有益效果：
在本发明所述的方法中，将蚀刻接触孔与蚀刻形成绝缘结构体的歩骤合并为一个歩骤 进行， 节省了一道光罩过程， 节约了成本， 缩短了阵列基板的制作时间， 提高了产能。 同 时将像素电极全面覆盖于开口区中，提高了像素电极对液晶分子的控制力，提高了液晶靣 板的穿透率。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地认说明书中变得显 而易见， 或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要 求书以及附图中所特别指出的结构来实现和获得。 图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技 术描述中所需要的 W图做简单的介绍- 图 为现有的 Fine Slit形式的 HVA像素电极平面示意图；
图 2为图 1的 A-A方 | 剂面示意图;
图 3为本发明的一个实施例的方法歩骤图；
图 4 为具有按本发明所述方法制成的像素电极的阵列基板的一个实施例的平靣示意 图；
图 5是图 4的 B- B方向剖面示意图；
其中， 1、 基底， 2、 栅线， 3 , 数据线， 4、 TFT (薄膜晶体管） ， 5、 像素电极， 5a、 Slit (缝隙） ， 5b、 凸条， 5c , 凹槽， 6、 公共电极线， 7、 接触孔， 8、 楊极绝缘层， 9、 沉积钝化层。 具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式,借此对本发明如何应用技术 手段来解决技术 题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是， 只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形 成的技术方案均在本发明的保护范围之内。
另外,在 Pf†图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中 执行， 并且， 虽然在流程图中示出了逻辑顺序， 但是在某些情况下， 可以以不同于此处的 顺序执行所示出或描述的步骤。
如图 1所示为现有的一种具有 Fine Slit形式 HVA像素电极的阵列基板。 该阵列基板 包括基底 1和像素单元。 像素单元包括设置于基底 1上的栅线 2、 数据线 3、 TFT4、 像素 电极 5和公共电极线 6。 其中， «线 2与公共电极线 6平行设置。 概线 2与公共电极 6均 与数据线 3垂直设置。 TFT4设置于機线 2上， 其機极、 源极和漏极分别与 «线 2、 数据 线 3和像素电极 5电连接。 在一种设置中， TFT4通过接触孔 7与像素电极 5连接。 像素 单元上设置有缝隙 5a, 缝隙 5a上不设置透明导电材料来形成像素电极。
图 2为图 1沿 A-A方向的剖面图。 如图所示， 基底 1上覆有栅极绝缘层 8。 在数据 线 3和栅极绝缘层 8上覆盖有沉积钝化层 9。 沉积纯化层 9上设置有像素电极 5。 在像素 电极 5之间设置有缝隙 5a， 缝隙 5a部分未设置导电材料。 由于缝隙 5a部分不设置导电 材料， 因此该部分对电场的控制力差， 进而导致该部分对液晶分子的控制力差。在电场控 制液晶分子翻转时， 缝隙 5a对应位置的液晶分子不能翻转到位， 因此会影响该位置的光 透过率。 在这种情况下， 就会在缝隙 5a对应位置引起暗纹， 损失液晶分子的透光率， 进 而损失液晶面板的穿透率。因此，需要一种新的制作工艺来改进像素电极结构及对应该像 素电极结构的阵列基板， 从而提高液晶分子的透光率。
如图 3所示为根据本发明的原理制作一种新的像素电极的方法步骤图。
在步骤 S001中， 在选择的基底上沉积第一金属村料， 并经过第一道光罩对第一金属 材料进行蚀刻以图案化从而形成第一金属导电层。 该处的第一金属导电层对应 «极金属 层。在该步骤中， 首先通过溅射方式在基底上形成一层金属层。然后在该金属层上涂布一 层正性 PR (光刻胶） 。 之后采用对应的光罩进行曝光处理。 之后经显影处理、 湿刻处理 和 PR剖离处理， 得到所需的極极金属层。
在步骤 S002中，首先在第一层金属导电层上沉积第一绝缘材料用以形成栅极绝缘层。 然后在栅极绝缘层上沉积半导体材料，并经过第二道光罩对半导体材料进行蚀刻以形成硅 岛图案。之后在裸露的概极绝缘层和蚀刻后的半导体材料上涂布一层正性 PR (光刻胶） 。 然后采用对应的光罩进行曝光处理。 之后经显影处理、 湿刻处理和 PR.剖离处理， 得到所 需的中间层。
在歩骤 S003中， 首先在中间层上沉积第二层金属材料， 并经过第三道光罩形成第二 金属导电层。 该处的第二金属导电层包括数据线、 TFT 的源极和漏极。 在该歩骤中， 首 先利用溅射方式在中间层上形成一层金属层。 然后在该金属层上涂布一层正性 PR (光刻 胶）。之后采 ^对应的光罩进行曝光的处理。之后经显影处理、湿刻处理和 PR剖离处理， 得到所需的第二金属导电层。
在歩骤 S004中， 首先在裸露的中间层及第二金属导电层上沉积纯化层， 然后采用对 应的第四道光罩在该沉积钝化层上进行蚀刻以同时形成接触孔和绝缘结构体。
在该过程中， 首先沉积钝化层用于对裸露的中间层及第二金属导电层进行绝缘保护， 然后在沉积钝化层上进行蚀刻处理。在本发明的一个实施例中， 在采用正性 PR (光刻胶） 的条件下，此处采用的第四道光罩上的透光区域设置为两部分。一部分透光区域对应阵列 基板上接触孔部位，该透光区域对应形成到达第二金属导电层的接触孔。另一部分透光区 域对应阵列基板上部分像素单元开口区域，对应该透光区域的阵列基板上的绝缘材料被 I* 刻形成凹槽。 同时， 第四道光罩上对应阵列基板上像素单元开口区域还设有不透光区域， 该不透光区域对应的阵列基板上的绝缘材料不被蚀刻从而在基板上形成凸条。阵列基板上 的凹槽和凸条形成具有立体形状的绝缘结构体。
通常情况下，接触孔和阵列基板上绝缘材料的蚀刻是通过两歩来完成的， 即采用一道 光罩蚀刻阵列基板上的绝缘材料形成接触孔,然后采用另一道光罩蚀刻阵列基板上的绝缘 材料来形成凸条和凹槽。在本发明中，采用第四道光罩同时饨刻形成接触孔、凸条和凹槽。 该制作方法节约了一张光罩和一道制程， 节约了成本， 同时缩短了阵列基板的制作 B寸间， 提高了产能。
在步骤 S005中， 在绝缘结构体表面以及裸露的其它层上全面涂敷透明导电村料， 并 经过第五道光罩形成透明导电层， 即像素电极。像素电极覆盖于整个绝缘结构体的凸条和 凹槽上，又由于绝缘结构体位于像素单元的开口区域，所以像素电极覆盖于整个像素单元 的开□区域。在这种情况下， 就会提高像素电极对电场的控制力， 从而提高了对液晶分子 的控制力。对液晶分子的控制力提高就会降低暗纹的出现，从而提高了液晶的透光率进而 提高了液晶靣板的穿透率。
图 4 所示为具有以上所述像素电极的阵列基板的一个实施例的平面示意图。 如图所 示， 该阵列基板包括基底〗和像素单元。 像素单元包括设置于基底 1上的機线 2、 数据线 3、 TFT4、 像素电极 5和公共电极线 6。 其中， 機线 2与公共电极线 6平行设置。 数概线 2和公共电极线 6均与据线 3垂直设置。 TFT4设置于 «线2上， 其極极、 源极和漏极分 别与栅线 2、 数据线 3和像素电极 5电连接。 其中， TFT4的漏极通过接触孔 7与像素电 极 5连接。 凸条 5b和凹槽 5c相间排列， 构成绝缘结构体。像素电极 5覆盖于绝缘结构体 再次如图 4所示，绝缘结构体为米字形结构。米字形结构包括垂直相交的水平主干和 竖直主干， 以及分别从中向两侧以一定夹角延伸出的若千分支。各个分支与引出其的主干 之间的夹角范围设置为 30°〜60 。 各个分支部分和主干部分为凸条形状， 分支之间为凹槽 形状。其中， 凸条和凹槽相间排列设置。在本发明的一个实施例中， 凸条和凹槽的宽度可 以设置为相等， 如图 4所示。在本发明的另一个实施例中， 凸条和凹槽的宽度也可设置为 不等。
图 5为图 4沿 B- B方向的剖面图。 如图所示， 基底 1上覆有栅极绝缘层 8。在数据线 3和機极绝缘层 8上覆盖有沉积钝化层 9。 像素电极 5与基底 1之间为绝缘结构体。 该绝 缘结构体包括凸条和凹槽。在凸条和凹槽上均覆盖透明导电材料形成像素电极，这样就提 高了液晶面板的像素电极覆盖面积，进而提高了像素电极对液晶分子的控制。对液晶分子 的控制提高就会降低暗纹的出现，就会提高液晶的透光率,进而提高了液晶面板的穿透率。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的 实施方式， 并非用以限定本发明。任何本发明所属技术领域内的技术人员， 在不脱离本发 明所公开的精神和范围的前提下，可以在实施的形式上及细节上 任何的修改与变化，但 本发明的专利保护范围， 仍须以所附的权利要求书所界定的范围为准。

Claims

权利要求书
1、 一种用于制作 HVA像素电极的方法， 其中， 包括以下步骤- 在一基底上沉积第一金属材料，并采用第一道光罩对所述第一金属材料进行蚀刻以图 案化形成第一金属导电层；
在所述第一金属导电层上沉积第一绝缘村料和半导体村料,并采用第二道光罩对所述 半导体材料进行饨刻以图案化形成硅岛图案，裸露的第一绝缘材料和蚀刻后的半导体材料 形成中间层；
在所述中间层上沉积第二金属材料,并采用第三道光罩对所述第二金属材料进行蚀刻 以图案化形成第二金属导电层；
在图案化的第二金属导电层以及裸露的中间层上涂敷第二绝缘材料，并通过第四道光 罩对所述第二绝缘材料进行蚀刻， 以形成至少到达所述第二金属导电层的接触孔， 其中， 所述第四道光罩设计成还能蚀刻出具有三维结构的绝缘结构体；
在所述绝缘结构体表面以及裸露出的其它层上全面涂敷透明导电材料,并通过第五道 光罩蚀刻以图案化形成透明导电层。
2、 如权利要求 1所述的用于制作 HVA像素电极的方法， 其中， 所述绝缘结构体为 米字形结构。
3、 如权利要求 2所述的用于制作 HVA像素电极的方法， 其中， 所述米字形结构包 括垂直相交的水平主干和竖直主千，以及分别从水平主干和竖直主干向两侧以一定夹角延 伸出的若干分支， 各个分支部分和主千部分具有凸条形状， 在分支之间具有凹槽形状。
4、 如权利要求 3所述的用于制 HVA像素电极的方法， 其中， 所述第四道光罩上 的透光区域对应形成阵列基板上的绝缘结构体的凹槽。
5、 如权利要求 4所述的用亍制作 HVA像素电极的方法， 其中， 经所述第五道光罩 蚀刻后形成的透明导电层覆盖于所述凸条的表面和所述凹槽的表面， 从而形成像素电极。
6、 一种阵列基板， 其中， 所述阵列基板包括；
基底；
在基底上形成的多个像素单元， 所述像素单元包括: 设置在开□区的像素电极， 所述像素电极设置于绝缘结构体上， 其中， 所述绝缘结构 体包括相间排列的凸条和凹槽， 制作所述像素电极包括以下步骤：
在一基底上沉积第一金属材料，并采用第一道光罩对所述第一金属材料进行蚀刻以图 案化形成第一金属导电层- 在所述第一金属导电层上沉积第一绝缘材料和半导体材料,并采用第二道光罩对所述 半导体材料进行蚀刻以图案化形成硅岛图案,裸露的第一绝缘材料和饨刻后的半导体材料 形成中间层；
在所述中间层上沉积第二金属材料，并采用第三道光罩对所述第二金属材料进行蚀刻 以图案化形成第二金属导电层；
在图案化的第二金属导电层以及裸露的中间层上涂敷第二绝缘材料，并通过第四道光 罩对所述第二绝缘材料进行蚀刻， 以形成至少到达所述第二金属导电层的接触孔， 其中， 所述第四道光罩设计成还能蚀刻出具有三维结构的绝缘结构体；
在所述绝缘结构体表面以及裸露出的其它层上全面涂敷透明导电材料，并通过第五道 光罩蚀刻以图案化形成透明导电层。
7、 如权利要求 6所述的阵列基板， 其中， 所述绝缘结构体为米字形结构。
8、 如权利要求 7所述的阵列基板， 其中， 所述米字形结构包括垂直相交的水平主干 和竖直主干， 以及分别从中向两侧以一定夹角延伸出的若干分支，各个分支部分和主干部 分具有所述凸条形状， 在分支之间具有所述凹槽形状。
9、 如权利要求 8所述的阵列基板， 其中， 所述凸条和所述凹槽的宽度设置为不等。
10、 如权利要求 8所述的阵列基板， 其中， 所述凸条和所述凹槽的宽度设置为相等。
PCT/CN2014/083744 2014-07-18 2014-08-05 用于制作hva像素电极的方法及阵列基板 WO2016008183A1 (zh)

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