WO2015192504A1 - 阵列基板及其制备方法、显示面板和显示装置 - Google Patents

阵列基板及其制备方法、显示面板和显示装置 Download PDF

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Publication number
WO2015192504A1
WO2015192504A1 PCT/CN2014/086921 CN2014086921W WO2015192504A1 WO 2015192504 A1 WO2015192504 A1 WO 2015192504A1 CN 2014086921 W CN2014086921 W CN 2014086921W WO 2015192504 A1 WO2015192504 A1 WO 2015192504A1
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Prior art keywords
insulating layer
thin film
film transistor
display
array substrate
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PCT/CN2014/086921
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English (en)
French (fr)
Inventor
盖翠丽
刘晓娣
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京东方科技集团股份有限公司
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Priority to US14/443,542 priority Critical patent/US20160247833A1/en
Publication of WO2015192504A1 publication Critical patent/WO2015192504A1/zh
Priority to US15/826,184 priority patent/US10490573B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to an array substrate and a method for fabricating the same, and a display panel including the array substrate and a display device.
  • Static electricity is ubiquitous in the manufacture, packaging, testing, and use of array substrates including thin film transistors.
  • the accumulated static charge is released in nanoseconds to microseconds at a few amperes or tens of amperes. Up to several hundred kilowatts, the discharge energy can reach up to millijoules, and the destruction of thin film transistors is extremely strong.
  • the design of electrostatic protection in the design of thin film transistors is directly related to the functional stability of the chip, which is extremely important.
  • the feature size of the device gradually becomes smaller, and the thickness of the insulating layer (between the gate electrode and the active layer, also referred to as a gate oxide layer or a gate insulating layer) in the thin film transistor is also proportionally reduced.
  • the gate insulating layer is usually composed of silica manufacturing, the dielectric strength of the silicon dioxide is approximately 8 ⁇ 10 6 V / cm, the thickness of the gate breakdown voltage of about 8V approximately 10nm insulating layer, although the breakdown The voltage is more than double the supply voltage of 3.3V, but the peak voltage of static electricity caused by various factors can far exceed 8V, which may cause the insulation layer to be broken down. Moreover, with the use of new processes such as polysilicon metallization, diffusion region metallization, polysilicon and diffusion region metallization, the parasitic resistance of the device is reduced, and the protection against electrostatic discharge is greatly reduced. In order to adapt to the increasing integration density and working speed of VLSI, it is necessary to improve the electrostatic protection capability of the thin film transistor.
  • the array substrate includes a display area for display and a drive area located around the display area.
  • a thin film transistor is disposed on the base substrate 1, and the thin film transistor is provided with an insulating layer 3 between the gate electrode 2 and the active layer 5, in the active layer 5
  • An etch stop layer 4 is further disposed, and a source/drain 6 is disposed on the etch barrier layer 4, and the source/drain electrodes 6 are respectively connected
  • the via 7 is electrically connected to the active layer 5.
  • the driving area of the array substrate is provided with an electrostatic protection structure to discharge the electrostatic charge, but when the accumulated electric charge is large, the electrostatic discharge current is large, and electrostatic discharge is generated at the via hole 7 of the thin film transistor of the driving region, thereby making it possible
  • the gate and source/drain electrodes 6 are short-circuited due to the breakdown of the insulating layer 3. Therefore, increasing the thickness of the insulating layer 3 of the thin film transistor of the driving region becomes an important measure for preventing electrostatic discharge, but in the thin film transistor of the display region of the array substrate, increasing the thickness of the insulating layer 3 causes a decrease in mobility and a threshold voltage value. The thickness of the insulating layer 3 of the thin film transistor in the display region cannot be excessively large due to adverse effects such as drift.
  • the mask used is as shown in FIG. 2, and the mask is used.
  • the display area mask 9 corresponding to the display area and the four drive area masks 8 corresponding to the surrounding drive areas are respectively included.
  • the above-mentioned mask is spliced and exposed during exposure, and then developed and etched to simultaneously obtain a pattern of the insulating layer in the display region and the driving region.
  • An object of the present invention is to solve the problem that an insulating layer between a gate and a source/drain of a thin film transistor of a driving region of an array substrate in the prior art is easily broken down, and an insulating layer of a thin film transistor for preventing a driving region is provided.
  • An array substrate which is broken down and which can maintain a good characteristic of a thin film transistor of a display region, and a method of manufacturing the same, and a display panel including the array substrate and a display device.
  • An embodiment of the present invention provides an array substrate including a display area for performing display and a driving area located around the display area, wherein the display area and the driving area each include a thin film transistor, the thin film transistor An insulating layer is disposed between the gate electrode and the active layer, wherein a thickness of the insulating layer of the thin film transistor of the driving region is greater than a thickness of an insulating layer of the thin film transistor of the display region.
  • the insulating layer of the thin film transistor of the driving region comprises a first insulating layer and a second insulating layer;
  • the insulating layer of the thin film transistor of the display region includes a second insulating layer.
  • the second insulating layer of the thin film transistor of the driving region is on the first insulating layer.
  • the thickness of the second insulating layer is to
  • the thickness of the first insulating layer is to
  • An embodiment of the present invention further provides a method for fabricating an array substrate, including the steps of forming an insulating layer in a driving region and a display region of the array substrate, where
  • a thin film transistor is disposed in each of the display region and the driving region, the insulating layer is disposed between a gate of the thin film transistor and the active layer, and a thickness of the insulating layer of the thin film transistor of the driving region is greater than the display The thickness of the insulating layer of the thin film transistor of the region.
  • the step of forming an insulating layer in the driving region and the display region of the array substrate comprises:
  • the same display region mask is used, the display region mask including a blank portion without graphics and a graphic portion having a pattern corresponding to the second insulating layer in the display area;
  • the photoresist layer in the display region is formed into a desired pattern by multiple exposures, respectively.
  • the blank portion and the graphic portion of the display area mask are symmetrically each occupying half of the display area.
  • Embodiments of the present invention also provide a display panel including the above array substrate.
  • Embodiments of the present invention also provide a display device including the above display panel.
  • the array substrate, the display panel and the display device of the present invention include a display area and a drive The moving region, and the thickness of the insulating layer of the thin film transistor in the driving region is larger than the thickness of the insulating layer of the thin film transistor in the display region.
  • the insulating layer can be prevented from being broken, so that the gate and the source/drain are not short-circuited; in addition, the insulating layer is also the storage capacitor (gate) a dielectric layer formed with a capacitance between the source and the drain, since the thickness of the insulating layer of the thin film transistor of the display region is thin, the storage capacitance value of the display region can be maintained or increased; and, at the same time, due to the thin film transistor of the display region Since the thickness of the insulating layer is thin, it does not cause adverse effects such as a decrease in mobility of the thin film transistor in the display region and a shift in threshold voltage value.
  • FIG. 1 is a schematic cross-sectional view showing the structure of a thin film transistor of an array substrate in the prior art.
  • FIG. 2 is a schematic view showing the structure of a mask used in the prior art for preparing an insulating layer of an array substrate.
  • FIG. 3 is a schematic cross-sectional view showing the structure of a thin film transistor of a display region and a driving region of an array substrate according to a first embodiment of the present invention.
  • FIG. 4 is a schematic view of a mask used for forming an insulating layer of a thin film transistor of an array substrate according to a second embodiment of the present invention.
  • FIG. 5 is a top plan view of an array substrate after forming a first insulating layer pattern according to a second embodiment of the present invention.
  • FIG. 6 is a top plan view showing a second embodiment of an array substrate after forming a second insulating layer pattern according to a second embodiment of the present invention.
  • FIG 3 is a schematic cross-sectional view showing the structure of a thin film transistor of a display region and a driving region of an array substrate according to the present embodiment.
  • the array substrate of this embodiment includes a display area for performing display and a driving area located around the display area.
  • the display area and the driving area each include a thin film transistor; the thin film transistor is at the gate 2 and the active layer.
  • An insulating layer 3 is provided between 5, and the thickness of the insulating layer 3 of the thin film transistor of the driving region is larger than the thickness of the insulating layer 3 of the thin film transistor of the display region.
  • the thickness of the insulating layer 3 of the thin film transistor of the driving region is larger than the thickness of the insulating layer 3 of the thin film transistor of the display region, so that it is generated between the gate 2 and the source/drain 6 of the driving region.
  • the insulating layer 3 can be prevented from being broken down, so that the gate and the source/drain are not short-circuited; in addition, the insulating layer 3 is also a dielectric layer of the storage capacitor (the capacitance formed between the gate and the source/drain). Since the thickness of the insulating layer 3 of the thin film transistor of the display region is thin, the storage capacitance value of the display region can be maintained or increased. Meanwhile, since the thickness of the insulating layer 3 of the thin film transistor of the display region is thin, the display is not caused.
  • the thin film transistor in the region has a bad influence such as a decrease in mobility and a shift in threshold voltage value.
  • the present invention will be specifically described by taking a bottom gate type thin film transistor as an example. However, it should be understood that the present invention is also applicable to a top gate type thin film transistor.
  • the array substrate includes a substrate 1 on which a gate 2 is disposed, an insulating layer 3 is disposed on the gate 2, and an active layer 5 is disposed on the insulating layer 3, and is disposed on the active layer 5.
  • the array substrate may further include a gate line, a data line, a pixel electrode, etc. His known structure is not described in detail here.
  • the insulating layer 3 of the thin film transistor of the driving region may include the first insulating layer 31 and the second insulating layer 32; and the insulating layer 3 of the thin film transistor of the display region includes only The second insulating layer 32. That is to say, at the time of preparation, the second insulating layer 32 can be simultaneously formed in the thin film transistors of the display region and the driving region, and the first insulating layer 31 can be formed only in the thin film transistor of the driving region.
  • the thickness of the second insulating layer 32 of the thin film transistor of the driving region and the display region is equal, and the thin film transistor of the driving region further has the first insulating layer 31, so that the total thickness of the insulating layer 3 of the thin film transistor of the driving region is larger than that of the display region.
  • the thickness of the insulating layer 3 of the thin film transistor is equal, and the thin film transistor of the driving region further has the first insulating layer 31, so that the total thickness of the insulating layer 3 of the thin film transistor of the driving region is larger than that of the display region.
  • the second insulating layer 32 of the thin film transistor of the driving region is preferably located on the first insulating layer 31 (or, for the bottom gate type thin film transistor, the second insulating layer 32 of the thin film transistor of the driving region is opposite to the first insulating layer 32
  • An insulating layer 31 is closer to the active layer 5), which is because such a structure is relatively easy to prepare (described in detail in the following preparation methods).
  • the thickness of the first insulating layer 31 can be easily and independently adjusted, that is, when the thickness of the insulating layer 3 of the thin film transistor of the driving region is to be increased, the film of the display region is not formed. The thickness of the insulating layer 3 of the transistor is affected.
  • the thickness of the insulating layer 3 of the display region can be set to a thickness which does not affect the characteristics of the thin film transistor by stepwise exposure while controlling the thickness of the insulating layer 3 of the thin film transistor of the driving region according to a specific application. That is, the insulating layer 3 in the display region and the driving region can also be formed in one patterning process, but they are set to different thicknesses by step exposure.
  • the thickness of the second insulating layer 32 is The thickness of the first insulating layer 31 can be adjusted according to the application condition of the array substrate, and the thickness is generally set at Wherein, the thickness of the above second insulating layer 32 can make the basic characteristics of the thin film transistor in the display region meet the use requirements, and the thickness of the above first insulating layer 31 can ensure that the insulating layer 3 of the thin film transistor in the driving region is not hit. wear.
  • the embodiment provides a method for fabricating the above array substrate, comprising the steps of forming the insulating layer in a driving region and a display region of the array substrate, wherein a thickness of the insulating layer of the thin film transistor of the driving region is greater than that of the thin film transistor of the display region The thickness of the insulating layer.
  • the array substrate shown in FIG. 3 is prepared by the following steps:
  • a gate metal layer may be deposited on the base substrate 1 by sputtering or thermal evaporation.
  • the material of the gate metal layer may be a metal such as Cr (chromium), W (tungsten), Ta (barium), Mo (molybdenum), Al (aluminum), Cu (copper) or the like and an alloy thereof.
  • a pattern of the gate 2 is formed by a patterning process.
  • the "patterning process” refers to a process of forming a complete film layer first, and then removing a part of the film layer to make the remaining film layer a desired pattern.
  • the removing step is performed by "lithography”
  • the photolithography generally comprises the steps of: coating a photoresist (ie, forming a photoresist layer covering the entire film layer); and exposing (using a mask)
  • the film plate illuminates a portion of the photoresist layer to change the properties of the photoresist layer at these locations; development (removing the portion of the photoresist layer that is illuminated or unilluminated, causing a portion of the film layer Exposure); etching (removing part of the film layer not covered by the photoresist layer, that is, achieving the effect of "removing a portion of the film layer”); and stripping the photoresist (removing the remaining photoresist layer, The remaining film is exposed and forms the desired pattern).
  • the material of the first insulating layer 31 may be deposited on the substrate 1 through the step S01 by a plasma enhanced chemical vapor deposition (PECVD) method, and then the first insulating layer 31 may be formed by a patterning process.
  • the material of the first insulating layer 31 may be an oxide or a nitride or an oxynitride.
  • the first insulating layer 31 is formed first because:
  • the display region and the driving region have the second insulating layer 32, but only the first insulating layer 31 is formed in the driving region, that is, the first insulating layer is formed.
  • the first insulating layer 31 is formed in the driving region, that is, the first insulating layer is formed.
  • the layer 32 is such that in the etching step, the material of the first insulating layer 31 in the display region cannot be removed separately without damaging the formed second insulating layer 32 (because the materials of the insulating layer are similar or identical, etching is performed) Will be removed together).
  • a material of the second insulating layer 32 may be deposited on the substrate 1 through the step S02 by a plasma enhanced chemical vapor deposition (PECVD) method, and then the second insulating layer 32 may be formed by a patterning process.
  • the material of the second insulating layer 32 may be an oxide or a nitride or an oxynitride.
  • the same display region mask 9 can be employed, as shown in FIG.
  • the mask shown in FIG. 4 includes a display area mask 9 corresponding to the display area and four drive area masks 8 respectively corresponding to the surrounding drive areas.
  • the display area mask 9 includes a non-patterned blank portion 91 and a pattern portion 92 having a pattern corresponding to the second insulating layer 32 in the display area; and in each step, the display area is respectively made by multiple exposures The photoresist layer forms the desired pattern.
  • the blank portion 91 of the display area mask 9 and the pattern portion 92 each occupies half of the display area, for example, occupying the upper half and the lower half, respectively, as shown in FIG.
  • the patterns of the first insulating layer 31 and the second insulating layer 32 are the same in the driving region, so that they can be prepared using the same driving region masking plate 8.
  • the patterns of the first insulating layer 31 and the second insulating layer 32 are different in the display region (specifically, only the second insulating layer 32 is present in the display region without the first insulating layer 31), therefore, the preparation An insulating layer 31 and a second insulating layer 32 are required to use different display area masks, which leads to an increase in cost.
  • a special display area mask 9 is preferably used.
  • the area mask 9 includes a blank portion 91 (i.e., a portion having no pattern, which may be a portion in which light is completely or completely impermeable) and a pattern portion 92 (i.e., having a second insulating layer 32 in the display region).
  • the portion corresponding to the pattern, the portion of the pattern portion 92 is permeable to light, and the portion is opaque, by two times when each insulating layer is formed (for half of the above blank portion 91 and the pattern portion 92)
  • the display area mask 9 is exposed to achieve the purpose of manufacturing a different pattern in the display area by using one display area mask 9.
  • the method of using the display area mask 9 described above may be:
  • a positive photoresist (commercial product number PR1-2000A) is coated on the material of the first insulating layer 31, and then the display is performed using the blank portion 91 of the display region mask 9.
  • the different positions of the area (such as the upper half and the lower half) are subjected to two exposures (it is to be noted that, during the exposure process, when the display area is exposed by using the blank portion 91 of the display area mask 9, the light is made only The blank portion 91 is passed through without passing through other portions of the reticle.)
  • the four drive regions are then sequentially exposed using four drive region masks 8.
  • the entire substrate is then simultaneously developed, etched, and stripped. Thereby, the material of all the first insulating layers 31 in the display region is removed, and only the material of the first insulating layer 31 exists in the four driving regions except the display region on the substrate.
  • step S02 is completed.
  • the central display region on the array substrate has no pattern (the material of the first insulating layer 31 is etched away), and the driving region located around the periphery forms the first A pattern of an insulating layer 31.
  • the second insulating layer 32 When the second insulating layer 32 is prepared, a positive photoresist is also applied on the material of the second insulating layer 32, and then the pattern portion 92 of the display region mask 9 is used to different positions of the display region (as in the above half
  • the lower half is subjected to two exposures (it is to be noted that, during the exposure process, when the display portion is exposed using the pattern portion 92 of the display region mask 9, light is transmitted only through the pattern portion 92 without Through the other parts of the reticle.)
  • the four drive areas are then sequentially exposed using four drive area masks 8.
  • the entire substrate is then simultaneously developed, etched, and stripped. Thereby, a pattern of the second insulating layer 32 in the display region and a pattern of the second insulating layer 32 in the four driving regions other than the display region are formed.
  • steps S03 is completed.
  • the central display region on the array substrate and the surrounding driving regions form a pattern of the second insulating layer 32.
  • the display area mask 9 and the driving area mask 8 can be spliced together, thereby simultaneously exposing the display area and the driving area; or, the display area mask 9 and the driving area are masked.
  • the diaphragm 8 can also be separated to expose the display area and the drive area, respectively.
  • Steps S02 and S03 since the display area mask 9 including the blank portion 91 and the pattern portion 92 is employed, the thickness of the insulating layer of the thin film transistor obtained in the driving region is larger than the display area without increasing the cost of the mask.
  • the thickness of the insulating layer of the thin film transistor is an insulating layer structure.
  • the thickness of the second insulating layer 32 is The thickness of the first insulating layer 31 can be adjusted according to the application condition of the array substrate, and the thickness is generally set at Wherein, the thickness of the above second insulating layer 32 can make the basic characteristics of the thin film transistor in the display region meet the use requirements, and the thickness of the above first insulating layer 31 can ensure that the insulating layer 3 of the thin film transistor in the driving region is not hit. wear.
  • a material of the active layer 5 may be first deposited on the base substrate 1 subjected to the step S03 by magnetron sputtering, thermal evaporation or other film formation method, and then the pattern of the active layer 5 is formed by a patterning process.
  • a material of the etch stop layer 4 may be deposited on the base substrate 1 subjected to the step S04 by magnetron sputtering, thermal evaporation or other film formation method, and then the etch stop layer 4 is formed by a patterning process. The pattern of the via 7 .
  • a material of the source/drain 6 may be deposited on the substrate 1 through the step S05 by magnetron sputtering, thermal evaporation or other film formation method, and then the source/drain 6 is formed by a patterning process. Graphics.
  • the insulating layer 3 of the thin film transistor of the driving region is obtained without increasing the cost of the mask.
  • the insulating layer structure having a thickness larger than the thickness of the insulating layer 3 of the thin film transistor of the display region.
  • This embodiment provides a display panel including the above array substrate.
  • the embodiment provides a display device including the above display panel.
  • the thickness of the insulating layer of the thin film transistor in the driving region is larger than the thickness of the insulating layer of the thin film transistor in the display region. Therefore, when the electrostatic discharge is generated between the gate and the source/drain of the driving region, the insulating layer can be prevented from being broken, so that the gate and the source/drain are not short-circuited; in addition, the insulating layer is also the storage capacitor (gate) a dielectric layer formed with a capacitance between the source and the drain, since the thickness of the insulating layer of the thin film transistor of the display region is thin, the storage capacitance value of the display region can be maintained or increased; and, at the same time, due to the thin film transistor of the display region Since the thickness of the insulating layer is thin, it does not cause adverse effects such as a decrease in mobility of the thin film transistor in the display region and a shift in threshold voltage value.

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Abstract

一种阵列基板及其制备方法、一种显示面板和一种显示装置。阵列基板、显示面板和显示装置包括显示区域和驱动区域；位于该显示区域和驱动区域中的薄膜晶体管在栅极（2）和有源层（5）之间设有绝缘层（3），且驱动区域的薄膜晶体管的绝缘层的厚度大于显示区域的薄膜晶体管的绝缘层的厚度。驱动区域的栅极（2）和源/漏极（6）产生静电释放时能够防止绝缘层被击穿，因而不会造成栅极（2）和源/漏极（6）短路；同时，由于显示区域的薄膜晶体管的绝缘层厚度较薄，不会造成显示区域的薄膜晶体管的迁移率下降和阈值电压值漂移等不良影响。

Description

阵列基板及其制备方法、显示面板和显示装置 技术领域
本发明属于显示技术领域，具体涉及一种阵列基板及其制备方法，以及包括该阵列基板的一种显示面板和一种显示装置。
背景技术
静电在包括薄膜晶体管在内的阵列基板的制造、封装、测试和使用过程中无处不在，积累的静电荷以几安培或几十安培的电流在纳秒到微秒的时间里释放，瞬间功率高达几百千瓦，放电能量可达毫焦耳，对薄膜晶体管的摧毁强度极大。
所以薄膜晶体管设计中静电保护的设计直接关系到芯片的功能稳定性，极为重要。随着工艺的发展，器件特征尺寸逐渐变小，薄膜晶体管中的绝缘层(位于栅极和有源层之间，也称为栅氧化层或栅极绝缘层)的厚度也成比例地缩小。栅极绝缘层通常由二氧化硅制造，二氧化硅的介电强度近似为8×106V/cm，因此厚度为10nm的栅极绝缘层的击穿电压约为8V左右，尽管该击穿电压比3.3V的电源电压要高一倍多，但是各种因素造成的静电的峰值电压可远超过8V，因此可能造成绝缘层被击穿。而且，随着多晶硅金属化、扩散区金属化、多晶硅与扩散区均金属化等新工艺的使用，器件的寄生电阻减小，防止静电放电的保护能力大大减弱。为适应超大规模集成电路的集成密度和工作速度的不断提高，需要提高薄膜晶体管的静电保护能力。
如图1所示，阵列基板包括用于进行显示的显示区域和位于显示区域周边的驱动区域。其中，在阵列基板的显示区域和驱动区域中均包括位于衬底基板1上的薄膜晶体管，所述薄膜晶体管在栅极2和有源层5之间设有绝缘层3，在有源层5上还设有刻蚀阻挡层4，在刻蚀阻挡层4上设有源/漏极6，该源/漏极6分别通 过过孔7与有源层5电性连接。
阵列基板的驱动区域设有静电防护结构以将静电的电荷释放，但当累积电荷较多时，静电放电流较大，并且会在驱动区域的薄膜晶体管的过孔7处产生静电释放，从而有可能由于绝缘层3被击穿而造成栅极和源/漏极6短路。因此，增加驱动区域的薄膜晶体管的绝缘层3的厚度成为防止静电放电的一个重要措施，但在阵列基板的显示区域的薄膜晶体管中，增加绝缘层3的厚度会造成迁移率下降和阈值电压值漂移等不良的影响，故显示区域中的薄膜晶体管的绝缘层3的厚度不能过大。
现有技术中在采用构图工艺形成如图1所示的阵列基板的绝缘层3(包括显示区域和驱动区域中的绝缘层)时，所用的掩膜板如图2所示，该掩膜板包括与显示区域对应的显示区域掩膜板9和与四周的驱动区域分别对应的四个驱动区域掩膜板8。在曝光时将上述的掩膜板拼接并进行曝光，之后再显影、刻蚀即可同时获得显示区域和驱动区域中绝缘层的图形。
发明内容
本发明的目的是解决现有技术中阵列基板的驱动区域的薄膜晶体管的栅极和源/漏极之间的绝缘层容易被击穿的问题，提供一种防止驱动区域的薄膜晶体管的绝缘层被击穿且能使显示区域的薄膜晶体管保持较好的特性的阵列基板及其制备方法，以及包括该阵列基板的一种显示面板和一种显示装置。
本发明的实施例提供一种阵列基板，其包括用于进行显示的显示区域和位于所述显示区域周边的驱动区域，所述显示区域和所述驱动区域中均包括薄膜晶体管，所述薄膜晶体管均在栅极和有源层之间设有绝缘层，其中，所述驱动区域的薄膜晶体管的绝缘层的厚度大于所述显示区域的薄膜晶体管的绝缘层的厚度。
优选地，所述驱动区域的薄膜晶体管的绝缘层包括第一绝缘层和第二绝缘层；
所述显示区域的薄膜晶体管的绝缘层包括第二绝缘层。
优选地所述驱动区域的薄膜晶体管的第二绝缘层位于第一绝缘层上。
优选地，所述第二绝缘层的厚度为
Figure PCTCN2014086921-appb-000001
至
Figure PCTCN2014086921-appb-000002
所述第一绝缘层的厚度为
Figure PCTCN2014086921-appb-000003
至
Figure PCTCN2014086921-appb-000004
本发明的实施例还提供一种阵列基板的制备方法，其包括在阵列基板的驱动区域和显示区域中形成绝缘层的步骤，其中，
所述显示区域和所述驱动区域中均包括薄膜晶体管，所述绝缘层设于薄膜晶体管的栅极和有源层之间，并且所述驱动区域的薄膜晶体管的绝缘层的厚度大于所述显示区域的薄膜晶体管的绝缘层的厚度。
优选地，所述在阵列基板的驱动区域和显示区域中形成绝缘层的步骤包括：
通过构图工艺形成包括所述驱动区域的薄膜晶体管的第一绝缘层的图形的步骤；以及
通过构图工艺形成包括所述驱动区域和所述显示区域的薄膜晶体管的第二绝缘层的图形的步骤。
优选地，在通过构图工艺形成包括第一绝缘层的图形的步骤和包括第二绝缘层的图形的步骤中，采用同一显示区域掩膜板，该显示区域掩膜板包括无图形的空白部分和具有与所述显示区域中的第二绝缘层的图形相对应的图形部分；且
在通过构图工艺形成包括第一绝缘层的图形的步骤和包括第二绝缘层的图形的步骤中，分别通过多次曝光使所述显示区域中的光刻胶层形成所需图形。
优选地，所述显示区域掩膜板的空白部分和图形部分对称的各占据所述显示区域的一半。
本发明的实施例还提供一种显示面板，其包括上述的阵列基板。
本发明的实施例还提供一种显示装置，其包括上述的显示面板。
本发明的阵列基板、显示面板和显示装置包括显示区域和驱 动区域，且驱动区域中的薄膜晶体管的绝缘层的厚度大于显示区域中的薄膜晶体管的绝缘层的厚度。因此，在驱动区域的栅极和源/漏极之间产生静电释放时能够防止绝缘层被击穿，因而不会造成栅极和源/漏极短路；另外，绝缘层也是存储电容(栅极和源/漏极间形成的电容)的介质层，由于显示区域的薄膜晶体管的绝缘层的厚度较薄，因此可以保持或增大显示区域的存储电容值；同时，由于显示区域的薄膜晶体管的绝缘层的厚度较薄，故不会造成显示区域的薄膜晶体管的迁移率下降和阈值电压值漂移等不良的影响。
附图说明
图1为现有技术中的阵列基板的薄膜晶体管的结构的示意剖面图。
图2为现有技术中制备阵列基板的绝缘层时所用的掩膜板的结构示意图。
图3为根据本发明第一实施例的一种阵列基板的显示区域和驱动区域的薄膜晶体管的结构的示意剖面图。
图4为根据本发明第二实施例的一种形成阵列基板的薄膜晶体管的绝缘层所用的掩膜板的示意图。
图5为根据本发明第二实施例的一种阵列基板在形成第一绝缘层图形后的俯视示意图。
图6为根据本发明第二实施例的一种阵列基板在形成第二绝缘层图形后的俯视示意图第二实施例。
其中，附图标记为：
1.衬底基板；2.栅极；3.绝缘层；31.第一绝缘层；32.第二绝缘层；4.刻蚀阻挡层；5.有源层；6.源/漏极；7.过孔；8.驱动区域掩膜板；9.显示区域掩膜板；91.空白部分；92.图形部分。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结 合附图和具体实施方式对本发明作进一步详细描述。
需要说明的是，本发明中所称的图形指的是通过构图工艺形成的各种结构；
第一实施例
图3为根据本实施例的一种阵列基板的显示区域和驱动区域的薄膜晶体管的结构的示意剖面图。
如图3所示，本实施例的阵列基板包括用于进行显示的显示区域和位于显示区域周边的驱动区域，显示区域和驱动区域中均包括薄膜晶体管；薄膜晶体管在栅极2和有源层5之间设有绝缘层3，且驱动区域的薄膜晶体管的绝缘层3的厚度大于显示区域的薄膜晶体管的绝缘层3的厚度。
由于本实施例的阵列基板中，驱动区域的薄膜晶体管的绝缘层3的厚度大于显示区域的薄膜晶体管的绝缘层3的厚度，故在驱动区域的栅极2和源/漏极6之间产生静电释放时能够防止绝缘层3被击穿，因而不会造成栅极和源/漏极短路；另外，绝缘层3也是存储电容(栅极和源/漏极间形成的电容)的介质层，由于显示区域的薄膜晶体管的绝缘层3的厚度较薄，因此可以保持或增大显示区域的存储电容值；同时，由于显示区域的薄膜晶体管的绝缘层3的厚度较薄，故不会造成显示区域的薄膜晶体管的迁移率下降和阈值电压值漂移等不良的影响。
具体地，如图3所示，以底栅型薄膜晶体管为例具体介绍本发明。但应当理解，本发明对顶栅型薄膜晶体管也是适用的。
阵列基板包括衬底基板1，在衬底基板1上设有栅极2，在栅极2上设有绝缘层3，在绝缘层3上设有有源层5，在有源层5上设有刻蚀阻挡层4，在刻蚀阻挡层4上同层间隔设置源/漏极6，源/漏极6分别通过设置在刻蚀阻挡层4中的过孔7与有源层5连接。需要重点说明的是，其中，驱动区域的薄膜晶体管的绝缘层3的总厚度大于显示区域的薄膜晶体管的绝缘层3的厚度。
当然，阵列基板中还可包括栅极线、数据线、像素电极等其 他的已知结构，在此不再详细描述。
具体地，作为本发明实施例的一种优选方式，驱动区域的薄膜晶体管的绝缘层3可包括第一绝缘层31和第二绝缘层32；而显示区域的薄膜晶体管的绝缘层3则只包括第二绝缘层32。也就说，在制备时，可同时在显示区域和驱动区域的薄膜晶体管中形成第二绝缘层32，而只在驱动区域的薄膜晶体管中形成第一绝缘层31。这样驱动区域和显示区域的薄膜晶体管的第二绝缘层32的厚度相等，而驱动区域的薄膜晶体管还具有第一绝缘层31，所以驱动区域的薄膜晶体管的绝缘层3的总厚度大于显示区域的薄膜晶体管的绝缘层3的厚度。
如图3所示，驱动区域的薄膜晶体管的第二绝缘层32优选位于第一绝缘层31上(或者说，对于底栅型的薄膜晶体管，驱动区域的薄膜晶体管的第二绝缘层32相对第一绝缘层31更靠近有源层5)，之所以如此，是因为这样的结构比较容易制备(在以下的制备方法中再详细描述)。
通过设置单独的第二绝缘层32，可使第一绝缘层31的厚度能够被方便地独立调节，即当要增加驱动区域的薄膜晶体管的绝缘层3的厚度时，不会对显示区域的薄膜晶体管的绝缘层3的厚度造成影响。
当然，也可以通过阶梯曝光将显示区域的绝缘层3的厚度设置为不影响薄膜晶体管特性的厚度，而同时根据具体应用情况来控制驱动区域的薄膜晶体管的绝缘层3的厚度。也就是说，显示区域和驱动区域中的绝缘层3也可在一次构图工艺中形成，但要通过阶梯曝光将它们设置为不同的厚度。
优选地，第二绝缘层32的厚度为
Figure PCTCN2014086921-appb-000005
而第一绝缘层31的厚度可根据阵列基板的应用情况不同进行调整，一般厚度设置在
Figure PCTCN2014086921-appb-000006
其中，以上第二绝缘层32的厚度可以使显示区域中的薄膜晶体管的基本特征满足使用要求，而以上第一绝缘层31的厚度则可保证驱动区域中的薄膜晶体管的绝缘层3不被击穿。
第二实施例
本实施例提供一种上述阵列基板的制备方法，包括在阵列基板的驱动区域和显示区域中形成上述绝缘层的步骤，其中，驱动区域的薄膜晶体管的绝缘层的厚度大于显示区域的薄膜晶体管的绝缘层的厚度。
具体地，采用以下步骤制备如图3所示的阵列基板：
S01.在衬底基板1上形成栅极2
可以采用溅射或热蒸发的方法在衬底基板1上沉积一层栅金属层。栅金属层的材料可以是Cr(铬)、W(钨)、Ta(钽)、Mo(钼)、Al(铝)、Cu(铜)等金属及其合金。通过构图工艺形成栅极2的图形。
其中，“构图工艺”是指先形成完整的膜层，之后通过除去该膜层的一部分从而使剩余膜层成为所需的图形的工艺。具体地，其中的除去步骤是通过“光刻”实现的，而光刻通常包括以下的步骤：涂布光刻胶(即形成覆盖以上膜层的整体的光刻胶层)；曝光(利用掩膜板对光刻胶层的部分区域进行光照，从而使这些位置的光刻胶层性质发生变化)；显影(除去光刻胶层中被光照的部分或未被光照的部分，使部分膜层暴露)；刻蚀(除去没有被光刻胶层覆盖的部分膜层，也就是达到“除去该膜层的一部分”的效果)；以及光刻胶剥离(将剩余的光刻胶层除去，使剩余的膜层暴露并形成所需图形)。
S02.在衬底基板1上形成第一绝缘层31
可以采用等离子体增强化学气相沉积(PECVD)方法，在经过步骤S01的衬底基板1上沉积第一绝缘层31的材料，然后通过构图工艺形成第一绝缘层31。其中，第一绝缘层31的材料可以选用氧化物或者氮化物或者氮氧化物。
之所以先形成第一绝缘层31，是因为：
根据本发明的实施例，显示区域和驱动区域中都有第二绝缘层32，但只在驱动区域中形成第一绝缘层31，即在形成第一绝缘 层31时，必须包括除去显示区域中的全部第一绝缘层31的材料的步骤。因此，若先形成第二绝缘层32(其在显示区域和驱动区域中都有)，则在制备第一绝缘层31时，第一绝缘层31的材料必然要覆盖显示区域中的第二绝缘层32，这样在刻蚀步骤中，就无法单独将显示区域中的第一绝缘层31的材料除去而不损伤已形成的第二绝缘层32(因为绝缘层的材料相似或相同，故刻蚀时会被一同除去)。
S03.在衬底基板1上形成第二绝缘层32
具体地，可以采用等离子体增强化学气相沉积(PECVD)方法，在经过步骤S02的衬底基板1上沉积第二绝缘层32的材料，然后通过构图工艺形成第二绝缘层32。其中，第二绝缘层32的材料可以选用氧化物或者氮化物或者氮氧化物。
优选地，在本步骤以及以上形成第一绝缘层31的步骤中，可采用同一显示区域掩膜板9，如图4所示。图4所示的掩膜板包括与显示区域对应的显示区域掩膜板9和与四周的驱动区域分别对应的四个驱动区域掩膜板8。该显示区域掩膜板9包括无图形的空白部分91和具有与显示区域中的第二绝缘层32的图形相对应的图形部分92；且每个步骤中，分别通过多次曝光使显示区域中的光刻胶层形成所需图形。
更优选地，显示区域掩膜板9的空白部分91和图形部分92对称的各占据显示区域的一半，例如，如图4所示分别占据上半部和下半部。
按照本发明的实施例，在驱动区域中，第一绝缘层31和第二绝缘层32的图形是一样的，故它们的制备可使用同样的驱动区域掩膜板8。
但与现有技术不同，在显示区域中第一绝缘层31和第二绝缘层32的图形不同(具体为显示区域中只有第二绝缘层32而无第一绝缘层31)，因此，制备第一绝缘层31和第二绝缘层32时需要使用不同的显示区域掩膜板，而这会导致成本提升。
为此，本实施例中优选使用特殊的显示区域掩膜板9，该显 示区域掩膜板9包括空白部分91(即无图形的部分，可为光可完全透过或完全不透过的部分)和图形部分92(即具有与显示区域中的第二绝缘层32的图形相对应的部分，图形部分92的部分位置可透光，部分位置不透光)，通过在形成每个绝缘层时两次(针对以上空白部分91和图形部分92各占一半的情况)用该显示区域掩膜板9进行曝光，即可实现用一个显示区域掩膜板9来制造显示区域中不同图形的目的。
具体地，使用上述显示区域掩膜板9的方法可为：
在制备第一绝缘层31时，在第一绝缘层31的材料上涂布正性光刻胶(市售商品号为PR1-2000A)，然后使用显示区域掩膜板9的空白部分91对显示区域的不同位置(如上半部和下半部)进行两次曝光(需要说明的是，在曝光制程过程中，在使用显示区域掩模版9的空白部分91对显示区域进行曝光时，使光只透过该空白部分91，而不透过掩模版上的其他部分。)然后使用四个驱动区域掩膜板8依次对四个驱动区域进行曝光。然后对整个衬底基板同时进行显影、刻蚀和剥离。从而实现除去显示区域中的全部第一绝缘层31的材料，只在衬底基板上除了显示区域以外的四个驱动区域中存在该第一绝缘层31的材料。从而步骤S02完成。
如图5所示，在阵列基板上完成第一绝缘层31构图工艺后，阵列基板上位于中心的显示区域没有图形(刻蚀掉第一绝缘层31的材料)，位于四周的驱动区域形成第一绝缘层31的图形。
在制备第二绝缘层32时，同样在第二绝缘层32的材料上涂布正性光刻胶，然后使用显示区域掩膜板9的图形部分92对显示区域的不同位置(如上半部和下半部)进行两次曝光(需要说明的是，在曝光制程过程中，在使用显示区域掩模版9的图形部分92对显示区域进行曝光时，使光只透过该图形部分92，而不透过掩模版上的其他部分。)然后使用四个驱动区域掩膜板8依次对四个驱动区域进行曝光。然后对整个衬底基板同时进行显影、刻蚀和剥离。从而形成显示区域中的第二绝缘层32的图形和除了显示区域以外的四个驱动区域中的第二绝缘层32的图形。从而步骤 S03完成。
如图6所示，在阵列基板上完成第二绝缘层32的图形的构图工艺后，阵列基板上位于中心的显示区域和位于四周的驱动区域形成第二绝缘层32的图形。
应当理解，以上所述的是显示区域掩膜板9的空白部分91和图形部分92各占显示区域的一半情况，但若二者的比例不同，也是可行的，只是其中一个步骤中可能需要更多次的曝光而已。
同时，上述的曝光过程中，显示区域掩膜板9和驱动区域掩膜板8可拼接在一起，从而同时实现对显示区域和驱动区域的曝光；或者，显示区域掩膜板9和驱动区域掩膜板8也可分开，从而分别用于对显示区域和驱动区域进行曝光。
步骤S02和S03由于采用了包括空白部分91和图形部分92在内的显示区域掩膜板9，在不增加掩膜板成本的条件下获得了驱动区域的薄膜晶体管的绝缘层的厚度大于显示区域的薄膜晶体管的绝缘层的厚度的绝缘层结构。
优选地，第二绝缘层32的厚度为
Figure PCTCN2014086921-appb-000007
而第一绝缘层31的厚度可根据阵列基板的应用情况不同进行调整，一般厚度设置在
Figure PCTCN2014086921-appb-000008
其中，以上第二绝缘层32的厚度可以使显示区域中的薄膜晶体管的基本特征满足使用要求，而以上第一绝缘层31的厚度则可保证驱动区域中的薄膜晶体管的绝缘层3不被击穿。
S04.在衬底基板1上形成有源层5
具体地，可以先在经过步骤S03的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层有源层5的材料，然后通过构图工艺形成有源层5的图形。
S05.在衬底基板1上形成刻蚀阻挡层4
具体地，可以先在经过步骤S04的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层刻蚀阻挡层4的材料，然后通过构图工艺形成刻蚀阻挡层4和过孔7的图形。
S06.在衬底基板1上形成源/漏极6
具体地，可以先在经过步骤S05的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层源/漏极6的材料，然后通过构图工艺形成源/漏极6的图形。
可选地，可以继续形成其它必要的功能层，在此不再一一赘述。
本发明的阵列基板的制备方法中由于采用了包括空白部分91和图形部分92的显示区域掩膜板9，故在不增加掩膜板成本的条件下获得了驱动区域的薄膜晶体管的绝缘层3的厚度大于显示区域的薄膜晶体管的绝缘层3的厚度的绝缘层结构。
第三实施例
本实施例提供一种显示面板，该显示面板包括上述的阵列基板。
第四实施例
本实施例提供一种显示装置，该显示装置包括上述的显示面板。
本发明的显示面板和显示装置中，驱动区域中的薄膜晶体管的绝缘层的厚度大于显示区域中的薄膜晶体管的绝缘层的厚度。因此，在驱动区域的栅极和源/漏极之间产生静电释放时能够防止绝缘层被击穿，因而不会造成栅极和源/漏极短路；另外，绝缘层也是存储电容(栅极和源/漏极间形成的电容)的介质层，由于显示区域的薄膜晶体管的绝缘层的厚度较薄，因此可以保持或增大显示区域的存储电容值；同时，由于显示区域的薄膜晶体管的绝缘层的厚度较薄，故不会造成显示区域的薄膜晶体管的迁移率下降和阈值电压值漂移等不良的影响。
应当理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域技术人员而言，在不脱离本发明的精神和实质的情况下，可以 做出各种变型和改进，这些变型和改进也属于本发明的保护范围。

Claims (10)

  1. 一种阵列基板，包括用于进行显示的显示区域和位于所述显示区域周边的驱动区域，所述显示区域和所述驱动区域中均包括薄膜晶体管，所述薄膜晶体管均在栅极和有源层之间设有绝缘层，其中，
    所述驱动区域的薄膜晶体管的绝缘层的厚度大于所述显示区域的薄膜晶体管的绝缘层的厚度。
  2. 如权利要求1所述的阵列基板，其中，
    所述驱动区域的薄膜晶体管的绝缘层包括第一绝缘层和第二绝缘层；
    所述显示区域的薄膜晶体管的绝缘层包括第二绝缘层。
  3. 如权利要求2所述的阵列基板，其中，
    所述驱动区域的薄膜晶体管的第二绝缘层位于第一绝缘层上。
  4. 如权利要求2所述的阵列基板，其中，
    所述第二绝缘层的厚度为
    Figure PCTCN2014086921-appb-100001
    至
    Figure PCTCN2014086921-appb-100002
    所述第一绝缘层的厚度为
    Figure PCTCN2014086921-appb-100003
    至
    Figure PCTCN2014086921-appb-100004
  5. 一种阵列基板的制备方法，包括在阵列基板的驱动区域和显示区域中形成绝缘层的步骤，其中，
    所述显示区域和所述驱动区域中均包括薄膜晶体管，所述绝缘层设于所述薄膜晶体管的栅极和有源层之间，并且所述驱动区域的薄膜晶体管的绝缘层的厚度大于所述显示区域的薄膜晶体管的绝缘层的厚度。
  6. 如权利要求5所述的阵列基板的制备方法，其中，所述在 阵列基板的驱动区域和显示区域中形成绝缘层的步骤包括：
    通过构图工艺形成包括所述驱动区域的薄膜晶体管的第一绝缘层的图形的步骤；以及
    通过构图工艺形成包括所述驱动区域和所述显示区域的薄膜晶体管的第二绝缘层的图形的步骤。
  7. 如权利要求6所述的阵列基板的制备方法，其中，
    在通过构图工艺形成包括第一绝缘层的图形的步骤和包括第二绝缘层的图形的步骤中，采用同一显示区域掩膜板，该显示区域掩膜板包括无图形的空白部分和具有与所述显示区域中的第二绝缘层的图形相对应的图形部分；且
    在通过构图工艺形成包括第一绝缘层的图形的步骤和包括第二绝缘层的图形的步骤中，分别通过多次曝光使所述显示区域中的光刻胶层形成所需图形。
  8. 如权利要求7所述的阵列基板的制备方法，其中，所述显示区域掩膜板的空白部分和图形部分对称的各占据所述显示区域的一半。
  9. 一种显示面板，包括如权利要求1至4中任意一项所述的阵列基板。
  10. 一种显示装置，包括如权利要9所述的显示面板。
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