US20160247833A1 - Array substrate, manufacturing method thereof, display panel and display device - Google Patents

Array substrate, manufacturing method thereof, display panel and display device Download PDF

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Publication number
US20160247833A1
US20160247833A1 US14/443,542 US201414443542A US2016247833A1 US 20160247833 A1 US20160247833 A1 US 20160247833A1 US 201414443542 A US201414443542 A US 201414443542A US 2016247833 A1 US2016247833 A1 US 2016247833A1
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insulation layer
display area
thin film
film transistor
area
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Cuili GAI
Xiaodi LIU
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BOE Technology Group Co Ltd
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Assigned to BOE TECHNOLOGY GROUP CO., LTD. reassignment BOE TECHNOLOGY GROUP CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: Liu, Xiaodi, GAI, CUILI
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

Definitions

  • the present invention belongs to the field of display technology, and particularly relates to an array substrate, a manufacturing method thereof, a display panel including the array substrate and a display device.
  • Static electricity exists everywhere during manufacturing, packaging, testing and using an array substrate including thin film transistors, accumulated electrostatic charges are released within nanoseconds to microseconds in the current of several amperes or tens of amperes, the instantaneous power is up to hundreds of kilowatts, and the discharge energy can reach millijoule, so that the destruction strength on the thin film transistors is very large.
  • an electrostatic protection design in the thin film transistor design directly relates to the stability of the function of a chip and is very important.
  • the gate insulation layer is usually made from silicon dioxide, the dielectric strength of which is approximately 8 ⁇ 10 6 V/cm, thus the breakdown voltage of the gate insulation layer with a thickness of 10 nm is about 8 V.
  • breakdown voltage is more than twice of 3.3 V supply voltage, the peak voltage of static electricity caused by all kinds of factors can be far higher than 8V, so that the insulation layer may be broken down.
  • the parasitic resistance of the device is reduced, so that the protection capacity of preventing electrostatic discharge is greatly weakened.
  • the electrostatic protection for the thin film transistor needs to be improved.
  • an array substrate includes a display area for displaying and a driving area located around the display area.
  • thin film transistors located on a base substrate 1 are provided in both the display area and the driving area of the array substrate, each thin film transistor is provided with an insulation layer 3 between a gate electrode 2 and an active layer 5 , an etching stop layer 4 is further arranged on the active layer 5 , source/drain electrodes 6 are arranged on the etching stop layer 4 , and the source/drain electrodes 6 are electrically connected with the active layer 5 through vias 7 , respectively.
  • An electrostatic protection structure is arranged in the driving area of the array substrate to release the electrostatic charges, but when too many charges are accumulated, the electrostatic discharge current is quite large and will cause electrostatic discharge at the vias 7 of the thin film transistor in the driving area, so that the gate electrode and the source/drain electrodes 6 may be short circuited due to the breakdown of the insulation layer 3 . Therefore, increasing the thickness of the insulation layer 3 of the thin film transistor in the driving area becomes an important measure for preventing electrostatic discharge, but in the thin film transistor in the display area of the array substrate, adverse effects such as a reduced migration rate and threshold voltage drift will be caused due to the increased thickness of the insulation layer 3 , so the thickness of the insulation layer 3 of the thin film transistor in the display area cannot be too large.
  • the insulation layer 3 including the insulation layers in the display area and the driving area of the array substrate as shown in FIG. 1
  • a used mask is shown in FIG. 2 , and the mask includes a display area mask 9 corresponding to the display area and four driving area masks 8 corresponding to the surrounding driving areas respectively.
  • the above-mentioned masks are spliced and exposure is carried out, and then development and etching are performed to simultaneously obtain patterns of the insulation layers in the display area and the driving areas.
  • the object of the present invention is to provide an array substrate, a manufacturing method thereof, a display panel including the array substrate, and a display device, which can prevent the insulation layer of the thin film transistor in a driving area from being broken down and can well maintain properties of the thin film transistor in a display area.
  • Embodiments of the present invention provide an array substrate, including a display area for displaying and a driving area located around the display area, wherein thin film transistors are provided in both the display area and the driving area, and the thin film transistors are provided with insulation layers between gate electrodes and active layers, wherein a thickness of the insulation layer of the thin film transistor in the driving area is larger than a thickness of the insulation layer of the thin film transistor in the display area.
  • the insulation layer of the thin film transistor in the driving area includes a first insulation layer and a second insulation layer
  • the insulation layer of the thin film transistor in the display area includes the second insulation layer.
  • the second insulation layer of the thin film transistor in the driving area is located on the first insulation layer.
  • a thickness of the second insulation layer is 1000-3000 ⁇ .
  • a thickness of the first insulation layer is 2000-6000 ⁇ .
  • the embodiments of the present invention further provide a manufacturing method of an array substrate, including a step of forming insulation layers in a driving area and a display area of the array substrate, wherein
  • thin film transistors are provided in both the display area and the driving area; a insulation layers are arranged between gate electrodes and active layers of the thin film transistors; and a thickness of the insulation layer of the thin film transistor in the driving area is larger than the thickness of the insulation layer of the thin film transistor in the display area.
  • the step of forming the insulation layers in the driving area and the display area of the array substrate includes:
  • a step of forming a pattern including a second insulation layer of the thin film transistors in the driving area and the display area through a patterning process is a step of forming a pattern including a second insulation layer of the thin film transistors in the driving area and the display area through a patterning process.
  • the same display area mask is adopted, and the display area mask includes a blank part without a pattern and a pattern part with a pattern corresponding to the second insulation layer in the display area;
  • a photoresist layer in the display area is exposed for multiple times to form the pattern required.
  • the blank part and the pattern part of the display area mask each symmetrically occupy a half of the display area respectively.
  • the embodiments of the present invention further provide a display panel, including the above-mentioned array substrate.
  • the embodiments of the present invention further provide a display device, including the above-mentioned display panel.
  • the array substrate, the display panel and the display device of the present invention include the display area and the driving area, and the thickness of the insulation layer of the thin film transistor in the driving area is larger than the thickness of the insulation layer of the thin film transistor in the display area. Therefore, when electrostatic discharge occurs between the gate electrode and the source/drain electrodes of the driving area, breakdown of the insulation layer can be prevented, thereby resulting in no short circuit of the gate electrode and the source/drain electrodes; in addition, the insulation layer is also a dielectric layer for a storage capacitor (the capacitor formed between the gate electrode and the source/drain electrodes), and since the thickness of the insulation layer of the thin film transistor in the display area is small, the storage capacitance of the display area can be maintained or increased; meanwhile, since the thickness of the insulation layer of the thin film transistor in the display area is small, adverse effects such as a reduced migration rate and threshold voltage drift of the thin film transistor in the display area will not be caused.
  • FIG. 1 is a schematic sectional view of a structure of a thin film transistor of an array substrate in the prior art.
  • FIG. 2 is a schematic diagram of a structure of a mask used for preparing an insulation layer of an array substrate in the prior art.
  • FIG. 3 is a schematic sectional view of structures of thin film transistors in a display area and a driving area of an array substrate according to a first embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a mask used for forming an insulation layer of a thin film transistor of an array substrate according to a second embodiment of the present invention.
  • FIG. 5 is a schematic top view of an array substrate according to the second embodiment of the present invention after formation of a pattern of a first insulation layer.
  • FIG. 6 is a schematic top view of the array substrate according to the second embodiment of the present invention after formation a pattern of a second insulation layer.
  • the so called patterns in the present invention refer to various structures formed by a patterning process.
  • FIG. 3 is a schematic sectional view of structures of thin film transistors of a display area and a driving area of an array substrate according to the embodiment of the present invention.
  • the array substrate in the embodiment includes a display area for displaying and a driving area located around the display area, wherein thin film transistors are provided in both the display area and the driving area; the thin film transistors are provided with insulation layers 3 between gate electrodes 2 and active layers 5 , and a thickness of the insulation layer 3 of the thin film transistor in the driving area is larger than a thickness of the insulation layer 3 of the thin film transistor in the display area.
  • the insulation layer 3 of the thin film transistor in the driving area is larger than the thickness of the insulation layer 3 of the thin film transistor in the display area, breakdown of the insulation layer 3 can be prevented when electrostatic discharge occurs between the gate electrode 2 and source/drain electrodes 6 of the driving area, thereby resulting in no short circuit of the gate electrode and the source/drain electrodes;
  • the insulation layer 3 is also a dielectric layer for a storage capacitor (the capacitor formed between the gate electrode and the source/drain electrodes), and since the thickness of the insulation layer 3 of the thin film transistor in the display area is small, the storage capacitance of the display area can be maintained or increased; meanwhile, since the thickness of the insulation layer 3 of the thin film transistor in the display area is small, adverse effects such as a reduced migration rate and threshold voltage drift of the thin film transistor in the display area will not be caused.
  • the present invention is specifically described with a bottom gate type thin film transistor as an example. However, it should be understood that the present invention is also applicable to top gate type thin film transistors.
  • the array substrate includes a base substrate 1 , wherein the gate electrode 2 is arranged on the base substrate 1 ; the insulation layer 3 is arranged on the gate electrode 2 ; the active layer 5 is arranged on the insulation layer 3 ; an etching stop layer 4 is arranged on the active layer 5 ; the source/drain electrodes 6 are arranged on the etching stop layer 4 in a same layer at interval; and the source/drain electrodes 6 are electrically connected with the active layer 5 through vias 7 formed in the etching stop layer 4 , respectively. It is important to note that the total thickness of the insulation layers 3 of the thin film transistor in the driving area is larger than the thickness of the insulation layer 3 of the thin film transistor in the display area.
  • the array substrate can further include other known structures, such as a gate line, a data line, a pixel electrode and the like, and no detailed description will be given herein.
  • the insulation layer 3 of the thin film transistor in the driving area may include a first insulation layer 31 and a second insulation layer 32 , while the insulation layer 3 of the thin film transistor in the display area only includes a second insulation layer 32 . That is to say, during preparation, the second insulation layers 32 can be simultaneously formed in the thin film transistors in the display area and the driving area, and the first insulation layer 31 is only formed in the thin film transistor in the driving area.
  • the thicknesses of the second insulation layers 32 of the thin film transistors in the display area and the driving area are equal, and the first insulation layer 31 is further formed in the thin film transistor in the driving area, so the total thickness of the insulation layer 3 of the thin film transistor in the driving area is larger than the thickness of the insulation layer 3 of the thin film transistor in the display area.
  • the second insulation layer 32 of the thin film transistor in the driving area is preferably located on the first insulation layer 31 (or, for the bottom gate type thin film transistor, the second insulation layer 32 of the thin film transistor in the driving area is closer to the active layer 5 than the first insulation layer 31 ), and this is because such a structure is relatively easy to manufacture (a detailed description will be given in the following manufacturing method).
  • the thickness of the first insulation layer 31 can be independently adjusted conveniently, namely, when the thickness of the insulation layer 3 of the thin film transistor in the driving area is to be increased, no influence is generated on the thickness of the insulation layer 3 of the thin film transistor in the display area.
  • the insulation layer 3 in the display area can also be configured by gradient exposure to have such a thickness that does not affect the property of the thin film transistor, and meanwhile the thickness of the insulation layer 3 of the thin film transistor in the driving area can be controlled according to specific application conditions. That is to say, the insulation layers 3 in the display area and the driving area can also be formed in one patterning process, but need to be configured by gradient exposure to have different thicknesses.
  • the thickness of the second insulation layer 32 is 1000-3000 ⁇ , while the thickness of the first insulation layer 31 can be adjusted according to different application conditions of the array substrate and is generally set to 2000-6000 ⁇ .
  • the thickness of the second insulation layer 32 can make basic features of the thin film transistor in the display area meet the application requirements, and the thickness of the first insulation layer 31 can ensure that the insulation layer 3 of the thin film transistor in the driving area is not broken down.
  • the embodiment provides a manufacturing method of the above-mentioned array substrate, including a step of forming the above-mentioned insulation layers in the driving area and the display area of the array substrate, wherein the thickness of the insulation layer of the thin film transistor in the driving area is larger than the thickness of the insulation layer of the thin film transistor in the display area.
  • the array substrate as shown in FIG. 3 is manufactured in the following steps:
  • a gate metal layer may be deposited on the base substrate 1 in a sputtering or thermal evaporation method.
  • the material of the gate metal layer can be metals such as Cr (chromium), W (wolframium), Ta (tantalum), Mo (molybdenum), Al (aluminum), Cu (copper) and alloys thereof.
  • a pattern of the gate electrode 2 is formed by a patterning process.
  • the “patterning process” refers to a process of firstly forming a complete film layer and then removing a part of the film layer to enable the remaining film layer to form the pattern required.
  • the removal step therein is achieved by photoetching, and the photoetching usually includes the following steps: coating a photoresist (namely, forming an integral photoresist layer covering the above film layer); exposing (illuminating a part of the area of the photoresist layer by using a mask to change the properties of the photoresist layers on these positions); developing (removing the illuminated part or non-illuminated part in the photoresist layer to expose a part of the film layer); etching (removing the part of the film layer uncovered by the photoresist layer, namely achieving the effect of “removing a part of the film layer”); and stripping the photoresist (removing the remaining photoresist layer, to expose the remaining film layer and form the pattern required).
  • a material of the first insulation layer 31 may be deposited on the base substrate 1 processed in step S 01 by using a plasma enhanced chemical vapor deposition (PECVD) method, and then the first insulation layer 31 is formed by a patterning process.
  • the material of the first insulation layer 31 may be an oxide or a nitride or an oxynitride.
  • the second insulation layers 32 are formed in both the display area and the driving area, but the first insulation layer 31 is only formed in the driving area, namely, when the first insulation layer 31 is formed, a step of removing the material of the entire first insulation layer 31 in the display area must be included. Therefore, if the second insulation layers 32 (which are formed in both the display area and the driving area) are formed at first, when the first insulation layer 31 is prepared, the material of the first insulation layer 31 inevitably covers the second insulation layer 32 in the display area, so that in the etching step, the material of the first insulation layer 31 in the display area cannot be separately removed without damaging the formed second insulation layer 32 (because the materials of the insulation layers are similar or same, thus the insulation layers will be removed together when being etched).
  • a material of the second insulation layer 32 may be deposited on the base substrate 1 processed in step S 02 by using the plasma enhanced chemical vapor deposition (PECVD) method, and then the second insulation layer 32 is formed by a patterning process.
  • the material of the second insulation layer 32 may be an oxide or a nitride or an oxynitride.
  • the same display area mask 9 can be adopted, as shown in FIG. 4 .
  • the mask shown in FIG. 4 includes the display area mask 9 corresponding to the display area and four driving area masks 8 corresponding to the surrounding driving areas respectively.
  • the display area mask 9 includes a blank part 91 without a pattern and a pattern part 92 with a pattern corresponding to the second insulation layer 32 in the display area; and in each step, the photoresist layer in the display area is exposed for multiple times to form the pattern required.
  • the blank part 91 and the pattern part 92 of the display area mask 9 each symmetrically occupy a half of the display area respectively, for example, as shown in FIG. 4 , respectively occupy the upper half part and the lower half part.
  • the patterns of the first insulation layer 31 and the second insulation layer 32 are same, and thus they can be prepared by using the same driving area mask 8 .
  • the patterns of the first insulation layer 31 and the second insulation layer 32 are different in the display area (specifically in the display area, only the second insulation layer 32 is formed, and no first insulation layer 31 is formed), therefore, in preparation of the first insulation layer 31 and the second insulation layer 32 , different display area masks need to be used, which increases the cost.
  • a special display area mask 9 is preferably used in the embodiment, the display area mask 9 including the blank part 91 (namely, a part without a pattern, and can be a part which is completely light transmissive or completely light tight) and the pattern part 92 (namely, a part with a pattern corresponding to the second insulation layer 32 in the display area; a part of positions of the pattern part 92 is light transmissive and a part of positions is light tight), and the display area mask 9 is used twice for exposure in formation of each insulation layer (in the case where the blank part 91 and the pattern part 92 each occupy a half respectively), to achieve the purpose of preparing different patterns in the display area by using the one display area mask 9 .
  • the method of using the above-mentioned display area mask 9 may be as the follows.
  • step S 02 is completed.
  • no pattern (the material of the first insulation layer 31 is etched off) is formed in the display area located at the center on the array substrate, and the pattern of the first insulation layer 31 is formed in the surrounding driving areas.
  • step S 03 is completed.
  • the pattern of the second insulation layers 32 are formed in the display area at the center of the array substrate and the driving areas surrounding the display area.
  • the blank part 91 and the pattern part 92 of the display area mask 9 each respectively occupy a half of the display area, but it is also feasible if the proportions of the two parts are different, but more times of exposure may be needed in one step.
  • the display area mask 9 and the driving area masks 8 may be spliced together, in order to simultaneously expose the display area and the driving areas; or, the display area mask 9 and the driving area masks 8 may also be separated, in order to respectively expose the display area and the driving areas.
  • steps S 02 and S 03 since the display area mask 9 including the blank part 91 and the pattern part 92 is adopted, an insulation layer structure, in which the thickness of the insulation layer of the thin film transistor in the driving area is larger than the thickness of the insulation layer of the thin film transistor in the display area, is obtained without increasing the cost of the mask.
  • the thickness of the second insulation layer 32 is 1000-3000 ⁇ , while the thickness of the first insulation layer 31 can be adjusted according to different application conditions of the array substrate and is generally set to 2000-6000 ⁇ .
  • the thickness of the second insulation layer 32 can make basic features of the thin film transistor in the display area meet the application requirements, and the thickness of the first insulation layer 31 can ensure that the insulation layer 3 of the thin film transistor in the driving area is not broken down.
  • a material layer of the active layer 5 can be firstly deposited on the base substrate 1 processed in step S 03 by magnetron sputtering, thermal evaporation or other film forming method, and then a pattern of the active layer 5 is formed by a patterning process.
  • a material layer of the etching stop layer 4 can be firstly deposited on the base substrate 1 processed in step S 04 by magnetron sputtering, thermal evaporation or other film forming method, and then patterns of the etching stop layer 4 and the vias 7 are formed by a patterning process.
  • a material layer of source/drain electrodes 6 can be firstly deposited on the base substrate 1 processed in step S 05 by magnetron sputtering, thermal evaporation or other film forming method, and patterns of the source/drain electrodes 6 are formed by a patterning process.
  • the display area mask 9 including the blank part 91 and the pattern part 92 is adopted, an insulation layer structure, in which the thickness of the insulation layer 3 of the thin film transistor in the driving area is larger than the thickness of the insulation layer 3 of the thin film transistor in the display area, is obtained without increasing the cost of the mask.
  • the embodiment provides a display panel, including the above-mentioned array substrate.
  • the embodiment provides a display device, including the above-mentioned display panel.
  • the thickness of the insulation layer of the thin film transistor in the driving area is larger than the thickness of the insulation layer of the thin film transistor in the display area. Therefore, when electrostatic discharge occurs between the gate electrode and the source/drain electrodes of the driving area, breakdown of the insulation layer can be prevented, thereby resulting in no short circuit of the gate electrode and the source/drain electrodes; in addition, the insulation layer is also a dielectric layer for a storage capacitor (the capacitor formed between the gate electrode and the source/drain electrodes), and since the thickness of the insulation layer of the thin film transistor in the display area is small, the storage capacitance of the display area can be maintained or increased; meanwhile, since the thickness of the insulation layer of the thin film transistor in the display area is small, adverse effects such as a reduced migration rate and threshold voltage drift of the thin film transistor in the display area will not be caused.

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WO2015192504A1 (zh) 2015-12-23

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