CN106098789A - 一种薄膜晶体管及其制备方法、阵列基板、显示装置 - Google Patents

一种薄膜晶体管及其制备方法、阵列基板、显示装置 Download PDF

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CN106098789A
CN106098789A CN201610683465.0A CN201610683465A CN106098789A CN 106098789 A CN106098789 A CN 106098789A CN 201610683465 A CN201610683465 A CN 201610683465A CN 106098789 A CN106098789 A CN 106098789A
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tft
capture portion
thin film
film transistor
active layer
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李栋
詹裕程
张帅
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201610683465.0A priority patent/CN106098789A/zh
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Priority to PCT/CN2017/096590 priority patent/WO2018033000A1/zh
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Abstract

本发明实施例提供一种薄膜晶体管及其制备方法、阵列基板、显示装置，涉及显示技术领域，能够避免通过改变栅极尺寸和形状对有源层进行遮光，而导致像素开口率下降的问题。该薄膜晶体管包括源极、漏极以及半导体有源层，半导体有源层包括载流子俘获部，载流子俘获部位于源极和漏极之间。其中，构成载流子俘获部的半导体材料具有陷阱和/或复合中心。

Description

一种薄膜晶体管及其制备方法、阵列基板、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法、阵列基板、显示装置。
背景技术
TFT(Thin Film Transistor，薄膜晶体管)被广泛地应用于电脑、手机等具有显示功能的产品中。其中，当光线照射TFT的有源层会产生光致漏电流。具体的，当照射至有源层的光线中光子的能量高于1.12eV(即硅元素的禁带宽度)时，可在有源层中激发产生电子-空穴对，使得该有源层处于非平衡状态。在此情况下，部分上述电子-空穴对在电场作用下分离，使得空穴向TFT的沟道流动，而电子向漏极流动从而形成漏电流，即上述光致漏电流，降低了TFT的性能。
为了解决上述问题，现有技术中可以对底栅型TFT中的栅极的尺寸和形状进行调整，例如增加栅极的面积，使得栅极的面积大于有源层的面积，以遮挡光线照射至该有源层。然而这样一来，会增加TFT的面积，从而降低了显示装置的像素开口率。
发明内容
本发明的实施例提供一种薄膜晶体管及其制备方法、阵列基板、显示装置，能够避免通过改变栅极尺寸和形状对有源层进行遮光，而导致像素开口率下降的问题。
为达到上述目的，本发明的实施例采用如下技术方案：
本发明实施例的一方面，薄膜晶体管，包括源极、漏极以及半导体有源层，所述半导体有源层包括载流子俘获部，所述载流子俘获部位于所述源极和所述漏极之间；其中，构成所述载流子俘获部的半导体材料具有陷阱和/或复合中心。
优选的，所述载流子俘获部位于靠近漏极的一侧。
优选的，所述薄膜晶体管为顶栅型薄膜晶体管，所述载流子俘获部包括第一子俘获部与第二子俘获部；所述第一子俘获部位于所述薄膜晶体管的栅极和漏极之间，所述第二子俘获部位于所述栅极和源极之间。
优选的，沿所述薄膜晶体管沟道长度方向，所述第一子俘获部和所述第二子俘获部的尺寸为0.3μm～2μm。
本发明实施例的另一方面，提供一种薄膜晶体管的制备方法，包括：在所述衬底基板上，通过构图工艺形成半导体有源层；对所述半导体有源层的部分进行离子处理，以使得所述半导体有源层上经过离子处理的部分形成载流子俘获部；其中，构成所述载流子俘获部的半导体材料具有陷阱和/或复合中心；在衬底基板上形成数据金属层，并通过构图工艺形成源极和漏极；所述载流子俘获部位于所述源极和漏极之间。
优选的，所述对所述半导体有源层的部分进行离子处理包括：在所述半导体有源层的表面形成光刻胶；对所述光刻胶进行掩膜、曝光、显影，以将对应待形成所述载流子俘获部位置处的光刻胶去除；对未被所述光刻胶覆盖的所述半导体有源层进行离子处理；去除所述光刻胶。
优选的，所述离子处理包括离子轰击工艺或离子掺杂工艺。
优选的，当构成所述载流子俘获部的半导体材料具有的陷阱为电子陷阱时，所述离子掺杂工艺包括采用金离子进行掺杂。
优选的，采用所述离子轰击工艺对所述半导体有源层的进行部分离子处理包括：采用500eV～5keV的离子，对所述半导体有源层的部分进行轰击，轰击时间为50s～200s；其中，所述离子由惰性元素构成。
本发明实施例的又一方面，提供一种阵列基板，包括上述任意一种薄膜晶体管。
本发明实施例的再一方面，提供一种显示装置，包括如上所述的阵列基板。
本发明实施例提供一种薄膜晶体管及其制备方法、阵列基板、显示装置。该薄膜晶体管包括源极、漏极以及半导体有源层。该半导体有源层包括载流子俘获部，载流子俘获部位于源极和漏极之间。其中，构成载流子俘获部的半导体材料具有陷阱和/或复合中心。在此情况下，当半导体有源层在光照作用下产生电子-空穴对，并在电场作用下分离时，一方面，上述陷阱会对处于自由状态的电子或空穴进行俘获，以减小电子或空穴在导带中处于自由状态的时间，使得半导体有源层达到稳定状态后，其内部光生载流子的数目有所减小。另一方面，上述复合中心会对电子和空穴进行俘获，以增加电子和空穴的复合几率，从而能够进一步减小上述光生载流子的数目，最终达到减小光致漏电流的目的。此外，上述在减小光致漏电流的过程中，并未对TFT栅极的尺寸或形状进行调整，因此避免通过改变栅极尺寸和形状对有源层进行遮光，而导致像素开口率下降的问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种底栅型TFT的结构示意图；
图2为本发明实施例提供的一种顶栅型TFT的结构示意图；
图3为本发明实施例提供的另一种顶栅型TFT的结构示意图；
图4为本发明实施例提供的一种TFT的制备方法流程图；
图5为图4中步骤S102的一种具体实施方式流程图；
图6为图5中步骤S201的制作过程示意图；
图7为图5中步骤S202的部分制作过程示意图；
图8为图5中步骤S202的部分制作过程示意图；
图9为图5中步骤S203的制作过程示意图；
图10为图4中步骤S102的另一种具体实施方式流程图；
图11为本发明实施例提供的一种离子掺杂工艺示意图。
附图标记：
01-衬底基板；10-源极；11-漏极；12-半导体有源层；120-载流子俘获部；1201-第一子俘获部；1202-第二子俘获部；13-栅极；14-栅极绝缘层；20-光刻胶；30-掩膜版；40-离子；A-待形成载流子俘获部的位置；M-间隙式杂质；N-替位式杂质。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种TFT，如图1或图2所示包括源极10、漏极11以及半导体有源层12。该半导体有源层12包括载流子俘获部120，该载流子俘获部120位于源极10和漏极11之间。
其中，构成载流子俘获部120的半导体材料具有陷阱和/或复合中心。
需要说明的是，本发明对TFT的类型不做限定，可以如图1所示为底栅型TFT，也可以如图2所示为顶栅型TFT。其中，底栅型TFT和顶栅型TFT，是根据栅极13和栅极绝缘层14相对于衬底基板01的上下位置进行的划分。具体的，对于底栅型TFT而言，栅极13相对于栅极绝缘层14而言，更靠近衬底基板01；而对于顶栅型TFT而言，栅极绝缘层14相对于栅极13而言，更靠近衬底基板01。
此外，上述陷阱可以包括电子陷阱和空穴陷阱。具体的，电子陷阱为能够俘获电子的杂质或缺陷；空穴陷阱为能够空穴的杂质或缺陷。另外，复合中心为能够俘获电子和空穴的杂质或缺陷。具体的，可以通过离子轰击工艺对半导体有源层12进行离子轰击，以打断半导体元素之间的共价键，从而形成上述缺陷。或者可以采用离子注入工艺，将与半导体材料不同元素的原子作为杂质原子，注入至半导体材料中以替代原有晶格原子或嵌入原有晶格原子的间隙中。
在此情况下，当半导体有源层在光照作用下产生电子-空穴对，并在电场作用下分离时，一方面，上述陷阱会对处于自由状态的电子或空穴进行俘获，以减小电子或空穴在导带中处于自由状态的时间，使得半导体有源层达到稳定状态后，其内部光生载流子的数目有所减小。另一方面，上述复合中心会对电子和空穴进行俘获，以增加电子和空穴的复合几率，从而能够进一步减小上述光生载流子的数目，最终达到减小光致漏电流的目的。此外，上述在减小光致漏电流的过程中，并未对TFT栅极的尺寸或形状进行调整，因此能够避免通过改变栅极尺寸和形状对有源层进行遮光，而导致像素开口率下降的问题。
需要说明的是，本发明对上述载流子俘获部120位于源极10和漏极11之间的面积不做限定。例如可以是位于源极10和漏极11之间的半导体有源层12均为上述载流子俘获部120，此时载流子俘获部120对载流子的俘获能力最强，TFT的光致漏电流最小。但是由于载流子俘获部120基本占据沟道位置，会大大降低TFT的电子迁移率，从而使得TFT的导通性能受到影响。因此为了通过上述载流子俘获部120对载流子进行俘获的过程中，保证TFT的电子迁移率，优选的，可以将位于源极10和漏极11之间的半导体有源层12的一部分作为上述载流子俘获部120。
在此情况下，由于TFT沟道边缘的电场强度较大，且该沟道边缘靠近漏极11的电场更大，因此电子-空穴对在该处最容易分离，从而产生漏电流。所以优选的，如图1或图2所示，上述载流子俘获部120可以位于靠近漏极11的一侧，从而将靠近漏极11位置处分离的载流子进行俘获，以减小上述载流子在导带中处于自由状态的时间。
此外，本发明对构成半导体有源层12的材料不做限定，例如可以采用非晶硅或多晶硅。其中采用工艺温度低于600℃的低温多晶硅(英文全称：Low Temperature Poly-Silicon，英文简称LTPS)技术，可以使得TFT的电子迁移率较高，例如可以达到300cm2/V·s。在此基础上，由于顶栅型LTPS TFT中的寄生电容可以通过栅极13自对准工艺降低，因此对于LTPS TFT而言顶栅型结构相对于底栅型结构而言，性能更加优越。
在此情况下，当TFT为顶栅型结构时，如图3所示，该载流子俘获部120包括第一子俘获部1201与第二子俘获部1202。
其中，第一子俘获部1201位于栅极13和漏极11之间，第二子俘获部1202位于所述栅极13和源极10之间。这样一来，由于TFT沟道边缘的电场强度较大，因此电子-空穴对在该处最容易分离，从而产生漏电流。所以，可以通过位于栅极13和漏极11之间的第一子俘获部1201将靠近漏极11位置处分离的载流子进行俘获。并且，通过位于所述栅极13和源极10之间的第二子俘获部1202将靠近源极10位置处分离的载流子进行俘获，从而达到减小上述载流子在导带中处于自由状态的时间的目的。
在此基础上，优选的，如图3所示沿该TFT沟道长度方向O-O，该第一子俘获部1201和第二子俘获部1202的尺寸H为0.3μm～2μm。一方面，由于当第一子俘获部1201和第二子俘获部1202的尺寸H小于0.3μm时，会增加制备工艺的精度，不利于降低生产成本。此外，上述尺寸H过小，会导致载流子俘获部120俘获载流子的能力下降，从而不利于降低光致漏电流。另一方面，由于当第一子俘获部1201和第二子俘获部1202的尺寸H大于2μm时，虽然能够增强载流子俘获部120俘获载流子的能力，但同时会降低TFT的电子迁移率，从而降低了TFT的导电性能。因此，当第一子俘获部1201和第二子俘获部1202的尺寸H为0.3μm～2μm时，既可以保证TFT的电子迁移率，又能够降低光致漏电流。在此基础上，优选的上述尺寸H可以为0.5μm、0.8μm、1.2μm、1.8μm。
本发明实施例提供一种阵列基板，包括如上所述的任意一种TFT，具有与前述实施例提供的TFT相同的结构和有益效果，由于前述实施例已经对TFT的结构和有益效果进行了详细的描述，此处不再赘述。
本发明实施例提供一种显示装置，包括如上所述的阵列基板，具有与前述实施例相同的有益效果，此处不再赘述。
本发明实施例提供一种TFT的制备方法，如图4所示，包括：
S101、在如图1或2所示的衬底基板01上，通过构图工艺形成半导体有源层12。
在本发明中，构图工艺，可指包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
S102、对该半导体有源层12的部分进行离子处理，以使得半导体有源层12上经过离子处理的部分形成载流子俘获部120。其中，构成该载流子俘获部120的半导体材料具有陷阱和/或复合中心。
S103、在衬底基板01上形成数据金属层，并通过构图工艺形成源极10和漏极11。其中，该载流子俘获部120位于源极10和漏极11之间。
在此情况下，当半导体有源层在光照作用下产生电子-空穴对，并在电场作用下分离时，一方面，上述陷阱会对处于自由状态的电子或空穴进行俘获，以减小电子或空穴在导带中处于自由状态的时间，使得半导体有源层达到稳定状态后，其内部光生载流子的数目有所减小。另一方面，上述复合中心会对电子和空穴进行俘获，以增加电子和空穴的复合几率，从而能够进一步减小上述光生载流子的数目，最终达到减小光致漏电流的目的。此外，上述在减小光致漏电流的过程中，并未对TFT栅极的尺寸或形状进行调整，因此避免通过改变栅极尺寸和形状对有源层进行遮光，而导致像素开口率下降的问题。
接下来，对上述步骤S102中对半导体有源层12的部分进行离子处理的方法，如图5所示，包括：
S201、如图6所示，在半导体有源层12的表面形成光刻胶20。
S202、如图7所示对光刻胶20进行掩膜、曝光。然后如图8所示通过显影工艺，以将对应待形成载流子俘获部120位置A处的光刻胶20去除。
其中，本发明对上述光刻胶20的类型不做限定，可以为正胶也可以为负胶。具体的，如图7和8所示，是以光刻胶20为正胶为例进行的说明，光刻胶20上被透过掩膜版30的透过区域的光线照射溶解，未被光线照射的地方不易溶解。负胶反之，此处不再赘述。
S203、如图9所示，对未被光刻胶20覆盖的半导体有源层12进行离子处理，以形成载流子俘获部120。
S204、去除光刻胶20。
综上所述，上述对半导体有源层12的部分进行离子处理的过程，以通过对光刻胶20进行构图工艺形成光刻胶图案，从而以该光刻胶图案为掩膜对半导体有源层12的部分进行离子处理。此外，还可以如图10所示，直接在半导体有源层12的上方设置掩膜版30，从而在该掩膜版30的作用下，使得离子40能够通过掩膜版30的透过区域，以对待形成载流子俘获部120位置A处的半导体有源层12进行离子处理。由于上述离子处理的过程中，离子40会对掩膜版30造成一定的损伤，所以优选以光刻胶图案为掩膜对半导体有源层12的部分进行离子处理的方法。
此外，本发明中的离子处理可以包括离子轰击工艺或离子掺杂工艺。具体的，离子处理可以是指采用离子源提供的离子对半导体有源层12进行轰击或掺杂。或者对离子源提供的离子在高频高压电场中进行加速处理，使得较大的粒子碰撞分子，将分子电离产生自由电子、离子以及自由基等粒子以构成等离子体。在此情况下，采用离子处理可以是指采用上述等离子体中的离子对半导体有源层12进行轰击或掺杂。
以下分别对离子轰击工艺或离子掺杂工艺进行详细的说明。
由于构成载流子俘获部120的半导体材料具有陷阱和/或复合中心。而陷阱可以包括电子陷阱和空穴陷阱。电子陷阱为能够俘获电子的杂质或缺陷；空穴陷阱为能够空穴的杂质或陷阱。另外，复合中心为能够俘获电子和空穴的杂质或缺陷。
基于此，就可以通过离子掺杂工艺，将与构成半导体有源层12的元素不同的原子作为杂质原子，注入至半导体材料以俘获电子和/或空穴，从而形成上述陷阱和/或复合中心。
具体的，以构成载流子俘获部120的半导体材料具有的陷阱为电子陷阱为例，可以采用离子掺杂工艺如图11所示，采用金(Au)离子或铜(Cu)离子进行掺杂。其中，经过上述掺杂工艺后，杂质原子，例如Au，可以位于晶格原子的间隙位置，以构成间隙式杂质M；或者上述杂质原子可以取代晶格原子位于晶格点处，以构成替位式杂质N。这样一来，上述间隙式杂质M和替位式杂质N能够吸引导电电子，变成负离子，从而形成上述电子陷阱。
此外，需要说明的是，在形成电子陷阱时，优选掺杂金(Au)离子，从而能够避免由于铜(Cu)离子尺寸过小，导致掺杂的铜(Cu)离子迁移至TFT沟道，造成沟道污染。
同理，当通过上述掺杂工艺形成的间隙式杂质M和替位式杂质N能够吸引价带空穴变成正离子时，能够形成上述空穴陷阱。其中，构成空穴陷阱的杂质能级高于构成电子陷阱的杂质能级。此外，而对于复合中心而言，通过掺杂工艺形成的间隙式杂质M和替位式杂质N能够同时吸引导电电子和价带空穴，以增加电子和空穴复合几率。
此外，在通过离子轰击工艺形成上述陷阱和/或复合中心的过程中，可以采用500eV～5keV的离子，对半导体有源层12的部分进行轰击，轰击时间为50s～200s。这样一来，能够在保证对半导体有源层12不造成损坏的基础上，达到有效的轰击效果，以形成能够俘获载流子的缺陷。
在此基础上，用于轰击的离子由惰性元素，例如氩(Ar)、氖(Ne)、氦(He)等元素。这样一来，在由上述惰性元素构成的离子轰击的过程中，该离子不会改变构成半导体有源层12的元素，而会将构成半导体有源层12的例如硅(Si)原子之间的共价键打断，从而形成缺陷，上述缺陷能够对电子和/或空穴进行俘获。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (11)

1.一种薄膜晶体管，包括源极、漏极以及半导体有源层，其特征在于，所述半导体有源层包括载流子俘获部，所述载流子俘获部位于所述源极和所述漏极之间；
其中，构成所述载流子俘获部的半导体材料具有陷阱和/或复合中心。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述载流子俘获部位于靠近漏极的一侧。
3.根据权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管为顶栅型薄膜晶体管，所述载流子俘获部包括第一子俘获部与第二子俘获部；
所述第一子俘获部位于所述薄膜晶体管的栅极和漏极之间，所述第二子俘获部位于所述栅极和源极之间。
4.根据权利要求3所述的薄膜晶体管，其特征在于，沿所述薄膜晶体管沟道长度方向，所述第一子俘获部和所述第二子俘获部的尺寸为0.3μm～2μm。
5.一种薄膜晶体管的制备方法，其特征在于，包括：
在所述衬底基板上，通过构图工艺形成半导体有源层；
对所述半导体有源层的部分进行离子处理，以使得所述半导体有源层上经过离子处理的部分形成载流子俘获部；其中，构成所述载流子俘获部的半导体材料具有陷阱和/或复合中心；
在衬底基板上形成数据金属层，并通过构图工艺形成源极和漏极；所述载流子俘获部位于所述源极和漏极之间。
6.根据权利要求5所述的薄膜晶体管的制备方法，其特征在于，所述对所述半导体有源层的部分进行离子处理包括：
在所述半导体有源层的表面形成光刻胶；
对所述光刻胶进行掩膜、曝光、显影，以将对应待形成所述载流子俘获部位置处的光刻胶去除；
对未被所述光刻胶覆盖的所述半导体有源层进行离子处理；
去除所述光刻胶。
7.根据权利要求5或6所述的薄膜晶体管的制备方法，其特征在于，所述离子处理包括离子轰击工艺或离子掺杂工艺。
8.根据权利要求7所述的薄膜晶体管的制备方法，其特征在于，当构成所述载流子俘获部的半导体材料具有的陷阱为电子陷阱时，所述离子掺杂工艺包括采用金离子进行掺杂。
9.根据权利要求7所述的薄膜晶体管的制备方法，其特征在于，采用所述离子轰击工艺对所述半导体有源层的进行部分离子处理包括：采用500eV～5keV的离子，对所述半导体有源层的部分进行轰击，轰击时间为50s～200s；
其中，所述离子由惰性元素构成。
10.一种阵列基板，其特征在于，包括如权利要求1-4所述的任意一种薄膜晶体管。
11.一种显示装置，其特征在于，包括如权利要求10所述的阵列基板。
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