CN103824779A - 一种薄膜晶体管及其制作方法、tft阵列基板、显示装置 - Google Patents

一种薄膜晶体管及其制作方法、tft阵列基板、显示装置 Download PDF

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CN103824779A
CN103824779A CN201410054172.7A CN201410054172A CN103824779A CN 103824779 A CN103824779 A CN 103824779A CN 201410054172 A CN201410054172 A CN 201410054172A CN 103824779 A CN103824779 A CN 103824779A
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film transistor
active layer
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王守坤
郭会斌
刘晓伟
冯玉春
郭总杰
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Abstract

本发明涉及一种薄膜晶体管制作方法，包括：形成半导体有源层和掺杂半导体有源层的步骤；形成源漏金属层的步骤；形成沟道区域的步骤；在形成沟道区域的步骤之后，通过离子注入的方式，在所述沟道区域内的半导体有源层表面注入用于降低TFT漏电流的离子的步骤。本发明还涉及一种薄膜晶体管、TFT阵列基板、显示装置。本发明的有益效果是：通过在沟道区域内注入用于降低TFT漏电流的离子，提升TFT电学性能，并且可控的改变沟道区域半导体有源层的厚度。

Description

一种薄膜晶体管及其制作方法、TFT阵列基板、显示装置
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种薄膜晶体管及其制作方法、TFT阵列基板、显示装置。
背景技术
薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display，简称TFT-LCD），具有体积小、功耗低、无辐射等特点，在当前的平板显示器市场中占据了主导地位。其中显示画面均匀、高解析度、无窜扰等是高品质TFT-LCD的关键要求，而与此有关的是TFT的电性参数-漏电流（Ioff），漏电流是TFT的一个重要参数，若其过大，则影响TFT的开关特性，从而导致TFT-LCD出现显示不均、发白、窜扰等显示类缺陷。
目前设计的非晶硅TFT-LCD各类产品，采用背沟道刻蚀技术后，沟道区域表层为非晶硅层，此区域的膜质如果有问题，TFT的性能就会有较大影响。
发明内容
为了解决上述技术问题，本发明提供一种TFT阵列基板制作方法，改善沟道区域膜质成分，其他膜层区域不受影响。
为了达到上述目的，本发明采用的技术方案是：一种薄膜晶体管的制作方法，包括：
形成半导体有源层和掺杂半导体有源层的步骤；
形成源漏金属层的步骤；
形成沟道区域的步骤；
在形成沟道区域的步骤之后，通过离子注入的方式，在所述沟道区域内的半导体有源层表面注入用于降低TFT漏电流的离子的步骤。
进一步的，所述离子为N离子、C离子或H离子。
进一步的，具体包括：
在基板上沉积栅金属层，通过构图工艺，得到栅极图形；
在栅极上沉积栅绝缘层、半导体有源层和掺杂半导体有源层和源漏金属层，通过构图工艺得到沟道区域以及源电极、漏电极的图形，并在源电极、漏电极的图形上的光刻胶剥离之前、通过离子注入的方式，在所述沟道区域内的半导体有源层表面注入用于降低TFT漏电流的离子。
进一步的，具体包括：
在基板上沉积源漏金属层，通过构图工艺得到源电极、漏电极的图形；
在源电极、漏电极上形成掺杂半导体有源层和半导体有源层，通过构图工艺形成沟道区域；
通过离子注入的方式，在所述沟道区域内的半导体有源层表面注入用于降低TFT漏电流的离子。
进一步的，所述离子注入方式，所采用的注入离子能量为20KV～80KV。
进一步的，所述离子注入方式，所的注入离子剂量为2*1017/cm2～5*1018/cm2。
本发明还提供一种薄膜晶体管，所述薄膜晶体管采用上述的薄膜晶体管的制作方法制作得到。
进一步的，所述离子为N离子时，所述离子为N离子时，所述半导体有源层注入离子部分所包含的Si、H、N的含量分别为30%～50%，4%～15%，35%～60%。
进一步的，所述离子为C离子时，所述半导体有源层注入离子部分所包含的Si、H、C的含量分别为30%～50%，4%～15%，40%～60%。
本发明还提供一种TFT阵列基板，所述阵列基板包括上述的薄膜晶体管。
本发明还提供一种显示装置，所述显示装置包括上述的TFT阵列基板。
本发明的有益效果是：通过在沟道区域内注入用于降低TFT漏电流的离子，提升TFT电学性能，并且可控的改变沟道区域半导体有源层的厚度。
附图说明
图1表示本发明TFT阵列基板形成公共电极图形后的结构示意图；
图2表示本发明TFT阵列基板形成栅极图形后的结构示意图；
图3表示本发明TFT阵列基板形成沟道区域后的结构示意图；
图4表示本发明TFT阵列基板在沟道区域内注入离子示意图；
图5表示本发明TFT阵列基板形成钝化层后的结构示意图；
图6表示本发明TFT阵列基本形成像素电极图形后的结构示意图。
具体实施方式
以下结合附图对本发明特征和原理进行详细说明，所举实施例仅用于解释本发明，并非以此限定本发明的保护范围。
本实施例提供一种薄膜晶体管的制作方法，包括：
形成半导体有源层和掺杂半导体有源层的步骤；
形成源漏金属层的步骤；
形成沟道区域的步骤；
在形成沟道区域的步骤之后，通过离子注入的方式，在所述沟道区域内的半导体有源层表面注入用于降低TFT漏电流的离子的步骤。
薄膜晶体管根据栅极和源漏极的位置可分为顶栅结构和底栅结构，底栅结构的薄膜晶体管的制作方法具体包括：
步骤一：在基板上沉积公共电极金属层，通过构图工艺，得到公共电极图形；
公共电极金属层可以为一层透明的导电薄膜，该透明导电薄膜可以采用氧化铟锡（ITO）、氧化铟锌、氧化铝锌等材料，形成公共电极金属层的工艺可以采用溅射沉积形成，也可以为本领域技术人员所知的其它工艺，经过曝光机图形曝光，刻蚀液刻蚀形成透明公共电极图形。
步骤二：在基板上沉积栅金属层，通过构图工艺，得到栅极图形；
栅金属层的材料可以为钼、铝、铝镍合金、钼钨合金、铬或铜等金属，也可以使用上述几种材料的组合结构。形成栅金属层的工艺可以采用溅射沉积形成，也可以为本领域技术人员所知的其它工艺，经过曝光机图形曝光，刻蚀液刻蚀形成栅极图形。
步骤三：在栅极上沉积栅绝缘层、半导体有源层和掺杂半导体有源层和源漏金属层，通过构图工艺得到沟道区域以及源电极、漏电极的图形，并在源电极、漏电极的图形上的光刻胶剥离之前、通过离子注入的方式，在所述沟道区域内的半导体有源层表面注入用于降低TFT漏电流的离子；
通过化学气相沉积gate SiNx和a-Si：H,分别作为栅绝缘层和半导体有源层和掺杂半导体有源层，然后通过溅射沉积金属层形成源漏金属层，然后经过曝光机图形曝光，刻蚀，形成TFT沟道区域。源漏金属层的材料可以为钼、铝、铝镍合金、钼钨合金、铬或铜等金属，也可以使用上述几种材料的组合结构。栅绝缘层的材料可以采用氧化物、氮化物或氧氮化合物。
步骤四：在所述源电极、漏电极上形成包括有接触过孔的钝化层的图形；钝化层的形成对TFT沟道区域进行保护，防止水分等物质的侵蚀。
步骤五：在所述钝化层上形成像素电极图形，所述像素电极通过所述接触过孔与所述漏电极相连接。
在钝化层上沉积一层透明的导电薄膜，该透明导电薄膜可以采用氧化铟锡（ITO）、氧化铟锌、氧化铝锌等材料，形成导电薄膜的工艺可以采用溅射沉积形成，也可以为本领域技术人员所知的其它工艺，经过曝光机图形曝光，刻蚀液刻蚀形成透明像素电极图形。
顶栅结构的薄膜晶体管的制作方法具体包括：
步骤一：在基板上沉积金属层，通过构图工艺，得到像素电极图形；
沉积一层透明的导电薄膜，该透明导电薄膜可以采用氧化铟锡（ITO）、氧化铟锌、氧化铝锌等材料，形成导电薄膜的工艺可以采用溅射沉积形成，也可以为本领域技术人员所知的其它工艺，经过曝光机图形曝光，刻蚀液刻蚀形成透明像素电极图形。
步骤二：在基板上沉积源漏金属层，通过构图工艺得到源电极、漏电极的图形；
通过化学气相沉积gate SiNx和a-Si：H,分别作为栅绝缘层和半导体有源层和掺杂半导体有源层，然后通过溅射沉积金属层形成源漏金属层，然后经过曝光机图形曝光，刻蚀，形成TFT沟道区域。源漏金属层的材料可以为钼、铝、铝镍合金、钼钨合金、铬或铜等金属，也可以使用上述几种材料的组合结构。栅绝缘层的材料可以采用氧化物、氮化物或氧氮化合物。
步骤三：在源电极、漏电极上形成掺杂半导体有源层和半导体有源层，通过构图工艺形成沟道区域；
将沟道区域注入N离子，使表面一部分膜层成分变为SiNx，这样可提高沟道表面层的稳定，当然也可以注入H离子，C离子等以达到提高沟道区域表面层的稳定。
步骤四：通过构图工艺在半导体有源层上形成栅绝缘层和栅极图形。
下面将结合本发明实施例中的附图，以底栅结构的薄膜晶体管为例对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的实施例中，构图工艺，包括曝光、显影、刻蚀等形成图形的工艺；源漏金属层，指形成源漏电极的金属。一次构图工艺，指使用一张掩模板（mask）的构图工艺。
本发明实施例提供一种TFT阵列基板的制造方法，参照图1～图6对该方法进行详细说明。
步骤一、形成公共电极图形。
此步骤可以采用任何可以通过一次构图工艺实现的现有技术来实现。比如，利用普通掩摸工艺实现，如图1所示，借助普通掩膜版（图中未示出）对衬底基板201上的金属层（图中未示出）进行图案化，以形成的图案化的公共电极202的图形。具体地，包括：在基板上沉积公共电极金属层，利用普通掩摸板进行曝光、显影和刻蚀，得到公共电极图形。
普通（常规）掩膜版指通常所使用的具有透光区和非透光区的掩膜版，借助该第一常规掩膜版对形成在公共电极金属层上的光刻胶层进行曝光显影后，需要保留的公共电极金属层上覆盖有光刻胶，而不需要保留的公共电极金属层上的光刻胶被去除，通过刻蚀步骤，将不需要的公共电极金属层刻蚀掉，剩余的公共电极金属层即为所需的图案化的公共电极202。
公共电极金属层采用氧化铟锡（ITO）,形成公共电极金属层的工艺可以为溅射工艺，也可以为本领域技术人员所知的其它工艺。
步骤二：形成栅极图形
此步骤可以采用任何可以通过一次构图工艺实现的现有技术来实现。比如，利用普通掩摸工艺实现，如图2所示，借助普通掩膜版（图中未示出）对衬底基板201上的栅极金属层（图中未示出）进行图案化，以形成的图案化的包括栅极203的图形。具体地，包括：在基板上沉积栅金属层，利用普通掩摸板进行曝光、显影和刻蚀，得到包括栅极203的图形。
普通（常规）掩膜版指通常所使用的具有透光区和非透光区的掩膜版，借助该第一常规掩膜版对形成在栅极金属层上的光刻胶层进行曝光显影后，需要保留的栅极金属层上覆盖有光刻胶，而不需要保留的栅极金属层上的光刻胶被去除，通过刻蚀步骤，将不需要的栅极金属层刻蚀掉，剩余的栅极金属层即为所需的图案化的栅极203。
形成栅极金属层的工艺可以为溅射工艺，也可以为本领域技术人员所知的其它工艺。
步骤三：形成栅绝缘层204、半导体有源层205、掺杂半导体有源层211、和沟道区域206，并在沟道区域半导体有源层205表面注入用于降低TFT漏电流的离子，形成离子注入层210。
如图3所示，通过化学气相沉积gate SiNx和a-Si：H,分别作为栅极绝缘层204和半导体有源层205，然后溅射沉积源漏金属层207，在源漏金属层207上涂布光刻胶，源漏金属层207与半导体有源层205之间设有掺杂半导体有源层211，所述掺杂半导体有源层为磷掺杂半导体有源层（n+a-Si），位于有源层与源漏金属层之间，目的是降低接触电阻。
利用灰色调或半色调掩模板对所述光刻胶进行曝光和显影，形成完全去除区、对应源电极、漏电极的完全保留区和对应沟道区域的部分保留区，之后刻蚀掉完全去除区的半导体有源层205和掺杂半导体有源层211、源漏金属层207，去除掉所述部分保留区的光刻胶，之后先刻蚀掉部分保留区的源漏金属层207掺杂半导体有源层211，形成薄膜晶体管的沟道区域206。
在本步骤工艺的过程中，TFT沟道部分，半导体有源层a-Si：H层的厚度及其膜质成分都会对TFT特性起着决定性作用，TFT沟道的a-Si：H层部分，需要背沟道处理，才能提升TFT性质（譬如降低光照漏电流photo Ioff）。
在对应源电极、漏电极的完全保留区光刻胶剥离之前，在沟道区域处采用离子注入的方法，将沟道区域a-Si：H层（半导体有源层205）注入N离子，使a-Si：H层表面一部分膜层成分变为SiNx,这样可提高沟道表面层的稳定，并且a-Si：H层的厚度，可以由注入离子的能量不同，可控的改变沟道a-Si：H层的厚度，而且注入的离子比的调节，可调整Si-H健和N-H键的比例，改善光照漏电流过大（photo Ioff）,TFT Ion改善沟道处TFT的电学性,而不引起其他膜层的电学和膜质较大变化，从而达到实现TFT性能提升的目的，图4中，箭头方向所指为离子注入的位置。
本实施例中通过注入N离子的方式以降低TFT漏电流的原理如下：
本发明实施例提供的TFT阵列基板的制造方法中，不改变正常的mask工序，在沟道区域内注入用于降低TFT漏电流的离子，提升了TFT电学性能，尤其是在对应源电极、漏电极的完全保留区的光刻胶剥离之前，在沟道区域内注入离子，使得其他膜层不受影响，在沟道区域处采用离子注入的方法，将沟道区域a-Si：H层（半导体有源层）注入N离子，注入N离子使a-Si：H层表面一部分膜层成分变为SiNx,这样可提高沟道表面层的稳定。因为a-Si:H层中的H在a-Si:H层中扩散，容易引起弱Si-Si键的断裂和H的聚集，受到光照后会发生不同的反应，在其内部产生缺陷而使薄膜性能下降，进而产生光致漏电流。半导体有源层a-Si:H层性能的衰退与Si-Si弱键有关，要提高其稳定性，应尽可能的消除或减少键能较弱的Si-Si键。所以在a-Si:H层中引入N离子，可以将键能较弱的Si-Si键打断，形成键能相对较强的Si-N键,从而降低a-Si:H层中多包含的Si-Si键的比例，达到膜质稳定的目的，从而达到实现TFT电学稳定的目的。
并且a-Si：H层的厚度，可以由注入离子的能量不同来进行调控，因为注入离子的能量不同，则离子到达膜层的深度会不一样，这样就会形成可控厚度的SiNx层（离子注入层210），从而达到可控的改变沟道区域a-Si：H层的离子注入层210的厚度的目的；同时可达到的调节a-Si:H层中离子比的目的，因为注入N离子会引起膜层里面原子的重新成键，而注入N离子含量的不同能够调整Si-H健和N-H键的比例，改善光照漏电流过大（photo Ioff）,TFT Ion改善沟道处TFT的电学性,而不引起其他膜层的电学和膜质较大变化，从而达到实现TFT性能提升的目的。
进一步的，所述离子注入方式，所采用的注入离子能量为20KV～80KV，但并不以此为限。
进一步的，所述离子注入方式，所的注入离子剂量为2*1017/cm2～5*1018/cm2，但并不以此为限。
本发明还提供一种薄膜晶体管，所述薄膜晶体管采用上述的薄膜晶体管的制作方法制作得到。
进一步的，所述离子为N离子时，所述离子为N离子时，所述半导体有源层注入离子部分所包含的Si、H、N的含量分别为30%～50%，4%～15%，35%～60%。
进一步的，所述离子为C离子时，所述半导体有源层注入离子部分所包含的Si、H、C的含量分别为30%～50%，4%～15%，40%～60%。
所述离子可以为N离子，也可以为C离子或H离子，也可以是其他离子，可以打断Si-Si键，以避免半导体有源层内部产生缺陷而使薄膜性能下降即可。
本实施例中通过注入H离子的方式以降低TFT漏电流的原理为：注入H离子，改变Si含量和H含量的配比，无掺杂的a-si薄膜（半导体有源层），悬挂键密度很高，电学性质差，不能满足器件的应用要求，H离子的引入可以饱和或者部分饱和薄膜中的悬挂键缺陷态，通过离子注入的方式注入H离子,可以进一步调节有源导电层（半导体有源层）中H离子含量，从而使悬挂键的密度降低，以达到膜质的稳定的目的，从而达到实现TFT电学稳定的目的。
步骤四：在所述源电极、漏电极图形上形成包括有接触过孔的钝化层208的图形。
如图4所示，在完成第二次构图工艺的基板201上沉积钝化层208，具体地，可以通过化学气相沉积工艺沉积厚度为
Figure BDA0000466906420000081
的钝化层208，钝化层208可以选用氧化物、氮化物或者氧氮化合物，钝化层208可以是单层结构也可以是多层结构，对应的反应气体可以为SiH4，NH3，N2或SiH2Cl2，NH3，N2。在钝化层上涂布光刻胶，利用掩模板对光刻胶进行曝光和显影之后进行刻蚀，形成包括有接触过孔的钝化层208的图形。
步骤五：所述钝化层上形成像素电极209的图形，所述像素电极209通过所述接触过孔与所述漏电极相连接。
如图5所示，具体的，可以通过溅射或热蒸发的方法在形成有钝化层208的基板201上沉积厚度为
Figure BDA0000466906420000091
的透明导电层，透明导电层可以采用ITO或者IZO，或者其他的透明金属氧化物。在透明导电层上涂布光刻胶，利用掩模板对光刻胶进行曝光和显影之后进行刻蚀，形成像素电极209，像素电极209通过接触过孔与漏电极相连接。
以上所述为本发明较佳实施例，应当指出，对于本领域普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干润饰和改进，这些润饰和改进也应视为本发明保护范围。

Claims (11)

1.一种薄膜晶体管的制作方法，其特征在于，包括：
形成半导体有源层和掺杂半导体有源层的步骤；
形成源漏金属层的步骤；
形成沟道区域的步骤；
在形成沟道区域的步骤之后，通过离子注入的方式，在所述沟道区域内的半导体有源层表面注入用于降低TFT漏电流的离子的步骤。
2.根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，所述离子为N离子、C离子或H离子。
3.根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，具体包括：
在基板上沉积栅金属层，通过构图工艺，得到栅极图形；
在栅极上沉积栅绝缘层、半导体有源层和掺杂半导体有源层和源漏金属层，通过构图工艺得到沟道区域以及源电极、漏电极的图形，并在源电极、漏电极的图形上的光刻胶剥离之前、通过离子注入的方式，在所述沟道区域内的半导体有源层表面注入用于降低TFT漏电流的离子。
4.根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，具体包括：
在基板上沉积源漏金属层，通过构图工艺得到源电极、漏电极的图形；
在源电极、漏电极上形成掺杂半导体有源层和半导体有源层，通过构图工艺形成沟道区域；
通过离子注入的方式，在所述沟道区域内的半导体有源层表面注入用于降低TFT漏电流的离子。
5.根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，所述离子注入方式，所采用的注入离子能量为20KV～80KV。
6.根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，所述离子注入方式，所注入的离子剂量为2*1017/cm2～5*1018/cm2。
7.一种薄膜晶体管，其特征在于，所述薄膜晶体管采用如权利要求1-6中任一项所述的薄膜晶体管的制作方法制作得到。
8.根据权利要求7所述的薄膜晶体管，其特征在于，所述离子为N离子时，所述半导体有源层注入离子部分所包含的Si、H、N的含量分别为30%～50%，4%～15%，35%～60%。
9.根据权利要求7所述的薄膜晶体管，其特征在于，所述离子为C离子时，所述半导体有源层注入离子部分所包含的Si、H、C的含量分别为30%～50%，4%～15%，40%～60%。
10.一种TFT阵列基板，其特征在于，所述阵列基板包括如权利要求7-9所述的薄膜晶体管。
11.一种显示装置，其特征在于，所述显示装置包括如权利要求10所述的TFT阵列基板。
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104300007A (zh) * 2014-10-27 2015-01-21 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板、显示装置
CN105977304A (zh) * 2016-05-31 2016-09-28 京东方科技集团股份有限公司 晶体管、其制造方法、阵列基板、显示面板及显示装置
CN106711231A (zh) * 2017-01-13 2017-05-24 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、显示基板及其制备方法
WO2018033000A1 (zh) * 2016-08-17 2018-02-22 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN108987279A (zh) * 2018-07-16 2018-12-11 惠科股份有限公司 薄膜晶体管的制造方法
WO2019006817A1 (zh) * 2017-07-06 2019-01-10 惠科股份有限公司 一种阵列基板和显示面板
CN109616417A (zh) * 2018-12-17 2019-04-12 惠科股份有限公司 主动开关及其制作方法、显示装置
CN109742027A (zh) * 2018-12-25 2019-05-10 惠科股份有限公司 一种薄膜晶体管的制作方法、薄膜晶体管和显示面板

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114582894A (zh) * 2022-03-10 2022-06-03 广州华星光电半导体显示技术有限公司 阵列基板及显示面板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020171084A1 (en) * 2001-05-16 2002-11-21 Kyounei Yasuda Thin film transistor and method of fabricating the same
CN101419973A (zh) * 2008-11-13 2009-04-29 信利半导体有限公司 一种三次光刻实现的tft像素结构及其制作方法
CN102176413A (zh) * 2011-03-25 2011-09-07 信利半导体有限公司 薄膜晶体管形成方法以及薄膜晶体管

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2223353A (en) * 1988-09-30 1990-04-04 Philips Electronic Associated Thin-film transistor
US5559344A (en) * 1992-01-31 1996-09-24 Hitachi, Ltd. Thin-film semiconductor element, thin-film semiconductor device and methods of fabricating the same
US5897346A (en) * 1994-02-28 1999-04-27 Semiconductor Energy Laboratory Co., Ltd. Method for producing a thin film transistor
US20070161165A1 (en) * 2006-01-12 2007-07-12 Toppoly Optoelectronics Corp. Systems and methods involving thin film transistors
KR20080077846A (ko) * 2007-02-21 2008-08-26 삼성전자주식회사 박막 트랜지스터 기판 및 이의 제조 방법
JP5395384B2 (ja) * 2007-09-07 2014-01-22 株式会社半導体エネルギー研究所 薄膜トランジスタの作製方法
TWI487104B (zh) * 2008-11-07 2015-06-01 Semiconductor Energy Lab 半導體裝置和其製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020171084A1 (en) * 2001-05-16 2002-11-21 Kyounei Yasuda Thin film transistor and method of fabricating the same
CN101419973A (zh) * 2008-11-13 2009-04-29 信利半导体有限公司 一种三次光刻实现的tft像素结构及其制作方法
CN102176413A (zh) * 2011-03-25 2011-09-07 信利半导体有限公司 薄膜晶体管形成方法以及薄膜晶体管

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104300007A (zh) * 2014-10-27 2015-01-21 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板、显示装置
CN105977304A (zh) * 2016-05-31 2016-09-28 京东方科技集团股份有限公司 晶体管、其制造方法、阵列基板、显示面板及显示装置
WO2018033000A1 (zh) * 2016-08-17 2018-02-22 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN106711231A (zh) * 2017-01-13 2017-05-24 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、显示基板及其制备方法
WO2019006817A1 (zh) * 2017-07-06 2019-01-10 惠科股份有限公司 一种阵列基板和显示面板
CN108987279A (zh) * 2018-07-16 2018-12-11 惠科股份有限公司 薄膜晶体管的制造方法
CN108987279B (zh) * 2018-07-16 2021-06-18 惠科股份有限公司 薄膜晶体管的制造方法
CN109616417A (zh) * 2018-12-17 2019-04-12 惠科股份有限公司 主动开关及其制作方法、显示装置
CN109742027A (zh) * 2018-12-25 2019-05-10 惠科股份有限公司 一种薄膜晶体管的制作方法、薄膜晶体管和显示面板

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