WO2019006817A1 - 一种阵列基板和显示面板 - Google Patents

一种阵列基板和显示面板 Download PDF

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Publication number
WO2019006817A1
WO2019006817A1 PCT/CN2017/096714 CN2017096714W WO2019006817A1 WO 2019006817 A1 WO2019006817 A1 WO 2019006817A1 CN 2017096714 W CN2017096714 W CN 2017096714W WO 2019006817 A1 WO2019006817 A1 WO 2019006817A1
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Prior art keywords
layer
doped
semiconductor layer
doped layer
channel portion
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PCT/CN2017/096714
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English (en)
French (fr)
Inventor
卓恩宗
樊堃
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US15/869,825 priority Critical patent/US10431693B2/en
Publication of WO2019006817A1 publication Critical patent/WO2019006817A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate and a display panel.
  • the liquid crystal display has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • Most of the liquid crystal displays on the market are backlight type liquid crystal displays, which include a liquid crystal panel and a backlight module.
  • the working principle of the liquid crystal panel is to place liquid crystal molecules in two parallel glass substrates, and apply a driving voltage on the two glass substrates to control the rotation direction of the liquid crystal molecules to refract the light of the backlight module to generate a picture.
  • a thin film transistor liquid crystal display includes a liquid crystal panel including a color filter substrate (CF Substrate, also referred to as a color filter substrate) and a thin film transistor array substrate (Thin Film Transistor Substrate, TFT Substrate).
  • CF Substrate also referred to as a color filter substrate
  • TFT Substrate Thin Film Transistor Substrate
  • a transparent electrode is present on the opposite inner side of the substrate.
  • a layer of liquid crystal molecules (LC) is sandwiched between the two substrates.
  • the liquid crystal panel controls the orientation of the liquid crystal molecules by an electric field, changes the polarization state of the light, and realizes the purpose of display by the penetration and blocking of the optical path by the polarizing plate.
  • a semiconductor layer is formed on a substrate, and is generally formed of an n-type semiconductor such as amorphous silicon or polycrystalline silicon.
  • amorphous silicon or polycrystalline silicon the electron mobility of polycrystalline silicon is higher than that of amorphous silicon.
  • the electronic mobility of polysilicon has been unable to display the needs of the device.
  • an embodiment of the present application provides an array substrate, and the display panel includes:
  • a substrate comprising a plurality of switch assemblies; wherein the switch assembly comprises:
  • a gate electrode formed on an upper surface of the substrate
  • a gate insulating layer formed on the gate electrode and the upper surface of the substrate to cover the gate electrode;
  • the semiconductor layer formed on an upper surface of the gate insulating layer and above the gate electrode, the semiconductor layer being formed of silicon germanium oxide, the semiconductor layer being formed with a channel portion;
  • a source electrode formed on a surface of the gate insulating layer and the semiconductor layer and located on a side of the channel portion;
  • a drain electrode is formed on the surface of the gate insulating layer and the semiconductor layer and on the other side of the channel portion.
  • the semiconductor layer includes a doped layer
  • the doped layer is located on top of the semiconductor layer and is separated by the channel portion to form two portions, a portion adjacent to the drain electrode and a portion adjacent to the source electrode;
  • the active layer is located at the bottom of the semiconductor layer, and the doped layer is located on an upper surface of the active layer.
  • the doped layer includes a first doped layer and a second doped layer
  • the second doped layer is located on top of the semiconductor layer, and the first doped layer is located at the bottom of the semiconductor layer and is located between the second doped layer and the active layer;
  • the doping concentration of the second doping layer is greater than the doping concentration of the first doping layer.
  • the display panel further includes:
  • a protective layer is formed on the upper surfaces of the source and drain electrodes, covering the source and drain electrodes, and the protective layer is located above the channel portion.
  • the display panel further includes:
  • a conductive layer is formed on the upper surface of the protective layer and separated by the channel portion.
  • the conductive layer is an oxide conductor layer.
  • the conductive layer is a metal layer.
  • the substrate is a glass substrate.
  • the gate insulating layer is formed of silicon nitride.
  • the gate insulating layer is formed of an oxide insulating film.
  • the semiconductor layer of the TFT substrate is generally amorphous silicon or polycrystalline silicon, wherein the electron mobility of the amorphous silicon is 0.5 to 0.8 cm 2 /Vs, and the electron mobility of the polycrystalline silicon is slightly higher than that of the amorphous silicon, but the electron mobility is not high. Can not meet the needs of existing display devices.
  • the present application further discloses a display panel, the display panel includes the array substrate described in the present application, and further includes:
  • control unit coupled to the pixel unit
  • the color filter substrate is disposed in parallel with the array substrate.
  • the array substrate further includes
  • a data line coupled to the plurality of pixel units to control display gray scale of the pixel unit
  • a scan line coupled to the plurality of pixel units to control the pixel unit to be turned on
  • a data driving circuit coupled to the data line
  • a scan drive circuit coupled to the scan line.
  • the present application also discloses a method of manufacturing a display panel, the manufacturing method comprising:
  • the semiconductor layer is formed of silicon germanium oxide.
  • the application greatly increases the electronic mobility of the active switch to meet the needs of the display device.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present application.
  • FIG 2 is another schematic structural view of an array substrate according to an embodiment of the present application.
  • FIG 3 is another schematic structural view of an array substrate according to an embodiment of the present application.
  • FIG. 4 is another schematic structural view of an array substrate according to an embodiment of the present application.
  • FIG. 5 is another schematic structural diagram of an array substrate according to an embodiment of the present application.
  • FIG. 6 is another schematic structural view of a display panel according to an embodiment of the present application.
  • FIG. 7 is a cross-sectional structural view of a display panel according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a method of manufacturing a display panel according to an embodiment of the present application.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • connection In the description of the present application, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or integrally connected; can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • Connected, or integrally connected can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • the specific meanings of the above terms in the present application can be understood in the specific circumstances for those skilled in the art.
  • the array substrate 100 in the following embodiments of the present application can be disposed in the display device of the embodiment of the present application. That is, the display device of the embodiment of the present application includes the array substrate 100 of any of the following embodiments.
  • the display device may be a liquid crystal display or an OLED (Organic Light-Emitting Diode) display.
  • the liquid crystal display includes a backlight module, and the backlight module can be used as a light source for supplying sufficient light source with uniform brightness and distribution.
  • the backlight module of the embodiment can be For the front light type, it may also be a backlight type. It should be noted that the backlight module of the embodiment is not limited thereto.
  • array substrate 100 The following describes the array substrate 100 as an example. It should be noted that the following description of the array substrate 100 is also applicable to the display device of the embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 1 shows only a partial structure of an array substrate.
  • the array substrate 100 of the embodiment of the present application includes a substrate 110 and a gate electrode 120. a gate insulating layer 130, a semiconductor layer 140, a source electrode 150, and a drain electrode 160.
  • the substrate 110 may include a glass plate, which has good light transmission type and is convenient to set. It should be noted that the substrate 110 of the embodiment is not limited thereto, and may also include other types, such as a flexible substrate.
  • the gate electrode 120 is formed on the upper surface of the substrate 110. Specifically, the gate electrode 120 may be formed by laying a gate line on the substrate 110.
  • the gate insulating layer 130 is formed on the upper surface of the gate electrode 120 and the substrate 110 to cover the gate electrode 120.
  • the gate insulating layer 130 serves as an insulating layer.
  • a silicon nitride film such as SiNx may be used, but an oxide insulator may be used as the insulating film, that is, an oxide insulator is used as the gate insulating layer 130.
  • the larger the dielectric constant of the oxide insulating film the more advantageous the operation of the thin film transistor.
  • the greater the insulation the better.
  • It may be an oxide insulating film having a superlattice structure of an oxide.
  • an amorphous oxide insulating film can also be used. In the case of the amorphous oxide insulating film, since the film formation temperature can be maintained at a low temperature, it is advantageous in the case of a substrate having poor heat resistance such as a plastic substrate.
  • barium aluminum silicate ScAlMgO 4
  • strontium aluminate sulphide ScAlZnO 4
  • strontium aluminum cobaltite ScAlCoO 4
  • strontium strontium manganate ScAlMnO 4
  • strontium gallium zinc hydride ScGaZnO 4
  • gallium magnesium scandium ScGaMgO 4
  • six tetroxide zinc aluminate scandium ScAlZn 3 O 6
  • seven tetroxide zinc aluminate scandium ScAlZn 4 O 7
  • seven zinc ten aluminum oxide of scandium ScAlZn 7 O 10
  • bismuth hexaluminate bismuth sulphate ScGaZn 3 O 6
  • bismuth pentoxide sulphide sulphate ScGaZn 5 O 8
  • an oxide such as alumina, titania, cerium oxide or cerium oxide or a composite oxide having a superlattice structure may also be used.
  • the semiconductor layer 140 is formed on the upper surface of the gate insulating layer 130 and above the gate electrode 120.
  • the semiconductor layer 140 is formed of silicon germanium oxide (SixGeyOz), and the semiconductor layer 140 is formed with a channel. Part 190.
  • the application can improve the electron mobility of the array substrate, and the electron mobility is the average carrier drift velocity generated under the unit electric field intensity.
  • the electron mobility represents the magnitude of the carrier's conductivity, and the carrier (electron or hole) concentration determines the conductivity of the semiconductor.
  • the electron mobility is inversely proportional to the effective mass and scattering probability of the carriers.
  • the effective mass of carriers is related to the material, in different semiconductors. Electronics have different effective qualities. The higher the electron mobility, the faster the device operates and the higher the cutoff frequency, making it suitable for display devices.
  • FIG. 2 is another schematic structural diagram of an array substrate according to an embodiment of the present application.
  • FIG. 2 shows only a part of the structure of the array substrate.
  • the array substrate of the embodiment of the present application includes the substrate 110 and the gate electrode 120. a gate insulating layer 130, a semiconductor layer 140, a source electrode 150, and a drain electrode 160.
  • the substrate 110 may include a glass plate, which has good light transmission type and is convenient to set. It should be noted that the substrate 110 of the embodiment is not limited thereto, and may also include other types, such as a flexible substrate.
  • the gate electrode 120 is formed on the upper surface of the substrate 110. Specifically, the gate electrode 120 may be formed by laying a gate line on the substrate 110.
  • the gate insulating layer 130 is formed on the upper surface of the gate electrode 120 and the substrate 110 to cover the gate electrode 120.
  • the gate insulating layer 130 serves as an insulating layer.
  • a silicon nitride film such as SiNx may be used, but an oxide insulator may be used as the insulating film, that is, an oxide insulator is used as the gate insulating layer 130.
  • the larger the dielectric constant of the oxide insulating film the more advantageous the operation of the thin film transistor.
  • the greater the insulation the better.
  • It may be an oxide insulating film having a superlattice structure of an oxide. Further, an amorphous oxide insulating film can also be used.
  • the film formation temperature can be maintained at a low temperature, it is advantageous in the case of a substrate having poor heat resistance such as a plastic substrate.
  • the specific components of the gate insulating layer are referred to the above embodiments, and are not described herein again.
  • the present application can improve the electron mobility of the active switch, and the mobility is the average drift velocity of the carrier generated under the unit electric field strength.
  • the mobility represents the amount of carrier conductivity, and the carrier (electron or hole) concentration determines the conductivity of the semiconductor.
  • the mobility is inversely proportional to the effective mass of the carriers and the probability of scattering.
  • the effective mass of carriers is related to materials, and electrons in different semiconductors have different effective masses. For example, the effective mass of electrons in silicon is 0.5m0 (m0 is the mass of free electrons), and the effective mass of electrons in gallium arsenide is 0.07m0.
  • the holes are divided into holes and light holes, which have an effective mass different from electrons.
  • carriers are mainly scattered by defects and impurities at low temperatures, and are mainly scattered by phonons generated by atomic lattice vibration at high temperatures.
  • the semiconductor layer 140 includes a doped layer 142 and an active layer 141; the doped layer 142 is located on top of the semiconductor layer 140, and is separated by the channel portion 190 to form two portions, and the drain electrode An adjacent portion and a portion adjacent to the source electrode 150; the active layer 141 is located at a bottom of the semiconductor layer 140, and the doped layer 142 is located at an upper surface of the active layer 141.
  • the doped layer 142 may be doped with an n-type semiconductor, such as doped polysilicon.
  • the source electrode 150 is formed on the surface of the gate insulating layer 130 and the semiconductor layer 140 and is located on the side of the channel portion 190. Specifically, the data line forming source electrode 150 may be laid on the gate insulating layer 130.
  • the drain electrode 160 is formed on the surface of the gate insulating layer 130 and the semiconductor layer 140 and on the other side of the channel portion 190. Specifically, a drain line 160 may be formed by laying a data line on the gate insulating layer 130.
  • FIG. 3 is another schematic structural diagram of an array substrate according to an embodiment of the present application.
  • FIG. 3 only shows a partial structure of the array substrate.
  • the array substrate 100 of the embodiment of the present application includes a substrate 110 and a gate electrode. 120, a gate insulating layer 130, a semiconductor layer 140, a source electrode 150, and a drain electrode 160.
  • the array substrate 100 further includes a protective layer 170 and a conductive layer 180; a protective layer 170 is formed on the upper surfaces of the source electrode 150 and the drain electrode 160, covering the source electrode 150 and the drain electrode 160, and the protective layer 170 is located in the channel Above section 190.
  • the protective layer 170 may be made of the same material as the gate insulating layer.
  • the conductive layer 180 is formed on the upper surface of the protective layer 170 and is separated by the channel portion 190.
  • the conductive layer 180 is an oxide conductor layer or a metal layer.
  • the substrate 110 can be made of a glass plate, which has good light transmission type and is convenient to set. It should be noted that the substrate 110 of the embodiment is not limited thereto, and may also include other types, such as a flexible substrate.
  • a gate electrode 120 is formed on an upper surface of the substrate 110. Specifically, the gate electrode 120 may be formed by laying a gate line on the substrate 110.
  • a gate insulating layer 130 is formed on the upper surface of the gate electrode 120 and the substrate 110 to cover the gate electrode 120.
  • the gate insulating layer 130 serves as an insulating layer.
  • the gate insulating layer 130 may be nitrided using SiNx or the like.
  • the larger the dielectric constant of the oxide insulating film the more advantageous the operation of the thin film transistor.
  • the greater the insulation the better.
  • It may be an oxide insulating film having a superlattice structure of an oxide. Further, an amorphous oxide insulating film can also be used.
  • the film formation temperature can be maintained at a low temperature, it is advantageous in the case of a substrate having poor heat resistance such as a plastic substrate.
  • the specific components of the gate insulating layer are referred to the above embodiments, and are not described herein again.
  • the semiconductor layer 140 is formed on the upper surface of the gate insulating layer 130 and above the gate electrode 120.
  • the semiconductor layer 140 is formed of silicon germanium oxide (SixGeyOz), and the semiconductor layer 140 is formed with the channel portion 190. .
  • the semiconductor layer 140 includes a doped layer 142 and an active layer 141; the doped layer 142 is located on top of the semiconductor layer 140, and is separated by the channel portion 190 to form two portions, and the drain electrode An adjacent portion and a portion adjacent to the source electrode 150; the active layer 141 is located at a bottom of the semiconductor layer 140, and the doped layer 142 is located at an upper surface of the active layer 141.
  • the doped layer 142 may be doped with an n-type semiconductor, such as doped polysilicon.
  • the source electrode 150 is formed on the surface of the gate insulating layer 130 and the semiconductor layer 140, and is located on the side of the channel portion 190. Specifically, the data line forming source electrode 150 may be laid on the gate insulating layer 130.
  • a drain electrode 160 is formed on the surface of the gate insulating layer 130 and the semiconductor layer 140, and is located on the other side of the channel portion 190. Specifically, a drain line 160 may be formed by laying a data line on the gate insulating layer 130.
  • FIG. 4 is another schematic structural diagram of an array substrate according to an embodiment of the present application, wherein FIG. 4 only shows a partial structure of the array substrate, and the array substrate 100 of the embodiment of the present application includes a substrate 110 and a gate electrode. 120, a gate insulating layer 130, a semiconductor layer 140, a source electrode 150, and a drain electrode 160.
  • the substrate 110 may include a glass plate, which has good light transmission type and is convenient to set. It should be noted that the substrate 110 of the embodiment is not limited thereto, and may also include other types, such as a flexible substrate.
  • the gate electrode 120 is formed on the upper surface of the substrate 110.
  • the substrate 110 can be A gate line is formed by laying a gate line.
  • the semiconductor layer 140 includes a doped layer 142 and an active layer 141; the doped layer 142 is located on top of the semiconductor layer 140, and is separated by the channel portion 190 to form two portions, and the drain electrode An adjacent portion and a portion adjacent to the source electrode 150; the active layer 141 is located at a bottom of the semiconductor layer 140, and the doped layer 142 is located at an upper surface of the active layer 141.
  • the doped layer 142 may be doped with an n-type semiconductor, such as doped polysilicon.
  • the doped layer 142 includes a first doped layer 143 and a second doped layer 144; the second doped layer 144 is located on top of the semiconductor layer 140, and the first doped layer 143 is located The bottom of the semiconductor layer 140 is between the second doped layer 144 and the active layer 141; the doping concentration of the second doped layer 144 is greater than the doping concentration of the first doped layer 143 .
  • the source electrode 150 is formed on the surface of the gate insulating layer 130 and the semiconductor layer 140 and is located on the side of the channel portion 190. Specifically, the data line forming source electrode 150 may be laid on the gate insulating layer 130.
  • the drain electrode 160 is formed on the surface of the gate insulating layer 130 and the semiconductor layer 140 and on the other side of the channel portion 190. Specifically, a drain line 160 may be formed by laying a data line on the gate insulating layer 130.
  • FIG. 5 is another schematic structural diagram of an array substrate according to an embodiment of the present application.
  • FIG. 5 shows only a partial structure of the array substrate.
  • the array substrate 100 of the embodiment of the present application includes a substrate 110 and a gate electrode. 120, a gate insulating layer 130, a semiconductor layer 140, a source electrode 150, and a drain electrode 160.
  • the substrate 110 may include a glass plate, which has good light transmission type and is convenient to set. It should be noted that the substrate 110 of the embodiment is not limited thereto, and may also include other types, such as a flexible substrate.
  • the gate electrode 120 is formed on the upper surface of the substrate 110. Specifically, the gate electrode 120 may be formed by laying a gate line on the substrate 110.
  • a gate insulating layer 130 is formed on the upper surface of the gate electrode 120 and the substrate 110, covering the surface The gate electrode 120 is described.
  • the gate insulating layer 130 serves as an insulating layer.
  • a silicon nitride film such as SiNx may be used, but an oxide insulator may be used as the insulating film, that is, an oxide insulator is used as the gate insulating layer 130.
  • the larger the dielectric constant of the oxide insulating film the more advantageous the operation of the thin film transistor.
  • the greater the insulation the better.
  • It may be an oxide insulating film having a superlattice structure of an oxide. Further, an amorphous oxide insulating film can also be used.
  • the film formation temperature can be maintained at a low temperature, it is advantageous in the case of a substrate having poor heat resistance such as a plastic substrate.
  • the specific components of the gate insulating layer are referred to the above embodiments, and are not described herein again.
  • the semiconductor layer 140 includes a doped layer 142 and an active layer 141; the doped layer 142 is located on top of the semiconductor layer 140, and is separated by the channel portion 190 to form two portions, and the drain electrode An adjacent portion and a portion adjacent to the source electrode 150; the active layer 141 is located at a bottom of the semiconductor layer 140, and the doped layer 142 is located at an upper surface of the active layer 141.
  • the doped layer 142 may be doped with an n-type semiconductor, such as doped polysilicon.
  • the doped layer 142 includes a first doped layer 143 and a second doped layer 144; the second doped layer 144 is located on top of the semiconductor layer 140, and the first doped layer 143 is located The bottom of the semiconductor layer 140 is between the second doped layer 144 and the active layer 141; the doping concentration of the second doped layer 144 is greater than the doping concentration of the first doped layer 143 .
  • the source electrode 150 is formed on the surface of the gate insulating layer 130 and the semiconductor layer 140 and is located on the side of the channel portion 190. Specifically, the data line forming source electrode 150 may be laid on the gate insulating layer 130.
  • the drain electrode 160 is formed on the surface of the gate insulating layer 130 and the semiconductor layer 140 and on the other side of the channel portion 190. Specifically, a drain line 160 may be formed by laying a data line on the gate insulating layer 130.
  • the array substrate 100 further includes a protective layer 170 formed on an upper surface of the source electrode 150 and the drain electrode 160, covering the source electrode 150 and the drain electrode 160, and the protective layer 170 is located in the channel portion 190 Above.
  • the protective layer 170 may be made of the same material as the gate insulating layer.
  • the array substrate further includes a conductive layer 180 formed on an upper surface of the protective layer 170 and separated by the channel portion 180.
  • the conductive layer 180 is an oxide conductor layer or a metal layer.
  • the embodiment further discloses a display panel, and the display panel includes
  • the plurality of pixel units 200 are correspondingly disposed on the display area of the array substrate 101; the control unit is coupled to the pixel unit 200; and the color filter substrate 102 is disposed in parallel with the array substrate.
  • a scanning line 121 and a data line 151 are arranged in the display area of the array substrate, and a plurality of rectangular squares are formed. Each rectangular square is correspondingly provided with one pixel unit 200.
  • the control unit includes a scanning driving circuit for driving the scanning lines. 310, and a data driving circuit 320 that drives the data lines, and a switching component 330 that controls the pixel unit 200.
  • the embodiment further discloses a manufacturing method of the display panel of the present application, where the manufacturing method includes:
  • the semiconductor layer is formed of silicon germanium oxide.
  • the substrate 110 may include a glass plate, which has a good light transmission type and is convenient to set. It should be noted that the substrate 110 of the embodiment is not limited thereto, and may also include other types, such as a flexible substrate.
  • the gate electrode 120 is formed on the upper surface of the substrate 110. Specifically, the gate electrode 120 may be formed by laying a gate line on the substrate 110.
  • the gate insulating layer 130 is formed on the upper surface of the gate electrode 120 and the substrate 110 to cover the gate electrode 120.
  • the gate insulating layer 130 serves as an insulating layer.
  • a silicon nitride film such as SiNx may be used, but an oxide insulator may be used as the insulating film, that is, an oxide insulator is used as the gate insulating layer 130.
  • the larger the dielectric constant of the oxide insulating film the more favorable the thin film transistor work.
  • the greater the insulation the better.
  • It may be an oxide insulating film having a superlattice structure of an oxide. Further, an amorphous oxide insulating film can also be used.
  • the film formation temperature can be maintained at a low temperature, it is advantageous in the case of a substrate having poor heat resistance such as a plastic substrate.
  • the specific components of the gate insulating layer are referred to the above embodiments, and are not described herein again.
  • the semiconductor layer 140 includes a doped layer 142 and an active layer 141; the doped layer 142 is located on top of the semiconductor layer 140, and is separated by the channel portion 190 to form two portions, and the drain electrode An adjacent portion and a portion adjacent to the source electrode 150; the active layer 141 is located at a bottom of the semiconductor layer 140, and the doped layer 142 is located at an upper surface of the active layer 141.
  • the doped layer 142 may be doped with an n-type semiconductor, such as doped polysilicon.
  • the doped layer 142 includes a first doped layer 143 and a second doped layer 144; the second doped layer 144 is located on top of the semiconductor layer 140, and the first doped layer 143 is located The bottom of the semiconductor layer 140 is between the second doped layer 144 and the active layer 141; the doping concentration of the second doped layer 144 is greater than the doping concentration of the first doped layer 143 .
  • the source electrode 150 is formed on the surface of the gate insulating layer 130 and the semiconductor layer 140 and is located on the side of the channel portion 190. Specifically, the data line forming source electrode 150 may be laid on the gate insulating layer 130.
  • the drain electrode 160 is formed on the surface of the gate insulating layer 130 and the semiconductor layer 140 and on the other side of the channel portion 190. Specifically, a drain line 160 may be formed by laying a data line on the gate insulating layer 130.
  • the display panel 100 further includes a protective layer 170 formed on an upper surface of the source electrode 150 and the drain electrode 160 covering the source electrode 150 and the drain electrode 160, and the protective layer 170 is located in the channel portion 190 Above.
  • the protective layer 170 may be made of the same material as the gate insulating layer.
  • the display panel further includes a conductive layer 180 formed on an upper surface of the protective layer 170 and separated by the channel portion 180.
  • the conductive layer 180 is an oxide conductor layer or a metal layer.
  • the display panel can be, for example, an LCD display panel, an OLED display panel, a QLED display panel, a curved display panel, or other display panel.

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  • Thin Film Transistor (AREA)

Abstract

一种阵列基板(100)和显示面板，阵列基板(100)包括：基板(110)、栅电极(120)、栅极绝缘层(130)、半导体层(140)、源电极(150)和漏电极(160)，栅电极(120)形成在基板(110)上表面；栅极绝缘层(130)形成在栅电极(120)和基板(110)上表面，覆盖栅电极(120)；半导体层(140)形成在栅极绝缘层(130)上表面，且位于栅电极(120)上方，半导体层(140)由硅锗氧化物形成，半导体层(140)形成有沟道部(190)；源电极(150)形成在栅极绝缘层(130)和半导体层(140)表面，且位于沟道部(190)一侧；漏电极(160)形成在栅极绝缘层(130)和半导体层(140)表面，且位于沟道部(190)另一侧。

Description

一种阵列基板和显示面板 【技术领域】
本申请涉及显示技术领域，尤其涉及一种阵列基板和显示面板。
【背景技术】
液晶显示器具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(Backlight Module)。液晶面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
其中，薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由于具有低的功耗、优异的画面品质以及较高的生产良率等性能，目前已经逐渐占据了显示领域的主导地位。同样，薄膜晶体管液晶显示器包含液晶面板和背光模组，液晶面板包括彩膜基板(Color Filter Substrate，CF Substrate，也称彩色滤光片基板)和薄膜晶体管阵列基板(Thin Film Transistor Substrate，TFT Substrate)，上述基板的相对内侧存在透明电极。两片基板之间夹一层液晶分子(Liquid Crystal，LC)。液晶面板是通过电场对液晶分子取向的控制，改变光的偏振状态，并藉由偏光板实现光路的穿透与阻挡，实现显示的目的。
在现有的TFT基板形成在一基板上有半导体层，一般为n型半导体形成，比如：非晶硅或多晶硅。其中，多晶硅的电子移动率比非晶硅的电子移动率高。但是，随着对显示面板要求的提高，多晶硅的电子移动率已不能显示装置的需求。
【发明内容】
本申请的一个目的在于提供一种显示面板，旨在设置半导体层满足显示装置的需求。
为解决上述问题，本申请的实施例提供了一种阵列基板，所述显示面板包括：
一基板，所述基板包括多个开关组件；其中，所述开关组件包括：
栅电极，形成在所述基板上表面；
栅极绝缘层，形成在所述栅电极和基板上表面，覆盖所述栅电极；
半导体层，形成在所述栅极绝缘层上表面，且位于所述栅电极上方，所述半导体层由硅锗氧化物形成，所述半导体层形成有沟道部；
源电极，形成在所述栅极绝缘层和半导体层表面，且位于所述沟道部一侧；
漏电极，形成在所述栅极绝缘层和半导体层表面，且位于所述沟道部另一侧。
进一步的，所述半导体层包括掺杂层；
所述掺杂层位于所述半导体层顶部，且被所述沟道部隔开，形成两部分，与所述漏电极相邻的部分和与所述源电极相邻的部分；
所述有源层位于所述半导体层底部，所述掺杂层位于所述有源层上表面。
进一步的，所述掺杂层包括第一掺杂层和第二掺杂层；
所述第二掺杂层位于所述半导体层顶部，所述第一掺杂层位于所述半导体层底部，且位于所述第二掺杂层和有源层之间；
所述第二掺杂层的掺杂浓度大于所述第一掺杂层的掺杂浓度。
进一步的，所述显示面板还包括：
保护层，形成在源电极和漏电极上表面，覆盖所述源电极和漏电极，且所述保护层位于所述沟道部上方。
进一步的，所述显示面板还包括：
导电层，形成在所述保护层上表面，且由所述沟道部隔开。
进一步的，所述导电层是氧化物导电体层。
进一步的，所述导电层是金属层。
进一步的，所述基板为玻璃基板。
进一步的，所述栅极绝缘层由氮化硅形成。
进一步的，所述栅极绝缘层是氧化物绝缘膜形成。
TFT基板的半导体层一般采用非晶硅或多晶硅，其中，非晶硅的电子移动率为0.5至0.8cm2/V.s，多晶硅的电子移动率比非晶硅略高，但是其电子移动率不高，不能满足现有显示装置的需求。
作为本申请的另一方面，本申请还公开了一种显示面板，所述显示面板包括本申请所述的阵列基板；还包括：
多个像素单元，对应设置于阵列基板的显示区域；
控制单元，与像素单元耦合；
彩膜基板，与阵列基板平行相向设置。
进一步的，所述阵列基板还包括
数据线，与多个像素单元耦合，控制像素单元的显示灰阶；
扫描线，与多个像素单元耦合，控制像素单元导通；
数据驱动电路，与数据线耦合；
扫描驱动电路，与扫描线耦合。
作为本申请的另一方面，本申请还公开了一种显示面板的制造方法，所述制造方法包括：
在基板上形成栅电极；
在栅电极上形成栅极绝缘层和半导体层；
在半导体层上形成源电极和漏电极；
所述述半导体层由硅锗氧化物形成。
本申请的大大提高了主动开关的电子移动率，使其满足显示装置的需求。
【附图说明】
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原 理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请一个实施例的阵列基板的结构示意图；
图2是本申请一个实施例的阵列基板的另一结构示意图；
图3是本申请一个实施例的阵列基板的另一结构示意图；
图4是本申请一个实施例的阵列基板的另一结构示意图；
图5是本申请一个实施例的阵列基板的另一结构示意图；
图6是本申请一个实施例的显示面板的另一结构示意图；
图7是本申请一个实施例的显示面板的剖面结构示意图；
图8是本申请一个实施例的显示面板的制造方法的示意图。
【具体实施方式】
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
在图中，结构相似的单元是以相同标号表示。
下面参考附图1-7和较佳的实施例进一步详细描述本申请的阵列基板。
本申请以下实施例中的阵列基板100可设置于本申请实施例的显示装置中，也就是说本申请实施例的显示装置包括有以下任一实施例的阵列基板100。所述显示装置可以为液晶显示器，也可以为OLED(Organic Light-Emitting Diode)显示器。其中，当本申请实施例的显示装置为液晶显示器时，液晶显示器包括有背光模组，背光模组可作为光源，用于供应充足的亮度与分布均匀的光源，本实施例的背光模组可以为前光式，也可以为背光式，需要说明的是，本实施例的背光模组并不限于此。
下面以阵列基板100为例进行详细说明，需要说明的是，以下对阵列基板100的描述同样适用于本申请实施例的显示装置中。
如图1所示，图1为本申请一实施例阵列基板的结构示意图，其中图1中仅示出了阵列基板的部分结构，本申请一实施例的阵列基板100包括基板110、栅电极120、栅极绝缘层130、半导体层140、源电极150和漏电极160。
其中，基板110可以包括玻璃板，其透光型好，方便设置。需要说明的是，本实施例的基板110并不限于此，也可以包括其他类型，比如：可挠式基板。
其中，栅电极120形成在所述基板110上表面。具体的，可以在基板110上铺设栅极线形成栅电极120。
其中，栅极绝缘层130形成在所述栅电极120和基板110上表面，覆盖所述栅电极120。栅极绝缘层130起到绝缘作用。栅极绝缘层130可以使用SiNx等氮化硅膜，但也可以将氧化物绝缘体用作绝缘膜，即将氧化物绝缘体用作栅极绝缘层130。在此情况下，氧化物绝缘膜的介电常数越大，越有利于薄膜晶体管的工作。此外，绝缘性越大越好。其可以是具有氧化物的超晶格构造的氧化物绝缘膜。进而，也能够使用非晶体的氧化物绝缘膜。在非晶体氧化物绝缘膜的情况下，能够将成膜温度维持在低温，因此，在塑料基板等耐热性欠缺的基板的情况下是有利的。
例如，也可以使用铝镁酸钪(ScAlMgO4)、铝锌酸钪(ScAlZnO4)、铝钴酸钪(ScAlCoO4)、铝锰酸钪(ScAlMnO4)、镓锌酸钪(ScGaZnO4)、镓镁酸钪(ScGaMgO4)或者六氧化三锌铝酸钪(ScAlZn3O6)、七氧化四锌铝酸钪(ScAlZn4O7)、十氧化七锌铝酸钪(ScAlZn7O10)、或者六氧化三锌镓酸钪(ScGaZn3O6)、八氧化五锌镓酸钪(ScGaZn5O8)、十氧化七锌镓酸钪(ScGaZn7O10)或者五氧化二锌铁酸钪(ScFeZn2O5)、六氧化三锌铁酸钪(ScFeZn3O6)、九氧化六锌铁酸钪(ScFeZn6O9)等。
此外，也可以使用氧化铝、氧化钛、氧化铪、氧化镧等氧化物以及超晶格构造的复合氧化物。
其中，半导体层140形成在所述栅极绝缘层130上表面，且位于所述栅电极120上方，所述半导体层140由硅锗氧化物(SixGeyOz)形成，所述半导体层140形成有沟道部190。
本申请可以提高了阵列基板的电子移动率，电子移动率是单位电场强度下所产生的载流子平均漂移速度。电子移动率代表了载流子导电能力的大小，它和载流子(电子或空穴)浓度决定了半导体的电导率。电子移动率与载流子的有效质量和散射概率成反比。载流子的有效质量与材料有关，不同的半导体中 电子有不同的有效质量。电子移动率越大，器件的运行速度越快，截止频率就越高，使其满足显示装置的需求。
如图2所示，图2为本申请一实施例阵列基板的另一结构示意图，其中图2仅示出了阵列基板的部分结构，本申请一实施例的阵列基板包括基板110、栅电极120、栅极绝缘层130、半导体层140、源电极150和漏电极160。
其中，基板110可以包括玻璃板，其透光型好，方便设置。需要说明的是，本实施例的基板110并不限于此，也可以包括其他类型，比如：可挠式基板。
其中，栅电极120形成在所述基板110上表面。具体的，可以在基板110上铺设栅极线形成栅电极120。
其中，栅极绝缘层130形成在所述栅电极120和基板110上表面，覆盖所述栅电极120。栅极绝缘层130起到绝缘作用。栅极绝缘层130可以使用SiNx等氮化硅膜，但也可以将氧化物绝缘体用作绝缘膜，即将氧化物绝缘体用作栅极绝缘层130。在此情况下，氧化物绝缘膜的介电常数越大，越有利于薄膜晶体管的工作。此外，绝缘性越大越好。其可以是具有氧化物的超晶格构造的氧化物绝缘膜。进而，也能够使用非晶体的氧化物绝缘膜。在非晶体氧化物绝缘膜的情况下，能够将成膜温度维持在低温，因此，在塑料基板等耐热性欠缺的基板的情况下是有利的。栅极绝缘层的具体成分参考上述实施方式，在此不再赘述。
本申请可以提高主动开关的电子迁移率，迁移率是单位电场强度下所产生的载流子平均漂移速度。迁移率代表了载流子导电能力的大小，它和载流子(电子或空穴)浓度决定了半导体的电导率。迁移率与载流子的有效质量和散射概率成反比。载流子的有效质量与材料有关，不同的半导体中电子有不同的有效质量。如硅中电子的有效质量为0.5m0(m0是自由电子质量)，砷化镓中电子的有效质量为0.07m0。空穴分重空穴和轻空穴，它们具有与电子不同的有效质量。半导体中载流子在低温下主要受到缺陷和杂质的散射，高温下主要受到由原子晶格振动产生的声子的散射。迁移率越大，器件的运行速度越快，截止频率就越高。因此，本申请的改进可以有效提高主动开关的性能。
所述半导体层140包括掺杂层142和有源层141；所述掺杂层142位于所述半导体层140顶部，且被所述沟道部190隔开，形成两部分，与所述漏电极160相邻的部分和与所述源电极150相邻的部分；所述有源层141位于所述半导体层140底部，所述掺杂层142位于所述有源层141上表面。
具体的，可以在掺杂层142中掺杂n型半导体，比如，掺杂多晶硅。
其中，源电极150形成在所述栅极绝缘层130和半导体层140表面，且位于所述沟道部190一侧。具体的，可以在栅极绝缘层130上铺设数据线形成源电极150。
其中，漏电极160形成在所述栅极绝缘层130和半导体层140表面，且位于所述沟道部190另一侧。具体的，可以在栅极绝缘层130上铺设数据线形成漏电极160。
如图3所示，图3为本申请一实施例阵列基板的另一结构示意图，其中图3仅示出了阵列基板的部分结构，本申请一实施例的阵列基板100包括基板110、栅电极120、栅极绝缘层130、半导体层140、源电极150和漏电极160。阵列基板100还包括保护层170和导电层180；保护层170形成在源电极150和漏电极160上表面，覆盖所述源电极150和漏电极160，且所述保护层170位于所述沟道部190上方。保护层170可以采用与栅极绝缘层相同的材料。
所述导电层180形成在所述保护层170上表面，且由所述沟道部190隔开。导电层180是氧化物导电体层，也可以金属层。
基板110可以采用玻璃板，其透光型好，方便设置。需要说明的是，本实施例的基板110并不限于此，也可以包括其他类型，比如：可挠式基板。
栅电极120形成在所述基板110上表面。具体的，可以在基板110上铺设栅极线形成栅电极120。
栅极绝缘层130形成在所述栅电极120和基板110上表面，覆盖所述栅电极120。栅极绝缘层130起到绝缘作用。栅极绝缘层130可以使用SiNx等氮化 硅膜，但也可以将氧化物绝缘体用作绝缘膜，即将氧化物绝缘体用作栅极绝缘层130。在此情况下，氧化物绝缘膜的介电常数越大，越有利于薄膜晶体管的工作。此外，绝缘性越大越好。其可以是具有氧化物的超晶格构造的氧化物绝缘膜。进而，也能够使用非晶体的氧化物绝缘膜。在非晶体氧化物绝缘膜的情况下，能够将成膜温度维持在低温，因此，在塑料基板等耐热性欠缺的基板的情况下是有利的。栅极绝缘层的具体成分参考上述实施方式，在此不再赘述。
半导体层140形成在所述栅极绝缘层130上表面，且位于所述栅电极120上方，所述半导体层140由硅锗氧化物(SixGeyOz)形成，所述半导体层140形成有沟道部190。
所述半导体层140包括掺杂层142和有源层141；所述掺杂层142位于所述半导体层140顶部，且被所述沟道部190隔开，形成两部分，与所述漏电极160相邻的部分和与所述源电极150相邻的部分；所述有源层141位于所述半导体层140底部，所述掺杂层142位于所述有源层141上表面。
具体的，可以在掺杂层142中掺杂n型半导体，比如，掺杂多晶硅。
源电极150形成在所述栅极绝缘层130和半导体层140表面，且位于所述沟道部190一侧。具体的，可以在栅极绝缘层130上铺设数据线形成源电极150。
漏电极160形成在所述栅极绝缘层130和半导体层140表面，且位于所述沟道部190另一侧。具体的，可以在栅极绝缘层130上铺设数据线形成漏电极160。
如图4所示，图4为本申请一实施例阵列基板的另一结构示意图，其中图4仅示出了阵列基板的部分结构，本申请一实施例的阵列基板100包括基板110、栅电极120、栅极绝缘层130、半导体层140、源电极150和漏电极160。
其中，基板110可以包括玻璃板，其透光型好，方便设置。需要说明的是，本实施例的基板110并不限于此，也可以包括其他类型，比如：可挠式基板。
其中，栅电极120形成在所述基板110上表面。具体的，可以在基板110 上铺设栅极线形成栅电极120。
所述半导体层140包括掺杂层142和有源层141；所述掺杂层142位于所述半导体层140顶部，且被所述沟道部190隔开，形成两部分，与所述漏电极160相邻的部分和与所述源电极150相邻的部分；所述有源层141位于所述半导体层140底部，所述掺杂层142位于所述有源层141上表面。
具体的，可以在掺杂层142中掺杂n型半导体，比如，掺杂多晶硅。
更具体的，所述掺杂层142包括第一掺杂层143和第二掺杂层144；所述第二掺杂层144位于所述半导体层140顶部，所述第一掺杂层143位于所述半导体层140底部之间，且位于第二掺杂层144和有源层141之间；所述第二掺杂层144的掺杂浓度大于所述第一掺杂层143的掺杂浓度。
其中，源电极150形成在所述栅极绝缘层130和半导体层140表面，且位于所述沟道部190一侧。具体的，可以在栅极绝缘层130上铺设数据线形成源电极150。
其中，漏电极160形成在所述栅极绝缘层130和半导体层140表面，且位于所述沟道部190另一侧。具体的，可以在栅极绝缘层130上铺设数据线形成漏电极160。
如图5所示，图5为本申请一实施例阵列基板的另一结构示意图，其中图5仅示出了阵列基板的部分结构，本申请一实施例的阵列基板100包括基板110、栅电极120、栅极绝缘层130、半导体层140、源电极150和漏电极160。
其中，基板110可以包括玻璃板，其透光型好，方便设置。需要说明的是，本实施例的基板110并不限于此，也可以包括其他类型，比如：可挠式基板。
其中，栅电极120形成在所述基板110上表面。具体的，可以在基板110上铺设栅极线形成栅电极120。
其中，栅极绝缘层130形成在所述栅电极120和基板110上表面，覆盖所 述栅电极120。栅极绝缘层130起到绝缘作用。栅极绝缘层130可以使用SiNx等氮化硅膜，但也可以将氧化物绝缘体用作绝缘膜，即将氧化物绝缘体用作栅极绝缘层130。在此情况下，氧化物绝缘膜的介电常数越大，越有利于薄膜晶体管的工作。此外，绝缘性越大越好。其可以是具有氧化物的超晶格构造的氧化物绝缘膜。进而，也能够使用非晶体的氧化物绝缘膜。在非晶体氧化物绝缘膜的情况下，能够将成膜温度维持在低温，因此，在塑料基板等耐热性欠缺的基板的情况下是有利的。栅极绝缘层的具体成分参考上述实施方式，在此不再赘述。
所述半导体层140包括掺杂层142和有源层141；所述掺杂层142位于所述半导体层140顶部，且被所述沟道部190隔开，形成两部分，与所述漏电极160相邻的部分和与所述源电极150相邻的部分；所述有源层141位于所述半导体层140底部，所述掺杂层142位于所述有源层141上表面。
具体的，可以在掺杂层142中掺杂n型半导体，比如，掺杂多晶硅。
更具体的，所述掺杂层142包括第一掺杂层143和第二掺杂层144；所述第二掺杂层144位于所述半导体层140顶部，所述第一掺杂层143位于所述半导体层140底部之间，且位于第二掺杂层144和有源层141之间；所述第二掺杂层144的掺杂浓度大于所述第一掺杂层143的掺杂浓度。
其中，源电极150形成在所述栅极绝缘层130和半导体层140表面，且位于所述沟道部190一侧。具体的，可以在栅极绝缘层130上铺设数据线形成源电极150。
其中，漏电极160形成在所述栅极绝缘层130和半导体层140表面，且位于所述沟道部190另一侧。具体的，可以在栅极绝缘层130上铺设数据线形成漏电极160。
所述阵列基板100还包括保护层170：保护层170形成在源电极150和漏电极160上表面，覆盖所述源电极150和漏电极160，且所述保护层170位于所述沟道部190上方。
其中，保护层170可以采用与栅极绝缘层相同的材料。
所述阵列基板还包括导电层180，所述导电层180形成在所述保护层170上表面，且由所述沟道部180隔开。导电层180是氧化物导电体层，也可以金属层。
参考图6、7，本实施方式还公开了一种显示面板，所述显示面板包括
多个像素单元200，对应设置于阵列基板101的显示区域；控制单元，与像素单元200耦合；彩膜基板102，与阵列基板平行相向设置。阵列基板的显示区域内设置有纵横交错的扫描线121和数据线151，形成多个矩形方格，每个矩形方格对应设置一个像素单元200；所述控制单元包括驱动扫描线的扫描驱动电路310，以及驱动数据线的数据驱动电路320，以及控制像素单元200的开关组件330。
参考图8，本实施方式还公开了一种本申请显示面板的制造方法，所述制造方法包括：
S81、在基板上形成栅电极；
S82、在栅电极上形成栅极绝缘层和半导体层；
S83、在半导体层上形成源电极和漏电极；
S84、所述述半导体层由硅锗氧化物形成。
参考图5，基板110可以包括玻璃板，其透光型好，方便设置。需要说明的是，本实施例的基板110并不限于此，也可以包括其他类型，比如：可挠式基板。
其中，栅电极120形成在所述基板110上表面。具体的，可以在基板110上铺设栅极线形成栅电极120。
其中，栅极绝缘层130形成在所述栅电极120和基板110上表面，覆盖所述栅电极120。栅极绝缘层130起到绝缘作用。栅极绝缘层130可以使用SiNx等氮化硅膜，但也可以将氧化物绝缘体用作绝缘膜，即将氧化物绝缘体用作栅极绝缘层130。在此情况下，氧化物绝缘膜的介电常数越大，越有利于薄膜晶体管 的工作。此外，绝缘性越大越好。其可以是具有氧化物的超晶格构造的氧化物绝缘膜。进而，也能够使用非晶体的氧化物绝缘膜。在非晶体氧化物绝缘膜的情况下，能够将成膜温度维持在低温，因此，在塑料基板等耐热性欠缺的基板的情况下是有利的。栅极绝缘层的具体成分参考上述实施方式，在此不再赘述。
所述半导体层140包括掺杂层142和有源层141；所述掺杂层142位于所述半导体层140顶部，且被所述沟道部190隔开，形成两部分，与所述漏电极160相邻的部分和与所述源电极150相邻的部分；所述有源层141位于所述半导体层140底部，所述掺杂层142位于所述有源层141上表面。
具体的，可以在掺杂层142中掺杂n型半导体，比如，掺杂多晶硅。
更具体的，所述掺杂层142包括第一掺杂层143和第二掺杂层144；所述第二掺杂层144位于所述半导体层140顶部，所述第一掺杂层143位于所述半导体层140底部之间，且位于第二掺杂层144和有源层141之间；所述第二掺杂层144的掺杂浓度大于所述第一掺杂层143的掺杂浓度。
其中，源电极150形成在所述栅极绝缘层130和半导体层140表面，且位于所述沟道部190一侧。具体的，可以在栅极绝缘层130上铺设数据线形成源电极150。
其中，漏电极160形成在所述栅极绝缘层130和半导体层140表面，且位于所述沟道部190另一侧。具体的，可以在栅极绝缘层130上铺设数据线形成漏电极160。
所述显示面板100还包括保护层170：保护层170形成在源电极150和漏电极160上表面，覆盖所述源电极150和漏电极160，且所述保护层170位于所述沟道部190上方。
其中，保护层170可以采用与栅极绝缘层相同的材料。
所述显示面板还包括导电层180，所述导电层180形成在所述保护层170上表面，且由所述沟道部180隔开。导电层180是氧化物导电体层，也可以金属层。
显示面板可例如为LCD显示面板、OLED显示面板、QLED显示面板、曲面显示面板或其他显示面板。
以上内容是结合具体的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种阵列基板，包括：
    一基板，所述基板包括多个开关组件；其中，所述开关组件包括：
    栅电极，形成在所述基板上表面；
    栅极绝缘层，形成在所述栅电极和基板上表面，覆盖所述栅电极；
    半导体层，形成在所述栅极绝缘层上表面，且位于所述栅电极上方，所述半导体层由硅锗氧化物形成，所述半导体层形成有沟道部；
    源电极，形成在所述栅极绝缘层和半导体层表面，且位于所述沟道部一侧；
    漏电极，形成在所述栅极绝缘层和半导体层表面，且位于所述沟道部另一侧；
    保护层，形成在源电极和漏电极上表面，覆盖所述源电极和漏电极，且所述保护层位于所述沟道部上方；
    导电层，形成在所述保护层上表面，且由所述沟道部隔开；
    其中,所述半导体层包括掺杂层和有源层；所述掺杂层位于所述半导体层顶部，且被所述沟道部隔开，形成两部分，与所述漏电极相邻的部分和与所述源电极相邻的部分；所述有源层位于所述半导体层底部，所述掺杂层位于所述有源层上表面；所述掺杂层包括第一掺杂层和第二掺杂层；所述第二掺杂层位于所述半导体层顶部，所述第一掺杂层位于所述半导体层底部，且位于所述第二掺杂层和有源层之间；所述第二掺杂层的掺杂浓度大于所述第一掺杂层的掺杂浓度。
  2. 一种阵列基板，包括：
    一基板，所述基板包括多个开关组件；其中，所述开关组件包括：
    栅电极，形成在所述基板上表面；
    栅极绝缘层，形成在所述栅电极和基板上表面，覆盖所述栅电极；
    半导体层，形成在所述栅极绝缘层上表面，且位于所述栅电极上方，所述 半导体层由硅锗氧化物形成，所述半导体层形成有沟道部；
    源电极，形成在所述栅极绝缘层和半导体层表面，且位于所述沟道部一侧；
    漏电极，形成在所述栅极绝缘层和半导体层表面，且位于所述沟道部另一侧。
  3. 如权利要求2所述的阵列基板，其中所述半导体层包括掺杂层和有源层；
    所述掺杂层位于所述半导体层顶部，且被所述沟道部隔开，形成两部分，与所述漏电极相邻的部分和与所述源电极相邻的部分；
    所述有源层位于所述半导体层底部，所述掺杂层位于所述有源层上表面。
  4. 如权利要求3所述的阵列基板，其中所述掺杂层包括第一掺杂层和第二掺杂层；
    所述第二掺杂层位于所述半导体层顶部，所述第一掺杂层位于所述半导体层底部，且位于所述第二掺杂层和有源层之间；
    所述第二掺杂层的掺杂浓度大于所述第一掺杂层的掺杂浓度。
  5. 如权利要求2所述的阵列基板，其中所述半导体层包括掺杂层和有源层；
    所述掺杂层位于所述半导体层顶部，且被所述沟道部隔开，形成两部分，与所述漏电极相邻的部分和与所述源电极相邻的部分；
    所述有源层位于所述半导体层底部，所述掺杂层位于所述有源层上表面；
    所述掺杂层包括第一掺杂层和第二掺杂层；
    所述第二掺杂层位于所述半导体层顶部，所述第一掺杂层位于所述半导体层底部，且位于所述第二掺杂层和有源层之间；
    所述第二掺杂层的掺杂浓度大于所述第一掺杂层的掺杂浓度。
  6. 如权利要求2所述的阵列基板，其中所述阵列基板还包括：
    保护层，形成在源电极和漏电极上表面，覆盖所述源电极和漏电极，且所述保护层位于所述沟道部上方；
    导电层，形成在所述保护层上表面，且由所述沟道部隔开。
  7. 如权利要求6所述的阵列基板，其中所述导电层是氧化物导电体层。
  8. 如权利要求2所述的阵列基板，其中所述阵列基板还包括：
    保护层，形成在源电极和漏电极上表面，覆盖所述源电极和漏电极，且所述保护层位于所述沟道部上方；
    导电层，形成在所述保护层上表面，且由所述沟道部隔开；
    所述导电层是氧化物导电体层。
  9. 如权利要求2所述的阵列基板，其中所述半导体层包括掺杂层和有源层；
    所述掺杂层位于所述半导体层顶部，且被所述沟道部隔开，形成两部分，与所述漏电极相邻的部分和与所述源电极相邻的部分；
    所述有源层位于所述半导体层底部，所述掺杂层位于所述有源层上表面；
    所述掺杂层包括第一掺杂层和第二掺杂层；
    所述第二掺杂层位于所述半导体层顶部，所述第一掺杂层位于所述半导体层底部，且位于所述第二掺杂层和有源层之间；
    所述第二掺杂层的掺杂浓度大于所述第一掺杂层的掺杂浓度；
    所述阵列基板还包括：保护层，形成在源电极和漏电极上表面，覆盖所述源电极和漏电极，且所述保护层位于所述沟道部上方；导电层，形成在所述保护层上表面，且由所述沟道部隔开；所述导电层是氧化物导电体层。
  10. 如权利要求6所述的阵列基板，其中所述导电层是金属层。
  11. 如权利要求2所述的阵列基板，其中所述阵列基板还包括：
    保护层，形成在源电极和漏电极上表面，覆盖所述源电极和漏电极，且所述保护层位于所述沟道部上方；
    导电层，形成在所述保护层上表面，且由所述沟道部隔开；
    所述导电层是金属层。
  12. 如权利要求2所述的阵列基板，其中所述半导体层包括掺杂层和有源层；
    所述掺杂层位于所述半导体层顶部，且被所述沟道部隔开，形成两部分，与所述漏电极相邻的部分和与所述源电极相邻的部分；
    所述有源层位于所述半导体层底部，所述掺杂层位于所述有源层上表面；
    所述掺杂层包括第一掺杂层和第二掺杂层；
    所述第二掺杂层位于所述半导体层顶部，所述第一掺杂层位于所述半导体层底部，且位于所述第二掺杂层和有源层之间；
    所述第二掺杂层的掺杂浓度大于所述第一掺杂层的掺杂浓度；
    所述阵列基板还包括：保护层，形成在源电极和漏电极上表面，覆盖所述源电极和漏电极，且所述保护层位于所述沟道部上方；导电层，形成在所述保护层上表面，且由所述沟道部隔开；所述导电层是金属层。
  13. 根据权利要求2所述的阵列基板，其中所述栅极绝缘层由氮化硅形成。
  14. 如权利要求2所述的阵列基板，其中所述半导体层包括掺杂层和有源层；
    所述掺杂层位于所述半导体层顶部，且被所述沟道部隔开，形成两部分，与所述漏电极相邻的部分和与所述源电极相邻的部分；
    所述有源层位于所述半导体层底部，所述掺杂层位于所述有源层上表面；
    所述掺杂层包括第一掺杂层和第二掺杂层；
    所述第二掺杂层位于所述半导体层顶部，所述第一掺杂层位于所述半导体层底部，且位于所述第二掺杂层和有源层之间；
    所述第二掺杂层的掺杂浓度大于所述第一掺杂层的掺杂浓度；
    所述阵列基板还包括：保护层，形成在源电极和漏电极上表面，覆盖所述源电极和漏电极，且所述保护层位于所述沟道部上方；导电层，形成在所述保护层上表面，且由所述沟道部隔开；所述导电层是氧化物导电体层，或者，所述导电层是金属层；
    所述栅极绝缘层由氮化硅形成。
  15. 根据权利要求2所述的阵列基板，其中所述栅极绝缘层是氧化物绝缘膜形成。
  16. 如权利要求2所述的阵列基板，其中所述半导体层包括掺杂层和有源 层；
    所述掺杂层位于所述半导体层顶部，且被所述沟道部隔开，形成两部分，与所述漏电极相邻的部分和与所述源电极相邻的部分；
    所述有源层位于所述半导体层底部，所述掺杂层位于所述有源层上表面；
    所述掺杂层包括第一掺杂层和第二掺杂层；
    所述第二掺杂层位于所述半导体层顶部，所述第一掺杂层位于所述半导体层底部，且位于所述第二掺杂层和有源层之间；
    所述第二掺杂层的掺杂浓度大于所述第一掺杂层的掺杂浓度；
    所述阵列基板还包括：保护层，形成在源电极和漏电极上表面，覆盖所述源电极和漏电极，且所述保护层位于所述沟道部上方；导电层，形成在所述保护层上表面，且由所述沟道部隔开；所述导电层是氧化物导电体层，或者，所述导电层是金属层；
    所述栅极绝缘层是氧化物绝缘膜形成。
  17. 如权利要求2所述的阵列基板，其中所述半导体层包括掺杂层和有源层；
    所述掺杂层位于所述半导体层顶部，且被所述沟道部隔开，形成两部分，与所述漏电极相邻的部分和与所述源电极相邻的部分；
    所述有源层位于所述半导体层底部，所述掺杂层位于所述有源层上表面；
    所述掺杂层包括第一掺杂层和第二掺杂层；
    所述第二掺杂层位于所述半导体层顶部，所述第一掺杂层位于所述半导体层底部，且位于所述第二掺杂层和有源层之间；
    所述第二掺杂层的掺杂浓度大于所述第一掺杂层的掺杂浓度；
    所述阵列基板还包括：保护层，形成在源电极和漏电极上表面，覆盖所述源电极和漏电极，且所述保护层位于所述沟道部上方；导电层，形成在所述保护层上表面，且由所述沟道部隔开；所述导电层是氧化物导电体层，或者，所述导电层是金属层；
    所述栅极绝缘层由氮化硅形成，或者，所述栅极绝缘层是氧化物绝缘膜形成。
  18. 一种显示面板，包括：
    多个像素单元，设置于阵列基板的显示区域；
    控制单元，与像素单元耦合；
    彩膜基板，与阵列基板相向设置；
    阵列基板，所述阵列基板包括：
    一基板，所述基板包括多个开关组件；其中，所述开关组件包括：
    栅电极，形成在所述基板上表面；
    栅极绝缘层，形成在所述栅电极和基板上表面，覆盖所述栅电极；
    半导体层，形成在所述栅极绝缘层上表面，且位于所述栅电极上方，所述半导体层由硅锗氧化物形成，所述半导体层形成有沟道部；
    源电极，形成在所述栅极绝缘层和半导体层表面，且位于所述沟道部一侧；
    漏电极，形成在所述栅极绝缘层和半导体层表面，且位于所述沟道部另一侧。
  19. 如权利要求18所述的显示面板，其中所述半导体层包括掺杂层和有源层；
    所述掺杂层位于所述半导体层顶部，且被所述沟道部隔开，形成两部分，与所述漏电极相邻的部分和与所述源电极相邻的部分；
    所述有源层位于所述半导体层底部，所述掺杂层位于所述有源层上表面；
    所述掺杂层包括第一掺杂层和第二掺杂层；
    所述第二掺杂层位于所述半导体层顶部，所述第一掺杂层位于所述半导体层底部，且位于所述第二掺杂层和有源层之间；
    所述第二掺杂层的掺杂浓度大于所述第一掺杂层的掺杂浓度。
  20. 如权利要求18所述的显示面板，其中所述半导体层包括掺杂层和有源层；
    所述掺杂层位于所述半导体层顶部，且被所述沟道部隔开，形成两部分，与所述漏电极相邻的部分和与所述源电极相邻的部分；
    所述有源层位于所述半导体层底部，所述掺杂层位于所述有源层上表面；
    所述掺杂层包括第一掺杂层和第二掺杂层；
    所述第二掺杂层位于所述半导体层顶部，所述第一掺杂层位于所述半导体层底部，且位于所述第二掺杂层和有源层之间；
    所述第二掺杂层的掺杂浓度大于所述第一掺杂层的掺杂浓度；
    所述阵列基板还包括：保护层，形成在源电极和漏电极上表面，覆盖所述源电极和漏电极，且所述保护层位于所述沟道部上方；导电层，形成在所述保护层上表面，且由所述沟道部隔开；所述导电层是氧化物导电体层，或者，所述导电层是金属层；
    所述栅极绝缘层由氮化硅形成，或者，所述栅极绝缘层是氧化物绝缘膜形成。
PCT/CN2017/096714 2017-07-06 2017-08-10 一种阵列基板和显示面板 WO2019006817A1 (zh)

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