WO2015172492A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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WO2015172492A1
WO2015172492A1 PCT/CN2014/086999 CN2014086999W WO2015172492A1 WO 2015172492 A1 WO2015172492 A1 WO 2015172492A1 CN 2014086999 W CN2014086999 W CN 2014086999W WO 2015172492 A1 WO2015172492 A1 WO 2015172492A1
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pixel electrode
array substrate
drain
insulating layer
substrate according
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PCT/CN2014/086999
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English (en)
French (fr)
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张锋
曹占锋
姚琪
舒适
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京东方科技集团股份有限公司
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Priority to US14/435,877 priority Critical patent/US9543331B2/en
Publication of WO2015172492A1 publication Critical patent/WO2015172492A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • the inventors have found that after the black matrix is integrated on the array substrate, since the black matrix is usually located between the drain of the thin film transistor and the pixel electrode, in order to realize the electrical connection between the drain and the pixel electrode, it is necessary to form in the black matrix.
  • the hole which affects the blackout effect of the black matrix on the drain, causes the drain to reflect light from the side of the via, reducing the display effect of the display device.
  • One of the technical problems to be solved by the present invention is to provide an array substrate, a preparation method thereof, and a display device, which can prevent the reflection of the drain and ensure the display effect of the display device.
  • an array substrate including:
  • the insulating layer is located between the drain and the pixel electrode
  • a via hole is formed in the insulating layer, and the drain and the pixel electrode are connected through the via hole.
  • the surface of the pixel electrode at the via is a rough surface.
  • the surface of the pixel electrode at the via is plasma treated.
  • the plasma comprises a hydrogen plasma or a silane plasma.
  • the pixel electrode is made of an indium oxide series metal oxide transparent conductive film.
  • the rough surface of the pixel electrode includes large indium metal indium.
  • an orthographic projection of a drain of the thin film transistor cell on the substrate substrate falls within an orthographic projection of the rough surface of the pixel electrode.
  • Another embodiment in accordance with the present invention provides a display device comprising an array substrate in accordance with any of the embodiments of the present invention.
  • a method for fabricating an array substrate including:
  • a drain, an insulating layer, and a pixel electrode of the thin film transistor unit on the base substrate, wherein the insulating layer is located between the drain and the pixel electrode, and the insulating layer is formed with a via, the drain a pole and the pixel electrode are connected through the via;
  • the surface of the pixel electrode at the via is treated as a rough surface.
  • the treating the surface of the pixel electrode at the via as a rough surface comprises:
  • the pixel electrode at the via is treated with a plasma such that the surface of the pixel electrode at the via is a rough surface.
  • the plasma comprises a hydrogen plasma or a silane plasma.
  • the pixel electrode is made of an indium oxide series metal oxide transparent conductive film.
  • the rough surface of the pixel electrode includes large indium metal indium.
  • an orthographic projection of a drain of the thin film transistor cell on the substrate substrate falls within an orthographic projection of the rough surface of the pixel electrode.
  • FIG. 1 is a schematic structural view 1 of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural view 2 of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic flow chart of a method for preparing an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural view 3 of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural view 4 of an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural view 5 of an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural view 6 of an array substrate according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram 7 of an array substrate according to an embodiment of the present invention.
  • an embodiment of the present invention provides an array substrate.
  • the array substrate includes:
  • a drain electrode 21 of the thin film transistor unit 2 located above the base substrate 1, an insulating layer 3, and a pixel electrode 4, the insulating layer 3 being located between the drain electrode 21 and the pixel electrode 4, the insulating layer 3 A via hole 5 is formed, and the drain electrode 21 and the pixel electrode 4 are connected through the via hole 5; wherein the surface of the pixel electrode 4 at the via hole 5 is a rough surface.
  • the COA technology is adopted, and the color film 6, the black matrix 7 and the thin film transistor unit 2 are all formed on the same base substrate 1. Since the thin film transistor unit 2 mainly forms a conductive channel in the active layer 22, electrical signal can be transferred between the source 23 and the drain 21. The illumination affects the ability of the conductive channel in the active layer 22 to transport carriers, thereby affecting the operation of the thin film transistor unit 2.
  • the black matrix 7 needs to be disposed at a position corresponding to the active layer 22 of the thin film transistor unit 2, and at the same time, in order to ensure the alignment accuracy between the color film 6 and the black matrix 7, the color film 6 is directly formed on the color film 6. Above the black matrix 7.
  • the insulating layer 3 includes at least a first insulating layer 8, a second insulating layer 9, and a color film 6 on the thin film transistor unit 2, wherein the first insulating layer 8 is directly
  • the thin film transistor unit 2 is covered, which is also commonly referred to as a passivation layer. Passivation layer process not only improves The ability of the display device to withstand harsh environments is also helpful to improve the photoelectric parameter performance of the thin film transistor unit 2.
  • the second insulating layer 9 is located above the color film and may be referred to as a flat layer. The arrangement of the flat layer facilitates the subsequent processing steps of the array substrate.
  • the black matrix 7 is directly disposed on the first insulating layer 8.
  • the black matrix 7 can be made of a black or dark resin. Since the black matrix 7 is first deposited with a light-shielding material on the formed first insulating layer 8, a plurality of black matrices 7 corresponding to the respective thin film transistor units 2 are formed by a patterning process including etching. In order to reduce the preparation process of the array substrate, a black photoresist is preferably used for fabrication, and the use of the photoresist can be omitted when the black matrix 7 is prepared by using the photosensitive properties of the photoresist.
  • the black matrix 7 is placed on the array substrate, and in order to ensure the connection between the pixel electrode and the drain, the black matrix 7 cannot completely shield the drain electrode 21, and the via hole 5 penetrating the insulating layer 3 makes the drain electrode 21 Partially exposed, although it is covered with a pixel electrode 4 connected to the drain 21, the pixel electrode 4 is usually made of indium tin oxide (ITO), indium zinc oxide (IZO), or tin, zinc, bismuth, or antimony.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • tin zinc, bismuth, or antimony.
  • the indium oxide series metal oxide transparent conductive film doped with one or more elements, preferably the transparent conductive film of the present invention is an ITO film, and therefore, the portion of the drain 21 corresponding to the via 5 is light from the outside. Specular reflection affects the display of the display device.
  • the surface of the pixel electrode at the via hole is treated as a rough surface, and the rough surface can reduce the pixel electrode at the via hole.
  • the light transmittance reduces the light that is in contact with the drain, and at the same time reduces the transmittance of the light reflected by the drain, reduces the reflection effect of the drain on the external light, and improves the display effect of the display device.
  • the surface of the pixel electrode at the via of the insulating layer is treated as a rough surface, which can reduce the transmittance of the pixel electrode at the via hole and reduce the light that contacts the drain, and can also The transmittance of the light reflected by the drain is lowered, the reflection effect of the drain on the external light is reduced, and the display effect of the display device is improved.
  • an orthographic projection of the drain of the thin film transistor unit on the substrate is dropped into the pixel electrode.
  • the orthographic projection of the rough surface is within the range.
  • the surface of the pixel electrode 4 at the via 5 is subjected to plasma treatment, and the processing method is simple, convenient, and easy to implement.
  • the plasma comprises a hydrogen plasma or a silane plasma.
  • Hydrogen The plasma is preferred for its embodiments because of its safe and non-toxic properties.
  • the hydrogen plasma undergoes a reduction reaction with indium oxide in the indium oxide-based metal oxide transparent conductive film to form metal indium and water, and the metal indium precipitates on the surface of the indium oxide-based metal oxide transparent conductive film to form large particles.
  • the surface flatness of the formed device is lowered, and the rough surface enhances the diffuse reflection effect of the light and reduces the light transmittance of the indium oxide-based metal oxide transparent conductive film. That is, the rough surface of the pixel electrode includes large indium metal indium.
  • the water formed by the reaction causes the originally transparent indium oxide-based metal oxide transparent conductive film to be whitened in color, and atomization occurs, thereby further reducing the light transmittance of the indium oxide-based metal oxide transparent conductive film.
  • the radio frequency power of the hydrogen plasma may range from 500 to 5000 W
  • the treatment time may range from 5 to 30 seconds
  • the pressure may range from 50 to 200 mTorr (1 Torr to 133.322 Pa).
  • the thin film transistor unit 2 in the array substrate shown in FIG. 1 is of a bottom gate type, that is, the structure of the thin film transistor unit 2 includes a gate electrode 24, a gate insulating layer 25, and a same layer and is insulated from bottom to top. A source 23 and a drain 21, and an active layer 22 connecting the source 23 and the drain 21.
  • the thin film transistor unit 2 can also be of a top gate type.
  • the structure of the top gate type thin film transistor unit 2 is almost opposite to that of the bottom gate type shown in FIG. 1, that is, the top gate type thin film transistor unit 2 includes a source 23 and a drain 21 which are disposed in the same layer and insulated from the bottom to the top.
  • the active layer 22, the gate insulating layer 25, and the gate electrode 24 connecting the source 23 and the drain 21 are connected.
  • the array substrate shown in FIG. 1 is a Twisted Nematic (TN) mode array substrate of the COA process.
  • the structure of the array substrate shown in FIG. 1 can be improved.
  • the array substrate further includes the pixel electrode 4 on the basis of the array substrate shown in FIG. a matching common electrode 10, and a third insulating layer 11 between the pixel electrode 4 and the common electrode 10, wherein the array substrate is an Advanced Super Dimension Switch (AADS) of the COA process.
  • AADS Advanced Super Dimension Switch
  • the pixel electrode 4 in FIG. 2 is located above the common electrode 10.
  • the via 5 also needs to penetrate through the third insulating layer 11.
  • the embodiment of the present invention further provides a display device, including any one of the above array substrates.
  • the display device can be any display such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like. Functional product or part.
  • the embodiment of the invention provides a method for preparing an array substrate, as shown in FIG. 3, the array substrate Preparation methods include:
  • Step S101 forming a drain of the thin film transistor unit, an insulating layer, and a pixel electrode.
  • the insulating layer is located between the drain and the pixel electrode, the insulating layer is formed with a via, and the drain and the pixel electrode are connected through the via;
  • Step S102 processing the surface of the pixel electrode at the via hole as a rough surface.
  • step S102 includes: treating the pixel electrode at the via hole with a plasma such that a surface of the pixel electrode at the via hole is a rough surface.
  • a transparent conductive film 12 is formed on the array substrate in which the thin film transistor unit 2, the first insulating layer 8, the black matrix 7, the color film 6, the second insulating layer 9, the common electrode 10, and the third insulating layer 11 are sequentially formed, the transparent The conductive film 12 is connected to the drain 21 of the thin film transistor unit 2 through via holes 5 which sequentially penetrate through the third insulating layer 11, the second insulating layer 9, the color film 6, and the first insulating layer 8, as shown in FIG.
  • a photoresist layer 13 having a pattern of pixel electrodes 4 is formed on the transparent conductive film by using a halftone mask, as shown in FIG. 5, and a patterning process is performed to form a comb-like shape.
  • the pixel electrode 4 is as shown in FIG. 6; the photoresist layer 13 at the via 5 is removed by an ashing process, so that the pixel electrode 4 at the via 5 is exposed, as shown in FIG. Processing the pixel electrode 4 at the via 5 such that the surface of the pixel electrode 4 becomes a rough surface, as shown in FIG. 8; finally, the remaining photoresist layer 13 on the array substrate is peeled off to form the array shown in FIG. The structure of the substrate.
  • the plasma includes a hydrogen plasma or a silane plasma.

Abstract

一种阵列基板及其制备方法、显示装置，能够防止漏极反光，保证了显示装置的显示效果。该阵列基板，包括：薄膜晶体管单元（2）的漏极（21）、绝缘层（3）和像素电极（4），所述绝缘层（3）位于所述漏极（21）和所述像素电极（4）之间，所述绝缘层（3）中形成有过孔（5），所述漏极（21）和所述像素电极（4）通过所述过孔（5）连接；其中，所述过孔（5）的像素电极（4）的表面为粗糙面。

Description

阵列基板及其制备方法、显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制备方法、显示装置。
背景技术
由于近年来人们对于显示装置的透光率、分辨率、功耗等的要求越来越高，显示装置都在向着高透过率、高分辨率、低功耗等方向发展。分辨率越高，使得每一个像素单元的尺寸越小，当像素单元的边长由几十微米变为十几微米时，若划分像素单元的黑矩阵的宽度仍然保持不变，相对于像素单元而言，黑矩阵将变得明显，将会影响显示装置的显示效果。
因此，将彩色滤光片与阵列基板集成在一起的一种集成技术(Color Filter on Array，简称COA)应运而生。由于此时黑矩阵位于阵列基板上，在适当减小黑矩阵的宽度时，也能保证黑矩阵能够充分遮挡栅线、数据线和薄膜晶体管单元等需遮光的结构，同时，减少漏光现象发生的可能性，在提高分辨率、透过率的同时又保证了显示装置的显示效果。
发明人发现，在将黑矩阵整合到阵列基板上之后，由于黑矩阵通常位于薄膜晶体管的漏极和像素电极之间，为了实现漏极与像素电极之间的电连接，需要在黑矩阵形成过孔，该过孔会影响黑矩阵对漏极的遮光效果，导致漏极反射来自过孔一侧的光，降低了显示装置的显示效果。
发明内容
本发明所要解决的技术问题之一在于提供一种阵列基板及其制备方法、显示装置，能够防止漏极反光，保证了显示装置的显示效果。
根据本发明的一个实施例提供一种阵列基板，包括：
衬底基板；
在所述衬底基板上的薄膜晶体管单元的漏极、绝缘层和像素电极，其中，
所述绝缘层位于所述漏极和所述像素电极之间，
所述绝缘层中形成有过孔，所述漏极和所述像素电极通过所述过孔连接，
所述过孔处的像素电极的表面为粗糙面。
在一个示例中，所述过孔处的像素电极的表面经过等离子体处理。
在一个示例中，所述等离子体包括氢等离子体或硅烷等离子体。
在一个示例中，所述像素电极由氧化铟系列金属氧化物透明导电薄膜制成。
在一个示例中，所述像素电极的粗糙面包括大颗粒的金属铟。
在一个示例中，所述薄膜晶体管单元的漏极在所述衬底基板上的正投影落入所述像素电极的所述粗糙面的正投影的范围内。
根据本发明的另一个实施例提供一种显示装置，包括根据本发明任一实施例的阵列基板。
根据本发明的再一个实施例提供一种阵列基板的制备方法，包括：
在衬底基板上形成薄膜晶体管单元的漏极、绝缘层和像素电极，其中，所述绝缘层位于所述漏极和所述像素电极之间，所述绝缘层形成有过孔，所述漏极和所述像素电极通过所述过孔连接；
将所述过孔处的像素电极表面处理为粗糙面。
在一个示例中，所述将所述过孔处的像素电极表面处理为粗糙面包括：
利用等离子体处理所述过孔处的像素电极，使得所述过孔处的像素电极表面为粗糙面。
在一个示例中，所述等离子体包括氢等离子体或硅烷等离子体。
在一个示例中，所述像素电极由氧化铟系列金属氧化物透明导电薄膜制成。
在一个示例中，所述像素电极的粗糙面包括大颗粒的金属铟。
在一个示例中，所述薄膜晶体管单元的漏极在所述衬底基板上的正投影落入所述像素电极的所述粗糙面的正投影的范围内。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明实施例中的阵列基板的结构示意图一；
图2为本发明实施例中的阵列基板的结构示意图二；
图3为本发明实施例中的阵列基板的制备方法的流程示意图；
图4为本发明实施例中的阵列基板的结构示意图三；
图5为本发明实施例中的阵列基板的结构示意图四；
图6为本发明实施例中的阵列基板的结构示意图五；
图7为本发明实施例中的阵列基板的结构示意图六；
图8为本发明实施例中的阵列基板的结构示意图七。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一
本发明实施例提供一种阵列基板，如图1所示，该阵列基板包括：
位于衬底基板1之上的薄膜晶体管单元2的漏极21、绝缘层3和像素电极4，所述绝缘层3位于所述漏极21和所述像素电极4之间，所述绝缘层3形成有过孔5，所述漏极21和所述像素电极4通过所述过孔5连接；其中，所述过孔5处的像素电极4的表面为粗糙面。
在本发明实施例中，采用了COA技术，将彩膜6、黑矩阵7与所述薄膜晶体管单元2都在同一衬底基板1上形成。由于薄膜晶体管单元2主要是通过在有源层22中形成导电沟道，使得源极23和漏极21之间可以实现电信号的传递。而光照会影响有源层22内的导电沟道对载流子的传输能力，进而影响薄膜晶体管单元2的工作效果。一般的，需要在对应于所述薄膜晶体管单元2的有源层22的位置设置黑矩阵7，同时，为了保证彩膜6和黑矩阵7之间的对位精度，将彩膜6直接形成在黑矩阵7之上。
具体的，在本发明实施例中，所述绝缘层3至少包括位于所述薄膜晶体管单元2之上的第一绝缘层8、第二绝缘层9和彩膜6，其中第一绝缘层8直接覆盖薄膜晶体管单元2，通常又称为钝化层。采用钝化层工艺不仅提高 了显示装置的耐严酷环境的能力，而且有助于改善薄膜晶体管单元2的光电参数性能。类似的，第二绝缘层9位于彩膜之上，可称为平坦层，平坦层的设置有利于该阵列基板后续加工步骤的进行。
另外，如图1所示，为了保证黑矩阵7对有源层22的遮光效果，将黑矩阵7直接设置于第一绝缘层8之上。
该黑矩阵7可选用黑色或深色的树脂制作。由于黑矩阵7在制作过程中，首先在所形成的第一绝缘层8上沉积一层遮光材料，之后通过包括刻蚀在内的构图工艺形成对应各个薄膜晶体管单元2的多个黑矩阵7。为了减少阵列基板的制备流程，优选黑色的光刻胶来制作，利用光刻胶的感光性质，制备黑矩阵7时可以省略光刻胶的使用。
由于采用了COA技术，黑矩阵7放置在阵列基板上，同时为了保证像素电极和漏极之间的连接，黑矩阵7无法完全遮蔽漏极21，贯穿绝缘层3的过孔5使得漏极21部分暴露在外，虽然在其上还覆盖有一层与漏极21连接的像素电极4，但像素电极4通常采用氧化铟锡(ITO)、氧化铟锌(IZO)，或者锡、锌、钽、锑等一种或多种元素掺杂的氧化铟系列金属氧化物透明导电薄膜，优选地本发明的透明导电薄膜为ITO薄膜，因此，过孔5对应的漏极21的部分会对来自外界的光进行镜面反射，影响了显示装置的显示效果。
因此，在本发明实施例中，为了防止漏极21被过孔5暴露在外的部分发生镜面反射，将过孔处的像素电极的表面处理为粗糙面，该粗糙面可以降低过孔处像素电极的透光率，减少接触到漏极的光线，同时还可降低漏极反射的光的透过率，减小漏极对外界光线的反射效果，改善显示装置的显示效果。
在本实施例的技术方案中，绝缘层过孔处的像素电极的表面处理为粗糙面，该粗糙面可以降低过孔处像素电极的透光率，减少接触到漏极的光线，同时还可降低漏极反射的光的透过率，减小漏极对外界光线的反射效果，改善显示装置的显示效果。例如，为了更好地减少接触到漏极的光线，以及降低漏极反射的光的透过率，所述薄膜晶体管单元的漏极在所述衬底基板上的正投影落入所述像素电极的所述粗糙面的正投影的范围内。
例如，所述过孔5处的像素电极4的表面经过等离子体处理，该处理方法简单、便捷，易于实现。
在本发明实施例中，所述等离子体包括氢等离子体或硅烷等离子体。氢 等离子体因其安全无毒的特性为本发明实施例的优选。具体的，氢等离子会与氧化铟系金属氧化物透明导电薄膜中的氧化铟发生还原反应，生成金属铟和水，金属铟在氧化铟系金属氧化物透明导电薄膜表面析出，形成大的颗粒，导致所形成的器件表面平整度下降，粗糙的表面会增强光的漫反射效应，降低氧化铟系金属氧化物透明导电薄膜透光率。也就是说，所述像素电极的粗糙面包括大颗粒的金属铟。反应生成的水会使原本透明的氧化铟系金属氧化物透明导电薄膜颜色变白，发生雾化现象，进一步降低氧化铟系金属氧化物透明导电薄膜的透光率。
例如，氢等离子体的射频功率的范围可为500～5000W，处理的时间范围可为5～30秒，压强范围可为50～200mTorr(1Torr≈133.322Pa)。
显然，图1所示的阵列基板中的薄膜晶体管单元2为底栅型的，即该薄膜晶体管单元2的结构由下至上包括：栅极24、栅极绝缘层25、同层设置且绝缘的源极23和漏极21、以及连接源极23和漏极21的有源层22。类似的，薄膜晶体管单元2也可为顶栅型。顶栅型的薄膜晶体管单元2的结构与图1所示的底栅型的近乎相反，即顶栅型的薄膜晶体管单元2由下至上包括：同层设置且绝缘的源极23和漏极21、连接源极23和漏极21的有源层22、栅极绝缘层25和栅极24。
显然，图1所示的阵列基板为COA工艺的扭曲向列型(Twisted Nematic，简称TN)模式的阵列基板。在此基础上，可以考虑对图1所示的阵列基板的结构进行改进，例如，如图2所示，该阵列基板在图1所示的阵列基板的基础上还包括与所述像素电极4配合的公共电极10，以及位于所述像素电极4和所述公共电极10之间的第三绝缘层11，此时该阵列基板为COA工艺的高级超维场转换(Advanced Super Dimension Switch，简称ADS)模式的阵列基板，显然，图2中的像素电极4位于公共电极10之上，为了实现像素电极4和漏极21之间的连接，过孔5还需要贯穿第三绝缘层11。
本发明实施例还提供了一种显示装置，包括上述的任一项阵列基板，具体的，该显示装置可以为：液晶面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。
实施例二
本发明实施例提供一种阵列基板的制备方法，如图3所示，该阵列基板 的制备方法包括：
步骤S101、形成薄膜晶体管单元的漏极、绝缘层和像素电极。所述绝缘层位于所述漏极和所述像素电极之间，所述绝缘层形成有过孔，所述漏极和所述像素电极通过所述过孔连接；
步骤S102、将所述过孔处的像素电极表面处理为粗糙面。
其中，步骤S102包括：利用等离子体处理所述过孔处的像素电极，使得所述过孔处的像素电极表面为粗糙面。
例如，在对过孔5处的像素电极4的表面进行处理时，需要利用光刻胶等形成保护层，将无需进行处理的像素电极进行保护，暴露需要进行处理得像素电极，以下，进行具体说明：
在依次形成有薄膜晶体管单元2、第一绝缘层8、黑矩阵7、彩膜6、第二绝缘层9、公共电极10和第三绝缘层11的阵列基板上形成透明导电薄膜12，该透明导电薄膜12通过依次贯穿第三绝缘层11、第二绝缘层9、彩膜6和第一绝缘层8的过孔5连接至薄膜晶体管单元2的漏极21，如图4所示。
在图4的基础上，利用半色调掩膜板，在该透明导电薄膜之上形成具有像素电极4的图案的光刻胶层13，如图5所示，进行构图工艺，形成梳齿状的像素电极4，如图6所示；利用灰化工艺去除过孔5处的光刻胶层13，使得过孔5处的像素电极4暴露在外，如图7所示，此时可利用等离子体处理所述过孔5处的像素电极4，使得像素电极4表面变为粗糙面，如图8所示；最后，剥离去除阵列基板上剩余的光刻胶层13，形成图2所示的阵列基板的结构。
例如，所述等离子体包括氢等离子体或硅烷等离子体。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年5月13日递交的中国专利申请第201410200290.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (13)

  1. 一种阵列基板，包括：
    衬底基板；
    在所述衬底基板上的薄膜晶体管单元的漏极、绝缘层和像素电极，其中，
    所述绝缘层位于所述漏极和所述像素电极之间，
    所述绝缘层中形成有过孔，所述漏极和所述像素电极通过所述过孔连接，
    所述过孔处的像素电极的表面为粗糙面。
  2. 根据权利要求1所述的阵列基板，其中，
    所述过孔处的像素电极的表面经过等离子体处理。
  3. 根据权利要求2所述的阵列基板，其中，
    所述等离子体包括氢等离子体或硅烷等离子体。
  4. 根据权利要求1-3中任一项所述的阵列基板，其中，
    所述像素电极由氧化铟系列金属氧化物透明导电薄膜制成。
  5. 根据权利要求4所述的阵列基板，其中，
    所述像素电极的粗糙面包括大颗粒的金属铟。
  6. 根据权利要求1-5中任一项所述的阵列基板，其中，
    所述薄膜晶体管单元的漏极在所述衬底基板上的正投影落入所述像素电极的所述粗糙面的正投影的范围内。
  7. 一种显示装置，包括如权利要求1-6中任一项所述的阵列基板。
  8. 一种阵列基板的制备方法，包括：
    在衬底基板上形成薄膜晶体管单元的漏极、绝缘层和像素电极，其中，所述绝缘层位于所述漏极和所述像素电极之间，所述绝缘层形成有过孔，所述漏极和所述像素电极通过所述过孔连接；
    将所述过孔处的像素电极表面处理为粗糙面。
  9. 根据权利要求8所述的阵列基板的制备方法，其中，所述将所述过孔处的像素电极表面处理为粗糙面包括：
    利用等离子体处理所述过孔处的像素电极，使得所述过孔处的像素电极表面为粗糙面。
  10. 根据权利要求9所述的阵列基板的制备方法，其中：
    所述等离子体包括氢等离子体或硅烷等离子体。
  11. 根据权利要求8-10中任一项所述的阵列基板的制备方法，其中，
    所述像素电极由氧化铟系列金属氧化物透明导电薄膜制成。
  12. 根据权利要求11所述的阵列基板的制备方法，其中，
    所述像素电极的粗糙面包括大颗粒的金属铟。
  13. 根据权利要求8-12中任一项所述的阵列基板的制备方法，其中，
    所述薄膜晶体管单元的漏极在所述衬底基板上的正投影落入所述像素电极的所述粗糙面的正投影的范围内。
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