US9543331B2 - Array substrate and manufacturing method thereof, display device - Google Patents

Array substrate and manufacturing method thereof, display device Download PDF

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Publication number
US9543331B2
US9543331B2 US14/435,877 US201414435877A US9543331B2 US 9543331 B2 US9543331 B2 US 9543331B2 US 201414435877 A US201414435877 A US 201414435877A US 9543331 B2 US9543331 B2 US 9543331B2
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pixel electrode
array substrate
via hole
thin film
drain electrode
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US20150372011A1 (en
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Feng Zhang
Zhanfeng CAO
Qi Yao
Shi SHU
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Assigned to BOE TECHNOLOGY GROUP CO., LTD. reassignment BOE TECHNOLOGY GROUP CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CAO, ZHANFENG, SHU, Shi, YAO, QI, ZHANG, FENG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G02F2001/136222—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the present invention relate to an array substrate and manufacturing method thereof, a display device.
  • COA Color Filter on Array
  • the black matrix is integrated onto the array substrate, in view of the fact that the black matrix is usually situated between a drain electrode of a thin film transistor and a pixel electrode, in order to achieve the electrical connection between the drain electrode and the pixel electrode, it is required that a via hole be formed in the black matrix.
  • This via hole will have an influence on the shading effect of the black matrix on the drain electrode, and this causes the drain electrode to reflect light from the via hole side. Thus, the display effect of the display device is degraded.
  • One of the technical problems to be solved by the present invention is to provide an array substrate and manufacturing method thereof, a display device, capable of preventing light reflection from a drain electrode, and ensuring the display effect of the display device.
  • an array substrate including
  • the insulating layer is located between the drain electrode and the pixel electrode
  • the insulating layer has a via hole formed therein, and the drain electrode and the pixel electrode are connected through the via hole,
  • a surface of the pixel electrode at the via hole is a rough face.
  • the surface of the pixel electrode at the via hole is subjected to a plasma treatment.
  • the plasma includes hydrogen plasma or silane plasma.
  • the pixel electrode is made of a transparent conductive thin film of an indium oxide based metal oxide.
  • the rough face of the pixel electrode includes metal indium in big particles.
  • an orthographic projection of the drain electrode of the thin film transistor unit on the base substrate falls within a scope of orthographic projection of the rough face of the pixel electrode.
  • a display device which includes the array substrate according to any embodiment of the invention.
  • a manufacturing method of an array substrate which includes:
  • a drain electrode of a thin film transistor unit an insulating layer and a pixel electrode on a base substrate, wherein, the insulating layer is located between the drain electrode and the pixel electrode, and has a via hole formed therein, and the drain electrode and the pixel electrode are connected through the via hole;
  • treating the surface of the pixel electrode at the via hole to be the rough face includes:
  • the plasma includes hydrogen plasma or silane plasma.
  • the pixel electrode is made of a transparent conductive thin film of an indium oxide based metal oxide.
  • the rough face of the pixel electrode includes metal indium in big particles.
  • an orthographic projection of the drain electrode of the thin film transistor unit on the base substrate falls within a scope of orthographic projection of the rough face of the pixel electrode.
  • FIG. 1 is a structurally schematic view 1 illustrating an array substrate in an embodiment of the invention
  • FIG. 2 is a structurally schematic view 2 illustrating an array substrate in an embodiment of the invention
  • FIG. 3 is a schematically flowchart illustrating a manufacturing method of an array substrate in an embodiment of the invention
  • FIG. 4 is a structurally schematic view 3 illustrating an array substrate in an embodiment of the invention.
  • FIG. 5 is a structurally schematic view 4 illustrating an array substrate in an embodiment of the invention.
  • FIG. 6 is a structurally schematic view 5 illustrating an array substrate in an embodiment of the invention.
  • FIG. 7 is a structurally schematic view 6 illustrating an array substrate in an embodiment of the invention.
  • FIG. 8 is a structurally schematic view 7 illustrating an array substrate in an embodiment of the invention.
  • the array substrate includes:
  • a drain electrode 21 of a thin film transistor unit 2 an insulating layer 3 and a pixel electrode 4 that are located on the base substrate 1 .
  • the insulating layer 3 is located between the drain electrode 21 and the pixel electrode 4 , and has a via hole 5 formed therein, and the drain electrode 21 and the pixel electrode 4 are connected through the via hole 5 .
  • a surface of the pixel electrode 4 at the via hole 5 is a rough face.
  • a color film 6 , a black matrix 7 and the thin film transistor unit 2 are all formed on the same base substrate 1 .
  • the thin film transistor unit 2 it is possible that transmission of electrical signals is achieved between a source electrode 23 and the drain electrode 21 mainly by forming a conductive channel in an active layer 22 . While illumination will have an influence on the capacity of transmitting carrier of the conductive channel within the active layer 22 , and in turn, the working effect of the thin film transistor unit 2 is affected.
  • the black matrix 7 be disposed at the location corresponding to the active layer 22 of the thin film transistor unit 2 , and moreover, in order to ensure an aligning accuracy between the color film 6 and the black matrix 7 , the color film 6 is directly formed on the black matrix 7 .
  • the insulating layer 3 at least includes a first insulating layer 8 , a second insulating layer 9 and a color film 6 that are located on the thin film transistor unit 2 , wherein, the first insulating layer 8 directly covers the thin film transistor unit 2 , and is usually called as a passivation layer.
  • the passivation-layer process not only enhances the capability of the display device in resisting rigorous circumstance, but also helps to improve the performance of photoelectric parameters of the thin film transistor unit 2 .
  • the second insulating layer 9 is located on the color film, and can be called as a planarizing layer, and provision of the planarizing layer facilitates execution of subsequent machining steps of the array substrate.
  • the black matrix 7 is directly disposed on the first insulating layer 8 .
  • the black matrix 7 may be produced by choosing a black or dark resin.
  • a layer of shading material is firstly deposited on the formed first insulating layer 8 , and after that, a plurality of black matrices 7 corresponding to thin film transistor units 2 are formed by a patterning process that includes etching. Therefore, in order to cut down the fabricating flow of the array substrate, a black photoresist is preferably used for production, and by utilizing the photosensitive property of the photoresist, use of a photoresist can be omitted upon manufacture of the black matrix 7 .
  • the black matrix 7 is placed on the array substrate, and moreover, for ensuring the connection between the pixel electrode and the drain electrode, the drain electrode 21 cannot be shaded by the black matrix 7 completely, and the via hole 5 penetrating the insulating layer 3 makes a part of the drain electrode 21 be exposed.
  • the via hole 5 is also covered by a layer of pixel electrode 4 connected to the drain electrode 21 , a transparent conductive thin film of indium tin oxide (ITO), indium zinc oxide (IZO) or other metal oxide in indium oxide based metal oxides (metal oxides in the family of indium oxide) that is doped with one or more selected from the group consisting of tin, zinc, tantalum, antimony and other elements is usually used for the pixel electrode 4 (preferably, the transparent conductive thin film in the invention is an ITO thin film), and then, light from the outside may be specularly reflected by a part of the drain electrode 21 in correspondence with the via hole 5 . Therefore, the display effect of the display device is affected.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • metal oxides in the family of indium oxide metal oxides in the family of indium oxide
  • a surface of the pixel electrode at the via hole is treated to be a rough face.
  • the transmittance of the pixel electrode at the via hole is reduced, and light in contact with the drain electrode is decreased.
  • the transmittance of light reflected by the drain electrode is reduced, and the reflective effect of the drain electrode on external lights is decreased.
  • the display effect of the display device is improved.
  • a surface of the pixel electrode at the via hole of the insulating layer is treated to be a rough face.
  • the transmittance of the pixel electrode at the via hole is reduced, and light in contact with the drain electrode is decreased.
  • the transmittance of light reflected by the drain electrode is reduced, and the reflective effect of the drain electrode on external lights is decreased.
  • the display effect of the display device is improved.
  • the orthographic projection of the drain electrode of the thin film transistor unit on the base substrate falls within the scope of the orthographic projection of the rough face of the pixel electrode.
  • a surface of the pixel electrode 4 at the via hole 5 is subjected to plasma treatment, and the treating method is simple, convenient, and easy to implement.
  • the plasma includes hydrogen plasma or silane plasma.
  • the hydrogen plasma is a preferred item of embodiments of the invention owing to its characteristic of being safe and non-toxic.
  • hydrogen plasma may create a reduction reaction with indium oxide in a transparent conductive thin film of a metal oxide in the family of indium oxide, so as to produce metal indium and water, and the metal indium precipitates from the surface of the transparent conductive thin film of a metal oxide in the family of indium oxide to form big particles, resulting in degradation in surface flatness of the formed device.
  • a rough surface can act to strengthen the diffusive reflection effect of light, thereby reducing the transmittance of the transparent conductive thin film of a metal oxide in the family of indium oxide.
  • the rough face of the pixel electrode includes metal indium in big particles.
  • the water produced by reaction may turn the color of the transparent conductive thin film of a metal oxide in the family of indium oxide that is originally transparent into white, and an atomization phenomenon occurs, so that transmittance of the transparent conductive thin film of a metal oxide in the family of indium oxide is further degraded.
  • the range of radio frequency power of hydrogen plasma may be 500 W to 5000 W
  • the time range for processing may be 5 to 30 seconds
  • the pressure range may be 50 to 200 mTorr (1 Torr ⁇ 133.322 Pa).
  • the thin film transistor unit 2 in the array substrate illustrated in FIG. 1 is of bottom-gate type, and that is, the structure of the thin film transistor unit 2 includes a gate electrode 24 , a gate insulating layer 25 , a source electrode 23 and a drain electrode 21 disposed in the same layer and insulated from each other, and an active layer 22 for connecting the source electrode 23 and the drain electrode 21 from bottom to up.
  • the thin film transistor unit 2 may also be of top-gate type. The structure of a top-gate thin film transistor unit 2 is nearly the opposite of that of bottom type illustrated in FIG. 1 .
  • the top-gate thin film transistor unit 2 includes a source electrode 23 and a drain electrode 21 disposed in the same layer and insulated from each other, an active layer for connecting the source electrode 23 and the drain electrode 21 , a gate insulating layer 25 and a gate electrode 24 from bottom to top.
  • the array substrate illustrated in FIG. 1 is a Twisted Nematic (briefly called as TN) mode array substrate with a COA process.
  • the array substrate further includes a common electrode 10 in cooperation with the pixel electrode 4 , and a third insulating layer 11 located between the pixel electrode 4 and the common electrode 10 .
  • the array substrate is an array substrate of Advanced Super Dimension Switch (briefly called as ADS) mode with a COA process.
  • ADS Advanced Super Dimension Switch
  • the pixel electrode 4 in FIG. 2 is located over the common electrode 10 , and for the sake of achieving the connection between the pixel electrode 4 and the drain electrode 21 , the via hole 5 also needs to penetrate the third insulating layer 11 .
  • the display device which includes any of the array substrates as stated above.
  • the display device may be a liquid crystal panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a cell phone, a tablet computer or any other product or component having a display function.
  • the manufacturing method of the array substrate includes:
  • Step S 101 a drain electrode of a thin film transistor unit, an insulating layer and a pixel electrode are formed.
  • the insulating layer is located between the drain electrode and the pixel electrode, and has a via hole formed therein, and the drain electrode and the pixel electrode are connected through the via hole;
  • Step S 102 a surface of the pixel electrode at the via hole is treated to be a rough face.
  • the step S 102 includes that, the pixel electrode at the via hole is treated by plasma, so that a surface of the pixel electrode at the via hole is a rough face.
  • a protective layer needs to be formed by using a photoresist or the like, so as to protect the pixel electrode without the necessity of being treated, and to expose the pixel electrode in need of being treated.
  • a photoresist or the like so as to protect the pixel electrode without the necessity of being treated, and to expose the pixel electrode in need of being treated.
  • a transparent conductive thin film 12 is formed on an array substrate with a thin film transistor unit 2 , a first insulating layer 8 , a black matrix 7 , a color film 6 , a second insulating layer 9 , a common electrode 10 and a third insulating layer 11 sequentially formed thereon, and is connected to a drain electrode 21 of the thin film transistor unit 2 through a via hole 5 that penetrates the third insulating layer 11 , the second insulating layer 9 , the color film 6 and the first insulating layer 8 in sequence, as illustrated in FIG. 4 .
  • a photoresist layer 13 having the pattern of a pixel electrode 4 is formed over the transparent conductive thin film, as illustrated in FIG. 5 , and a patterning process is conducted, so as to form the comb-tooth-shaped pixel electrode 4 , as illustrated in FIG. 6 .
  • the photoresist layer 13 at the via hole 5 is removed by an ashing process, so that the pixel electrode 4 at the via hole 5 is exposed to the outside, as illustrated in FIG. 7 , and at this time, the pixel electrode 4 at the via hole 5 may be treated by using plasmas, so that a surface of the pixel electrode 4 turns into a rough face, as illustrated in FIG. 8 .
  • the remaining photoresist layer 13 on the array substrate is removed, and the structure of the array substrate illustrated in FIG. 2 is formed.
  • the plasma includes hydrogen plasma or silane plasma.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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US14/435,877 2014-05-13 2014-09-20 Array substrate and manufacturing method thereof, display device Active US9543331B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201410200290.4 2014-05-13
CN201410200290.4A CN103985717A (zh) 2014-05-13 2014-05-13 一种阵列基板及其制备方法、显示装置
CN201410200290 2014-05-13
PCT/CN2014/086999 WO2015172492A1 (zh) 2014-05-13 2014-09-20 阵列基板及其制备方法、显示装置

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US10216028B2 (en) 2015-07-17 2019-02-26 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof, display panel, display device

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CN104297980A (zh) * 2014-10-31 2015-01-21 京东方科技集团股份有限公司 一种coa基板及其制作方法和显示装置
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