WO2015151197A1 - 半導体装置、プレライトプログラム、および復元プログラム - Google Patents

半導体装置、プレライトプログラム、および復元プログラム Download PDF

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Publication number
WO2015151197A1
WO2015151197A1 PCT/JP2014/059546 JP2014059546W WO2015151197A1 WO 2015151197 A1 WO2015151197 A1 WO 2015151197A1 JP 2014059546 W JP2014059546 W JP 2014059546W WO 2015151197 A1 WO2015151197 A1 WO 2015151197A1
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Prior art keywords
threshold voltage
data
twin
memory element
memory
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PCT/JP2014/059546
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English (en)
French (fr)
Japanese (ja)
Inventor
谷　国雄
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ルネサスエレクトロニクス株式会社
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Priority to EP14846736.8A priority Critical patent/EP3128517A4/en
Priority to KR1020157001541A priority patent/KR20160140329A/ko
Priority to PCT/JP2014/059546 priority patent/WO2015151197A1/ja
Priority to JP2014559030A priority patent/JP6234945B2/ja
Priority to US14/430,428 priority patent/US9640267B2/en
Priority to CN201480002015.XA priority patent/CN105283919B/zh
Priority to TW103131145A priority patent/TWI620187B/zh
Publication of WO2015151197A1 publication Critical patent/WO2015151197A1/ja
Priority to US15/473,439 priority patent/US10121546B2/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
    • G11C16/105—Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/107—Programming all cells in an array, sector or block to the same state prior to flash erasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells

Definitions

  • the present invention relates to a semiconductor device, a prewrite program, and a restoration program, for example, a semiconductor device including two nonvolatile memory cells that hold complementary data, a prewrite program for erasing complementary data, and a complementary program A typical data restoration program.
  • Patent Document 1 a semiconductor device described in Japanese Patent Application Laid-Open No. 2008-117510 (Patent Document 1) holds binary data due to a difference in flash erasing type negative threshold voltage, and has different retention characteristics due to a difference in binary data held.
  • a readout circuit (SA) for differentially amplifying complementary data output from the element and the second storage element to determine storage information of the twin cell is provided.
  • the threshold voltages of the two cells are both reduced by erasing the twin cell data.
  • the difference between the threshold voltages of the two cells in the written state before erasing the twin cell data may remain after erasing the twin cell data.
  • the user may wish to erase the twin cell data simply to write new data (to free up an area) or may wish to erase the twin cell data to maintain confidentiality.
  • the former case there is no problem even if the difference between the threshold voltages of the two cells remains after erasing the twin cell data.
  • the latter case if the difference between the threshold voltages of the two cells remains after erasing the twin cell data, the writing state before erasing the twin cell data is read, which is not preferable in terms of maintaining confidentiality. There is.
  • the first prewrite process for increasing both the threshold voltage of the first memory element and the threshold voltage of the second memory element when the control circuit receives the first erase command. Thereafter, the threshold voltage of the first memory element and the threshold voltage of the second memory element are decreased until the threshold voltage of the first memory element and the threshold voltage of the second memory element become lower than a predetermined erase verify level. It controls the execution of the erasure process that decreases both.
  • the control circuit controls execution of the second prewrite process for increasing the threshold voltage of one of the first memory element and the second memory element, and then performs the erase process. Control execution.
  • FIG. 3 is a flowchart illustrating an operation procedure of the semiconductor device according to the first embodiment. It is a figure showing the structure of the microcomputer of 2nd Embodiment. It is a figure showing the structure of a flash memory module.
  • A) is a figure showing the example of the bias voltage given to a split gate type flash memory element.
  • B) is a figure showing the example of the bias voltage given to the stacked gate type flash memory element using a hot carrier write system.
  • (C) is a figure showing the example of the bias voltage given to the stacked gate type
  • A) is a diagram showing a state in which twin cell data stores “0”.
  • (B) is a diagram showing a state in which twin cell data stores “1”.
  • (C) is a diagram showing an initialized state of twin cell data. It is a figure showing the structure of a positive write data latch circuit. It is a figure showing the structure of a negative write data latch circuit. It is a flowchart showing the procedure of the program of the twin cell data of 2nd Embodiment.
  • (A) is a figure showing the change of the threshold voltage at the time of writing in case program data is "1".
  • (B) is a figure showing the change of the threshold voltage at the time of writing in case program data is "0". It is a flowchart showing the procedure of the block erase 1 of the twin cell data of 2nd Embodiment.
  • FIG. 7B is a diagram showing a change in threshold voltage when block erase 1 is executed from the data “0” storage state. It is a flowchart showing the procedure of the block erase 2 of the twin cell data of 2nd Embodiment. It is a flowchart showing the procedure of a 2nd prewrite process.
  • (A) And (b) is a figure showing the change of the threshold voltage Vth at the time of performing 2nd pre-write in the head area
  • (A) to (d) are diagrams showing changes in the threshold voltage Vth when the second prewrite is executed in an area other than the head area and the intermediate area and then the erasure process is executed. It is a flowchart showing the procedure of the decompression
  • FIG. 1 is a diagram illustrating the configuration of the semiconductor device according to the first embodiment.
  • the semiconductor device 100 includes a memory array 101 and a control circuit 105.
  • Memory array 101 includes a plurality of twin cells 104.
  • the twin cell 104 holds binary data (twin cell data) according to a difference in threshold voltage Vth, and includes a first memory element 102 and a second memory element 103 that can be electrically rewritten.
  • the control circuit 105 controls erasure of twin cell data.
  • the control circuit 105 receives a first erase command sent from the outside, the control circuit 105 performs a first prewrite process for increasing both the threshold voltage Vth of the first memory element 102 and the threshold voltage Vth of the second memory element 103. Control execution. Thereafter, the control circuit 105 causes the threshold voltage Vth of the first memory element 102 and the second memory until the threshold voltage Vth of the first memory element 102 and the threshold voltage Vth of the second memory element 103 become lower than a predetermined erase verify level. Execution of the erasing process for decreasing both the threshold voltages Vth of the elements 103 is controlled.
  • control circuit 105 When the control circuit 105 receives a second erase command sent from the outside, the control circuit 105 executes the second prewrite process for increasing the threshold voltage Vth of one of the first memory element 102 and the second memory element 103. Control. Thereafter, the control circuit 105 causes the threshold voltage Vth of the first memory element 102 and the second memory until the threshold voltage Vth of the first memory element 102 and the threshold voltage Vth of the second memory element 103 become lower than a predetermined erase verify level. Execution of the erasing process for decreasing both the threshold voltages Vth of the elements 103 is controlled.
  • FIG. 2 is a flowchart showing an operation procedure of the semiconductor device according to the first embodiment.
  • step S901 when the first erase command is input from the outside to the control circuit 105, the process proceeds to step S902.
  • step S904 when the second erase command is input from the outside to the control circuit 105, the process proceeds to step S905.
  • step S902 the control circuit 105 controls execution of the first prewrite process.
  • step S905 the control circuit 105 controls the execution of the second prewrite process.
  • step S903 the control circuit 105 controls execution of the erasure process.
  • the first erase command allows the user to erase twin cell data in order to write new data
  • the second erase command allows the user to Confidential twin cell data can be erased.
  • FIG. 3 is a diagram illustrating a configuration of the microcomputer 1 (semiconductor device) according to the second embodiment.
  • the microcomputer (MCU) 1 shown in FIG. 3 is formed on a single semiconductor chip such as single crystal silicon by, for example, complementary MOS integrated circuit manufacturing technology.
  • the microcomputer 1 has a high-speed bus HBUS and a peripheral bus PBUS, although not particularly limited.
  • the high-speed bus HBUS and the peripheral bus PBUS are not particularly limited, but each have a data bus, an address bus, and a control bus. By providing two buses, it is possible to reduce the load on the bus and to guarantee a high-speed access operation compared to the case where all circuits are commonly connected to the common bus.
  • the high-speed bus HBUS includes a central processing unit (CPU) 2, a direct memory access controller (DMAC) 3, a bus interface control between the high-speed bus HBUS and the peripheral bus PBUS, or a bus that includes an instruction control unit and an execution unit to execute instructions.
  • a bus interface circuit (BIF) 4 that performs bridge control is connected.
  • RAM random access memory
  • FMDL flash memory module
  • the peripheral bus PBUS controls a flash sequencer (FSQC) 7 that performs command access control to the flash memory module (FMDL) 6, external input / output ports (PRT) 8 and 9, timer (TMR) 10, and microcomputer 1.
  • FSQC flash sequencer
  • FMDL flash memory module
  • PRT external input / output ports
  • TMR timer
  • microcomputer 1 microcomputer 1.
  • a clock pulse generator (CPG) 11 for generating an internal clock CLK is connected.
  • the microcomputer 1 includes a clock terminal to which an oscillator is connected to XTAL / EXTAL or an external clock is supplied, an external hardware standby terminal STB for instructing a standby state, an external reset terminal RES for instructing a reset, an external power supply A terminal Vcc and an external ground terminal Vss are provided.
  • the flash sequencer 7 as a logic circuit and the flash memory module 6 having an array configuration are designed using different CAD tools, and are therefore shown as separate circuit blocks for convenience.
  • Configure flash memory The flash memory module 6 is connected to the high-speed bus HBUS via a read-only high-speed access port (HACSP).
  • the CPU 2 or the DMAC 3 can read-access the flash memory module 6 from the high-speed bus HBUS via the high-speed access port.
  • the CPU 2 or the DMAC 3 issues a command to the flash sequencer 7 via the peripheral bus PBUS via the bus interface 4 when performing write and initialization access to the flash memory module 6.
  • the flash sequencer 7 initializes the flash memory module 6 and controls the write operation from the peripheral bus PBUS through the low-speed access port (LACSP).
  • LACSP low-speed access port
  • FIG. 4 is a diagram showing the configuration of the flash memory module 6.
  • the flash memory module 6 stores 1-bit information using two nonvolatile memory cells. That is, the memory array MARY includes a plurality of two rewritable nonvolatile memory cells MCP and MCN as 1-bit twin cells TC. FIG. 4 representatively shows only one pair. In this specification, the memory cell MCP is called a positive cell, and the memory cell MCN is called a negative cell. Memory array MARY is divided into four memory mats MAT0 to MAT3. Here, the size of one memory mat MAT is 8 Kbytes.
  • Nonvolatile memory cells MCP and MCN are, for example, split gate type flash memory elements exemplified in FIG.
  • This memory element has a control gate CG and a memory gate MG disposed on a channel formation region between the source / drain regions via a gate insulating film.
  • a charge trap region (SiN) such as silicon nitride is disposed between the memory gate MG and the gate insulating film.
  • the source or drain region on the selection gate side is connected to the bit line BL (SBLP or SBBL), and the source or drain region on the memory gate side is connected to the source line SL.
  • BL 1.5V
  • CG 0V
  • MG ⁇ 10V
  • SL 6
  • WELL 0V
  • a charge trap is performed by a high electric field between the well region (WELL) and the memory gate MG. Electrons are extracted from the region (SiN) to the well region (WELL).
  • This processing unit is a plurality of memory cells sharing the memory gate MG.
  • BL 0V
  • CG 0.9V
  • MG 10V
  • SL 6
  • WELL 0V
  • a write current is supplied from the source line SL to the bit line, thereby controlling the control gate CG.
  • Hot electrons generated at the boundary between the memory gate MG and the memory gate MG are injected into the charge trap region (SiN). Since the electron injection is determined by whether or not a bit line current is passed, this process is controlled in units of bits.
  • the memory element is not limited to the split gate type flash memory element, and may be a stacked gate type flash memory element exemplified in FIGS. 5B and 5C.
  • This memory element is configured by stacking a floating gate FG and a control gate WL via a gate insulating film on a channel formation region between a source / drain region.
  • the threshold voltage Vth is increased by the hot carrier writing method, and the threshold voltage Vth is decreased by the emission of electrons to the well region WELL.
  • the threshold voltage Vth is increased by the FN tunnel writing method, and the threshold voltage Vth is decreased by the emission of electrons to the bit line BL.
  • the voltage applied to the memory gate MG, control gate CG, source line SL, WELL, and bit line BL described above is generated and supplied by the power supply circuit VPG under the control of the flash sequencer 7.
  • the memory element is a split gate flash memory element.
  • Information storage by one twin cell TC composed of nonvolatile memory cells MCP and MCN is performed by storing complementary data in the nonvolatile memory cells MCP and MCN.
  • each of the memory cells MCP and MCN has cell data “1” (low threshold voltage state; state in which the threshold voltage is smaller than the erase verify level) or cell data “0” (high threshold voltage state; the threshold voltage is in the erase verify state). State above the level).
  • the twin cell data “0” is a state in which the positive cell MCP holds the cell data “0” and the negative cell MCN holds the cell data “1”.
  • the twin cell data “1” is a state in which the positive cell MCP holds the cell data “1” and the negative cell MCN holds the cell data “0”.
  • the state where both the positive cell MCP and the negative cell MCN of the twin cell hold the cell data “1” is an initialized state.
  • the initialized state is also called a blank erase state.
  • twin cell data erasure In the erasing operation, since the erasure target block is erased at once, both the positive cell MCP and the negative cell MCN are in a state of holding the cell data “1”. Further, changing from the initialized state to the twin cell data “1” holding state or the twin cell data “0” holding state is called normal writing of the twin cell data.
  • the memory gate MG is connected to a common memory gate selection line MGL
  • the control gate CG is connected to a common word line WL.
  • the sources of the memory cells MCP and MCN are connected to a common source line SL.
  • twin cells are arranged in a matrix and connected to the corresponding memory gate selection line MGL and word line WL in an array unit in the row direction.
  • the drain terminals of the memory cells MCP and MCN are connected to the sub bit lines SBLP and SBLN in units of columns, and are connected to the main bit lines MBLP and MBLN via the sub bit line selectors SELP and SELN.
  • a plurality of sub bit lines SBLP, SBLN are connected to the main bit lines MBLP, MBLN in a hierarchical manner by sub bit line selectors SELP, SELN.
  • the word line WL is selected by the first row decoder RDEC1.
  • the memory gate selection line MGL and the sub bit line selectors SELP and SELN are selected by the second row decoder RDEC2.
  • the selection operation by the first row decoder 24 and the second row decoder 25 follows the address information supplied to the HACSP in the read access, and follows the address information supplied to the LACSP in the data write operation and the initialization operation.
  • the power supply circuit VPG generates various operating voltages necessary for reading, writing, and initialization.
  • the timing generator TMG generates an internal control signal that defines internal operation timing in accordance with an access strobe signal supplied from the CPU 2 or the like to the HACSP, an access command supplied from the FSQC 7 to the LACSP, or the like.
  • the sub bit line selectors SELP and SELN are turned on / off by the SG signal, and are valid at the time of reading / writing / erasing.
  • the main bit lines MBLP and MBLN are connected to a read sense amplifier SA included in the read sense amplifier circuit 121 via Y selectors YSELP and YSELN included in the Y select unit 122.
  • the Y selectors YSELP and YSELN select the main bit lines MBLP and MBLN to be connected according to the result decoded by the address at the time of reading / writing.
  • the read sense amplifier SA reads twin cell data from the difference between the threshold voltages Vth of the positive cell MCP and the negative cell MCN connected to the selected main bit lines MBLP and MBLN.
  • the memory data read by the read sense amplifier SA is output to the data bus D (31: 0) by the output buffer OBUF.
  • the data output to the data bus D (31: 0) is output to the input / output circuit IOBUF.
  • the output buffer OBUF includes buffers B0 to B31 that receive an output from each read sense amplifier SA.
  • the input / output circuit IOBUF outputs data read by the read sense amplifier SA to the outside, and processes write data input from the outside of the flash memory module 6 at the time of writing.
  • the column decoder CDEC turns on the rewrite column selectors MC2GP and MC2GN by the C2 signal, and the input / output circuit IOBUF transmits data to the positive write data latch circuit WDLP and the negative write data latch circuit WDNL via the signal lines D0P and D0N.
  • the selection operation of the column decoder CDEC follows address information supplied to the LACSP.
  • twin cell data When erasing twin cell data, it is performed in units of 8 Kbytes of memory mat, and an erase voltage is applied to the twin cell TC of the memory mat.
  • the control circuit 120 controls the erase voltage to be applied to SG, MG, SL, and WELL.
  • the main bit lines MBLP and MBLN are connected to the verify circuit VERC of the verify unit 124 via verify selectors MC1GP and MC1GN controlled by the C1 signal, respectively.
  • the verify circuit VERC determines whether or not the threshold voltage Vth of the memory cell exceeds a specified value when the memory is erased or written.
  • the verification result is output to the control circuit 120, and the control circuit 120 determines whether or not repeated pulse application is necessary.
  • it is possible to set either the first write verify voltage WVER1 or the second write verify voltage WVER2 in order to determine whether or not the threshold voltage of the memory cell has exceeded a specified value. It is. There is a relationship of WVER1 ⁇ WVER2 between the first write verify voltage WVER1 and the second write verify voltage WVER2.
  • the verify circuit VERC includes a positive verify sense amplifier VSP and a negative verify sense amplifier VSN.
  • the positive verify sense amplifier VSP compares the voltage of the main bit line MBLP with the reference voltage.
  • the first write verify voltage WVER1 is supplied at the time of normal writing
  • the second write verify voltage WVER2 is supplied at the time of the second prewrite processing in the block erase 2
  • the erase verify voltage EVER is set at the time of erasing. Supplied.
  • the negative verify sense amplifier VSN compares the voltage of the main bit line MBLN with the reference voltage.
  • the first write verify voltage WVER1 is supplied at the time of normal writing
  • the second write verify voltage WVER2 is supplied at the time of the second prewrite processing in the block erase 2
  • the erase verify voltage EVER is set at the time of erasing. Supplied.
  • FIG. 7 shows a structure of positive write data latch circuit WDLP.
  • the positive write data latch circuit WDLP includes a data holding unit 91 and a setting unit 92.
  • Data holding unit 91 includes inverters IV1 and IV2 that are alternately connected.
  • the input of inverter IV1 and the output of inverter IV2 are connected to signal line D0P connected to input / output circuit IOBUF.
  • the output of inverter IV1 and the input of inverter IV2 are connected to node ND1.
  • Setting unit 92 includes P channel MOS transistors P1, P2 provided between power supply voltage VDD and ground voltage Vss, and N channel MOS transistors N1, N2, N3.
  • the gate of the P channel MOS transistor P1 receives an inverted signal / enable of the program pulse valid signal.
  • the gate of P channel MOS transistor P2 and the gate of N channel MOS transistor N1 are connected to node ND1.
  • N channel MOS transistor N2 has its gate receiving program pulse enable signal enable.
  • N channel MOS transistor N3 has its gate receiving pulse PLS.
  • FIG. 8 shows a configuration of negative write data latch circuit WDLN.
  • Negative write data latch circuit WDLN includes a data holding unit 93 and a setting unit 94.
  • Data holding unit 93 includes inverters IV3 and IV4 that are alternately connected.
  • the input of inverter IV3 and the output of inverter IV4 are connected to signal line D0N connected to input / output circuit IOBUF.
  • the output of inverter IV3 and the input of inverter IV4 are connected to node ND2.
  • Setting unit 94 includes P channel MOS transistors P3 and P4 provided between power supply voltage VDD and ground voltage Vss, and N channel MOS transistors N4, N5 and N6.
  • the gate of the P channel MOS transistor P3 receives the inverted signal / enable of the program pulse valid signal.
  • the gate of P channel MOS transistor P4 and the gate of N channel MOS transistor N4 are connected to node ND2.
  • N channel MOS transistor N5 has its gate receiving program pulse valid signal enable.
  • N channel MOS transistor N6 has its gate receiving pulse PLS.
  • FIG. 9 is a flowchart showing the procedure of the twin cell data program (also referred to as normal writing) according to the second embodiment.
  • FIG. 10A shows a change in threshold voltage Vth at the time of writing when the program data is “1”.
  • FIG. 10B shows a change in threshold voltage Vth at the time of writing when the program data is “0”.
  • step S101 a program command, a program address, and program data from the CPU 2 are input to the flash memory module 6.
  • a twin cell TC is selected by the first row decoder RDEC1, the second row decoder RDEC2, and the column decoder CDEC according to the input program address.
  • the column decoder CDEC turns on the rewrite column selectors MC2GP and MC2GN according to the C2 signal, and the input / output circuit IOBUF is connected to the positive write data latch circuit WDLP and the negative write data according to the program data input via the signal lines D0P and D0N. Data is set in the latch circuit WDLN.
  • step S102 the control circuit 120 starts writing.
  • step S103 the control circuit 120 sets MG, CG, SL to the write bias voltage (voltage that increases Vth) shown in FIG. 5A, and writes the write bias voltage to one memory cell of the selected twin cell TC. Is applied to increase the threshold voltage Vth of one memory cell of the twin cell TC.
  • step S105 write verification is performed. That is, when the program data is “0”, the threshold voltage Vth of the positive cell MCP is set to the first write verify voltage WVER1 shown in FIGS. 10A and 10B by the positive verify sense amplifier VSP. It is determined whether or not. That is, when the program data is “1”, the threshold voltage Vth of the negative cell MCN is set to the first write verify voltage WVER1 shown in FIGS. 10A and 10B by the negative verify sense amplifier VSN. It is determined whether or not.
  • step S105 if the threshold voltage Vth is equal to or lower than the first write verify voltage WVER1, the process proceeds to step S107. If the threshold voltage Vth exceeds the first write verify voltage WVER1, the process ends normally. (Step S106).
  • step S107 the control circuit 120 increments the write count WC by one.
  • step S108 if the write count WC is less than or equal to the threshold value TH, the process returns to step S103, and if the write count WC exceeds the threshold value TH, the process ends in error (step S109).
  • FIG. 11 is a flowchart showing the procedure of block erase 1 (erase in the first erase mode) of twin cell data according to the second embodiment.
  • FIG. 12A shows a change in threshold voltage Vth when block erase 1 is executed from the data “1” storage state.
  • FIG. 12B shows a change in threshold voltage Vth when block erase 1 is executed from the data “0” storage state.
  • step S201 the block erase 1 command from the CPU 2 and the designation of the block to be erased are input to the flash memory module 6.
  • One of the memory mats MAT0 to MAT3 is designated as the block to be erased.
  • first prewrite processing is performed to temporarily set the cell data of both the positive cell MCP and the negative cell MCN to “0”.
  • the write bias voltage applied to both the positive cell MCP and the negative cell MCN is set to be higher than the write bias voltage at the time of normal writing (voltage for increasing Vth shown in FIG. 5A). By making it small, a stress smaller than the stress due to normal writing is given.
  • the increase amount of the threshold voltage of the memory cell having the smaller threshold voltage is smaller than the increase amount of the threshold voltage Vth during normal writing.
  • the purpose of performing the first prewrite is to reduce variations in erase stress between the positive cell MCP and the negative cell MCN, and to suppress deterioration of the retention characteristics.
  • the threshold voltage Vth is further lowered, and a strong stress is applied to the memory cell in a state where the threshold voltage Vth is low, thereby reducing reliability.
  • the write is not performed until the threshold voltage Vth of the memory cell becomes higher than the first write verify voltage WVER1 as in the normal write, but the threshold voltage Vth Is only raised to some extent. Therefore, the read verification of the write data as in normal writing is not performed. The reason is to shorten the time required for the block erase 1.
  • step S202 the control circuit 120 sets the initial value of the address ADR as the start address of the block to be erased.
  • the address ADR is a format of an address that designates a 32-bit boundary for accessing 32-bit data. That is, the address ADR is such that the lower 2 bits of the address assigned every 8 bits are deleted and the lower 3 bits are made the least significant bit.
  • 32 twin cells TC designated by the head address are selected by the first row decoder RDEC1, the second row decoder RDEC2, and the column decoder CDEC.
  • the input / output circuit IOBUF sets all write data to “0”.
  • the column decoder CDEC turns on the rewrite column selectors MC2GP and MC2GN by the C2 signal, and the input / output circuit IOBUF has all the positive write data connected to the twin cells TC of the block to be erased via the signal lines D0P and D0N. “0” is set in latch circuit WDLP and negative write data latch circuit WDLN.
  • step S203 the control circuit 120 starts writing.
  • step S204 the control circuit 120 causes the selected twin cell TC to apply a write bias voltage smaller than that during normal writing to the selected twin cell TC through MG, CG, and SL.
  • the threshold voltage Vth is increased.
  • step S205 the control circuit 120 increments the address ADR by one.
  • step S206 if the address ADR is (maximum address +1), the first prewrite ends, and the process proceeds to step S207. If the address ADR is not (maximum address + 1), the process returns to step S203.
  • the maximum address corresponds to an address indicating the last 32-bit area of the block to be erased.
  • step S207 the control circuit 120 sets the initial value of the address ADR as the start address of the block to be erased.
  • a twin cell TC is selected by the first row decoder RDEC1, the second row decoder RDEC2, and the column decoder CDEC according to the address ADR.
  • step S208 the control circuit 120 starts erasing.
  • step S209 the control circuit 120 sets MG, CG, and SL to the erase bias voltage (voltage that decreases Vth) shown in FIG. 5A, and applies the erase bias voltage to the 32 selected twin cells TC. By doing so, the threshold voltage Vth of both memory cells MCP and MCN of the twin cell is decreased.
  • step S210 erase verify is performed. That is, it is determined by the positive verify sense amplifier VSP whether or not the threshold voltage Vth of the positive cell MCP is lower than the erase verify voltage EVER shown in FIGS. 12 (a) and 12 (b). Further, the negative verify sense amplifier VSN determines whether or not the threshold voltage Vth of the negative cell MCN is lower than the erase verify voltage EVER shown in FIGS. 12 (a) and 12 (b).
  • step S211 when at least one threshold voltage Vth of both cells MCP and MCN is equal to or higher than the erase verify voltage EVER, the process returns to step S209, and the threshold voltage Vth of both cells MCP and MCN is erase verified. If lower than voltage EVER, the process proceeds to step S212.
  • step S212 the control circuit 120 increments the address ADR by one.
  • step S213 if the address ADR is (maximum address + 1), the erasing is finished and the process is finished. If the address ADR is not (maximum address + 1), the process returns to step S210.
  • the magnitude relationship between the threshold voltages Vth of the positive cell MCP and the negative cell MCN after the completion is the threshold before the block erase is performed.
  • the magnitude relationship of the voltage Vth is maintained. If reading is performed in a state in which this relationship is maintained, there is a difference between the threshold voltages Vth of the positive cell MCP and the negative cell MCN, so that the twin cell data before the block erase 1 is read out.
  • the purpose of block erase 1 is to secure a memory area for the next writing, there is no particular problem, and there is an advantage that the execution time is shorter than the block erase 2 command described later.
  • FIG. 13 is a flowchart showing the procedure of block erase 2 (erase in the second erase mode) of twin cell data according to the second embodiment.
  • FIG. 14 is a flowchart showing the procedure of the second prewrite process.
  • step S301 the block erase 2 command from CPU 2 and the designation of the block to be erased are input to flash memory module 6.
  • One of the memory mats MAT0 to MAT3 is designated as the block to be erased.
  • step S302 the second prewrite process shown in FIG. 14 is performed.
  • steps S207 to S213 an erase process similar to that in block erase 1 is performed.
  • control circuit 120 sets the start address of the block to be erased to address ADR.
  • 32 twin cells TC designated by a total of 4 addresses including a head address and subsequent 3 addresses are selected by the first row decoder RDEC1, the second row decoder RDEC2, and the column decoder CDEC (this embodiment) In this form, 8-bit data is allocated to one address).
  • the control circuit 120 sets MG, CG, and SL to the read voltage shown in FIG. 5A, and the 32-bit twin read through the read sense amplifier SA, the output buffer, and the data bus D (31: 0). Cell data is sent to the control circuit 120.
  • step S402 the column decoder CDEC turns on the rewrite column selectors MC2GP and MC2GN in response to the C2 signal, and the input / output circuit IOBUF passes through the signal lines D0P and D0N and continues to the top area (continuous with the top address) of the block to be erased.
  • Write data of inverted data of twin cell data read out from a 32-bit area specified by 4 addresses in total (3 addresses) is set. That is, when the read twin cell data is “1”, the threshold voltage Vth of the positive cell MCP is low and the threshold voltage Vth of the negative cell MCN is high. In the second prewrite process, only the threshold voltage Vth of the positive cell MCP having the lower threshold voltage Vth is increased.
  • the threshold voltage Vth of the negative cell MCN is low and the threshold voltage Vth of the positive cell MCP is high. In the second prewrite process, only the threshold voltage Vth of the negative cell MCN having the lower threshold voltage Vth is increased.
  • the write data corresponding to the read twin cell data is 32h′00000000.
  • the write data corresponding to the read twin cell data is 32h′33333333.
  • step S403 the control circuit 120 starts the first writing.
  • step S404 the control circuit 120 sets MG, CG, and SL to the write bias voltage (voltage that increases Vth) shown in FIG. 5A, and sets one of the 32 selected twin cells TC as a memory cell. By applying the write bias voltage, the threshold voltage Vth of one of the 32 twin cells TC is increased. The write bias voltage is not applied to the other memory cell, and therefore the threshold voltage Vth is maintained.
  • the inverted data of the twin cell data read from the head area of the block to be erased is written in the head area (32-bit area specified by the head address) of the block to be erased.
  • the inverted data of the twin cell data read from the head area of the erase target block is written in addition to the head area of the erase target block.
  • step S405 write verification is performed. That is, when the write data is “0”, the positive verify sense amplifier VSP determines whether or not the threshold voltage Vth of the positive cell MCP exceeds the second write verify voltage WVER2. When the write data is “1”, the negative verify sense amplifier VSN determines whether or not the threshold voltage Vth of the negative cell MCN exceeds the second write verify voltage WVER2.
  • step S406 if the threshold voltage Vth of the memory cell that increases the threshold voltage Vth is equal to or lower than the second write verify voltage WVER2 for at least one of the 32 twin cells TC, the process returns to step S404. If the threshold voltage Vth of the memory cell that increases the threshold voltage Vth exceeds the second write verify voltage WVER2 for all 32 twin cells TC, the process proceeds to step S407.
  • step S407 the control circuit 120 increments the address ADR by one.
  • step S408 if the address ADR is an intermediate address, the process proceeds to step S407. If the address ADR is not an intermediate address, the process returns to step S403.
  • the intermediate address is an address that designates the first 32-bit area of the intermediate area described later. Therefore, each 32-bit area from the head address of the block to be erased to the address immediately before the intermediate address is prewritten based on the inverted data read from the head area.
  • step S409 the control circuit 120 sets the intermediate address of the block to be erased to the address ADR.
  • 32 twin cells TC designated by the intermediate address are selected by the first row decoder RDEC1, the second row decoder RDEC2, and the column decoder CDEC.
  • the control circuit 120 sets MG, CG, and SL to the read voltage shown in FIG. 5A, and the 32-bit twin read through the read sense amplifier SA, the output buffer, and the data bus D (31: 0). Cell data is sent to the control circuit 120.
  • step S410 the column decoder CDEC turns on the rewrite column selectors MC2GP and MC2GN by the C2 signal, and the input / output circuit IOBUF passes through the signal lines D0P and D0N to specify the intermediate area (specified by the intermediate address) of the block to be erased.
  • Write data of inverted data of twin cell data read out from a 32-bit area) is set.
  • step S411 the control circuit 120 starts the second writing.
  • step S412 the control circuit 120 sets MG, CG, and SL to the write bias voltage (voltage that increases Vth) shown in FIG. 5A, and sets one of the selected 32 twin cells TC as a memory cell.
  • the threshold voltage Vth of one of the 32 twin cells TC is increased.
  • the write bias voltage is not applied to the other memory cell, and therefore the threshold voltage Vth is maintained.
  • the inverted data of the twin cell data read from the intermediate area of the erase target block is written.
  • the inverted data of the twin cell data read from the intermediate area of the erasure target block is written.
  • step S413 write verify is performed. That is, when the write data is “0”, the positive verify sense amplifier VSP determines whether or not the threshold voltage Vth of the positive cell MCP exceeds the second write verify voltage WVER2. When the write data is “1”, the negative verify sense amplifier VSN determines whether or not the threshold voltage Vth of the negative cell MCN exceeds the second write verify voltage WVER2.
  • step S414 if the threshold voltage Vth of the memory cell that increases the threshold voltage Vth is equal to or lower than the second write verify voltage WVER2 for at least one of the 32 twin cells TC, the process returns to step S411. If the threshold voltage Vth of the memory cell that increases the threshold voltage Vth exceeds the second write verify voltage WVER2 for all 32 twin cells TC, the process proceeds to step S415.
  • step S415 the control circuit 120 increments the address ADR by one.
  • step S416 if the address ADR is (final address + 1), the process ends. If the address ADR is not (final address + 1), the process returns to step S411. That is, each 32-bit area from the intermediate area of the block to be erased to the 32-bit area specified by the final address is prewritten based on the inverted data read from the intermediate area.
  • FIG. 15A shows a change in threshold voltage Vth when “0” is written in the second prewrite process from the data “1” storage state in the first area and the intermediate area, and then the erasure process is executed. It is.
  • FIG. 15B shows a change in the threshold voltage Vth when “1” is written in the second prewrite process from the data “0” storage state in the head area and the intermediate area, and then the erasure process is executed. It is.
  • FIG. 16A shows the change in threshold voltage Vth when data “1” is written in the second pre-write process after the data “1” is stored in the area other than the head area and the intermediate area, and then the erase process is executed.
  • FIG. 16B shows the change in the threshold voltage Vth when “1” is written in the second prewrite process from the data “1” storage state in the areas other than the head area and the intermediate area, and then the erase process is executed.
  • FIG. FIG. 16C shows a change in the threshold voltage Vth when “1” is written in the second prewrite process from the data “0” storage state in the areas other than the head area and the intermediate area, and then the erase process is executed.
  • FIG. FIG. 16D shows the change in threshold voltage Vth when “0” is written in the second prewrite process from the data “0” storage state in the area other than the head area and the intermediate area, and then the erase process is executed.
  • the magnitude relationship between the threshold voltages Vth of the positive cell MCP and the negative cell MCN after completion does not maintain the magnitude relationship of the threshold voltage Vth before the block erase is performed. Even if there are portions maintained in units of several bits or several addresses, the continuity of the write data in the entire memory mat is lost.
  • the block erase 2 takes time to read data, and therefore, the execution time becomes long, but there is an advantage that highly confidential data can be protected.
  • FIG. 17 is a flowchart showing the procedure of restoring the twin cell data according to the second embodiment.
  • step S501 the restoration command from the CPU 2 and the designation of the restoration target block are input to the flash memory module 6. Any one of the memory mats MAT0 to MAT3 is designated as the restoration target block.
  • step S502 the control circuit 120 sets the start address of the restoration target block to the address ADR.
  • step S503 according to the address ADR, 32 twin cells TC specified by the first row decoder RDEC1, the second row decoder RDEC2, and the column decoder CDEC as a total of four addresses including the address ADR and the subsequent three addresses of the address ADR. Is selected.
  • the control circuit 120 sets MG, CG, and SL to the read voltage shown in FIG. 5A, and the 32-bit twin read through the read sense amplifier SA, the output buffer, and the data bus D (31: 0). Cell data is sent to the control circuit 120.
  • the read twin cell data is determined as “1”, and the threshold voltage Vth of the negative cell MCN is determined. If the threshold voltage Vth of the positive cell MCP is higher than that, the read twin cell data is determined to be “0”.
  • step S504 the column decoder CDEC turns on the rewrite column selectors MC2GP and MC2GN by the C2 signal, and the input / output circuit IOBUF receives the same write data as the read twin cell data through the signal lines D0P and D0N.
  • the input / output circuit IOBUF sets the write data to “0” because the threshold voltage Vth of the negative cell MCN is low and the threshold voltage Vth of the positive cell MCP is high. Only the threshold voltage Vth of the positive cell MCP is increased by setting.
  • step S505 the control circuit 120 starts writing.
  • step S506 the control circuit 120 increases the threshold voltage Vth of one memory cell of the twin cell TC by applying a write bias voltage to the twin cell TC through the selected MBL, SBL, SG, MG, SL, and WELL.
  • step S507 write verification is performed. That is, when the write data is “0”, the positive verify sense amplifier VSP determines whether or not the threshold voltage Vth of the positive cell MCP exceeds the first write verify voltage WVER1. When the write data is “1”, the negative verify sense amplifier VSN determines whether or not the threshold voltage Vth of the negative cell MCN exceeds the first write verify voltage WVER1.
  • step S508 if the threshold voltage Vth of the memory cell that increases the threshold voltage Vth is equal to or lower than the first write verify voltage WVER1 for at least one of the 32 twin cells TC, the process returns to step S506. If the threshold voltage Vth of the memory cell that increases the threshold voltage Vth exceeds the first write verify voltage WVER1 for all 32 twin cells TC, the process proceeds to step S509.
  • step S509 the control circuit 120 increments the address ADR by one.
  • step S510 when the address ADR is (final address + 1), the process ends. If the address ADR is not (final address + 1), the process returns to step S503.
  • the control circuit 120 sets the threshold values of the positive cell and negative cell pairs in the data write state before prewrite in at least some of the plurality of twin memory cells to be erased based on the second erase command.
  • the erasing process is carried out so that one or more memory cells are placed in an erased state in which the magnitude relationship is reversed. More specifically, in at least one of a plurality of twin memory cells to which a write bias voltage is simultaneously applied by pre-write, an erased state in which the magnitude relationship between the threshold values of the positive cell and negative cell pair is reversed is realized.
  • the erase process for erasing a plurality of twin memory cells to be erased on the basis of the first erase command basically, the magnitude relationship between the threshold values of the positive cell and negative cell pairs in the write state before the pre-write. Is not changed. Therefore, the number of cell pairs whose threshold magnitude relationship is reversed by the erase process is larger in the erase process of the second erase command than in the first erase command.
  • the data values of a plurality of twin cells to be erased in accordance with the second erase command have a larger number of bits than the data value before erasure when data reading is attempted.
  • the erasure by the second erasure command is less reproducible than the erasure by the first erasure comment, and the confidentiality of the data before erasure is maintained.
  • the first erase command allows the user to erase twin cell data simply for writing new data.
  • the twin cell data that the user has kept secret can be erased.
  • the original data can be restored from the blank erase state after the execution of the first erase command.
  • the second prewrite process and the restoration process in the block erase 2 described in the first and second embodiments are controlled by the control circuit 120 in the flash memory module 6. Therefore, it is necessary to implement the functions of the second prewrite process and the restoration process in the block erase 2 in the control circuit 120 in the flash memory module 6.
  • the CPU 2 executes the prewrite program and the restoration program in the block erase 2 so that the second prewrite processing and the restoration function are not implemented in the control circuit 120 in the flash memory module 6.
  • the second prewrite and restoration can be executed.
  • FIG. 18 is a diagram illustrating the processing procedure of the prewrite program. Processing is started at Step 0.
  • the CPU 2 sets a value instructing the supply of the second write verify voltage WVER2 as a reference voltage to the positive verify sense amplifier VSP and the negative verify sense amplifier VSN in the register 131 in the control circuit 120.
  • the default value of the register 131 is a value for instructing the first write verify voltage WVER1 to be supplied as a reference voltage to the positive verify sense amplifier VSP and the negative verify sense amplifier VSN.
  • Step 2 the CPU 2 sets the address ADR as the head address of the block to be erased.
  • the CPU 2 outputs a read command consisting of a read command Read and an address ADR.
  • the control circuit 120 reads out twin cell data of 32 twin cells TC designated by a total of four addresses, that is, the address ADR and the subsequent three addresses of the address ADR, and outputs them to the CPU 2.
  • the twin cell data output from the control circuit 120 is 32-bit DATA.
  • Step 4 the CPU 2 outputs a program command composed of a program command Write, an address ADR, and data / DATA.
  • the control circuit 120 writes 32-bit data / DATA to 32 twin cells TC designated by a total of 4 addresses including the address ADR and the subsequent 3 addresses of the address ADR.
  • / DATA is obtained by inverting each bit of DATA read in Step 3.
  • the second write verify voltage WVER2 is supplied to the verify sense amplifiers VSP and VSN according to the setting of the register 131, one threshold voltage Vth of the positive cell MCP and the negative cell MCN of each twin cell TC is The write process is continued until the second write verify voltage WVER2 is exceeded.
  • Step 5 the CPU 2 increments the address ADR by one.
  • Step 6 when the address ADR is the (intermediate address + 4) of the block to be erased, the CPU 2 advances the process to Step 7. If the address ADR is not the intermediate address of the erasure target block, the CPU 2 returns the process to step 4.
  • Step 7 the CPU 2 outputs a read command consisting of a read command Read and an address ADR.
  • the control circuit 120 reads out twin cell data of 32 twin cells TC designated by a total of four addresses, that is, the address ADR and the subsequent three addresses of the address ADR, and outputs them to the CPU 2.
  • the twin cell data output from the control circuit 120 is 32-bit DATA.
  • Step 8 the CPU 2 outputs a program command including a program command Write, an address ADR, and data / DATA.
  • the control circuit 120 writes 32-bit data / DATA to 32 twin cells TC designated by a total of 4 addresses including the address ADR and the subsequent 3 addresses of the address ADR.
  • / DATA is obtained by inverting each bit of DATA read in Step 7.
  • Step 9 the CPU 2 increments the address ADR by one.
  • Step 10 when the address ADR is (last address + 4) of the erasure target block, the CPU 2 ends the process. When the address ADR is not (final address + 1) of the block to be erased, the CPU 2 returns the process to Step 8.
  • FIG. 19 is a diagram showing the processing procedure of the restoration program. Processing is started at Step 0.
  • Step 1 the CPU 2 sets the address ADR as the head address of the restoration target block.
  • Step 2 the CPU 2 outputs a read command including a read command Read and an address ADR.
  • the control circuit 120 reads out twin cell data of 32 twin cells TC designated by a total of four addresses, that is, the address ADR and the subsequent three addresses of the address ADR, and outputs them to the CPU 2.
  • the twin cell data output from the control circuit 120 is 32-bit DATA.
  • Step 3 the CPU 2 outputs a program command including a program command Write, an address ADR, and data DATA.
  • the control circuit 120 writes 32-bit DATA to 32 twin cells TC designated by a total of 4 addresses including the address ADR and the subsequent 3 addresses of the address ADR.
  • DATA is the same as DATA read in Step 2.
  • the first write verify voltage WVER1 is supplied to the verify sense amplifiers VSP and VSN, one threshold voltage Vth of the positive cell MCP and the negative cell MCN of each twin cell TC is the first write verify voltage. The writing process continues until WVER1 is exceeded.
  • Step 4 the CPU 2 increments the address ADR by one.
  • Step 5 when the address ADR is (last address + 4) of the erasure target block, the CPU 2 ends the process. When the address ADR is not (final address + 1) of the block to be erased, the CPU 2 returns the process to Step 2.
  • the block erase 2 program and the restoration program are stored in any one of the memory mats MAT0 to MAT3 of the flash memory module 6 shown in FIG. 4, and transferred to the RAM 5 in FIG. 3 before the block erase 2 and restoration processing. , Read by the CPU 2 and executed.
  • the block erase 2 program and the restoration program may be written into the RAM 5 by an external device (for example, a writer) of the microcomputer 1 via an input / output port inside the microcomputer 1.
  • the CPU 2 executes the prewrite program and the restoration program. By executing, block erase 2 and restoration similar to those of the second embodiment can be realized.
  • the present invention is not limited to the above embodiment, and includes, for example, the following modifications.
  • the erase target block may be divided into N parts, and data obtained by inverting the data read from the head area of each divided area may be written in the entire area. Alternatively, data obtained by inverting the data read from the head area of the erase target block may be written in the entire area of the erase target block. Alternatively, data may be read from each area of the block to be erased and data obtained by inverting the read data may be written to each area. Random data may be written to the erasure target block without reading data from the erasure target block.
  • the threshold voltage Vth of the memory cell on the side that increases the threshold voltage Vth exceeds the second write verify voltage WVER2.
  • the present invention is not limited to this, and it is determined whether or not the threshold voltage Vth of the memory cell that increases the threshold voltage Vth exceeds the first write verify voltage WVER1. It may be done.
  • the magnitude relationship between the threshold voltages Vth of the positive cell MCP and the negative cell MCN after the end of the block erase 2 is the probability that the threshold voltage Vth before the block erase 2 is performed is the second write verify voltage. Although it is higher than when WVER2 is used, the magnitude relationship of the threshold voltage Vth before the block erase 2 is not maintained.
  • the threshold voltage Vth of the memory cell on the side where the threshold voltage Vth is increased in the second prewrite process It may be determined whether or not exceeds the first write verify voltage WVER1.
  • block erase 1 or its prewrite program
  • restoration process or its restoration program
  • block erase 2 (or its prewrite program) may not be implemented in the flash memory module. .
  • MCU 1 microcomputer
  • CPU central processing unit
  • DMAC direct memory access controller
  • BIF bus interface circuit
  • RAM random access memory
  • FMDL flash memory module
  • FSQC flash Sequencer
  • PRT External input / output port
  • CPG 11 Clock pulse generator
  • RDEC1 First row decoder RDEC2 Second row decoder
  • IOBUF input / output circuit CDEC column decoder
  • VPG power supply circuit TMG timing generator
  • TMG timing generator 100 semiconductor device, 101, MARY memory array, 102, first storage element, 103, second Memory element, 104 twin cell, 105, 120 control circuit, 121 read sense amplifier circuit, 122 Y select unit, 123 write latch unit, 124 verify unit, 131 register, P1 to P6, P channel MOS transistor, N1 to N6 N channel MOS Transistor, IV1 to IV4 inverter, HACSP high speed access port,

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  • Computer Security & Cryptography (AREA)
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PCT/JP2014/059546 2014-03-31 2014-03-31 半導体装置、プレライトプログラム、および復元プログラム WO2015151197A1 (ja)

Priority Applications (8)

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EP14846736.8A EP3128517A4 (en) 2014-03-31 2014-03-31 Semiconductor device, pre-write program, and restoration program
KR1020157001541A KR20160140329A (ko) 2014-03-31 2014-03-31 반도체 장치, 프리라이트 프로그램 및 복원 프로그램
PCT/JP2014/059546 WO2015151197A1 (ja) 2014-03-31 2014-03-31 半導体装置、プレライトプログラム、および復元プログラム
JP2014559030A JP6234945B2 (ja) 2014-03-31 2014-03-31 半導体装置、およびプレライトプログラム
US14/430,428 US9640267B2 (en) 2014-03-31 2014-03-31 Semiconductor device, pre-write program, and restoration program
CN201480002015.XA CN105283919B (zh) 2014-03-31 2014-03-31 半导体装置
TW103131145A TWI620187B (zh) 2014-03-31 2014-09-10 半導體裝置、預寫入程式及復原程式
US15/473,439 US10121546B2 (en) 2014-03-31 2017-03-29 Semiconductor device, pre-write program, and restoration program

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