WO2015125412A1 - ワークの両頭研削方法 - Google Patents
ワークの両頭研削方法 Download PDFInfo
- Publication number
- WO2015125412A1 WO2015125412A1 PCT/JP2015/000295 JP2015000295W WO2015125412A1 WO 2015125412 A1 WO2015125412 A1 WO 2015125412A1 JP 2015000295 W JP2015000295 W JP 2015000295W WO 2015125412 A1 WO2015125412 A1 WO 2015125412A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- grinding
- workpiece
- double
- nanotopography
- grindstone
- Prior art date
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
- B24B7/10—Single-purpose machines or devices
- B24B7/16—Single-purpose machines or devices for grinding end-faces, e.g. of gauges, rollers, nuts, piston rings
- B24B7/17—Single-purpose machines or devices for grinding end-faces, e.g. of gauges, rollers, nuts, piston rings for simultaneously grinding opposite and parallel end faces, e.g. double disc grinders
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
Definitions
- the present invention particularly relates to a double-head grinding method for a workpiece capable of reducing nanotopography generated in a slicing process.
- the PV (Peak to Valley) value is an extremely shallow wave of 0.1 ⁇ m to 0.2 ⁇ m.
- the nanotopography of a semiconductor wafer having a mirror surface through a double-side polishing process which is the final process in the semiconductor wafer processing process, is generally measured by an optical interference measuring machine.
- an optical interference measuring machine since the main surface of a semiconductor wafer that has not been subjected to mirror polishing in the middle of processing such as a cutting process or a double-head grinding process is a non-mirror surface, measurement of nanotopography by the reflection interference type measuring machine cannot be performed.
- Patent Document 1 as a method for calculating the nanotopography of a semiconductor wafer having no mirror surface, an arithmetic bandpass filter process is performed on the obtained warp shape using a capacitance type measuring machine. Describes a method that enables simple measurement of nanotopography. Note that the PV value of the cross-sectional shape (difference between the maximum value and the minimum value) is adopted as a quantitative value of this simple nanotopography, and this value is hereinafter referred to as “pseudo-nanotopography”.
- Nanotopography is created during the wafer processing process (slicing process to polishing process), and the nanotopography formed in the slicing process remains until after the final process unless reduced in the double-head grinding process. This nanotopography is said to affect the yield of STI (Shallow Trench Isolation) process in device manufacturing.
- STI Shallow Trench Isolation
- Patent Document 2 discloses that the flow rate of hydrostatic water supplied to the hydrostatic pad for supporting the wafer in a non-contact manner in the double-head grinding apparatus is adjusted. Thus, a method for suppressing nanotopography formed in the double-head grinding process is described.
- the present invention has been made in view of the above-described problems.
- the double-headed workpiece that can reduce the nanotopography formed in the previous process such as the slicing process without deteriorating the flatness.
- the object is to provide a grinding method.
- a ring-shaped workpiece is supported by the ring-shaped holder and rotated from the outer peripheral side along the radial direction, and supported by the ring-shaped holder by a pair of grindstones.
- a double-sided grinding method for grinding the both surfaces of the workpiece simultaneously wherein the wear amount of the grinding wheel per 1 ⁇ m of grinding allowance of the workpiece is set to be 0.10 ⁇ m or more and 0.33 ⁇ m or less,
- a double-head grinding method for a workpiece characterized in that both surfaces of the workpiece are ground simultaneously.
- the nanotopography generated in the slicing step or the like can be effectively reduced by setting the wear amount of the grindstone per 1 ⁇ m of the workpiece grinding allowance to 0.10 ⁇ m or more. Further, by setting the wear amount of the grindstone per 1 ⁇ m of the workpiece grinding allowance to 0.33 ⁇ m or less, the wear amount does not become excessive, and the paired grindstones can be kept parallel to each other. Deterioration can be prevented. As a result, it is possible to effectively reduce nanotopography generated in the slicing process or the like while preventing deterioration of flatness.
- the grindstone having a vitrified bond grindstone disposed on the outer periphery of the annular base metal can be used.
- the wear amount of the grindstone per 1 ⁇ m of grinding allowance of the work is determined by the wear amount of the grindstone obtained from the displacement of the advance position of the grindstone at the time of grinding. It can be calculated as a value divided by the grinding allowance that is the difference between the two. In this way, the wear amount of the grindstone per 1 ⁇ m of grinding allowance of the workpiece can be easily calculated.
- the double-head grinding method for a workpiece of the present invention can prevent deterioration of the flatness of the workpiece after grinding, and can reduce the nanotopography formed in the slicing step or the like. Thus, if nanotopography is reduced in the grinding process, it is possible to effectively reduce the nanotopography on the surface of the mirror-finished wafer obtained after all the workpiece processing steps are completed.
- the present invention is not limited to this.
- an effective double-head grinding method for reducing the nanotopography formed in the wafer processing process in the double-head grinding process has not been found.
- the nanotopography formed by the slicing process etc. remained until the final process (double-side polishing process) unless it was reduced by the double-head grinding process. Therefore, the present inventor has paid attention to a grindstone used for double-head grinding, and has found that as the wear amount of the double-head grindstone increases, the workpiece tends to bite and the grindstone is less likely to idle.
- the present inventor has found that if the wear amount of the grindstone is increased excessively, the paired grindstones cannot be kept parallel to each other, and the flatness is deteriorated.
- the present inventor conducted further experiments, and in the double-head grinding, if the wear amount of the grindstone per 1 ⁇ m of the grinding allowance of the workpiece is set to be 0.10 ⁇ m or more and 0.33 ⁇ m or less, It was discovered that the nanotopography formed in the slicing step or the like can be reduced while preventing the deterioration of flatness, and the present invention has been completed.
- FIG. 5 is a graph showing the relationship between the pseudo nanotopography of the wafer surface after the double-head grinding process and the nanotopography of the wafer surface processed in the order of the etching process and the double-side polishing process after the double-head grinding process.
- This wafer was a single crystal silicon wafer having a diameter of 300 mm.
- Pseudo nanotopography was measured using SBW-330 (manufactured by Kobelco Research Institute), and nanotopography was measured using Wafer Light II (manufactured by KLA-Tencor).
- a double-head grinding apparatus 1 used in the double-head grinding method of the present invention mainly includes a pair of grindstones 2 that simultaneously grind both surfaces of a workpiece W, a ring-shaped holder 3 that supports the workpiece W, and a ring shape.
- a pair of static pressure support members 4 that support the holder 3 in a non-contact manner by the static pressure of the fluid are provided.
- the grindstone 2 is connected to a grindstone motor 5 so that it can rotate at high speed.
- the grindstone 2 is not particularly limited, but may be one in which a vitrified bond grindstone is disposed on the outer periphery of the annular base metal.
- the ring-shaped holder 3 supports the workpiece W from the outer peripheral side along the radial direction and can rotate.
- the double-head grinding apparatus 1 is provided with a drive gear (not shown) connected to a motor (not shown), and the ring-shaped holder 3 can be rotated through the drive gear.
- the inner peripheral part of the ring-shaped holder 3 is formed with a protrusion projecting inward and engages with a notch that is a notch formed in the workpiece W.
- the material of the ring-shaped holder 3 is not particularly limited, but for example, alumina ceramics can be used. If the material is made of alumina ceramic as described above, the workability is good and it is difficult to thermally expand even during processing, so that it can be processed with high accuracy.
- the static pressure support member 4 includes a holder static pressure portion that supports the ring-shaped holder 3 in a non-contact manner on the outer peripheral side, and a wafer static pressure portion that supports the wafer in a non-contact manner on the inner peripheral side. Further, the static pressure support member 4 is formed with a hole for inserting a drive gear used for rotating the ring-shaped holder 3 and a hole for inserting the grindstone 2.
- the ring-shaped holder 3 is used to support from the outer peripheral side along the radial direction of the workpiece W. At this time, the protrusion of the ring-shaped holder 3 and the notch of the workpiece can be engaged and supported.
- the double-head grinding apparatus 1 includes the above-described static pressure support member 4, the ring-shaped holder 3 that supports the workpiece is interposed between the pair of static pressure support members 4.
- the ring-shaped holder 3 is arranged so as to have a gap, and a fluid such as water is supplied from the static pressure support member 4 to support the ring-shaped holder 3 in a non-contact manner.
- the position of the ring-shaped holder 3 that supports the workpiece W during double-head grinding is stabilized by supporting the ring-shaped holder 3 in a non-contact manner while supplying fluid between the static pressure support member 4 and the ring-shaped holder 3.
- the work W is rotated by rotating the ring-shaped holder 3 while the work W is supported by the ring-shaped holder 3.
- the pair of grindstones 2 are respectively brought into contact with both surfaces of the work W while being rotated against the work W, and the facing grindstone 2 is fed forward while supplying grinding water at a predetermined flow rate.
- both surfaces of the workpiece W are ground simultaneously.
- the grindstone 2 used here may be one in which a vitrified bond grindstone is arranged on the outer periphery of an annular base metal.
- the wear amount of the grindstone 2 per 1 ⁇ m of grinding allowance of the workpiece W is set to be 0.10 ⁇ m or more and 0.33 ⁇ m or less.
- the amount of wear of the grindstone 2 can be set by adjusting in advance the load applied to each grindstone 2, the rotational speed of the grindstone 2, the rotational speed of the workpiece W, the type of the grindstone 2, and the like.
- the wear amount of the grindstone 2 per 1 ⁇ m of the grinding allowance of the workpiece W is determined based on the wear amount of the grindstone 2 obtained from the displacement of the advance position of the grindstone 2 at the time of grinding. It is possible to calculate as a value divided by the grinding allowance that is the difference between the two.
- Example 1 A single crystal silicon wafer was ground by the double-head grinding method of the present invention using a double-head grinding apparatus 1 as shown in FIG. This single crystal silicon wafer was made to have a diameter of 300 mm cut out from a silicon single crystal ingot manufactured by the CZ method (Czochralski method). Then, five single crystal silicon wafers to be ground were selected from the cut single crystal silicon wafers. The pseudo nanotopography of these five single crystal silicon wafers was 1.0 ⁇ m when measured with SBW-330 (manufactured by Kobelco Research Institute). In Example 1, double-head grinding was carried out by setting the wear amount of the grindstone per 1 ⁇ m of the workpiece grinding allowance to be 0.10 ⁇ m.
- the pseudo-nanotopography reduction capability is a reduction rate of pseudo-nanotopography obtained by the following formula (1), and the larger the value, the easier the ability to reduce pseudo-nanotopography, which is a quantitative value of nanotopography. Indicates high.
- (Pseudo nanotopography reduction ability) (Pseudo nanotopography before grinding-pseudo nanotopography after grinding) ⁇ (pseudo nanotopography before grinding) ⁇ 100 (1)
- the single crystal silicon wafer was processed in the order of an etching process and a double-side polishing process, which were post processes, to obtain a mirror wafer.
- Nanotopography was measured on the five mirror wafers using Wafer Light II (manufactured by KLA-Tencor). The average value is shown in FIG.
- Example 1 has a 9.2% higher pseudo-nanotopography reduction capability than Comparative Example 1 described later.
- FIG. 3 it was confirmed that the nanotopography of the mirror wafer was 3.1 nm smaller than Comparative Example 1 described later.
- the flatness (SFQR) of a mirror surface wafer is also favorable as shown in FIG.
- Example 2 Double-head grinding is performed under the same conditions as in Example 1 except that the wear amount of the grinding wheel per 1 ⁇ m of grinding allowance of the workpiece is set to be 0.14 ⁇ m. A crystalline silicon wafer was processed to obtain a mirror wafer. Moreover, the average value of pseudo nanotopography reduction ability, the average value of nanotopography, and the average value of flatness (SFQR) were measured by the same method as in Example 1. The results are shown in FIG. 2, FIG. 3, and FIG.
- Example 2 has a 9.9% higher ability to reduce pseudo nanotopography than Comparative Example 1 described later.
- the nanotopography of the mirror wafer was 3.0 nm smaller than Comparative Example 1 described later.
- the flatness (SFQR) of a mirror surface wafer is also favorable as shown in FIG.
- Example 3 Double-head grinding was performed under the same conditions as in Example 1 except that the wear amount of the grinding wheel per 1 ⁇ m of grinding allowance of the workpiece was set to 0.33 ⁇ m. A crystalline silicon wafer was processed to obtain a mirror wafer. Moreover, the average value of pseudo nanotopography reduction ability, the average value of nanotopography, and the average value of flatness (SFQR) were measured by the same method as in Example 1. The results are shown in FIG. 2, FIG. 3, and FIG.
- Example 3 has a 9.7% higher ability to reduce pseudo nanotopography than Comparative Example 1 described later.
- the nanotopography of the mirror wafer was 3.1 nm smaller than Comparative Example 1 described later.
- the flatness (SFQR) of a mirror surface wafer is also favorable as shown in FIG.
- Example 1 Double-head grinding is performed under the same conditions as in Example 1 except that the wear amount of the grinding wheel per 1 ⁇ m of grinding allowance of the workpiece is set to 0.08 ⁇ m. A crystalline silicon wafer was processed to obtain a mirror wafer. Moreover, the average value of pseudo nanotopography reduction ability, the average value of nanotopography, and the average value of flatness (SFQR) were measured by the same method as in Example 1. The results are shown in FIG. 2, FIG. 3, and FIG. As described above, it was confirmed that the ability to reduce pseudo-nanotopography was inferior to that of Examples 1 to 3, and the nanotopography of the mirror surface wafer was increased by about 3.0 nm.
- the double-head grinding method of the present invention can reduce the nanotopography formed in the previous step while preventing deterioration of flatness in double-head grinding, as a result, It has been found that good mirror wafers with small nanotopography can be obtained after all processing steps have been completed.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Grinding Of Cylindrical And Plane Surfaces (AREA)
Abstract
Description
このようなものを用いることで、砥石の自生発刃作用を効果的に促進できるため、安定した連続研削をより確実に行うことができる。
このようにすれば、簡単にワークの研削取り代1μmあたりの砥石の摩耗量を算出することができる。
上記説明したように、ウェーハの加工工程で形成されたナノトポグラフィを、両頭研削工程において低減させる有効な両頭研削方法は見出されていなかった。そして、スライス工程等で形成されたナノトポグラフィは、両頭研削工程で低減されない限り、最終工程(両面研磨工程)まで残存してしまっていた。そこで、本発明者は、両頭研削に使用する砥石に着目し、両頭研削用の砥石の摩耗量が多くなるほど、ワークに食いつき、砥石が空転しにくい傾向があることを見出した。そして、両頭研削用の砥石の摩耗量を増やすことで、ワークの偏極点に、砥石が食いつきやすくなり、偏極点を効果的に研削して、ナノトポグラフィの低減が可能であると考えた。その一方で、本発明者は砥石の摩耗量を増やし過ぎると、対になっている砥石同士を平行に保つことができなくなり、平坦度の悪化を招くことを見出した。
図5は、両頭研削工程後のウェーハの表面の疑似ナノトポグラフィと、両頭研削工程後、エッチング工程、両面研磨工程の順に加工処理されたウェーハの表面のナノトポグラフィとの関係を示すグラフである。尚、このウェーハは直径300mmの単結晶シリコンウェーハとした。疑似ナノトポグラフィは、SBW-330(コベルコ科研製)、ナノトポグラフィは、Wafer Sight II(KLA-Tencor製)を用いて測定した。
図1に示すように、本発明の両頭研削方法で使用する両頭研削装置1は、主に、ワークWの両面を同時に研削する一対の砥石2、ワークWを支持するリング状ホルダー3、リング状ホルダー3を流体の静圧により非接触支持する一対の静圧支持部材4を備えている。
ここで、両頭研削装置1が、上記した静圧支持部材4を具備している場合には、ワークを支持するリング状ホルダー3を、一対の静圧支持部材4の間に静圧支持部材4とリング状ホルダー3が隙間を有するようにして配置し、静圧支持部材4から例えば水などの流体を供給し、リング状ホルダー3を非接触支持する。
このようなものを用いることで、砥石の自生発刃作用を効果的に促進できるため、安定した連続研削をより確実に行うことができる。
図1に示すような、両頭研削装置1を用いて本発明の両頭研削方法で単結晶シリコンウェーハの研削を行った。この単結晶シリコンウェーハは、CZ法(チョクラルスキー法)で製造されたシリコン単結晶インゴットから、切り出された直径300mmのものとした。
そして、切り出された単結晶シリコンウェーハから、研削する単結晶シリコンウェーハを5枚選択した。これら、5枚の単結晶シリコンウェーハの疑似ナノトポグラフィを、SBW-330(コベルコ科研製)で測定したところ1.0μmであった。
実施例1において、ワークの研削取り代1μmあたりの砥石の摩耗量は、0.10μmとなるように設定して両頭研削を実施した。
(擬似ナノトポグラフィ低減能力)
=(研削前の擬似ナノトポグラフィ-研削後の擬似ナノトポグラフィ)÷(研削前の擬似ナノトポグラフィ)×100 ・・・式(1)
また、図3に示すように鏡面ウェーハのナノトポグラフィは、後述する比較例1よりも3.1nm小さいことが確認できた。
また、図4に示すように鏡面ウェーハの平坦度(SFQR)も良好であることが分かった。
ワークの研削取り代1μmあたりの砥石の摩耗量を、0.14μmとなるように設定したこと以外、実施例1と同様な条件で両頭研削を行い、その後、実施例1と同様な条件で単結晶シリコンウェーハを加工処理し鏡面ウェーハを得た。
また、実施例1と同様な方法で、擬似ナノトポグラフィ低減能力の平均値、ナノトポグラフィの平均値、平坦度(SFQR)の平均値を測定した。
その結果を図2、図3、図4に示す。
また、図3に示すように鏡面ウェーハのナノトポグラフィは、後述する比較例1よりも3.0nm小さいことが確認できた。
また、図4に示すように鏡面ウェーハの平坦度(SFQR)も良好であることが分かった。
ワークの研削取り代1μmあたりの砥石の摩耗量を、0.33μmとなるように設定したこと以外、実施例1と同様な条件で両頭研削を行い、その後、実施例1と同様な条件で単結晶シリコンウェーハを加工処理し鏡面ウェーハを得た。
また、実施例1と同様な方法で、擬似ナノトポグラフィ低減能力の平均値、ナノトポグラフィの平均値、平坦度(SFQR)の平均値を測定した。その結果を図2、図3、図4に示す。
また、図3に示すように鏡面ウェーハのナノトポグラフィは、後述する比較例1よりも3.1nm小さいことが確認できた。
また、図4に示すように鏡面ウェーハの平坦度(SFQR)も良好であることが分かった。
ワークの研削取り代1μmあたりの砥石の摩耗量を、0.08μmとなるように設定したこと以外、実施例1と同様な条件で両頭研削を行い、その後、実施例1と同様な条件で単結晶シリコンウェーハを加工処理し鏡面ウェーハを得た。
また、実施例1と同様な方法で、擬似ナノトポグラフィ低減能力の平均値、ナノトポグラフィの平均値、平坦度(SFQR)の平均値を測定した。その結果を図2、図3、図4に示す。
上述のように、実施例1~3よりも擬似ナノトポグラフィ低減能力は劣り、鏡面ウェーハのナノトポグラフィは約3.0nmも大きくなってしまうことが確認された。
ワークの研削取り代1μmあたりの砥石の摩耗量を、0.40μmとなるように設定したこと以外、実施例1と同様な条件で両頭研削を行った。
このとき、砥石の摩耗量が大きすぎるため、両頭研削中に砥石同士を平行に保つことができず、図4に示すように鏡面ウェーハの平坦度(SFQR)が大幅に悪化してしまった。
また、図2、図3に示すように擬似ナノトポグラフィ低減能力及び鏡面ウェーハのナノトポグラフィは比較例1よりも更に悪化してしまい、実施例1~3に大幅に劣ることが確認された。
Claims (3)
- リング状ホルダーによって、薄板状のワークを径方向に沿って外周側から支持して自転させるとともに、一対の砥石によって、前記リング状ホルダーにより支持した前記ワークの両面を同時に研削するワークの両頭研削方法であって、
前記ワークの研削取り代1μmあたりの前記砥石の摩耗量が、0.10μm以上0.33μm以下となるように設定して、前記ワークの両面を同時に研削することを特徴とするワークの両頭研削方法。 - 前記砥石として、円環状台金の外周にビトリファイドボンド砥石を配置したものを用いることを特徴とする請求項1に記載のワークの両頭研削方法。
- 前記ワークの研削取り代1μmあたりの前記砥石の摩耗量は、研削時の砥石の前進位置の変位から求めた砥石の摩耗量を、研削開始前と研削終了後のワークの厚さの差である研削取り代で割った値として算出することを特徴とする請求項1又は請求項2に記載のワークの研削方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/116,130 US9962802B2 (en) | 2014-02-20 | 2015-01-23 | Workpiece double-disc grinding method |
SG11201606945PA SG11201606945PA (en) | 2014-02-20 | 2015-01-23 | Workpiece double-disc grinding method |
KR1020167022753A KR102098260B1 (ko) | 2014-02-20 | 2015-01-23 | 워크의 양두연삭방법 |
CN201580008363.2A CN105980103B (zh) | 2014-02-20 | 2015-01-23 | 工件的双头磨削方法 |
DE112015000522.6T DE112015000522T5 (de) | 2014-02-20 | 2015-01-23 | Werkstückdoppelscheibenschleifverfahren |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014031004A JP6040947B2 (ja) | 2014-02-20 | 2014-02-20 | ワークの両頭研削方法 |
JP2014-031004 | 2014-02-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015125412A1 true WO2015125412A1 (ja) | 2015-08-27 |
Family
ID=53877940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2015/000295 WO2015125412A1 (ja) | 2014-02-20 | 2015-01-23 | ワークの両頭研削方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US9962802B2 (ja) |
JP (1) | JP6040947B2 (ja) |
KR (1) | KR102098260B1 (ja) |
CN (1) | CN105980103B (ja) |
DE (1) | DE112015000522T5 (ja) |
SG (1) | SG11201606945PA (ja) |
TW (1) | TWI602656B (ja) |
WO (1) | WO2015125412A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7159861B2 (ja) | 2018-12-27 | 2022-10-25 | 株式会社Sumco | 両頭研削方法 |
CN110118683B (zh) * | 2019-06-12 | 2020-06-19 | 华东理工大学 | 一种微试样研磨装置 |
CN114227524A (zh) * | 2021-12-30 | 2022-03-25 | 西安奕斯伟材料科技有限公司 | 双面研磨装置和双面研磨方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000052209A (ja) * | 1998-08-06 | 2000-02-22 | Nippon Sheet Glass Co Ltd | 両頭平面研削装置およびそれを用いた研削方法 |
JP2007096015A (ja) * | 2005-09-29 | 2007-04-12 | Shin Etsu Handotai Co Ltd | 半導体ウェーハの両頭研削装置、静圧パッドおよびこれを用いた両頭研削方法 |
JP2007210054A (ja) * | 2006-02-08 | 2007-08-23 | Toshiba Ceramics Co Ltd | カップ型砥石および両頭研削装置ならびに両頭研削方法 |
JP4420023B2 (ja) * | 2004-08-17 | 2010-02-24 | 信越半導体株式会社 | 半導体ウェーハの測定方法、その製造工程の管理方法、及び半導体ウェーハの製造方法 |
JP2013229586A (ja) * | 2012-03-30 | 2013-11-07 | Mitsubishi Chemicals Corp | 第13族窒化物結晶基板の製造方法 |
WO2014006818A1 (ja) * | 2012-07-03 | 2014-01-09 | 信越半導体株式会社 | 両頭研削装置及びワークの両頭研削方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3616578A (en) * | 1969-01-10 | 1971-11-02 | Ingersoll Milling Machine Co | Method for turning workpieces |
JPS5733928A (en) * | 1980-07-29 | 1982-02-24 | Inoue Japax Res Inc | Carbon electrode for electric discharge machining |
JPS5871062A (ja) * | 1981-10-24 | 1983-04-27 | Ntn Toyo Bearing Co Ltd | 円錐ころ軸受内輪の加工方法 |
US5643051A (en) * | 1995-06-16 | 1997-07-01 | The University Of Connecticut | Centerless grinding process and apparatus therefor |
KR100227924B1 (ko) * | 1995-07-28 | 1999-11-01 | 가이데 히사오 | 반도체 웨이퍼 제조방법, 그 방법에 사용되는 연삭방법 및 이에 사용되는 장치 |
JP3471167B2 (ja) * | 1996-05-21 | 2003-11-25 | 昭和電工株式会社 | 立方晶窒化ホウ素の製造方法 |
TW589415B (en) * | 1998-03-09 | 2004-06-01 | Shinetsu Handotai Kk | Method for producing silicon single crystal wafer and silicon single crystal wafer |
JP2005238444A (ja) * | 1999-05-07 | 2005-09-08 | Shin Etsu Handotai Co Ltd | 両面同時研削方法および両面同時研削盤並びに両面同時ラップ方法および両面同時ラップ盤 |
US6811465B1 (en) * | 1999-10-27 | 2004-11-02 | Unova U.K. Limited | Workpiece grinding method which achieves a constant stock removal rate |
DE10023002B4 (de) * | 2000-05-11 | 2006-10-26 | Siltronic Ag | Satz von Läuferscheiben sowie dessen Verwendung |
US6709981B2 (en) * | 2000-08-16 | 2004-03-23 | Memc Electronic Materials, Inc. | Method and apparatus for processing a semiconductor wafer using novel final polishing method |
KR100842473B1 (ko) * | 2000-10-26 | 2008-07-01 | 신에츠 한도타이 가부시키가이샤 | 웨이퍼의 제조방법 및 연마장치 및 웨이퍼 |
DE10058305A1 (de) * | 2000-11-24 | 2002-06-06 | Wacker Siltronic Halbleitermat | Verfahren zur Oberflächenpolitur von Siliciumscheiben |
JP4093793B2 (ja) * | 2002-04-30 | 2008-06-04 | 信越半導体株式会社 | 半導体ウエーハの製造方法及びウエーハ |
JP2005246510A (ja) * | 2004-03-02 | 2005-09-15 | Nissan Motor Co Ltd | 金属材料の高平滑研削方法及び金属材料高平滑研削装置 |
CN101056741B (zh) * | 2004-11-19 | 2010-12-08 | 丰田万磨株式会社 | 砂轮 |
JP5141072B2 (ja) * | 2006-04-25 | 2013-02-13 | 日本精工株式会社 | 軸受ユニット用外輪の製造方法 |
DE102006032455A1 (de) * | 2006-07-13 | 2008-04-10 | Siltronic Ag | Verfahren zum gleichzeitigen beidseitigen Schleifen mehrerer Halbleiterscheiben sowie Halbleierscheibe mit hervorragender Ebenheit |
KR100772034B1 (ko) * | 2006-12-08 | 2007-10-31 | 주식회사 썬텍인더스트리 | 코팅된 3차원 연마재 구조물을 갖는 연마포지의 제조방법 |
JP2009094326A (ja) | 2007-10-10 | 2009-04-30 | Disco Abrasive Syst Ltd | ウェーハの研削方法 |
JP4985451B2 (ja) | 2008-02-14 | 2012-07-25 | 信越半導体株式会社 | ワークの両頭研削装置およびワークの両頭研削方法 |
-
2014
- 2014-02-20 JP JP2014031004A patent/JP6040947B2/ja active Active
-
2015
- 2015-01-23 WO PCT/JP2015/000295 patent/WO2015125412A1/ja active Application Filing
- 2015-01-23 DE DE112015000522.6T patent/DE112015000522T5/de active Pending
- 2015-01-23 KR KR1020167022753A patent/KR102098260B1/ko active IP Right Grant
- 2015-01-23 CN CN201580008363.2A patent/CN105980103B/zh active Active
- 2015-01-23 US US15/116,130 patent/US9962802B2/en active Active
- 2015-01-23 SG SG11201606945PA patent/SG11201606945PA/en unknown
- 2015-02-09 TW TW104104270A patent/TWI602656B/zh active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000052209A (ja) * | 1998-08-06 | 2000-02-22 | Nippon Sheet Glass Co Ltd | 両頭平面研削装置およびそれを用いた研削方法 |
JP4420023B2 (ja) * | 2004-08-17 | 2010-02-24 | 信越半導体株式会社 | 半導体ウェーハの測定方法、その製造工程の管理方法、及び半導体ウェーハの製造方法 |
JP2007096015A (ja) * | 2005-09-29 | 2007-04-12 | Shin Etsu Handotai Co Ltd | 半導体ウェーハの両頭研削装置、静圧パッドおよびこれを用いた両頭研削方法 |
JP2007210054A (ja) * | 2006-02-08 | 2007-08-23 | Toshiba Ceramics Co Ltd | カップ型砥石および両頭研削装置ならびに両頭研削方法 |
JP2013229586A (ja) * | 2012-03-30 | 2013-11-07 | Mitsubishi Chemicals Corp | 第13族窒化物結晶基板の製造方法 |
WO2014006818A1 (ja) * | 2012-07-03 | 2014-01-09 | 信越半導体株式会社 | 両頭研削装置及びワークの両頭研削方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2015155129A (ja) | 2015-08-27 |
US9962802B2 (en) | 2018-05-08 |
CN105980103A (zh) | 2016-09-28 |
JP6040947B2 (ja) | 2016-12-07 |
US20170136596A1 (en) | 2017-05-18 |
TWI602656B (zh) | 2017-10-21 |
DE112015000522T5 (de) | 2016-10-13 |
SG11201606945PA (en) | 2016-10-28 |
TW201600247A (zh) | 2016-01-01 |
KR102098260B1 (ko) | 2020-04-07 |
KR20160124110A (ko) | 2016-10-26 |
CN105980103B (zh) | 2017-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7867059B2 (en) | Semiconductor wafer, apparatus and process for producing the semiconductor wafer | |
JP6244962B2 (ja) | 半導体ウェーハの製造方法 | |
US7704126B2 (en) | Method for producing a semiconductor wafer with profiled edge | |
JP5494552B2 (ja) | 両頭研削方法及び両頭研削装置 | |
TWI445125B (zh) | A method of manufacturing a two-head grinding apparatus and a wafer | |
JP5967040B2 (ja) | 鏡面研磨ウェーハの製造方法 | |
SG173290A1 (en) | Method for producing a semiconductor wafer | |
JP6079554B2 (ja) | 半導体ウェーハの製造方法 | |
JP2009302409A (ja) | 半導体ウェーハの製造方法 | |
JP6040947B2 (ja) | ワークの両頭研削方法 | |
JP2010021394A (ja) | 半導体ウェーハの製造方法 | |
KR101752986B1 (ko) | SiC 기판의 제조 방법 | |
JP2002231665A (ja) | エピタキシャル膜付き半導体ウエーハの製造方法 | |
US20150266155A1 (en) | Method for producing polished-article | |
CN109643650B (zh) | 半导体晶片的研磨方法及半导体晶片 | |
JP6610587B2 (ja) | ウェーハの製造方法 | |
JPH11348031A (ja) | 半導体基板の製造方法、外面加工装置及び単結晶インゴット | |
JP2015153999A (ja) | 半導体ウェーハの製造方法 | |
JP2010153844A (ja) | 活性層用ウェーハの製造方法 | |
JPH08274050A (ja) | 半導体ウェハの製造方法 | |
Chung et al. | Comparison of free abrasive machining processes in wafer manufacturing | |
JP2009135180A (ja) | 半導体ウェーハの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15752243 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 15116130 Country of ref document: US |
|
ENP | Entry into the national phase |
Ref document number: 20167022753 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 112015000522 Country of ref document: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 15752243 Country of ref document: EP Kind code of ref document: A1 |