WO2015118790A1 - 接合材、接合方法、および電力用半導体装置 - Google Patents

接合材、接合方法、および電力用半導体装置 Download PDF

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Publication number
WO2015118790A1
WO2015118790A1 PCT/JP2014/084497 JP2014084497W WO2015118790A1 WO 2015118790 A1 WO2015118790 A1 WO 2015118790A1 JP 2014084497 W JP2014084497 W JP 2014084497W WO 2015118790 A1 WO2015118790 A1 WO 2015118790A1
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Prior art keywords
bonding
power semiconductor
silver
bismuth
bonding material
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PCT/JP2014/084497
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English (en)
French (fr)
Inventor
浩次 山▲崎▼
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to CN201480073843.2A priority Critical patent/CN105934308B/zh
Priority to JP2015528782A priority patent/JP5866075B2/ja
Priority to DE112014006349.5T priority patent/DE112014006349T5/de
Priority to US15/112,078 priority patent/US10043775B2/en
Publication of WO2015118790A1 publication Critical patent/WO2015118790A1/ja

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Definitions

  • the present invention relates to a plate-like bonding material in which the heat-resistant temperature after bonding is higher than the bonding temperature by utilizing a solid phase diffusion reaction of silver, a bonding method using the same, and a power semiconductor device.
  • next-generation devices power semiconductor elements based on silicon carbide (SiC) or gallium nitride (GaN) are being actively developed as next-generation devices. These are operated with a large current and have an operating temperature of 175 ° C. or higher, and are said to be 300 ° C. in the future. At that time, when the bonding material itself is melted and bonded like solder, it is necessary to bond at a temperature higher than the heat-resistant temperature of the bonded portion, and of course, the options of the bonding material itself are limited, and the bonding target is also limited. There were restrictions to prevent deterioration.
  • a bonding material for example, see Patent Document 1 in which nano or micro size metal particles called a sinterable metal or metal paste are blended with an organic solvent has been attracting attention.
  • the organic component covering the surface of the metal particles is decomposed by heat, so that the metal particles are sintered to form a bonded portion, and the heat resistance temperature after sintering (bonding) is integrated.
  • the temperature is about the same as the melting point of the metal (for example, 960 ° C. in the case of silver).
  • the organic solvent decomposes at about 200 to 300 ° C., so that it can be joined at a temperature that does not degrade the object to be joined, and high heat resistance can be achieved after joining.
  • the metal sintered body has an elastic modulus lower than that of an integral metal because it has voids. Nevertheless, since the elastic modulus is still higher than that of conventional solder or the like, the stress relaxation property in the heat cycle is lowered, and it is difficult to maintain the bonding strength for a long period of time. Therefore, a technique has been proposed in which a filler having a lubricity or a resin filler having a lower elastic modulus than metal particles is mixed in the bonding material to relieve stress (for example, see Patent Document 2 or 3).
  • JP 2012-054358 A (paragraph 0010, FIG. 1) JP 2010-267579 A (paragraph 0013, FIG. 1) JP 2011-198674 A (paragraphs 0010 to 0013, FIGS. 1 and 2)
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a joint having both heat resistance and stress relaxation properties.
  • the bonding material according to the present invention forms a silver diffusion layer by solid phase diffusion reaction in the metal member by heating it in contact with the metal member to be bonded, and is bonded to the metal member.
  • a plate-like bonding material composed of an alloy of bismuth and silver, characterized by containing bismuth in an amount of 1% by mass to 5% by mass.
  • the bonding method according to the present invention includes a heat treatment step in which the bonding material is heat-treated at a temperature of 150 ° C. or more and 300 or less, and a bonding material that has undergone the heat treatment step is sandwiched between two bonding objects. And a diffusion layer forming step of forming the silver diffusion layer on each of the two bonding objects by heating to a temperature lower than the melting point of the two.
  • the power semiconductor device includes a circuit board on which a circuit pattern is formed, and a power semiconductor element bonded to the circuit pattern, wherein the power semiconductor element and the circuit pattern are: It joins by the said joining method, It is characterized by the above-mentioned.
  • FIG. 1 to 2 are diagrams for explaining a bonding material, a bonding method using the bonding material, and a power semiconductor device manufactured using them according to the first embodiment of the present invention.
  • FIG. 1 is a cross-sectional view of a bonding material or a bonding portion for each process when bonding a power semiconductor element to a circuit board using a bonding material
  • FIG. 1 (a) is for using an alloy material as a bonding material
  • FIG. 1B is a cross-sectional view showing a state before joining objects to be joined
  • FIG. 1C is a cross-sectional view showing a state of a joined portion after joining. is there.
  • FIG. 2 is a cross-sectional view showing the configuration of a power semiconductor device bonded (manufactured) using a bonding material and a bonding method.
  • the power semiconductor device 100 is a DBC substrate in which copper (Cu) conductive layers 3a and 3b are formed on both surfaces of a base material 3i made of silicon nitride (Si 3 N 4 ) as a circuit board.
  • Vertical power semiconductor elements 2A and 2B are mounted on the circuit surface (conductive layer 3a) side of 3 (Direct Bonded Copper).
  • Lead terminals 4 as wiring members are bonded to the surface electrodes of the power semiconductor elements 2A and 2B by using a plate-shaped bonding material 1 mainly composed of silver, and the back surface is also bonded to the DBC substrate 3. Bonded using the material 1.
  • the entire surface of the DBC substrate 3 is sealed by the sealing body 5 except for the back surface (conductive layer 3b) side of the DBC substrate 3 and the connection end side of the lead terminal 4 to the external circuit.
  • the power semiconductor element 2 may be a general element based on a silicon wafer.
  • silicon carbide is used as a base material for the purpose of application to a so-called wide band gap semiconductor material having a wider band gap than silicon such as silicon carbide (SiC), gallium nitride (GaN), or diamond.
  • the device type is IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal Oxide)
  • switching elements such as Semiconductor Field-Effect-Transistor) or rectifying elements such as diodes.
  • a drain electrode is formed on the surface of the power semiconductor element 2 on the DBC substrate 3 side.
  • the gate electrode and the source electrode are formed on the surface opposite to the drain electrode (upper side in the figure), but the upper surface is used for main power in order to simplify the explanation. Only the source electrode will be described.
  • the DBC substrate 3 has a size of 40 mm ⁇ 40 mm, and the configuration in the thickness direction is: conductive layer 3a: 0.4 mm / base material 3i: 0.3 mm / conductive layer 3b: 0.4 mm.
  • the surface of the drain electrode serving as a bonding surface with the DBC substrate 3 (via the bonding material 1) is covered with gold (Au: surface layer 2 f).
  • the surface serving as a bonding surface with the power semiconductor element 2 (through the bonding material 1) is covered with silver (Ag: surface layer 3 f).
  • the power semiconductor device 100 is characterized in that at least the power semiconductor element 2 is joined to a circuit board (for example, the DBC substrate 3) and a wiring member (for example, the lead terminal 4).
  • An alloy of silver and bismuth (alloy foil 1F) containing 1 to 5 wt% of bismuth (Bi) is used as the bonding material 1.
  • a heat treatment step of holding the alloy foil 1F before bonding at 150 to 300 ° C. for 10 to 100 hours is provided.
  • the bonding material 1 is an alloy containing silver as a main component, and the silver component on the contact surface side with the bonding target is solid-phase diffused into the metal covering the bonding surface of the bonding target to form a silver diffusion layer. It is what joins by doing. Therefore, the form of the present bonding material 1 is not basically changed before and after the bonding. Therefore, in the present specification, particularly when explaining the process, when the state before joining is indicated as “alloy foil 1 ⁇ / b> F”, it does not mean that it is different from the joining material 1.
  • a flaky alloy (alloy foil 1F) to be used as the bonding material 1 with the bismuth content as a parameter.
  • An evaluation was made as to the presence or absence of rolling cracks when prepared and formed into flakes.
  • the power semiconductor element 2 and the DBC substrate 3 are actually joined using the alloy foil 1 ⁇ / b> F as shown in FIG. 10S) was prepared, and heat cycle resistance was evaluated by a thermal shock (heat cycle) test. Details will be described below.
  • the bismuth content is 0.5 wt% (Comparative Example 1), 1 wt% (Example 1), 3 wt% (Example 2), 5 wt% (Example 3). If it was in the range of 1 to 5 wt%, no rolling cracks occurred and good results ( ⁇ ) were obtained.
  • the bismuth content was 6 wt% (Comparative Example 2), which was higher than 5 wt%, a roll crack of about 3 mm, which was the same as the standard, was generated, and thus “ ⁇ ” was set.
  • the bismuth content was 7 wt% (Comparative Example 3)
  • rolling cracks were generated by 3 mm or more, and therefore, “x” was obtained, and good results were not obtained.
  • the alloy foil 1F having a bismuth content of 7 wt% was 200 ° C. ⁇ 48 hrs in a nitrogen atmosphere.
  • Annealing (thermal) treatment was performed.
  • the SiC power semiconductor element 2 thickness 0.3 mm ⁇ 5 mm ⁇ 5 mm
  • the bonding surface is covered with gold (surface layer 2f)
  • silver plating on the bonding surface
  • the alloy foil 1F after the annealing treatment was inserted between the DBC substrate 3 (only the conductive layer 3a portion is shown in the figure) that has been applied (formation of the surface layer 3f).
  • the evaluation sample 10S was placed in a heat cycle apparatus, and a thermal shock test was performed under the condition of ⁇ 55 ° C. ⁇ 30 min / 200 ° C. ⁇ 30 min.
  • the thermal shock cycle reaches 1000 cycles, the evaluation sample 10S is taken out from the apparatus, and the cross section of the element diagonal is observed (observation length: 10 mm ⁇ ⁇ 2 ⁇ 14 mm), and the crack length at the joint end is measured. did.
  • the crack length that affects heat dissipation in actual use is set to 1.4 mm, which is 10% of the total length of 14 mm.
  • the crack length was 1.4 mm or more, the heat cycle resistance (“H / C resistance” in the table) was evaluated as “ ⁇ ”, and when it was 1.4 mm or less, it was evaluated as “ ⁇ ”.
  • the crack growth is 1.4 mm or less. It was good ( ⁇ ).
  • the bismuth content is less than 1 wt%, 0.5 wt% (Comparative Example 1), the crack has progressed by 1.4 mm or more, so “x” is obtained, and even when 6 wt% (Comparative Example 2) is greater than 5 wt%. Since the crack was developed by 1.4 mm or more, it became “x”.
  • FIG. 3A A cross-sectional photograph of a typical bonding material is shown in FIG. 3A is a cross-sectional photograph before annealing
  • FIG. 3B is a cross-sectional photograph after annealing.
  • the white portion is the bismuth-rich precipitated phase X
  • the black color is the phase Y of the base material (Ag).
  • Image software ImageJ was used to measure the particle size of the bismuth-rich precipitated phase X.
  • the cross-sectional photograph is binarized, the bismuth-rich precipitated phase X is displayed in white, and the area S is calculated from a scale estimated in advance surrounding the white portion.
  • the particle size L was calculated from the obtained area S based on the following formula.
  • S ⁇ ⁇ (L / 2) ⁇ 2 (1)
  • S: Area, L: Particle size of bismuth-rich precipitated phase L ⁇ (4 ⁇ S / ⁇ ) (2)
  • the particle diameter of the bismuth-rich precipitated phase X was 3 to 8 ⁇ m before annealing (FIG. 3A) when the bismuth content was 1 to 5 wt%, but after annealing (FIG. 3B )) Is 0.2 to 1.0 ⁇ m, which is considered to support the above mechanism.
  • the thermal conductivity of tin (Sn) -based and lead (Pb) -based solder materials is about 50 W / m ⁇ K
  • the thermal conductivity of pure silver is about 420 W / m ⁇ K.
  • the thermal conductivity of the alloy foil 1F having a bismuth content of 1 to 5 wt% was measured by the optical alternating current method at Bethel Co., Ltd., it was about 150 to 300 W / m ⁇ K, about 3 times that of solder. It was confirmed that the material has high thermal conductivity and excellent heat dissipation.
  • Example 4 and Example 6 As a result, from the evaluation results of Example 4 and Example 6 in which the annealing temperature was set to 150 ° C., Example 5 and Example 7 in which the annealing temperature was set to 300 ° C., the crack progress was observed when the annealing temperature was in the range of 150 ° C. to 300 ° C. Became “ ⁇ ” at 1.4 mm or less.
  • the annealing temperature In the case of 140 ° C. (Comparative Example 4 and Comparative Example 6) where the annealing temperature is lower than 150 ° C., the softening due to the refinement of the structure of the Ag—Bi alloy does not proceed and the stress relaxation property is low, so It has progressed more than 4mm and became "x".
  • the annealing time is set to 10 hrs (Example 8, Example 11, Example 14, Example 17), and the annealing time is set to 30 hrs (Example 9, Example). 12, Example 15, Example 18), when set to 100 hrs (Example 10, Example 13, Example 16, Example 19), that is, when the annealing time is in the range of 10 to 100 hrs, crack growth is 1 It became "(circle)" in 4 mm or less.
  • the annealing time is set to 8 hrs, which is shorter than 10 hrs (Comparative Example 8, Comparative Example 9, Comparative Example 10, and Comparative Example 11), the softening due to the refinement of the structure of the Ag—Bi alloy does not progress, and the stress relaxation property Is low, the crack progressed by 1.4 mm or more and became “x”.
  • the annealing temperature is 300 ° C., which is the upper limit of the temperature range
  • holding for 120 hours exceeding the time range described above results in low stress relaxation and a crack progressing by 1.4 mm or more, indicating “x”.
  • the crystal grains of bismuth are coarsened by heat rather than the fine dispersion effect and function to suppress the grain boundary sliding.
  • the temperature is lower than 300 ° C. in the temperature range, it has been confirmed that the heat cycle resistance against cracking is “O” until the holding time is 100 hrs. It is unclear whether a fine dispersion effect can be seen.
  • the joining atmosphere, joining temperature, pressurization, and holding time are mainly parameters.
  • a formic acid reducing atmosphere is used as the bonding atmosphere, but a hydrogen reducing atmosphere may be used.
  • the bonding temperature may be any temperature that promotes the solid phase diffusion reaction between the metal covering the bonding surface to be bonded and the Ag—Bi alloy, and is 300 ° C. in the parameter test, but in the range of 250 to 300 ° C. If there is, the same effect can be obtained. If the bonding temperature is set to a temperature lower than 250 ° C., the solid phase diffusion reaction with the bonding surface does not proceed, so that a good bonding portion cannot be obtained. Even when the temperature is set lower than 250 ° C., the diffusion proceeds if the holding time is lengthened. However, it is considered that it cannot be applied practically in view of the mass production process.
  • the bonding temperature is set to a temperature higher than 300 ° C.
  • the copper constituting the conductive layers 3a and 3b of the DBC substrate 3 is softened. Therefore, when the evaluation sample 10S is created at a bonding temperature higher than 300 ° C., the initial bonded portion is good, but when the heat cycle test is performed, the DBC substrate 3 is warped, the surface is wavy, and becomes uneven. Then, a crack occurs due to the warp of the DBC substrate 3 at the joint end, and it becomes impossible to follow the unevenness of the DBC substrate 3 inside the joint, and a crack in the vertical direction occurs with respect to the joint surface. Therefore, the bonding temperature is preferably 250 ° C. to 300 ° C.
  • the bonding time may be a time during which a solid phase diffusion reaction occurs between the metal that covers the bonding surface to be bonded and the Ag—Bi alloy. In the above, the time is 10 min. ing. If the joining time is too long, the tact time in the mass production process is long and disadvantageous, so 5 to 10 min is optimal.
  • the applied pressure depends on the flatness of the bonding surface
  • the surface flatness Ra of the power semiconductor element 2 used in this evaluation is 50 nm or less
  • the flatness Ra of the surface of the DBC substrate 3 used in the evaluation is used. All were 1 ⁇ m or less. With such flatness, good bonding can be obtained by pressing the Ag—Bi alloy foil 1F under a pressure of 10 to 30 MPa.
  • the surface flatness Ra of the alloy foil 1F is 1 ⁇ m or less.
  • the metal covering the bonding surface is a combination of any of gold, silver, and copper for both the power semiconductor element 2 and the DBC substrate 3, good bonding is obtained.
  • tin has a melting point of about 230 ° C. and melts at a joining temperature of 250 to 300 ° C.
  • silver diffuses into tin and a fine intermetallic compound (Ag 3 Sn) and a eutectic phase of tin and silver (Sn-3Ag (wt%)) having a melting point of 220 ° C. are formed, Since heat resistance is impaired, it is not preferable.
  • a tin single phase having a low melting point, a eutectic phase of tin and silver, or a eutectic phase of tin and bismuth remains at the interface between Sn and the Ag—Bi alloy. It is necessary to heat enough so that there is no. And it is necessary to make all the interface parts be formed of at least an intermetallic compound of Ag 3 Sn and Ag 5 Sn.
  • an Ag—Bi alloy is used for joining the power semiconductor element 2 and the DBC substrate 3 or joining the power semiconductor element 2 and the lead terminal 4.
  • An example using the bonding material 1 was shown.
  • the power semiconductor device 100 is not limited to the DBC substrate 3 and is usually provided with a heat sink under the circuit board, and the bonding material 1 of the present invention is also applied to the connection between the circuit board and the heat sink. It is possible to do.
  • the example in which silicon carbide is used for the power semiconductor element 2 functioning as a switching element or a rectifying element has been described.
  • This can also be applied to other silicon-based devices.
  • an element called a wide bandgap semiconductor element such as silicon carbide, gallium nitride-based material or diamond
  • the power loss is lower than that of an element formed from silicon that has been conventionally used.
  • the efficiency of the power semiconductor device 100 can be increased.
  • the withstand voltage is high and the allowable current density is also high, the power semiconductor device 100 can be downsized.
  • the wide band gap semiconductor element has high heat resistance, it can operate at a high temperature, and the heat sink fins can be downsized and the water cooling section can be air cooled. Therefore, the power semiconductor device 100 can be further downsized. Can be realized.
  • the power semiconductor element 2 is mounted using the Ag—Bi alloy-based bonding material 1 described in the embodiment of the present invention, the heat dissipation characteristics and the electrical conductivity are excellent, and at the time of manufacturing and driving. Since a strong bond can be maintained even under a thermal cycle, a highly reliable power semiconductor device 100 can be obtained.
  • the metal member to be bonded (for example, the surface layer 2f of the element electrode of the power semiconductor element 2 and the surface layer of the conductive layer 3a of the DBC substrate 3). 3f) is heated in contact with the metal member to form silver diffusion layers Ld2 and Ld3 by solid phase diffusion reaction in the metal member (for example, gold, silver, and copper as materials) and bonded to the metal member.
  • This is a plate-like bonding material 1 made of an alloy of bismuth and silver, and is composed so as to contain bismuth in an amount of 1% by mass to 5% by mass. And a stress-relaxing joint can be obtained.
  • the bonding material 1 is a rolled material having a thickness of 50 ⁇ m to 100 ⁇ m, and the bonded body 10 can be formed without increasing the thickness excessively, and a small and highly efficient power semiconductor device 100 can be easily manufactured. Can do. Moreover, the surface precision suitable for joining can be obtained easily.
  • the bonding material 1 is heat-treated at a temperature of 150 ° C. or higher and 300 or lower, and two bonding objects (for example, the power semiconductor element 2 and the DBC substrate 3).
  • the stress relaxation effect can be obtained with certainty.
  • the heating temperature in the diffusion layer forming step is 250 ° C. or higher and 300 ° C. or lower, a strong bond can be obtained without deteriorating the bonding target.
  • the diffusion layer forming step is performed in a reducing atmosphere (for example, a hydrogen atmosphere or a formic acid atmosphere), an oxide film is not generated on the bonding material 1 or the bonding surface of the bonding target, and the silver diffusion layers Ld2 and Ld3 are reliably formed. Can be formed.
  • a reducing atmosphere for example, a hydrogen atmosphere or a formic acid atmosphere
  • metal layers 2f and 3f of gold, silver, or copper are formed as metal members on the opposing surfaces of the power semiconductor element 2 and the circuit pattern (conductive layer 3a), the silver Diffusion layers Ld2 and Ld3 are reliably obtained.

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Abstract

本発明は、耐熱性と応力緩和性を両立させた接合を得ることを目的とし、接合対象である金属部材（例えば、表面層（２ｆ）、（３ｆ））に接触させた状態で加熱することにより、金属部材（例えば、材料として金、銀、銅）の中に固相拡散反応による銀の拡散層（Ｌｄ２）、（Ｌｄ３）を形成し、金属部材と接合される、ビスマスと銀の合金で構成された板状の接合材（１）であって、ビスマスを１質量％以上、５質量％以下含有する構成とした。

Description

接合材、接合方法、および電力用半導体装置
　本発明は、銀の固相拡散反応を利用することで、接合後の耐熱温度が接合温度よりも高くなる板状の接合材と、それを用いた接合方法、および電力用半導体装置に関する。
　近年、電力用半導体装置に対する信頼性の要求はますます高まり、特に熱膨張係数差の大きい電力用半導体素子と回路基板との接合部についての寿命信頼性の向上が求められている。従来、電力用半導体素子としては、シリコン（Ｓｉ）やガリウム砒素（ＧａＡｓ）を基材としたものが多く使われ、その動作温度は１００℃～１２５℃である。これらの素子を回路基板に接合する際には、はんだ材が多用されてきた。
　一方、省エネルギーの観点から次世代デバイスとしてシリコンカーバイド（ＳｉＣ）や窒化ガリウム（ＧａＮ）を基材とした電力用半導体素子の開発が盛んになされている。これらは、大電流で動作するとともに、動作温度が１７５℃以上とされており、将来的には３００℃になるとも言われている。その際、はんだのように接合材自体を融解して接合する場合、接合部の耐熱温度より高い温度で接合する必要があり、接合材自体の選択肢が限られることは勿論のこと、接合対象を劣化させないための制約があった。
　そこで、焼結性金属あるいは金属ペーストと呼ばれるナノあるいはマイクロサイズの金属粒子と有機溶剤を配合した接合材（例えば、特許文献１参照。）が注目されている。このような接合材は、金属粒子の表面を覆っていた有機成分が熱によって分解することで、金属粒子同士が焼結して接合部を形成し、焼結（接合）後の耐熱温度は一体の金属の融点と同程度の温度（例えば、銀の場合は９６０℃）となる。有機成分にもよるが、有機溶剤は約２００～３００℃で分解するので、接合対象を劣化させない温度で接合でき、接合後は高耐熱化が図れる。
　一方、金属の焼結体は、特許文献１に記載されているように、一体の金属と比べれば、空隙を有する分、弾性率は低くなる。それでも、従来のはんだ等と比べると、依然弾性率は高いので、ヒートサイクルでの応力緩和性が低くなり、接合強度を長期間にわたって維持することは困難であった。そこで、潤滑性を有する粒子、あるいは金属粒子よりも弾性率の低い樹脂のフィラーを接合材中に混入し、応力を緩和する技術が提案されている（例えば、特許文献２または３参照。）。
特開２０１２－０５４３５８号公報（段落００１０、図１） 特開２０１０－２６７５７９号公報（段落００１３、図１） 特開２０１１－１９８６７４号公報（段落００１０～００１３、図１、図２）
　しかしながら、樹脂材料の耐熱温度を、次世代デバイスで想定される運転温度よりも高くすることは困難であり、高温で使用すると、接合材中の樹脂の劣化によって、接合強度が低下することになる。つまり、耐熱性と応力緩和性を両立させた接合を得ることは困難であった。
　本発明は、上記のような問題点を解決するためになされたものであり、耐熱性と応力緩和性を両立させた接合を得ることを目的とする。
　本発明にかかる接合材は、接合対象である金属部材に接触させた状態で加熱することにより、前記金属部材の中に固相拡散反応による銀の拡散層を形成し、前記金属部材と接合される、ビスマスと銀の合金で構成された板状の接合材であって、ビスマスを１質量％以上、５質量％以下含有することを特徴とする。
　また、本発明にかかる接合方法は、上記接合材を１５０℃以上、３００以下の温度で熱処理する熱処理工程と、２つの接合対象の間に、前記熱処理工程を経た接合材を挟み、前記接合材の融点よりも低い温度に加熱して、前記２つの接合対象のそれぞれに前記銀の拡散層を形成する拡散層形成工程と、を含むことを特徴とする。
　また、本発明にかかる電力用半導体装置は、回路パターンが形成された回路基板と、前記回路パターンに接合された電力用半導体素子と、を備え、前記電力用半導体素子と前記回路パターンとが、上記接合方法によって接合されていることを特徴とする。
　この発明によれば、銀にビスマスを所定範囲の割合で添加することで、耐熱性と応力緩和性を両立させた接合を得ることができる。また、その接合を用いることで、高温に対応し、信頼性の高い電力用半導体装置を得ることができる。
本発明の実施の形態１にかかる接合材を用いた接合方法を説明するための工程ごとの接合材あるいは接合部分の断面図である。 本発明の実施の形態１にかかる接合材および接合方法を用いて製造した電力用半導体装置の構成を示す断面図である。 本発明の実施の形態１にかかる接合材の断面模式図である。
実施の形態１．
　図１～図２は、本発明の実施の形態１にかかる接合材、接合材を用いた接合方法、およびそれらを用いて製造された電力用半導体装置について説明するためのものである。図１は接合材を用いて電力用半導体素子を回路基板に接合する際の工程ごとの接合材あるいは接合部分の断面図であって、図１（ａ）は合金材を接合材として用いるために薄片状に圧延する様子を示す断面模式図、図１（ｂ）は接合対象どうしを接合する前の状態を示す断面図、図１（ｃ）は接合後の接合部分の状態を示す断面図である。また、図２は接合材および接合方法を用いて接合（製造）した電力用半導体装置の構成を示す断面図である。
　接合材および接合材を用いた接合方法について説明する前に、その好適な適用対象である電力用半導体装置の構成について説明する。
　電力用半導体装置１００は、図２に示すように、回路基板として、窒化ケイ素（Ｓｉ３Ｎ４）製の基材３ｉの両面に銅（Ｃｕ）の導電層３ａ、３ｂが形成されたＤＢＣ基板３（Direct　Bonded　Copper）の回路面（導電層３ａ）側に、縦型の電力用半導体素子２Ａ、２Ｂ（まとめて電力用半導体素子２）が実装されたものである。電力用半導体素子２Ａ、２Ｂの表面電極には、配線部材であるリード端子４が銀を主体とした板状の接合材１を用いて接合されているとともに、裏面もＤＢＣ基板３に対して接合材１を用いて接合されている。そして、ＤＢＣ基板３の裏面（導電層３ｂ）側と、リード端子４の外部回路との接続端側を除き、全面が封止体５によって封止されてパッケージ化されたものである。
　電力用半導体素子２は、シリコンウエハを基材とした一般的な素子でも良い。しかし、本発明においては炭化ケイ素（ＳｉＣ）や窒化ガリウム（ＧａＮ）、またはダイヤモンドといったシリコンと較べてバンドギャップが広い、いわゆるワイドバンドギャップ半導体材料への適用を目的とし、炭化ケイ素を基材として適用した。デバイス種類としては、ＩＧＢＴ（Insulated　
Gate　Bipolar　Transistor）やＭＯＳＦＥＴ（Metal　Oxide　
Semiconductor　Field-Effect-Transistor）のようなスイッチング素子、またはダイオードのような整流素子がある。例えば、ＭＯＳＦＥＴの場合、電力用半導体素子２のＤＢＣ基板３側の面にはドレイン電極が形成されている。そして、ドレイン電極と反対側（図で上側）の面には、ゲート電極やソース電極が、領域を分けて形成されているが、説明を簡略化するため、上側の面は、主電力用のソース電極のみを記載して説明する。
　ＤＢＣ基板３は、４０ｍｍ×４０ｍｍのサイズを有し、厚み方向の構成は、導電層３ａ：０．４ｍｍ／基材３ｉ：０．３ｍｍ／導電層３ｂ：０．４ｍｍである。電力用半導体素子２の電極のうち、（接合材１を介した）ＤＢＣ基板３との接合面となるドレイン電極の表面は、金（Ａｕ：表面層２ｆ）で覆われている。また、ＤＢＣ基板３の導電層３ａ、３ｂのうち、（接合材１を介した）電力用半導体素子２との接合面となる表面は、銀（Ａｇ：表面層３ｆ）で覆われている。そして、本発明の実施の形態１にかかる電力用半導体装置１００の特徴は、少なくとも電力用半導体素子２と回路基板（例えばＤＢＣ基板３）や配線部材（例えば、リード端子４）との接合に、１～５ｗｔ％のビスマス（Ｂｉ）を含有する銀とビスマスの合金（合金箔１Ｆ）を接合材１として用いたものである。また、接合方法として、接合前の合金箔１Ｆを１５０℃から３００℃で１０～１００時間保持するという熱処理工程を設けたことにある。
　なお、接合材１は、銀を主成分とする合金であり、接合対象との接触表面側の銀成分が、接合対象の接合面を覆う金属内に固相拡散し、銀の拡散層を形成することで接合するものである。そのため、本接合材１は、基本的には、接合の前後においてその形態が変化するものではない。したがって、本明細書においては、とくに工程を説明する際に、接合前の状態を示す場合は「合金箔１Ｆ」と記載することがあるが、接合材１と異なることを意味するわけではない。
　上述した、接合材１の組成、熱処理条件（温度、保持時間）を最適化するため、はじめに、ビスマス含有率をパラメータとして、接合材１として使用するための薄片状の合金（合金箔１Ｆ）を作成し、薄片状にした際の圧延割れの有無について評価を行った。そして、圧延割れが生じなかった組成のものを用いて、図１に示すように、電力用半導体素子２とＤＢＣ基板３とを実際に合金箔１Ｆを用いて接合して接合体１０（評価サンプル１０Ｓと称す）を作成し、熱衝撃（ヒートサイクル）試験によって耐ヒートサイクル性の評価を行った。以下、詳細に説明する。
　＜合金（箔）の作成＞
　合金中のビスマス含有率（ｗｔ％）が所望の含有率になるように、純度９９．９ｗｔ％の粒状の銀と粉末状のビスマス（針状）をそれぞれ電子天秤で秤量して、石英ガラス製るつぼに入れ、大気中でガストーチまたは高周波誘導加熱装置で加熱・溶解した。炉全体を銀の融点以上に保持し、ビスマスがまんべんなく分散するように石英ガラス保護管で攪拌した後、冷却・凝固させて試料合金１Ｒを作成した。その後、図１（ａ）に示すように、試料合金１Ｒに圧延処理をおこない、厚さ：５０～１００μｍ、幅：４０ｍｍのＡｇ―Ｂｉ合金薄片（合金箔１Ｆ）を作製した。
　＜ビスマス含有率＞
　合金箔１Ｆを作成した際の圧延処理で、合金箔１Ｆの両端部に３ｍｍ以上の圧延割れが生じていなければ評価結果として「○」、圧延割れが生じていれば「×」とした。ビスマスの含有率を０．５ｗｔ％～７ｗｔ％までの間で変化させて６種の評価サンプル１０Ｓ（実施例１～３、比較例１～３）を作成し、評価した。その評価結果を表１に示す。なお、合金箔１Ｆの作製方法については、シート成形方法、プレス成形、粉末焼成法などを適用でき、圧延処理に限定するものではない。
Figure JPOXMLDOC01-appb-T000001
　その結果、同様の圧延工程で比較すると、ビスマスの含有率が０．５ｗｔ％（比較例１）、１ｗｔ％（実施例１）、３ｗｔ％（実施例２）、５ｗｔ％（実施例３）の１～５ｗｔ％の範囲であれば、圧延割れは生じず良好な結果（○）であった。ビスマス含有率が５ｗｔ％よりも高い６ｗｔ％（比較例２）だと、ちょうど基準と同じ３ｍｍ程度の圧延割れが生じていたため、「△」とした。ビスマス含有率が７ｗｔ％（比較例３）だと、圧延割れが３ｍｍ以上生じてしまったため「×」とし、良好な結果が得られなかった。
　次に、圧延割れを生じたビスマス含有率が７ｗｔ％の合金箔１Ｆ（比較例３）を除き、ビスマス含有率が０．５～５ｗｔ％の合金箔１Ｆを窒素雰囲気中で２００℃×４８ｈｒｓのアニール（熱）処理を行った。そして、図１（ｂ）に示すように、接合表面が金（表面層２ｆ）で覆われたＳｉＣの電力用半導体素子２（厚み０．３ｍｍ×５ｍｍ×５ｍｍ）と、接合表面に銀めっきが施（表面層３ｆが形成）されているＤＢＣ基板３（図では導電層３ａ部分のみ示す。）との間に、アニール処理後の合金箔１Ｆを挿入した。その状態で、ギ酸還元雰囲気中にて、室温から昇温し、接合温度３００℃に到達した時点で温度を保持し、１０ＭＰa加圧しながら接合時間として１０ｍｉｎ保持した。このように加熱、加圧によって、素子電極の表面層２ｆの金と合金箔１Ｆの固相拡散反応（素子電極の金内に、合金中の銀が固相拡散した拡散層Ｌｄ２の生成）、ＤＢＣ基板３表面層３ｆの銀と合金箔１Ｆの固相拡散反応（ＤＢＣ基板３側の銀内に、合金中の銀が拡散した拡散層Ｌｄ３の生成）を促進させることができる。保持後、加圧を止めて、冷却し、評価サンプル
１０Ｓ（実施例１～３、比較例１～２）を得た。
　次に、評価サンプル１０Ｓをヒートサイクル装置内に設置し、－５５℃×３０ｍｉｎ／２００℃×３０ｍｉｎの条件で熱衝撃試験を行った。熱衝撃サイクルが、１０００サイクルになった時点で評価サンプル１０Ｓを装置から取り出し、素子対角の断面観察（観察長さ：１０ｍｍ×√２≒１４ｍｍ）を行い、接合端部のクラック長さを測定した。接合部にクラックが生じると、その箇所は放熱性が損なわれるため、実使用上放熱性への影響が生じるクラック長さを全長１４ｍｍの１０％である１．４ｍｍとした。そして、クラック長さが１．４ｍｍ以上であれば、耐ヒートサイクル性（表中「耐Ｈ／Ｃ性」）を「×」、１．４ｍｍ以下であれば「○」と評価した。
　その結果、ビスマスの含有率が１ｗｔ％（実施例１）、３ｗｔ％（実施例２）、５ｗｔ％（実施例３）、つまり１～５ｗｔ％の範囲であれば、クラック進展が１．４ｍｍ以下であり良好（○）であった。一方、ビスマス含有率が１ｗｔ％よりも少ない０．５ｗｔ％（比較例１）では、クラックが１．４ｍｍ以上進展していたため「×」となり、５ｗｔ％よりも多い６ｗｔ％（比較例２）でも、クラックが１．４ｍｍ以上進展していたため「×」となった。これは、ビスマス含有率が１～５ｗｔ％の範囲では、銀に添加したビスマスが、銀結晶粒を微細化する役割を果たして、延性が向上したためと考えられる。また、Ａｇ－Ｂｉの合金箔１Ｆに対して接合前にアニール処理を行うことで、圧延時に生じた加工硬化を解消するとともに、さらに銀結晶粒および一部析出したビスマスリッチな析出相の微細分散化を助長し、結晶粒界が増加する事で、粒界すべりを促進し、軟化の促進と延性の向上が図られたのではないかと考えられる。
　代表的な接合材の断面写真を図３に示す。図３において、図３（ａ）はアニール前、図３（ｂ）はアニール後の断面写真である。また、白色の箇所がビスマスリッチな析出相Ｘで、黒色は母材（Ａｇ）の相Ｙである。ビスマスリッチな析出相Ｘの粒径測定には、画像ソフトＩｍａｇｅＪを用いた。具体的には、断面写真を２値化して、ビスマスリッチな析出相Ｘを白色で表示し、その白色部分を囲って、事前に見積もったスケールから面積Ｓを算出する。得られた面積Ｓから下記式に基づき、粒径Ｌを算出した。
　Ｓ＝π×（Ｌ／２）＾２　　　　　　　　　　　　　　　　　　　（１）
　　Ｓ：面積、Ｌ：ビスマスリッチな析出相の粒径　
　Ｌ＝√（４×Ｓ／π）　　　　　　　　　　　　　　　　　　　　（２）
　その結果、ビスマスリッチな析出相Ｘの粒径は、ビスマス含有率が１～５ｗｔ％のとき、アニール前（図３（ａ））は３～８μｍだったのが、アニール後（図３（ｂ））には０．２～１.０μｍとなっており、このことからも上記メカニズムを裏付けていると考えられる。
　ビスマスよりも銀の方が高い熱伝導率を有するので、熱伝導率の観点から考えると、ビスマスを添加しない方が好ましい。しかし、例えば、スズ（Ｓｎ）系、鉛（Ｐｂ）系のはんだ材料の熱伝導率は約５０Ｗ／ｍ・Ｋ程度、純銀の熱伝導率は約４２０Ｗ／ｍ・Ｋである。一方、ビスマスの含有率が１～５ｗｔ％の合金箔１Ｆの熱伝導率を株式会社ベテルにて光交流法で測定したところ、約１５０～３００Ｗ／ｍ・Ｋ程度であり、はんだの約３倍熱伝導率が高く、放熱性に優れた材料であることが確認された。
＜熱処理条件（温度）＞
　次に、アニール処理温度の最適値について検討した。ビスマス含有率が１～５ｗｔ％とした試料合金１Ｒを圧延して合金箔１Ｆとした後、アニール温度をパラメータとし、アニール時間は、上記と同じ４８ｈｒｓに固定して、熱処理を行った。そして、上記と同様のプロセスで８種の評価サンプル１０Ｓ（実施例４～７、比較例４～７）を作製し、ヒートサイクル後の断面観察により、クラック進展度を評価した。その評価結果を表２に示す。
Figure JPOXMLDOC01-appb-T000002
　その結果、アニール温度を１５０℃に設定した実施例４、実施例６、３００℃に設定した実施例５、実施例７の評価結果から、アニール温度が１５０℃～３００℃の範囲では、クラック進展が１．４ｍｍ以下で「○」になった。一方、アニール温度が１５０℃よりも低い１４０℃（比較例４、比較例６）の場合は、Ａｇ－Ｂｉ合金の組織の微細化による軟化が進まず、応力緩和性が低いため、クラックが１．４ｍｍ以上進展しており「×」となった。アニール温度が３００℃よりも高い３２０℃（比較例５、比較例７）の場合は、微細分散効果よりも、熱によってビスマスの結晶粒が粗大化して、粒界すべりを抑制するような働きをしてしまうためか、応力緩和性が低くなり、クラックが１．４ｍｍ以上進展しており「×」となった。この結果、アニール温度には適正値（範囲）があり、ビスマス含有率が１～５ｗｔ％のＡｇ－Ｂｉ合金においては１５０～３００℃が適正値であることが確認された。
＜熱処理条件（時間）＞
　次に、アニール処理時間の最適値について検討した。ビスマス含有率が１～５ｗｔ％とした試料合金１Ｒを圧延して合金箔１Ｆとした後、上述したアニール温度の上限値と下限値のそれぞれで、アニール時間をパラメータとして熱処理を行った。そして、上記と同様のプロセスで１９種の評価サンプル１０Ｓ（実施例８～１９、比較例８～１４）を作製し、ヒートサイクル後の断面観察により、クラック進展度を評価した。その評価結果を表３に示す。
Figure JPOXMLDOC01-appb-T000003
　その結果、アニール温度が１５０または３００℃において、アニール時間を１０ｈｒｓに設定した場合（実施例８、実施例１１、実施例１４、実施例１７）、３０ｈｒｓに設定した場合（実施例９、実施例１２、実施例１５、実施例１８）、１００ｈｒｓに設定した場合（実施例１０、実施例１３、実施例１６、実施例１９）、つまり、アニール時間を１０～１００ｈｒｓの範囲では、クラック進展が１．４ｍｍ以下で「○」になった。アニール処理時間が１０ｈｒｓよりも短い８ｈｒｓに設定した場合（比較例８、比較例９、比較例１０、比較例１１）は、Ａｇ－Ｂｉ合金の組織の微細化による軟化が進まず、応力緩和性が低いため、クラックが１．４ｍｍ以上進展しており「×」となった。
　アニール処理温度が温度範囲の上限である３００℃の場合、上述した時間範囲を超える１２０ｈｒｓ保持すると、応力緩和性が低くなり、クラックが１．４ｍｍ以上進展しており「×」となった。これは、微細分散効果よりも熱によって、ビスマスの結晶粒が粗大化して、粒界すべりを抑制するような働きをしてしまうためと考えられる。なお、温度範囲のうち、３００℃よりも低い温度の場合、保持時間が１００ｈｒｓまでは、耐ヒートサイクル性クラック耐性が「○」となることは確認しているが、それ以上長い時間において、どの程度まで微細分散効果が見られるかは不明である。しかし、量産プロセスにおいてはより短時間での処理が望まれ、１００ｈｒｓ（約４日間）以上のアニール処理だと量産プロセスとしてはタクトの観点で不適である。そのため、１００ｈｒｓまでの処理範囲でクラック耐性が確認できていれば量産上問題はない。この結果、アニール処理時間においては、ビスマス含有率が１～５ｗｔ％のＡｇ－Ｂｉ合金において、１５０～３００℃のアニール処理だと、１０～１００ｈｒｓであれば良好な結果が得られることが確認された。
　接合条件については、主に接合雰囲気、接合温度、加圧、保持時間がパラメータとなる。上述したパラメータ試験においては、接合雰囲気としてギ酸還元雰囲気を用いたが、水素還元雰囲気でも良い。
　接合温度については接合対象の接合面を覆う金属とＡｇ－Ｂｉ合金との間の固相拡散反応を促進する温度であれば良く、パラメータ試験では３００℃としたが、２５０～３００℃の範囲であれば同様の効果が得られる。接合温度を２５０℃よりも低い温度に設定すると、接合面との固相拡散反応が進まないため、良好な接合部が得られない。なお、２５０℃よりも低い温度に設定した場合でも、保持時間を長くすれば、拡散は進行するが、量産プロセスを考えると実用上適用できないと考えられる。
　一方、接合温度を３００℃よりも高い温度に設定すると、ＤＢＣ基板３の導電層３ａ、３ｂを構成する銅の軟化が生じてくる。そのため、３００℃よりも高い接合温度で評価サンプル１０Ｓを作成すると、初期接合部は良好でも、ヒートサイクル試験をかけると、ＤＢＣ基板３に反りが生じるとともに、表面がうねり、凹凸形状になる。すると、接合端部では、ＤＢＣ基板３の反りによってクラックが生じ、接合内部では、ＤＢＣ基板３の凹凸に追随できなくなって、接合面に対して縦方向のクラックが生じてしまう。そのため、接合温度は２５０℃～３００℃が好ましい。
　接合時間については、接合対象の接合面を覆う金属とＡｇ－Ｂｉ合金との間の固相拡散反応が生じる時間であれば良く、上記では１０ｍｉｎとしたが、５ｍｉｎでも良好な接合部が得られている。接合時間は長すぎると量産プロセスでのタクトが長く不利であるため、５～１０ｍｉｎが最適である。
　加圧力は、接合面の平坦性にもよるが、今回評価に使用した電力用半導体素子２の表面平坦性Ｒａはいずれも５０ｎｍ以下であり、評価に使用したＤＢＣ基板３の表面の平坦性Ｒａはいずれも１μｍ以下であった。このような平坦性であれば、Ａｇ－Ｂｉ系の合金箔１Ｆを１０～３０ＭＰａ加圧すれば良好な接合が得られている。なお合金箔１Ｆの表面平坦性Ｒａはいずれも１μｍ以下のものを使用している。
　接合面を覆う金属は、電力用半導体素子２およびＤＢＣ基板３ともに、金、銀、銅のいずれかの組み合わせであれば良好な接合が得られている。なお、スズでも良好な接合部が得られるが、スズは融点が２３０℃程度であり、接合温度２５０～３００℃では溶融してしまう。その場合、スズ中に銀が拡散して、微細な金属間化合物（Ａｇ３Ｓｎ）とともに、融点２２０℃のスズと銀の共晶相（Ｓｎ－３Ａｇ（ｗｔ％））が形成されるので、耐熱性が損なわれるため好ましくない。また、スズ中にビスマスが拡散して、融点１３８℃のスズとビスマスの共晶相（Ｓｎ－５８Ｂｉ（ｗｔ％））が形成されるので、耐熱性が損なわれるため好ましくない。
　なお、スズ表面に接合する必要がある場合、ＳｎとＡｇ―Ｂｉ合金との界面には、融点の低いスズ単独相、あるいはスズと銀の共晶相、スズとビスマスとの共晶相が残らないように十分加熱をする必要がある。そして、界面部分が、少なくともＡｇ３Ｓｎ、Ａｇ５Ｓｎなる金属間化合物で全て形成されるようにする必要がある。
　接合対象に関して、本実施の形態１にかかる電力用半導体装置１００では、電力用半導体素子２とＤＢＣ基板３との接合、あるいは電力用半導体素子２とリード端子４との接合にＡｇ－Ｂｉ合金の接合材１を用いた例を示した。しかし、電力用半導体装置１００には、ＤＢＣ基板３に限らず、通常、回路基板の下に放熱板が設けられており、回路基板と放熱板との接合にも本発明の接合材１を適用することは可能である。
　また、本実施の形態１にかかる電力用半導体装置１００では、スイッチング素子や整流素子として機能する電力用半導体素子２に、炭化ケイ素を用いた例を示したが、これに限ることはなく、従来のシリコン系の素子でも適用できる。しかし、炭化ケイ素や、窒化ガリウム系材料又はダイヤモンドのようにワイドバンドギャップ半導体素子と称される素子を用いた場合、従来から用いられてきたケイ素で形成された素子よりも電力損失が低いため、電力用半導体装置１００の高効率化が可能となる。また、耐電圧性が高く、許容電流密度も高いため、電力用半導体装置１００の小型化が可能となる。さらにワイドバンドギャップ半導体素子は、耐熱性が高いので、高温動作が可能であり、ヒートシンクの放熱フィンの小型化や、水冷部の空冷化も可能となるので、電力用半導体装置１００の一層の小型化が可能になる。
　一方、ワイドバンドギャップ半導体素子の性能を発揮するには、電力用半導体素子２に電流が流れるときの電気抵抗を下げるとともに、電力用半導体素子２で発生した熱を効率よく放熱する必要がある。そのため、本発明の実施の形態に記載したＡｇ－Ｂｉ合金系の接合材１を用いて電力用半導体素子２を実装すれば、放熱特性、電気伝導性にも優れるとともに、製造時や駆動時の熱サイクル下でも強固な接合を維持できるので、信頼性の高い電力用半導体装置１００を得ることができる。
　以上のように、本実施の形態にかかる接合材１によれば、接合対象である金属部材（例えば、電力用半導体素子２の素子電極の表面層２ｆ、ＤＢＣ基板３の導電層３ａの表面層３ｆ）に接触させた状態で加熱することにより、金属部材（例えば、材料として金、銀、銅）の中に固相拡散反応による銀の拡散層Ｌｄ２、Ｌｄ３を形成し、金属部材と接合される、ビスマスと銀の合金で構成された板状の接合材１であって、ビスマスを１質量％以上、５質量％以下含有するように構成したので、弾性率を適度に緩和し、耐熱性と応力緩和性を両立させた接合を得ることができる。
　また、接合材１は、５０μｍ～１００μｍの厚みを有する圧延材であり、厚みを余分に増加させることなく接合体１０を形成でき、小型で高効率な電力用半導体装置１００を容易に製作することができる。また、接合に適した面精度を容易に得ることができる。
　また、本実施の形態にかかる接合方法によれば、接合材１を１５０℃以上、３００以下の温度で熱処理する熱処理工程と、２つの接合対象（例えば、電力用半導体素子２、ＤＢＣ基板３）の間に、熱処理工程を経た接合材１を挟み、接合材１の融点よりも低い温度に加熱して、２つの接合対象のそれぞれに銀の拡散層Ｌｄ２、Ｌｄ３を形成する拡散層形成工程と、を含むようにしたので、応力緩和性に優れ、強固な接合を得ることができる。
　熱処理工程における熱処理時間を１０時間以上、１００時間以下にすれば、応力緩和効果を確実に得ることができる。
　拡散層形成工程における加熱温度が、２５０℃以上、３００℃以下であるので、接合対象を劣化させることなく、強固な接合を得ることができる。
　拡散層形成工程が、還元雰囲気（例えば、水素雰囲気あるいはギ酸雰囲気）で行われるので接合材１や接合対象の接合面に酸化被膜を生じさせることがなく、確実に銀の拡散層Ｌｄ２、Ｌｄ３を形成させることができる。
　また、本実施の形態にかかる電力用半導体装置１００によれば、回路パターン（導電層３ａ）が形成された回路基板（ＤＢＣ基板３）と、回路パターン（導電層３ａ）に接合された電力用半導体素子２と、を備え、電力用半導体素子２と回路パターン（導電層３ａ）とが、本実施の形態にかかる接合方法によって接合されているので、電力用半導体素子２とＤＢＣ基板３との接合は、耐熱性が高く、かつ応力緩和性を備えている。そのため、高温運転やパワーサイクルを繰り返しても、強固な接合を維持し、信頼性の高い電力用半導体装置１００を得ることができる。
　電力用半導体素子２および回路パターン（導電層３ａ）の相対向する面のそれぞれには、金属部材として、金、銀、銅のいずれかによる金属層２ｆ、３ｆが形成されているので、銀の拡散層Ｌｄ２、Ｌｄ３が確実に得られる。
　１：接合材、　１Ｆ：合金箔（接合材）、　２：電力用半導体素子、
　２ｆ：表面層、　３：ＤＢＣ基板（回路基板）、　３ａ：導電層（回路パターン）、
　３ｆ：表面層、　４：リード端子、　５：封止体、　１０：接合体、
　１０Ｓ：評価サンプル、　１００：電力用半導体装置。

Claims (11)

  1. 　接合対象である金属部材に接触させた状態で加熱することにより、前記金属部材の中に固相拡散反応による銀の拡散層を形成し、前記金属部材と接合される、ビスマスと銀の合金で構成された板状の接合材であって、
    　ビスマスを１質量％以上、５質量％以下含有することを特徴とする接合材。
  2. 　前記ビスマスと銀の合金は、ビスマスリッチな相の粒径が、０．２～１.０μｍであることを特徴とする請求項１に記載の接合材。
  3. 　５０μｍ～１００μｍの厚みを有する板材であることを特徴とする請求項１または２に記載の接合材。
  4. 　請求項１から３のいずれか１項に記載の接合材を用いて接合する方法であって、
    　前記接合材を１５０℃以上、３００以下の温度で熱処理する熱処理工程と、
    　２つの接合対象の間に、前記熱処理工程を経た接合材を挟み、前記接合材の融点よりも低い温度に加熱して、前記２つの接合対象のそれぞれに前記銀の拡散層を形成する拡散層形成工程と、
    　を含むことを特徴とする接合方法。
  5. 　前記熱処理の時間が１０時間以上、１００時間以下であることを特徴とする請求項４に記載の接合方法。
  6. 　前記拡散層形成工程における加熱温度が、２５０℃以上、３００℃以下であることを特徴とする請求項４または５に記載の接合方法。
  7. 　前記拡散層形成工程が、還元雰囲気で行われることを特徴とする請求項４から６のいずれか１項に記載の接合方法。
  8. 　回路パターンが形成された回路基板と、
    　前記回路パターンに接合された電力用半導体素子と、を備え、
    　前記電力用半導体素子と前記回路パターンとが、請求項４から７のいずれか１項に記載の接合方法によって接合されていることを特徴とする電力用半導体装置。
  9. 　前記電力用半導体素子および前記回路パターンの相対向する面のそれぞれには、前記金属部材として、金、銀、銅のいずれかによる金属層が形成されていることを特徴とする請求項８に記載の電力用半導体装置。
  10. 　前記電力用半導体素子がワイドバンドギャップ半導体材料により形成されていることを特徴とする請求項８または９に記載の電力用半導体装置。
  11. 　前記ワイドバンドギャップ半導体材料は、炭化ケイ素、窒化ガリウム系材料、およびダイヤモンドのうちのいずれかであることを特徴とする請求項１０に記載の電力用半導体装置。
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