WO2015110027A1 - 像素结构及其制作方法和显示面板 - Google Patents

像素结构及其制作方法和显示面板 Download PDF

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Publication number
WO2015110027A1
WO2015110027A1 PCT/CN2015/071288 CN2015071288W WO2015110027A1 WO 2015110027 A1 WO2015110027 A1 WO 2015110027A1 CN 2015071288 W CN2015071288 W CN 2015071288W WO 2015110027 A1 WO2015110027 A1 WO 2015110027A1
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insulating layer
layer
metal layer
pixel structure
substrate
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PCT/CN2015/071288
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English (en)
French (fr)
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杜鹏
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深圳市华星光电技术有限公司
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Priority to US14/782,192 priority Critical patent/US20160329361A1/en
Publication of WO2015110027A1 publication Critical patent/WO2015110027A1/zh

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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a method for fabricating a pixel structure, a pixel structure, and a display panel.
  • TFT-LCDs thin-film transistor liquid crystal displays
  • the prior art proposes a method of increasing the thickness of the metal layer to effectively reduce the resistance and reduce the load of the signal line.
  • a large step is generated after the metal layer is patterned, which in turn affects.
  • the subsequent layer production especially the problem of subsequent film breakage at the cross-line, seriously reduces the product yield.
  • the pixel electrode of the light transmission area of the existing pixel structure tends to adopt a m-shaped structure, that is, the light transmission area is composed of a plurality of strip-shaped pixel electrodes, each of which has a slit interval, and the slit portion has no electrode. Therefore, the electric field strength is weak, which causes a loss of partial transmittance and lowers the actual quality.
  • the main object of the present invention is to provide a pixel structure, a manufacturing method thereof and a display panel, which are intended to effectively solve the problem of signal delay of a large-sized display panel and improve display quality.
  • the present invention provides a method for fabricating a pixel structure, including the steps of:
  • first insulating layer Forming a planarized first insulating layer on the substrate, the first insulating layer filling a void of the first metal layer and exposing a surface of the first metal layer.
  • the forming a planarized first insulating layer on the substrate comprises:
  • first insulating layer covering the first metal layer on the substrate, the first insulating layer filling Filling a gap of the first metal layer;
  • the first insulating layer is planarized such that the first insulating layer exposes a surface of the first metal layer.
  • the planarizing the first insulating layer comprises:
  • the step of forming a planarized first insulating layer on the substrate further comprises:
  • the groove is elongated and the plurality of grooves are arranged in parallel.
  • the second insulating layer comprises a gate insulating layer and a passivation layer.
  • the present invention also provides a pixel structure disposed on a substrate, including a patterned first metal layer and a planarized first insulating layer formed on the substrate, the first insulating layer filling the first a void of a metal layer and exposing the surface of the first metal layer.
  • the pixel structure has a light transmissive region, and the pixel structure further includes a second insulating layer and a pixel electrode layer, wherein:
  • the second insulating layer is formed on the first insulating layer of the light transmitting region, and the second insulating layer has a plurality of grooves thereon;
  • the pixel electrode layer is a unitary structure, and the whole block covers the second insulating layer.
  • the groove is elongated and the plurality of grooves are arranged in parallel.
  • the present invention also provides a display panel including a substrate and a pixel structure, the pixel structure being disposed on the substrate, the pixel structure including a patterned first metal layer formed on the substrate and planarized a first insulating layer filling a gap of the first metal layer and exposing a surface of the first metal layer.
  • the first insulating layer fills the gap of the first metal layer and exposes the first metal layer, thereby eliminating the The step of a metal layer eliminates the adverse effect on the subsequent layer due to the step difference, so that a first metal layer thicker than the conventional method can be fabricated, thereby effectively reducing the size of the large-sized panel trace. Load, reduce signal line resistance, reduce signal delay, and improve display quality.
  • FIG. 1 is a cross-sectional view showing an embodiment of a pixel structure of the present invention
  • FIG. 2 is a cross-sectional view of a light transmitting region of a pixel structure in the prior art
  • Figure 3 is a cross-sectional view showing a light transmitting region of the pixel structure of the present invention.
  • FIG. 4 is a flow chart showing a first embodiment of a method of fabricating a pixel structure of the present invention
  • FIG. 5 is a specific flowchart of step S103 in Figure 4.
  • FIG. 6 is a schematic structural view showing a patterned first metal layer formed on a substrate in the present invention.
  • FIG. 7 is a schematic structural view showing a first insulating layer and a photoresist layer formed on a substrate in the present invention
  • Figure 8 is a schematic view showing the structure of the pixel structure of Figure 7 after development in the present invention.
  • FIG. 9 is a schematic structural view showing a planarized first insulating layer formed on a substrate in the present invention.
  • FIG. 10 is a flow chart of a second embodiment of a method of fabricating a pixel structure of the present invention.
  • FIG. 11 is a specific flowchart of step S304 in FIG.
  • the pixel structure is disposed on a substrate 10 and includes a patterned first metal (M1) layer 20 sequentially formed on the substrate 10 and planarized.
  • GI gate insulating
  • AS source/drain electrode
  • M2 second metal
  • PAV passivation
  • Passivation Passivation
  • the first metal layer 20 is patterned to have a plurality of voids to form a step, the first insulating layer 30 fills the gap, and exposes the surface of the first metal layer 20, and the surface of the first insulating layer is preferably the first metal The surface of the layer is flush.
  • the first metal layer 20 is formed on the substrate 10 by deposition or the like, and is patterned.
  • the first metal layer 20 may be a metal or an alloy such as Cr, W, Ti, Ta, Mo, etc., and the first metal layer 20 has a thick thickness up to twice or more the thickness of the first metal layer 20 in the ordinary pixel structure. Can effectively reduce the resistance and reduce the signal delay. Since the first metal layer 20 is thick, the patterned first metal layer 20 forms a large step due to the void.
  • the first insulating layer 30 may be a gate insulating (GI) layer, and its composition may be silicon nitride (SiNx), silicon oxide (SiOx), or the like.
  • the first insulating layer 30 is formed on the entire substrate 10 by deposition or the like, covers the entire first metal layer 20, and after being planarized, exposes the surface of the first metal layer 20, and preferably the surface of the first metal layer 20.
  • the flushing eliminates the step difference of the first metal layer 20. Thereby, the adverse effect on the subsequent layer fabrication due to the step difference of the first metal layer 20 is eliminated, so that the first metal layer 20 thicker than the conventional method can be fabricated.
  • the gate insulating layer 40 and the passivation layer 80 constitute a second insulating layer of the light transmission region (right side) of the pixel structure, and the second insulating layer (the gate insulating layer 40 and the passivation layer 80) is formed in the transparent layer
  • the first insulating layer 30 of the light region is provided, and the second insulating layer has a plurality of grooves.
  • the groove is preferably elongated, and the plurality of grooves are parallel to each other and evenly arranged, and finally the second insulating layer has a concave-convex 3D structure as a whole.
  • the pixel electrode layer 90 is a unitary structure, and the whole block is covered on the second insulating layer (the gate insulating layer 40 and the passivation layer 80), and the groove on the second insulating layer is also concave-convex. 3D structure.
  • the material of the pixel electrode layer 90 is preferably a transparent conductive material of indium tin oxide (ITO).
  • FIG. 2 is a cross-sectional view of a light transmissive region of a pixel structure in the prior art
  • FIG. 3 is a cross-sectional view of a light transmissive region of the pixel structure of the present invention.
  • the gate insulating (GI) layer 2 and the passivation (PAV) layer 3 of the light-transmitting region in the prior art completely cover the substrate 1, and the pixel electrode layer 4 is formed on the passivation layer 3 and formed.
  • the stripe pattern, that is, the pixel electrode layer 4 is a plurality of strip electrodes arranged at intervals.
  • the light-transmitting region in the present invention sequentially includes a first insulating layer 30, a second insulating layer (gate insulating layer 40 and passivation layer 80), and a pixel electrode layer 90 formed on the substrate 10, as a whole.
  • the light-transmitting region is entirely covered by the pixel electrode layer 90, and the pixel electrode layer 90 has a stripe-like (or concave-convex) 3D structure along with grooves on the lower second insulating layer (the gate insulating layer 40 and the passivation layer 80).
  • the second insulating layer protrudes from the portion of the pixel electrode layer 90
  • the electric field strength is large and the transmittance is high; the groove portion of the second insulating layer (the gate insulating layer 40 and the passivation layer 80) is still covered by the pixel electrode layer 90, and the electric field intensity of this region is obtained compared with the prior art.
  • a great improvement has been made, thereby increasing the overall transmittance of the pixel structure.
  • the first insulating layer 30 fills the gap of the first metal layer 20 and exposes the first metal layer 20, eliminating the first metal layer 20.
  • the step difference eliminates the adverse effect on the subsequent layer production caused by the step difference, so that the first metal layer 20 thicker than the conventional method can be fabricated, thereby effectively reducing the load of the large-sized panel trace. Reduce signal line resistance and reduce signal delay.
  • a second insulating layer having a concave-convex (or stripe-like) 3D structure is formed on the first insulating layer 30 of the light-transmitting region by using a common photomask without additional cost, so that The pixel electrode layer 90 is entirely covered on the second insulating layer, so that the pixel electrode layer 90 completely covers the light transmitting region, which improves the transmittance of the pixel and ultimately improves the display quality.
  • the method for fabricating the pixel structure includes the following steps:
  • Step S101 forming a patterned first metal layer on the substrate
  • a first metal layer 20 is first formed on the substrate 10 by deposition or the like.
  • the first metal layer 20 may be a metal or an alloy such as Cr, W, Ti, Ta, Mo, etc., of the first metal layer 20
  • the thickness is thicker, up to twice or more the thickness of the first metal layer 20 in the ordinary pixel structure, which can effectively reduce the resistance and reduce the signal delay.
  • the first metal layer 20 is then patterned to finally form a patterned first metal layer 20 as shown in FIG. 6.
  • the patterned first metal layer 20 creates a lot of voids, since the first metal layer 20 is thicker. Therefore, the patterned first metal layer 20 forms a large step.
  • Step S102 forming a first insulating layer covering the first metal layer on the substrate
  • the first insulating layer 30 is formed on the entire substrate 10 by deposition or the like, covering the entire first metal layer 20, and filling the gap of the first metal layer 20.
  • the first insulating layer 30 may be a gate insulating layer, and its composition may be silicon nitride (SiNx), silicon oxide (SiOx), or the like.
  • Step S103 planarizing the first insulating layer to expose the first insulating layer to the surface of the first metal layer 20
  • the first insulating layer 30 is planarized so that the surface of the first insulating layer 30 is flat and the surface of the first metal layer 20 is exposed to eliminate the step difference of the first metal layer 20.
  • the first insulating layer 30 is preferably flush with the surface of the first metal layer 20 (as shown in FIG. 9).
  • the subsequent processes include the steps of sequentially forming the gate insulating layer, the semiconductor layer, the source and drain electrodes, the second metal layer, the passivation layer, and the pixel electrode layer, which are the same as the existing 4mask/5mask fabrication method, and are not described herein again.
  • planarization treatment of the first insulating layer 30 is preferably performed in the flow of FIG. 5, in order to explain the processing process more intuitively, please refer to FIG. 7 to FIG. 9 at the same time, and FIG. 6 to FIG. 9 sequentially show the planarization.
  • Step S201 coating a photoresist layer on the first insulating layer
  • the photoresist (PR, Photo Resist) layer 31 coated in this embodiment is a negative photoresist layer.
  • Step S202 developing with the first metal layer as a photomask, removing the photoresist layer above the first metal layer to expose the first insulating layer
  • Exposure development is performed by the ultraviolet light through the front surface of the substrate 10, and the patterned first metal layer 20 is used as a mask in a self-aligned manner, so that it is not necessary to add an additional mask.
  • the photoresist layer 31 above the first metal layer 20 is removed, the first insulating layer 30 is exposed, and the portion without the first metal layer 20 is still covered by the photoresist layer 31.
  • Step S203 etching the first insulating layer to remove the exposed first insulating layer above the first metal layer to expose the surface of the first metal layer
  • the first insulating layer 30 is dry etched to remove the first insulating layer 30 exposed above the first metal layer 20 to expose the surface of the first metal layer 20. Then, the first insulating layer 30 having no region of the first metal layer 20 is further processed such that the surface of the first insulating layer 30 is flat, and preferably the first insulating layer 30 is flush with the surface of the first metal layer 20. After flattening, it is finally shown in Figure 9.
  • the first insulating layer 30 fills the gap of the patterned first metal layer 20, eliminating the step formed by the patterned first metal layer 20, and eliminating the subsequent layer formation caused by the step difference.
  • the adverse effects are generated, so that the first metal layer 20 thicker than the conventional method can be fabricated, so that the resistance can be effectively reduced and the signal delay can be reduced.
  • the method for fabricating the pixel structure includes the following steps:
  • Step S301 forming a patterned first metal layer on the substrate
  • a first metal layer 20 is first formed on the substrate 10 by deposition or the like.
  • the first metal layer 20 may be a metal or an alloy such as Cr, W, Ti, Ta, Mo, etc., and the first metal layer 20 The thickness is thicker, up to twice or more the thickness of the first metal layer 20 in the ordinary pixel structure, which can effectively reduce the resistance and reduce the signal delay.
  • the first metal layer 20 is patterned to finally form the patterned first metal layer 20 as shown in FIG. 2, and the patterned first metal layer 20 creates a lot of voids, since the first metal layer 20 is thicker. Therefore, the patterned first metal layer 20 forms a large step.
  • Step S302 forming a first insulating layer covering the first metal layer on the substrate
  • the first insulating layer 30 is formed on the entire substrate 10 by deposition or the like, covers the entire first metal layer 20, and fills the gap of the first metal layer 20.
  • the first insulating layer 30 is preferably a gate insulating layer, and its composition may be silicon nitride (SiNx), silicon oxide (SiOx), or the like.
  • Step S303 planarizing the first insulating layer to expose the first insulating layer to the surface of the first metal layer 20
  • the first insulating layer 30 is planarized so that the surface of the first insulating layer 30 is flat and the surface of the first metal layer 20 is exposed to eliminate the step difference of the first metal layer 20.
  • the first insulating layer 30 is preferably flush with the surface of the first metal layer 20.
  • Step S304 forming a second insulating layer having a plurality of grooves on the first insulating layer of the light transmitting region
  • the groove is preferably elongated, and the plurality of grooves are parallel to each other and uniformly arranged on the second insulating layer.
  • the second insulating layer preferably includes a gate insulating (GI) layer 40 and a passivation (PAV) layer 80.
  • GI gate insulating
  • PAV passivation
  • Step S401 forming a gate insulating layer on the first insulating layer
  • the gate insulating layer 40 is formed on the first insulating layer 30.
  • Step S402 forming a semiconductor layer, a source/drain electrode, and a second metal layer on the gate insulating layer of the first metal layer region
  • a semiconductor layer 50, a source/drain electrode 60, and a second metal layer 70 are sequentially formed on the gate insulating layer 40 of the first metal layer 20 region (left side).
  • Step S403 forming a passivation layer on the gate insulating layer
  • the passivation layer 80 covers the semiconductor layer 50, the source and drain electrodes 60, and the second metal layer 70.
  • Step S404 forming a plurality of grooves on the gate insulating layer and the passivation layer of the light transmitting region
  • the gate insulating layer 40 and the passivation layer 80 constitute a second insulating layer, and the gate insulating layer 40 and the blunt process in the second insulating layer are processed by a conventional photomask and dry etching.
  • Layer 80 A plurality of grooves which are elongated and parallel to each other are formed, the grooves exposing the first insulating layer 30, and finally the second insulating layer as a whole has a concave-convex 3D structure.
  • Step S305 forming an integral pixel electrode layer on the second insulating layer
  • the pixel electrode layer 90 is entirely covered on the second insulating layer (the gate insulating layer 40 and the passivation layer 80), and the groove on the second insulating layer is also present. Concave 3D structure.
  • the material of the pixel electrode layer 90 is preferably a transparent conductive material of indium tin oxide (ITO).
  • the light transmitting region is covered by the pixel electrode layer 90 as a whole, when the panel is in operation, the electric field intensity of the pixel electrode layer 90 of the protruding portion of the second insulating layer is large, and the transmittance is high; the groove portion of the second insulating layer still has pixels.
  • the electrode layer 90 is covered, and the electric field intensity of this region is greatly improved compared with the prior art, thereby improving the transmittance of the entire pixel structure.
  • the first insulating layer 30 fills the gap of the first metal layer 20 and exposes the first metal layer 20, eliminating the first The step of the metal layer 20 is eliminated, thereby eliminating the adverse effect on the subsequent layer fabrication caused by the step difference, so that the first metal layer 20 thicker than the conventional method can be fabricated, thereby effectively reducing the large-sized panel trace
  • the load reduces the signal line resistance and reduces the signal delay.
  • a second insulating layer having a concave-convex (or stripe-like) 3D structure is formed on the first insulating layer 30 of the light-transmitting region by using a common photomask without additional cost, so that The pixel electrode layer 90 is entirely covered on the second insulating layer, so that the pixel electrode layer 90 completely covers the light transmitting region, which improves the transmittance of the pixel and ultimately improves the display quality.
  • the present invention also provides a display panel including a substrate and a pixel structure, the pixel structure being disposed on the substrate, including a patterned first metal layer and a planarized first insulating layer formed on the substrate, An insulating layer fills a void of the first metal layer and exposes a surface of the first metal layer.
  • the pixel structure described in this embodiment is the pixel structure involved in the foregoing embodiment of the present invention, and details are not described herein again.
  • the first insulating layer fills the gap of the first metal layer and exposes the first metal layer, thereby eliminating the step difference of the first metal layer, thereby eliminating the step difference.
  • the adverse effect on the subsequent layer production can be made, so that the first metal layer thicker than the conventional method can be made, so that the load of the large-sized panel trace can be effectively reduced.
  • Low signal line resistance reduces signal delay.
  • a second insulating layer having a concave-convex (or stripe-like) 3D structure is formed on the first insulating layer of the light-transmitting region by using a common photomask without additional cost, so that the pixel can be used.
  • the electrode layer is covered on the second insulating layer, so that the pixel electrode layer covers the transparent region, which improves the transmittance of the pixel and ultimately improves the display quality.

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Abstract

一种像素结构及其制作方法和显示面板，像素结构的制作方法包括步骤：在基板（10）上形成一图案化的第一金属层（20）；在基板上形成一平坦化的第一绝缘层（30），第一绝缘层填充第一金属层的空隙，并露出第一金属层表面，从而消除了第一金属层的段差，继而消除了因段差带来的对后续层别的制作产生的不利影响，因此可以制作比传统方法更厚的第一金属层，从而可以有效降低大尺寸面板走线的负载，降低信号线电阻，减小信号延迟，提升显示质量。

Description

像素结构及其制作方法和显示面板 技术领域
本发明涉及液晶显示技术领域，尤其是涉及一种像素结构的制作方法、像素结构及显示面板。
背景技术
目前，大尺寸、高分辨率显示面板已经成为薄膜晶体管液晶显示器(TFT-LCD)的一个发展趋势。然而，随着尺寸的变大，信号线的负载也会增大，从而引起信号延迟，严重影响显示质量。为了解决上述问题，现有技术中提出增加金属层厚度来有效降低电阻、减小信号线负载的方法，但随着金属层厚度增加，金属层图案化后就会产生较大的段差，继而影响后续层别的制作，特别是造成后续薄膜在跨线处发生断线等问题，严重降低产品成品率。
此外，现有像素结构透光区的像素电极往往采用米字形的结构，亦即透光区由很多条状的像素电极组成，每条像素电极之间具有狭缝间隔，由于狭缝部分没有电极，因此电场强度较弱，从而引起部分穿透率的损失，降低了现实质量。
发明内容
本发明的主要目的在于提供一种像素结构及其制作方法和显示面板，旨在有效解决大尺寸显示面板信号延迟问题，提升显示质量。
为达以上目的，本发明提出一种像素结构的制作方法，包括步骤：
在基板上形成一图案化的第一金属层；
在基板上形成一平坦化的第一绝缘层，所述第一绝缘层填充所述第一金属层的空隙，并露出所述第一金属层表面。
优选地，所述在基板上形成一平坦化的第一绝缘层包括：
在基板上形成一覆盖所述第一金属层的第一绝缘层，所述第一绝缘层填 充所述第一金属层的空隙；
平坦化所述第一绝缘层，以使所述第一绝缘层露出所述第一金属层表面。
优选地，所述平坦化所述第一绝缘层包括：
在所述第一绝缘层上涂覆负性光阻层；
以所述第一金属层作为光罩进行显影，除去所述第一金属层上方的负性光阻层以暴露出所述第一绝缘层；
刻蚀所述第一绝缘层，除去所述第一金属层上方暴露出来的第一绝缘层，以露出所述第一金属层表面。
优选地，所述在基板上形成一平坦化的第一绝缘层的步骤之后还包括：
在透光区的第一绝缘层上形成一具有多个凹槽的第二绝缘层；
在所述第二绝缘层上形成一整体的像素电极层，所述像素电极层整块覆盖于所述第二绝缘层。
优选地，所述凹槽呈狭长状，且所述多个凹槽平行排布。
优选地，所述第二绝缘层包括栅绝缘层和钝化层。
本发明同时提出一种像素结构，其配置于一基板上，包括形成于所述基板上的图案化的第一金属层和平坦化的第一绝缘层，所述第一绝缘层填充所述第一金属层的空隙，并露出所述第一金属层表面。
优选地，所述像素结构具有一透光区，所述像素结构还包括第二绝缘层和像素电极层，其中：
所述第二绝缘层形成于所述透光区的第一绝缘层上，且所述第二绝缘层上具有多个凹槽；
所述像素电极层为一整体结构，且整块覆盖于所述第二绝缘层上。
优选地，所述凹槽呈狭长状，且所述多个凹槽平行排布。
本发明同时提出一种显示面板，包括一基板和像素结构，所述像素结构配置于所述基板上，所述像素结构包括形成于所述基板上的图案化的第一金属层和平坦化的第一绝缘层，所述第一绝缘层填充所述第一金属层的空隙，并露出所述第一金属层表面。
本发明所提供的一种像素结构的制作方法，通过形成一平坦化的第一绝缘层，使得第一绝缘层填充第一金属层的空隙并露出第一金属层，消除了第 一金属层的段差，从而消除了因段差而带来的对后续层别的制作产生的不利影响，因此可以制作比传统方法更厚的第一金属层，从而可以有效降低大尺寸面板走线的负载，降低信号线电阻，减小信号延迟，提升显示质量。
附图说明
图1是本发明的像素结构一实施例的剖视图；
图2是现有技术中的像素结构的透光区的剖视图；
图3是本发明的像素结构的透光区的剖视图；
图4是本发明的像素结构的制作方法第一实施例的流程图；
图5是图4中步骤S103的具体流程图；
图6是本发明中在基板上形成图案化的第一金属层后的结构示意图；
图7是本发明中在基板上形成第一绝缘层和光阻层后的结构示意图；
图8是本发明中对图7中的像素结构显影后的结构示意图；
图9是本发明中在基板上形成平坦化的第一绝缘层后的结构示意图；
图10是本发明的像素结构的制作方法第二实施例的流程图；
图11是图10中步骤S304的具体流程图。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
参见图1，提出本发明的像素结构一实施例，所述像素结构配置于一基板10上，包括依次形成于所述基板10上的图案化的第一金属(M1)层20、平坦化的第一绝缘层30、栅绝缘(GI，Gate Insulator)层40、半导体(Semiconductor)层50、源漏电极(AS)60、第二金属(M2)层70、钝化(PAV，Passivation)层80和像素电极层90。
所述第一金属层20进行图案化后具有很多空隙而形成段差，所述第一绝缘层30填充所述空隙，并露出第一金属层20表面，且第一绝缘层表面优选与第一金属层表面平齐。
其中，第一金属层20通过沉积等方式形成于基板10上，并进行图案化处理。该第一金属层20可以是Cr、W、Ti、Ta、Mo等金属或合金，第一金属层20的厚度较厚，可达普通像素结构中的第一金属层20厚度的两倍或以上，可以有效降低电阻，减小信号延迟。由于第一金属层20较厚，因此图案化后的第一金属层20会因空隙而形成较大的段差。
第一绝缘层30可以是栅绝缘(GI，Gate Insulator)层，其成分可以是氮化硅(SiNx)、氧化硅(SiOx)等。第一绝缘层30通过沉积等方式形成于整个基板10上，覆盖整个第一金属层20，并在进行了平坦化处理后，露出第一金属层20表面，并优选与第一金属层20表面平齐，消除了第一金属层20的段差。从而消除了因第一金属层20的段差而带来的对后续层别的制作产生的不利的影响，因此可以制作比传统方法更厚的第一金属层20。
进一步地，所述栅绝缘层40和钝化层80组成像素结构透光区(右侧)的第二绝缘层，所述第二绝缘层(栅绝缘层40和钝化层80)形成于透光区的第一绝缘层30上，且第二绝缘层具有多个凹槽。所述凹槽优选呈狭长状，且多个凹槽相互平行，均匀排布，最终第二绝缘层整体呈凹凸状的3D结构。所述像素电极层90为一整体结构，且整块平铺覆盖于第二绝缘层(栅绝缘层40和钝化层80)上，随着第二绝缘层上的凹槽也呈凹凸状的3D结构。所述像素电极层90的材质优选透明导电材质氧化铟锡(ITO)。
结合参见图2和图3，其中图2为现有技术中的像素结构的透光区的剖视图，图3为本发明的像素结构的透光区的剖视图。从图2中可以看出，现有技术中透光区的栅绝缘(GI)层2和钝化(PAV)层3完全覆盖基板1，像素电极层4形成于钝化层3上，并形成条纹状的图案，即像素电极层4为间隔排布的若干条状电极。在面板正常工作时，有像素电极的地方电场较强，对应的穿透率较高；而各像素电极之间的部分电场强度则较小，穿透率会有一定的损失。
从图3中可以看出，本发明中透光区依次包括形成于基板10上的第一绝缘层30、第二绝缘层(栅绝缘层40和钝化层80)和像素电极层90，整个透光区被像素电极层90整体覆盖，像素电极层90随着下方的第二绝缘层(栅绝缘层40和钝化层80)上的凹槽呈条纹状(或凹凸状)的3D结构。面板工作时，第二绝缘层(栅绝缘层40和钝化层80)凸出部分的像素电极层90的 电场强度较大，穿透率较高；第二绝缘层(栅绝缘层40和钝化层80)凹槽部分依然有像素电极层90覆盖，与现有技术相比，这个区域的电场强度得到了很大的提高，从而提高了像素结构整体的穿透率。
据此，本发明的像素结构，通过形成一平坦化的第一绝缘层30，使得第一绝缘层30填充第一金属层20的空隙并露出第一金属层20，消除了第一金属层20的段差，从而消除了因段差而带来的对后续层别的制作产生的不利影响，因此可以制作比传统方法更厚的第一金属层20，从而可以有效降低大尺寸面板走线的负载，降低信号线电阻，减小信号延迟。
同时，利用上述结构，在不增加额外成本的前提下，利用普通光罩在透光区的第一绝缘层30上形成具有凹凸状(或条纹状)3D结构的第二绝缘层，从而可以将像素电极层90整块平铺覆盖于第二绝缘层上，使得像素电极层90全面覆盖透光区，提高了像素的穿透率，最终提高了显示质量。
结合参见图1、图4、图5，提出本发明的像素结构的制作方法第一实施例，所述像素结构的制作方法包括以下步骤：
步骤S101、在基板上形成一图案化的第一金属层
本步骤S101中，首先在基板10上通过沉积等方式形成一第一金属层20，该第一金属层20可以是Cr、W、Ti、Ta、Mo等金属或合金，第一金属层20的厚度较厚，可达普通像素结构中的第一金属层20厚度的两倍或以上，可以有效降低电阻，减小信号延迟。然后对第一金属层20进行图案化处理，最终形成如图6所示的图案化的第一金属层20，图案化的第一金属层20产生了很多空隙，由于第一金属层20较厚，因此图案化后的第一金属层20会形成较大的段差。
步骤S102、在基板上形成一覆盖第一金属层的第一绝缘层
如图7所示，第一绝缘层30通过沉积等方式形成于整个基板10上，覆盖整个第一金属层20，并填充第一金属层20的空隙。所述第一绝缘层30可以是栅绝缘层，其成分可以是氮化硅(SiNx)、氧化硅(SiOx)等。
步骤S103、平坦化第一绝缘层，以使第一绝缘层露出第一金属层20表面
对第一绝缘层30进行平坦化处理，使得第一绝缘层30表面平整并露出第一金属层20表面，以消除掉第一金属层20的段差。所述第一绝缘层30优选与第一金属层20表面平齐(如图9所示)。
后续流程包括依次形成栅绝缘层、半导体层、源漏电极、第二金属层、钝化层和像素电极层的制作方法和现有的4mask/5mask制作方法相同，在此不再赘述。
其中，对第一绝缘层30的平坦化处理，优选以图5中的流程进行，为了更加直观的说明处理过程，请同时参见图7-图9，图6-图9依次展示了平坦化的第一绝缘层在基板上的形成过程。具体流程如下：
步骤S201、在第一绝缘层上涂覆光阻层
如图7所示，本实施例涂覆的光阻(PR，Photo Resist)层31为负性光阻层。
步骤S202、以第一金属层作为光罩进行显影，除去第一金属层上方的光阻层以暴露出第一绝缘层
利用紫外光通过基板10的本面进行曝光显影，采用自对准方式，利用已经形成的图案化的第一金属层20作为光罩(mask)，因此不需要增加额外的光罩。显影之后，如图8所示，第一金属层20上方的光阻层31被除去，第一绝缘层30暴露出来，而没有第一金属层20的地方仍然被光阻层31覆盖。
步骤S203、刻蚀第一绝缘层，以除去第一金属层上方暴露出来的第一绝缘层，以露出第一金属层表面
对第一绝缘层30进行干刻蚀，除去第一金属层20上方暴露出来的第一绝缘层30，以露出第一金属层20表面。然后，再处理没有第一金属层20区域的第一绝缘层30，使得第一绝缘层30表面平整，优选第一绝缘层30与第一金属层20表面平齐。平坦化后最终如图9所示。
最终，第一绝缘层30填充了图案化后的第一金属层20的间隙，消除了图案化后的第一金属层20形成的段差，消除了因段差而带来的对后续层别的制作产生的不利的影响，因此可以制作比传统方法更厚的第一金属层20，从而可以有效降低电阻，减小信号延迟。
结合参见图1、图10、图11，提出本发明的像素结构的制作方法第二实施例，所述像素结构的制作方法包括以下步骤：
步骤S301、在基板上形成一图案化的第一金属层
本步骤S301中，首先在基板10上通过沉积等方式形成一第一金属层20，该第一金属层20可以是Cr、W、Ti、Ta、Mo等金属或合金，第一金属层20 的厚度较厚，可达普通像素结构中的第一金属层20厚度的两倍或以上，可以有效降低电阻，减小信号延迟。然后对第一金属层20进行图案化处理，最终形成如图2所示的图案化的第一金属层20，图案化的第一金属层20产生了很多空隙，由于第一金属层20较厚，因此图案化后的第一金属层20会形成较大的段差。
步骤S302、在基板上形成一覆盖第一金属层的第一绝缘层
第一绝缘层30通过沉积等方式形成于整个基板10上，覆盖整个第一金属层20，并填充第一金属层20的空隙。所述第一绝缘层30优选栅绝缘层，其成分可以是氮化硅(SiNx)、氧化硅(SiOx)等。
步骤S303、平坦化第一绝缘层，以使第一绝缘层露出第一金属层20表面
对第一绝缘层30进行平坦化处理，使得第一绝缘层30表面平整并露出第一金属层20表面，以消除掉第一金属层20的段差。所述第一绝缘层30优选与第一金属层20表面平齐。
步骤S304、在透光区的第一绝缘层上形成一具有多个凹槽的第二绝缘层
所述凹槽优选呈狭长状，并且多个凹槽之间相互平行，均匀的排布于第二绝缘层上。
所述第二绝缘层优选包括栅绝缘(GI)层40和钝化(PAV)层80，本步骤具体流程如下(参见图11)：
步骤S401、在第一绝缘层上形成栅绝缘层
在基板10上形成平坦化的第一绝缘层30后，再在第一绝缘层30上形成栅绝缘层40。
步骤S402、在第一金属层区域的栅绝缘层上形成半导体层、源漏电极和第二金属层
如图1所示，依次在第一金属层20区域(左侧)的栅绝缘层40上形成半导体层50、源漏电极60和第二金属层70。
步骤S403、在栅绝缘层上形成钝化层
所述钝化层80覆盖半导体层50、源漏电极60和第二金属层70。
步骤S404、在透光区的栅绝缘层和钝化层上形成多个凹槽
在透光区(图1右侧)，所述栅绝缘层40和钝化层80组成第二绝缘层，采用普通光罩和干蚀刻等制程在第二绝缘层中的栅绝缘层40和钝化层80上 形成多个呈狭长状且相互平行的凹槽，所述凹槽露出第一绝缘层30，最终第二绝缘层整体呈凹凸状的3D结构。
在第二绝缘层上形成凹槽后，进入下一步骤：
步骤S305、在第二绝缘层上形成一整体的像素电极层
如图1和图3所示，所述像素电极层90整块平铺覆盖于第二绝缘层(栅绝缘层40和钝化层80)上，随着第二绝缘层上的凹槽也呈凹凸状的3D结构。所述像素电极层90的材质优选透明导电材质氧化铟锡(ITO)。
由于透光区被像素电极层90整体覆盖，面板工作时，第二绝缘层凸出部分的像素电极层90的电场强度较大，穿透率较高；第二绝缘层凹槽部分依然有像素电极层90覆盖，与现有技术相比，这个区域的电场强度得到了很大的提高，从而提高了像素结构整体的穿透率。
据此，本发明的像素结构的制作方法，通过形成一平坦化的第一绝缘层30，使得第一绝缘层30填充第一金属层20的空隙并露出第一金属层20，消除了第一金属层20的段差，从而消除了因段差而带来的对后续层别的制作产生的不利影响，因此可以制作比传统方法更厚的第一金属层20，从而可以有效降低大尺寸面板走线的负载，降低信号线电阻，减小信号延迟。
同时，利用上述结构，在不增加额外成本的前提下，利用普通光罩在透光区的第一绝缘层30上形成具有凹凸状(或条纹状)3D结构的第二绝缘层，从而可以将像素电极层90整块平铺覆盖于第二绝缘层上，使得像素电极层90全面覆盖透光区，提高了像素的穿透率，最终提高了显示质量。
本发明同时提出一种显示面板，包括一基板和像素结构，所述像素结构配置于基板上，包括形成于基板上的图案化的第一金属层和平坦化的第一绝缘层，所述第一绝缘层填充所述第一金属层的空隙，并露出所述第一金属层表面。本实施例中所描述的像素结构为本发明中上述实施例所涉及的像素结构，在此不再赘述。
本发明的显示面板，通过形成一平坦化的第一绝缘层，使得第一绝缘层填充第一金属层的空隙并露出第一金属层，消除了第一金属层的段差，从而消除了因段差而带来的对后续层别的制作产生的不利影响，因此可以制作比传统方法更厚的第一金属层，从而可以有效降低大尺寸面板走线的负载，降 低信号线电阻，减小信号延迟。
同时，利用上述结构，在不增加额外成本的前提下，利用普通光罩在透光区的第一绝缘层上形成具有凹凸状(或条纹状)3D结构的第二绝缘层，从而可以将像素电极层整块平铺覆盖于第二绝缘层上，使得像素电极层全面覆盖透光区，提高了像素的穿透率，最终提高了显示质量。
应当理解的是，以上仅为本发明的优选实施例，不能因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (16)

  1. 一种像素结构的制作方法，其特征在于，包括步骤：
    在基板上形成一图案化的第一金属层；
    在基板上形成一平坦化的第一绝缘层，所述第一绝缘层填充所述第一金属层的空隙，并露出所述第一金属层表面。
  2. 根据权利要求1所述的像素结构的制作方法，其特征在于，所述在基板上形成一平坦化的第一绝缘层包括：
    在基板上形成一覆盖所述第一金属层的第一绝缘层，所述第一绝缘层填充所述第一金属层的空隙；
    平坦化所述第一绝缘层，以使所述第一绝缘层露出所述第一金属层表面。
  3. 根据权利要求2所述的像素结构的制作方法，其特征在于，所述平坦化所述第一绝缘层包括：
    在所述第一绝缘层上涂覆负性光阻层；
    以所述第一金属层作为光罩进行显影，除去所述第一金属层上方的负性光阻层以暴露出所述第一绝缘层；
    刻蚀所述第一绝缘层，除去所述第一金属层上方暴露出来的第一绝缘层，以露出所述第一金属层表面。
  4. 根据权利要求1所述的像素结构的制作方法，其特征在于，所述在基板上形成一平坦化的第一绝缘层的步骤之后还包括：
    在透光区的第一绝缘层上形成一具有多个凹槽的第二绝缘层；
    在所述第二绝缘层上形成一整体的像素电极层，所述像素电极层整块覆盖于所述第二绝缘层。
  5. 根据权利要求4所述的像素结构的制作方法，其特征在于，所述凹槽呈狭长状，且所述多个凹槽平行排布。
  6. 根据权利要求4所述的像素结构的制作方法，其特征在于，所述第二绝缘层包括栅绝缘层和钝化层。
  7. 一种像素结构，其配置于一基板上，其特征在于，包括形成于所述基板上的图案化的第一金属层和平坦化的第一绝缘层，所述第一绝缘层填充所述第一金属层的空隙，并露出所述第一金属层表面。
  8. 根据权利要求7所述的像素结构，其特征在于，所述像素结构具有一透光区，所述像素结构还包括第二绝缘层和像素电极层，其中：
    所述第二绝缘层形成于所述透光区的第一绝缘层上，且所述第二绝缘层上具有多个凹槽；
    所述像素电极层为一整体结构，且整块覆盖于所述第二绝缘层上。
  9. 根据权利要求8所述的像素结构，其特征在于，所述凹槽呈狭长状。
  10. 根据权利要求8所述的像素结构，其特征在于，所述多个凹槽平行排布。
  11. 根据权利要求8所述的像素结构，其特征在于，所述第二绝缘层包括栅绝缘层和钝化层。
  12. 一种显示面板，包括一基板和像素结构，所述像素结构配置于所述基板上，其特征在于，所述像素结构包括形成于所述基板上的图案化的第一金属层和平坦化的第一绝缘层，所述第一绝缘层填充所述第一金属层的空隙，并露出所述第一金属层表面。
  13. 根据权利要求12所述的显示面板，其特征在于，所述像素结构具有一透光区，所述像素结构还包括第二绝缘层和像素电极层，其中：
    所述第二绝缘层形成于所述透光区的第一绝缘层上，且所述第二绝缘层上具有多个凹槽；
    所述像素电极层为一整体结构，且整块覆盖于所述第二绝缘层上。
  14. 根据权利要求13所述的显示面板，其特征在于，所述凹槽呈狭长状。
  15. 根据权利要求13所述的显示面板，其特征在于，所述多个凹槽平行排布。
  16. 根据权利要求13所述的显示面板，其特征在于，所述第二绝缘层包括栅绝缘层和钝化层。
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