WO2015101261A1 - 扫描驱动电路和有机发光显示器 - Google Patents
扫描驱动电路和有机发光显示器 Download PDFInfo
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- WO2015101261A1 WO2015101261A1 PCT/CN2014/095370 CN2014095370W WO2015101261A1 WO 2015101261 A1 WO2015101261 A1 WO 2015101261A1 CN 2014095370 W CN2014095370 W CN 2014095370W WO 2015101261 A1 WO2015101261 A1 WO 2015101261A1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
Definitions
- the present invention relates to the field of scan driving circuits, and in particular to a scan driving circuit and an organic light emitting display applied to a pixel circuit of a scan driving organic light emitting device.
- a conventional organic light emitting display includes a data driver that supplies a data signal to a data line, a first scan driver that sequentially supplies a scan signal to one of the scan lines, a second scan driver that sequentially supplies a scan signal to the other scan line, and a first scan.
- the driver and the second scan driver provide timing controllers for timing signals and high and low level signals, and display units for a plurality of pixels.
- the function of the first scan driver and the second scan driver is to sequentially generate drive signals for the display panel to control the brightness of the pixels in the display panel.
- the voltage value input from the third level terminal is smaller than the voltage value input from the second level terminal.
- the first transistor M1 includes an input terminal connected to the scan signal output terminal OUT or the scan signal input terminal IN of the previous first-stage structure, a gate terminal and an output terminal connected to the first clock terminal CKL1.
- the second transistor M2 includes a gate terminal connected to the output terminal of the first transistor M1, an input terminal connected to the second clock terminal CKL2, and an output terminal connected to the scan signal output terminal OUT.
- the third transistor M3 includes an input terminal connected to the first level terminal VGH, a gate terminal connected to the scan signal output terminal OUT, and an output terminal.
- the fourth transistor M4 includes an input terminal connected to the output terminal of the third transistor M3, a gate terminal connected to the first clock terminal CKL1, and an output terminal connected to the second level terminal VGL1.
- the high level signal is input from the first level terminal VGH (it can be understood that the voltage input by the first level terminal VGH is a positive voltage), the first clock signal is input from the first clock terminal CLK1, and the second clock signal is input from the second clock terminal CLK2.
- the cascade structure of the first scan driver and the second scan driver of the scan driving circuit includes nine transistors, and only two clock signals are used, the number of transistors used in the scan driving circuit can be small, so Improve product reliability while reducing product design and production costs.
- the presence of the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 can make the output of the driving signal output terminal EM of the scan driving circuit more accurate and reliable.
- the clock signal received by the first clock terminal CLK1 (ie, CLK1) is low, the transistors M1, M4, and M7 are both turned on, and the IN is low (capacitor C1 is charged), and the second
- the clock signal received by the clock terminal CLK2 (ie, CLK2) is at a high level, so that the transistor M2 is turned on, and the output scan signal OUT is at a high level; the transistor M7 is turned on and the gate of the transistor M9 is also at a low level, M9 Turn on, EM is low.
- the first low level signal (VGL1) and the second low level signal (VGL2) are the same low level signal, that is, the second low level signal input end VGL2 is connected to the second.
- the level terminal VGL1 is equivalent to the second pole of the ninth transistor M9 being directly connected to the second level terminal VGL1. At this time, the voltage values input by the first low level signal (VGL1) and the second low level signal (VGL2) are the same.
- the voltage value (vgl2) of the second low level signal is higher than the voltage value of the first low level signal ( Vgl1) is small, preferably the voltage value (vgl2) of the second low level signal is smaller than the voltage value (vgl1) of the first low level signal by Vth.
- the output signal EM quickly changes from a low level to a high level by using a voltage jump and a positive feedback across the third capacitor C3.
- the output signal EM quickly changes from a high level to a low level by using a voltage jump and a positive feedback across the third capacitor C3.
- the third capacitor C3 is used as a positive feedback function, so that the output high and low levels are more rapid and stable, so that the load capacity and the high and low level conversion capability of the driving circuit can be improved, and the output high and low levels are closer to the power supply. Level.
- the organic light emitting display further includes a data driver 114 and a timing controller 118.
- the data driver 114 provides data signals to the pixel circuits 112 of the organic light emitting display
- the second scan driver 116 provides scan signals to the pixel circuits 112 of the organic light emitting display.
- the timing controller 118 is the first scan driver 110 and the second scan driver 116.
- the first clock terminal, the second clock terminal, the scan signal input terminal, the first level terminal, the second level terminal, and the third level terminal provide timing signals and high and low level signals, and ELVDD supplies power to the pixel circuits 112 of all the organic light emitting displays. signal.
Abstract
Description
Claims (10)
- 一种扫描驱动电路,其特征在于,包括依次输出选择信号的第一扫描驱动器和依次输出发射信号的第二扫描驱动器,所述第一扫描驱动器包括多个第一级联结构,所述第二扫描驱动器包括多个第二级联结构,所述第一级联结构或/和所述第二级联结构中的每个级联结构包括:第一晶体管,包括与前一级联结构的扫描信号输出端或扫描信号输入端相连的输入端、与第一时钟端连接的栅极端及输出端;第二晶体管,包括与第一晶体管的输出端连接的栅极端、与第二时钟端连接的输入端及与扫描信号输出端连接的输出端;第三晶体管,包括与第一电平端连接的输入端、与扫描信号输出端连接的栅极端及输出端;第四晶体管,包括与第三晶体管的输出端连接的输入端、与第一时钟端连接的栅极端及与第二电平端连接的输出端;第五晶体管,包括与第一电平端连接的输入端、与第三晶体管的输出端连接的栅极端及与扫描信号输出端连接的输出端;第六晶体管,包括与第一电平端连接的输入端、与扫描信号输出端连接的栅极端及输出端;第七晶体管,包括与第六晶体管的输出端端连接的输入端、与第一时钟端连接的栅极端及与第二电平端连接的输出端;第八晶体管,包括与第一电平端连接的输入端、与扫描信号输出端连接的栅极端及与驱动信号输出端连接的输出端;第九晶体管,包括与驱动信号输出端连接的输入端、与第六晶体管的输出端连接的栅极端及与第三电平端连接的输出端;以及连接于第二晶体管的栅极端和输出端之间的第一电容。
- 根据权利要求1所述的扫描驱动电路,其特征在于,所述第一级联结构和所述第二级联结构中的每个级联结构的第一时钟端接收到的信号和第二时钟端接收到的信号的频率一致,当第一时钟端接收到的信号为高电平时第二时钟端接收到的信号为低电平,当第一时钟端接收到的信号为低电平时第二时钟端 接收到的信号为高电平。
- 根据权利要求2所述的扫描驱动电路,其特征在于,所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、和第九晶体管为薄膜场效应晶体管。
- 根据权利要求1所述的扫描驱动电路,其特征在于,所述第一电平端和所述第六晶体管的栅极端之间连接有第二电容。
- 根据权利要求1至4中任一权利要求所述的扫描驱动电路,其特征在于,所述驱动信号输出端和所述第九晶体管的栅极端之间连接有第三电容。
- 根据权利要求1至4中任一权利要求所述的扫描驱动电路,其特征在于,所述第二电平端和所述第九晶体管的栅极端之间连接有第三电容。
- 根据权利要求6所述的扫描驱动电路,其特征在于,所述第三电平端与所述第二电平端为同一电平端。
- 根据权利要求6所述的扫描驱动电路,其特征在于,从所述第三电平端输入的电压值比从所述第二电平端输入的电压值小。
- 根据权利要求6所述的扫描驱动电路,其特征在于,从所述第一电平端输入的电压为高电平,从所述第二电平端和第三电平端输入的电压为低电平。
- 一种有机发光显示器,包括像素电路、数据驱动器和时序控制器,其特征在于,还包括如权利要求1至9中任一权利要求所述的扫描驱动电路,所述时序控制器为所述扫描驱动电路的第一时钟端、第二时钟端、扫描信号输入端、第一电平端、第二电平端和第三电平端提供时序信号和高低电平信号,所述扫描驱动电路的驱动信号输出端和像素电路的驱动信号输入端连接,以输出驱动信号驱动像素电路工作。
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JP2016543693A JP6316437B2 (ja) | 2013-12-30 | 2014-12-29 | 走査駆動回路及び有機発光表示装置 |
KR1020167020703A KR101878380B1 (ko) | 2013-12-30 | 2014-12-29 | 스캐닝 구동 회로와 유기 발광 디스플레이 |
US15/107,676 US10013919B2 (en) | 2013-12-30 | 2014-12-29 | Scanning drive circuit and organic light-emitting display |
EP14876723.9A EP3091532B1 (en) | 2013-12-30 | 2014-12-29 | Scanning drive circuit and organic light-emitting display |
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CN201310744988 | 2013-12-30 | ||
CN201310744988.8 | 2013-12-30 | ||
CN201410464972.6 | 2014-09-12 | ||
CN201410464972.6A CN104183219B (zh) | 2013-12-30 | 2014-09-12 | 扫描驱动电路和有机发光显示器 |
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EP (1) | EP3091532B1 (zh) |
JP (1) | JP6316437B2 (zh) |
KR (1) | KR101878380B1 (zh) |
CN (1) | CN104183219B (zh) |
TW (1) | TWI534781B (zh) |
WO (1) | WO2015101261A1 (zh) |
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US10013919B2 (en) | 2018-07-03 |
TW201528241A (zh) | 2015-07-16 |
TWI534781B (zh) | 2016-05-21 |
KR101878380B1 (ko) | 2018-07-13 |
KR20160104044A (ko) | 2016-09-02 |
JP2017503208A (ja) | 2017-01-26 |
EP3091532A1 (en) | 2016-11-09 |
US20160321999A1 (en) | 2016-11-03 |
EP3091532A4 (en) | 2017-08-30 |
EP3091532B1 (en) | 2020-04-08 |
JP6316437B2 (ja) | 2018-04-25 |
CN104183219A (zh) | 2014-12-03 |
CN104183219B (zh) | 2017-02-15 |
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