1284881 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種使用非晶石夕薄膜電晶體為電路組 成元件之掃描位移電路’該位移電路具有抑制^晶石夕薄膜 電晶體元件臨界電壓位移現象之機制，使其臨界電壓彳立淨多 之程度減缓，進而提高掃描位移電路之穩定性，延長位移 電路的使用時間。 【先前技術】 近年來，薄膜電晶體面板技術不斷地進步，其中包括 可整合於面板上驅動電路之設計。如S0G(system on glass) 技術，可用非晶矽（amorphous silicon ; a-Si)製程與低 溫多晶矽（Low Temperature poly-siiicon ; LTps)製程來 實現’ LTPS TFT與a-Si TFT的最大分別，在於其電性與 製程繁簡的差異。LTPS TFT擁有較高的載子移動率，然: 其製程上卻較繁複；而a-Si TFT則反之，雖然a—Si的載 子移動率不如LTPS，但由於其製程較簡單且成熟，因此在 成本上具有不錯的競爭優勢。 但是，由於製程能力的限制，導致所製造出來的Tft 元件其界電壓值（Vth)會隨著外加偏壓（bias stress) 的影響而逐漸上升，這是a—si TFT無法實現s〇G(system 〇n glass)的重要原因。在習知技術中，使用非晶矽薄膜電晶 ，為組成元件之掃描位移電路，其中有數個非晶矽薄膜電 :體元件會有臨界電壓位移（Vth 之不穩定現象， ^著使用時間的增加，臨界電壓位移的程度會嚴重影響掃 1284881 描位移電路的正常運作，甚至最後掃描位移電路會因此而 失效。 τπ η: 習知美國專利 us 6, 690, 347 「Shift register and liquid crystal display using the samej (Feb. 10, 2004) 有提出一掃描位移電路。請同時參閱「第6、7圖」所示， 係為該專利之位移暫存器電路示意圖與時序圖。該電路 中，電晶體NT2與電晶體NT4只有在輸入端子IN為高位 準狀態（VDD)時及輸出端子〇υτ為高位準狀態（VDD)時 之2個脈衝波（puise)的時間，電晶體NT2與電晶體NT4 的閘-源極電壓VgS2與Vgs4電壓偏壓值才為零，其餘所 有時間電晶體NT2與電晶體NT4的閘-源極電壓Vgs2與 Vgs4電壓偏壓值都為正偏壓’如「第7圖」所示。因此， =晶體NT2與電晶體NT4會因受長時間的正偏壓條件影 響，而產生嚴重之臨界電壓位移現象，如「第8圖」所示， 電曰曰，NT2與NT4之臨界電壓將隨使用時間而逐漸上升。 招金1電NT2與電晶體NT4產生嚴重之臨界電壓位移 列問題：八臨界電壓值會比正常值增大許多，這會產生下 蕤J曾ΐϊ出端子’維持為低位準狀態⑽）時，須 VSS之間保持在低阻2^；使^端子㈣與電源電壓 界雷抗之狀態。然而，當電晶體NT2的臨 其他个斲J曰大，造成輸出端子OUT容易受 面板之驅動發生誤動作。 失真，進而使顯不 128488l 了 2·當輸出端備維持為低位準狀態（vss)時，為 而影缴脈況就CK的南位準信號（VDD)藉由電晶體NT1 維出端子ουτ之低電壓位準（vss)，必須使節點P1 狀熊在低：準狀態（vss)，以確保電晶體NT1是處於截止 體^而Bmpi要維持在低位準狀態（VSS)是藉由電晶 斷你* 2持力導通所達成。然而，當NT4的臨界電壓值不 值^I這會使得節點P1與電源電壓vss之間的阻抗 響而I 、大，造成節點P1容易受其他信號或雜訊之影 :言：法維持在低位準狀態（vss)。因此，時脈訊號CK 出=早準^號（VDD)就可能經由電晶體NT1而影響到輸 插信^Γτ之低電壓位準（vss)，使位移電路所提供之掃 m㈢失真，而使顯示面板之驅動發生誤動作。 【發明内容】 爰是’本發明之主要目的係在加人—能抑制非晶石夕薄 #晶體（a-Si m)元件產生臨界電壓位移現象之電路 ::機，’避免a-Si TFT因臨界電壓位移現象而影響位 移暫存器電路之掃描信號。 —·本發明之另一目的在利用前述之電路動作機制，使 Ματ臨界電壓位移之程度減緩，進而提高掃描位移電 路之穩讀（Stability)，提高a—Si TFT的壽命（Hfe time)，延長位移電路的使用時間。 本發明係應用於使用非晶矽薄膜電晶體為組成元件 4移暫存器，可整合於玻璃基板之掃描驅動電路，其各 階依序串接在一起並將輸出訊號G1、G2、G3、G4···送至面 1284881 板之閘極控制線；其電源有高位準供應電壓與低位準供應 電壓，輸入信號包括第一時脈訊號、第二時脈訊號與啟動 信號。 起始動作係將串接一啟動信號輸入至第一階，其餘各 p白之輸入彳自號是輸入前一階之輸出訊號，且奇數階之位移 暫存器電路之第一時脈端、第二時脈端分別由兩個訊號相 位相反的第一時脈訊號、第二時脈訊號所提供；而該偶數 階之時脈訊號之輸入與奇數階相反，即偶數階之位移暫存 器電路之第一時脈端、第二時脈端分別由上述之第二時脈 訊號、第一時脈訊號所提供；及一接收次一階輸出訊號之 重置端。 ° 本發明之奇數階内部電路，包含一第一電晶體，其閘 極連接輸入端，汲極連接至高位準供應電壓；一第二電晶 ^ ’其閘極連接重置端，源極連接至第―時脈端，汲極與 、「電晶體之源極連接形成一第―節點；—第三電晶體， 、及極與第-節點連接，源極連接至第二時脈端。 第四電日日體，其閘極連接至第一時脈端，汲極連接 第^準供應電壓，源極與第三電晶體之閘極連接形成一 1站，第五電晶體，其閘極連接至第一節點，汲極 Τ至第二節點，源極接入-低位準供應電壓；及一第六 =晶體’其閘極連接至第二時脈端，汲極連接至第一時脈 端，源極連接至第二節點。 第七電a曰體，其閘極連接至第一節點，汲極連接至 寺脈翊源極與本階之輸出端連接；一電容，連接於 1284881 節點與輪出端間；一第八電晶體，其開 :體=接至輸出端’源極接入第二時脈端第二 源極連接至第一時脈端。 輪出鈿 藉此’當相位相反的第一時脈訊號、第二時 ^本發明之位移電路在動作時，第三電晶體、第八電:1 :正=晶體是處於一種正負偏墨交替的驅動條 =負偏壓交替方式可以抑制其臨界位移現象，使電 曰曰體之5s界電壓值不隨使用時間而過度增加。如此，可提 ,；SiTFT,^ :間’同時避免a-Si TFT因臨界電壓位移現象 個位移暫存器電路輸出之掃描信號。 響 【實施方式】 明如=有關本發明之詳細内容及技術說明，現配合圖式說 方塊二1、2圖』所示’係本發明之位移暫存器 ==輸出、入訊號時序圖。如圖所示:係應用於使 用非曰曰石夕溥膜電晶體為組成元件之位移暫存器，可整人於 ，璃基板之掃描驅動電路，其各階依序串接在一起並^輸 、G2、G3、G4···送至面板之閘極控制線；其電源 有回位準供應電壓Vdd與低位準供應電壓Vss，輸入信號 包括兩相位相反之第一時脈訊號CLK、第二時脈訊號⑽ 與啟動信號STV。 階 起始動作係將串接一啟動信號STV輪入至第 1284881 siu ’其餘各階之輸入端IN是輸入前—階之輸出訊號（(ji、 G2、G3、G4…），且奇數階之位移暫存器電路之第一時脈 端CK、第二時脈端CKB分別輸入兩個相位相反的第一時脈 訊號CLK、第二時脈訊號CLKB所提供。而，該偶數階之時 脈訊號之第-時脈端CK改輸人第二時脈訊號⑽，第二 時脈端CKB改輸入第一時脈訊號cu ;及一 輸出訊號提供之重置端RT。 ' 其輸入信號包括第一時脈訊號CLK、第二時脈訊號 CLKB、啟動信號STV與輸出信號（Π、G2、G3、G4之時序 關係圖如「第2圖」所示。 請參閱「第3圖」所示，其第—時脈端CK與第二時 脈端CKB分別由兩個相位相反的第—時脈訊號CLK、第二 時脈§fl5虎CLKB所提供之奇數階内部電路，勹人 -第-電晶體Π’其閘極連接至輪入端=，汲極連 接南位準供應電MVdd;-第二電晶體T2，其閘極連接至 重置端RT ’源極連接至第—時脈端CK，_ 體T1之源極連接形成一第一節點N1 ·— 曰曰 ’—弟三電晶艘Tq， 其汲極與第一節點N1連接，源極連接至第二 極連接面位準供應電壓Vdd，源極與第=|曰 連接形成-第二節點N2 ; 一第五電曰二:曰體们之閘極 至第-節點〜接至第二 準供應電壓Vss’此時因為第五電晶體τ ' 小於第四電晶體Τ4之導通電阻，所以第五電晶通體電：:: 1284881 比第四電晶體T4大’例如具有5:1之尺寸比率 第時脈& CK，源極連接至第二節點Ν2。 一第七電晶體Τ7’其閘極連接至第—節㈣，沒極 連接至第—時脈端CK，源極與輸出端GUT連接；一電容 ci，係連接於該第一節點N1與輸出端〇υτ間。 第八電晶體Τ8 ’其閘極與第二節點Ν2連接，沒極 連接至輸出端_，源極連接至第二時脈端⑽；一第九 電晶體T9’其閘極連接至第二時脈端c〇，汲極連接至輸 出端OUT，源極連接至第一時脈端CK。 而，當上述之電路為偶數階之内部電路時，其時脈訊 號之第一時脈端CK改輸入第二時脈訊號CLKB，第二時脈 端CKB改為輸入第一時脈訊號CLK。 其電路動作原理依下列各端子與節點之脈波階段說 明如I 相’點之電壓變化請參閱「第4圖」所示： :白，a·輸入端ΙΝ之觸發脈波會與第二時脈端⑽的 二二f同相位，即當輸入端⑺產生觸發脈波而為高位 健一 =Vdd)時，第二時脈端CKB為高位準電壓（vdd),而 1V1端以此時則為低位準電壓（Vss)，此時第一節點 VHH诘由低位準供應電壓VSS升高為高位準供應電壓 \ 電晶體T1的臨界電壓Vthl (Vdd_Vthl)，而 輸出=υτ輸出之電壓維持為低位準電壓(vss)。 一雪曰^輸入端IN為高位準電壓（Vdd)之脈波期間，第 曰曰1會因為輸入端IN為高位準電壓⑽）而導 1284881 通；第二電晶體T2會因為重置端RT為低位準電壓（vss) η四電晶㈣會因為第一時脈端CK為低位準電 言立進雷茂第六電晶體τ6會因為第二時脈端⑽為 =i(Vdd)而導通，此時第—時脈端CK為低位準電 3SS)，所以第二節點N2之電壓會由原來的高位準供應 ^塾減去第四電晶體T4的臨界電壓vth4 ( Vdd—v伽） 降低為低位準電壓（Vss)。 同時’因為第二節點呢之電壓為低位準電壓如）， 2三電晶體T3會截止’且由於第三電晶體T3之源極 進带，至第二時脈端⑽’而第二時脈端CKB此時為高位 W壓（Vdd)’所以第三電晶體T3此時之閘_源極電壓 田=)的偏壓條件為一負偏壓（Negative Bias)。相同的， 曰二第一即點N2之電壓為低位準電壓（Vss),所以第八電 :體T8會截止，且由於第八電晶體T8之源極端接至第二 、脈端CKB，而第二時脈端cKB此時為高位準電壓（Vdd)， 所从第八電晶體T8此時之閘—源極電壓（Vgs8)的偏壓條件 為負偏壓（Negative Bias)。 在此同時，因為第一節點N1升高為（vdd-Vthl)，所 以第五電晶體T5、第七電晶體T7會導通，而此時第一時 脈端 CK 為 Low(Vss)。 第九電晶體T9會導通，因為第二時脈端ckb為高位 準電壓（Vdd)，此時第一時脈端CK為低位準電壓（vss)， 所以此時輸出端OUT的電壓仍會維持在低位準電壓 〇ss);而電容C1兩端電壓差為第一節點N1電壓 12 1284881 (Vdd - Vthl)減去輸出端OUT的電壓（VSS)，即為 (Vdd-Vthl-Vss)。 階段b ··當輸入端IN變為低位準電壓（Vss)時， 第一時脈端CKB變為低位準電壓（Vss)，而第—時脈端、 變為咼位準電壓（Vdd)，同時，第一節點N1之電壓合因K 舉升壓（bootstrap)效應由（Vdd-Vthl)再升高為 ㈢自1284881 IX. Description of the invention: [Technical field of the invention] The present invention relates to a scanning displacement circuit using an amorphous slab film transistor as a circuit component. The displacement circuit has a threshold voltage for suppressing a smectite thin film transistor element. The mechanism of the displacement phenomenon slows down the threshold voltage and increases the stability of the scanning displacement circuit and prolongs the use time of the displacement circuit. [Prior Art] In recent years, thin film transistor panel technology has been continuously advanced, including a design that can be integrated into a driver circuit on a panel. For example, S0G (system on glass) technology can be achieved by using amorphous silicon (a-Si) process and low temperature poly-siiicon (LTps) process to achieve the maximum difference between LTPS TFT and a-Si TFT. The difference between its electrical and process complexity. LTPS TFT has a higher carrier mobility, but its process is more complicated; while a-Si TFT is the opposite, although a-Si carrier mobility is not as good as LTPS, but because its process is simple and mature, It has a good competitive advantage in terms of cost. However, due to the limitation of the process capability, the boundary voltage value (Vth) of the fabricated Tft component gradually increases with the influence of the bias stress, which is that the a-si TFT cannot realize s〇G ( System 〇n glass) is an important reason. In the prior art, an amorphous germanium thin film electro-crystal is used as a scanning displacement circuit for a component, in which a plurality of amorphous germanium thin films have a critical voltage displacement (Vth instability, and time of use) Increasing, the degree of critical voltage displacement will seriously affect the normal operation of the sweeping 1284881 displacement circuit, and even the final scanning displacement circuit will be invalidated. τπ η: US patent US 6, 690, 347 "Shift register and liquid crystal display using The samej (Feb. 10, 2004) has proposed a scanning displacement circuit. Please also refer to the "Phase 6 and Figure 7" as shown in the schematic diagram of the displacement register circuit and timing diagram of the patent. In this circuit, the transistor NT2 and transistor NT4 only have two pulse waves when the input terminal IN is in the high level state (VDD) and the output terminal 〇υτ is in the high level state (VDD), and the transistors NT2 and the transistor NT4 The gate-source voltage VgS2 and Vgs4 voltage bias values are zero, and the gate-source voltages Vgs2 and Vgs4 voltage bias values of the transistor NT2 and the transistor NT4 are positively biased as in all other times. 7), therefore, = crystal NT2 and transistor NT4 will be affected by long-term positive bias conditions, resulting in severe threshold voltage shift phenomenon, as shown in Figure 8, eDonkey, NT2 The threshold voltage with NT4 will gradually increase with the use time. Zhaojin 1 power NT2 and transistor NT4 produce severe critical voltage displacement column problem: the eight threshold voltage value will increase much more than the normal value, which will produce the next 蕤J Zeng When the output terminal 'maintains in the low level state (10)), the VSS must be kept at a low resistance 2^; the ^ terminal (4) and the power supply voltage boundary are in a state of being resistant. However, when the other side of the transistor NT2 is large, the output terminal OUT is easily driven by the panel to malfunction. Distortion, and thus the display is not 128488l. 2. When the output device is maintained in the low level state (vss), the south level signal (VDD) of the CK is transmitted by the transistor NT1 to the terminal ουτ. The low voltage level (vss) must make the node P1 bear in the low: quasi-state (vss) to ensure that the transistor NT1 is in the cut-off body and Bmpi is maintained in the low level (VSS) by the electric crystal You* 2 reached through the power. However, when the threshold voltage of NT4 is not worth ^I, the impedance between node P1 and the power supply voltage vss will be louder and larger, causing node P1 to be vulnerable to other signals or noise: Word: Method is maintained at low level Status (vss). Therefore, the clock signal CK out = early quasi-number (VDD) may affect the low voltage level (vss) of the input signal ^ τ via the transistor NT1, so that the sweep circuit provides the m (three) distortion, so that The drive of the display panel has malfunctioned. SUMMARY OF THE INVENTION The main purpose of the present invention is to add a person--a circuit capable of suppressing the occurrence of a threshold voltage shift phenomenon of an amorphous (a-Si m) element:: machine, 'avoiding a-Si TFT The scanning signal of the displacement register circuit is affected by the threshold voltage displacement phenomenon. - Another object of the present invention is to reduce the degree of Ματ threshold voltage displacement by utilizing the aforementioned circuit action mechanism, thereby improving the stability of the scanning displacement circuit, and improving the lifetime of the a-Si TFT (Hfe time). The time of use of the displacement circuit. The invention is applied to the scanning drive circuit which can be integrated into the glass substrate by using the amorphous germanium thin film transistor as the component element shift register, and the steps are serially connected together and the output signals G1, G2, G3, G4 are outputted. ···Send to the gate control line of the 1284881 board; its power supply has a high level of supply voltage and a low level of supply voltage, the input signal includes the first clock signal, the second clock signal and the start signal. The initial action is to input a serial start signal to the first stage, and the remaining input signals of the other white are the output signals of the input first stage, and the first clock end of the odd-order shift register circuit, The second clock end is respectively provided by the first clock signal and the second clock signal with opposite phases of the two signals; and the input of the even-order clock signal is opposite to the odd order, that is, the even-order shift register The first clock end and the second clock end of the circuit are respectively provided by the second clock signal and the first clock signal; and a reset end for receiving the second-order output signal. The odd-numbered internal circuit of the present invention comprises a first transistor having a gate connected to the input terminal and a drain connected to the high level supply voltage; a second transistor 2' having a gate connection reset terminal and a source connection To the first-clock end, the drain is connected to the source of the transistor to form a first node; the third transistor, and the pole is connected to the first node, and the source is connected to the second clock terminal. a four-day solar body, the gate is connected to the first clock terminal, the drain is connected to the first supply voltage, and the source is connected to the gate of the third transistor to form a station, the fifth transistor, and the gate thereof Connected to the first node, the drain is connected to the second node, the source is connected to the low level supply voltage; and a sixth = crystal 'the gate is connected to the second clock terminal, and the drain is connected to the first clock The terminal is connected to the second node. The seventh electric a body is connected to the first node, the drain is connected to the source of the temple, and the output of the current is connected; a capacitor is connected to the 1284881 node. Between the wheel and the wheel; an eighth transistor, its opening: body = connected to the output terminal 'source connected to the second clock end The second source is connected to the first clock end. The wheel is turned out by the first clock signal when the phase is opposite, and the second time is when the displacement circuit of the invention is in operation, the third transistor, the eighth power: 1 : Positive = crystal is in a positive and negative partial ink alternate driving strip = negative bias alternate mode can suppress its critical displacement phenomenon, so that the 5s boundary voltage value of the electric raft does not increase excessively with the use time. So, it can be mentioned that ;SiTFT, ^ : between 'while avoiding a-Si TFT due to the critical voltage displacement phenomenon of the displacement register circuit output of the scan signal. [Embodiment] Mingru = related to the details and technical description of the present invention, now with the map The block diagrams of Figures 2 and 2 are shown as 'displacement register of the present invention==output and input signal timing diagram. As shown in the figure: it is applied to the use of non-stones and cerium films as components. The displacement register can be used for the whole person, the scanning drive circuit of the glass substrate, and the steps are serially connected in series and sent to G2, G3, G4··· to the gate control line of the panel; Returning the quasi-supply voltage Vdd and the low-level supply voltage Vss, the input signal The first clock signal CLK, the second clock signal (10) and the start signal STV are opposite to each other. The order start action is to serially connect the start signal STV to the 1248881 siu 'the rest of the input terminals IN is the input The front-order output signal ((ji, G2, G3, G4...), and the first clock terminal CK and the second clock terminal CKB of the odd-order shift register circuit respectively input the first two opposite phases The clock signal CLK and the second clock signal CLKB are provided. However, the first-time pulse end of the even-order clock signal is changed to the second clock signal (10), and the second clock end CKB is changed to the first input. The clock signal cu; and an output signal provided by the reset terminal RT. 'The input signal includes the first clock signal CLK, the second clock signal CLKB, the start signal STV and the output signal (Π, G2, G3, G4 The timing diagram is shown in Figure 2. Referring to FIG. 3, the first-time clock terminal CK and the second clock-end terminal CKB are respectively provided by two opposite phase first clock signals CLK and second clock §fl5 tiger CLKB. The internal circuit of the step, the first-electrode Π' has its gate connected to the wheel-in terminal=, the drain is connected to the south-level supply MVdd; the second transistor T2, whose gate is connected to the reset terminal RT' The source is connected to the first-clock end CK, and the source of the body T1 is connected to form a first node N1 · - 曰曰 ' - Di three electric crystal boat Tq, the drain is connected to the first node N1, and the source is connected To the second pole connection surface level supply voltage Vdd, the source is connected with the first =|曰 to form a second node N2; a fifth electrode two: the gates of the body are connected to the first node to the second The supply voltage Vss' is at this time because the fifth transistor τ ' is smaller than the on-resistance of the fourth transistor Τ4, so that the fifth electro-optic body is::: 1284881 is larger than the fourth transistor T4, for example, having a size ratio of 5:1 The first clock & CK, the source is connected to the second node Ν2. a seventh transistor Τ7' has its gate connected to the first section (four), a pole is connected to the first-clock terminal CK, and the source is connected to the output terminal GUT; a capacitor ci is connected to the first node N1 and the output End between τ. The eighth transistor Τ8' has its gate connected to the second node Ν2, the fused terminal is connected to the output terminal _, the source is connected to the second clock terminal (10), and the ninth transistor T9' is connected to the second terminal The pulse terminal c〇, the drain is connected to the output terminal OUT, and the source is connected to the first clock terminal CK. When the circuit is an even-numbered internal circuit, the first clock terminal CK of the clock signal is changed to the second clock signal CLKB, and the second clock terminal CKB is input to the first clock signal CLK. The principle of circuit operation depends on the pulse phase of each terminal and node. For example, the voltage change of the I phase 'point is shown in Figure 4: : White, the trigger pulse of the input terminal and the second time The second and second f of the pulse end (10) are in phase, that is, when the input end (7) generates a trigger pulse wave and is high level one = Vdd), the second clock terminal CKB is a high level voltage (vdd), and the 1V1 end is at this time The low level voltage (Vss), at which time the first node VHH 升高 is raised from the low level supply voltage VSS to the high level supply voltage \ the threshold voltage Vthl (Vdd_Vthl) of the transistor T1, and the output = υ τ output voltage is maintained at a low level Voltage (vss). During the pulse period of the input terminal IN being the high level voltage (Vdd), the first 会1 will pass the 1284881 pass because the input terminal IN is the high level voltage (10); the second transistor T2 will be the reset terminal RT. For low level voltage (vss) η four-electrode (4) will be turned on because the first clock terminal CK is low. The sixth transistor τ6 will turn on because the second clock terminal (10) is =i(Vdd). At this time, the first-clock terminal CK is the low-level quasi-electricity 3SS), so the voltage of the second node N2 is reduced from the original high-level supply ^塾 by the threshold voltage vth4 (Vdd-v gamma) of the fourth transistor T4. It is a low level voltage (Vss). At the same time, 'because the voltage of the second node is a low level voltage, for example, 2, the three transistors T3 will be turned off' and because the source of the third transistor T3 is brought into the band, to the second clock terminal (10)' and the second clock The terminal CKB is now the high-order W voltage (Vdd)', so the bias condition of the third transistor T3 at this time is the negative bias (Negative Bias). Similarly, the voltage of the first point N2 is the low level voltage (Vss), so the eighth power: the body T8 will be cut off, and since the source terminal of the eighth transistor T8 is connected to the second, pulse end CKB, The second clock terminal cKB is now a high level voltage (Vdd), and the bias condition of the gate-source voltage (Vgs8) from the eighth transistor T8 is a negative bias (Negative Bias). At the same time, since the first node N1 is raised to (vdd - Vthl), the fifth transistor T5 and the seventh transistor T7 are turned on, and at this time, the first clock terminal CK is Low (Vss). The ninth transistor T9 is turned on because the second clock terminal ckb is a high level voltage (Vdd), and at this time, the first clock terminal CK is a low level voltage (vss), so the voltage at the output terminal OUT is maintained at this time. The low voltage level 〇ss); and the voltage difference across the capacitor C1 is the first node N1 voltage 12 1284881 (Vdd - Vthl) minus the output terminal OUT voltage (VSS), which is (Vdd-Vthl-Vss). Stage b · When the input terminal IN becomes a low level voltage (Vss), the first clock terminal CKB becomes a low level voltage (Vss), and the first clock terminal becomes a 咼 level voltage (Vdd), At the same time, the voltage of the first node N1 is increased from (Vdd-Vthl) to (3) from the (K)-bootstrap effect.
(Vdd-Vthl + Δνρ)，輸出端out輸出之電壓會由低位準電 壓（Vss)升高變為高位準電壓（Vdd)。(Vdd-Vthl + Δνρ), the output voltage of the output terminal out will rise from the low level voltage (Vss) to the high level voltage (Vdd).
因為，此時輸入端IN變為低位準電壓（Vss)，所以第 一電晶體τι會因為輸入端IN為低位準電壓（Vss)而截 止；、第二電晶體T2會因為重置端RT為低位準電壓（Vss) 而截止，第六電晶體T6會因為第二時脈端⑽為低位準 電£ (Vss)而截止，第·四電晶體T4會因為第一時脈端α 〇高位準電壓（Vdd)而導通；而第五電晶體Τ5_為此時 =一卽點Ν1之電壓為⑽一刪+ AVp)而導通，但由於 電μ體T5之元件尺寸W/L會比第四電晶體了4之元件 枚、W/L大很多’因此即使第四電晶體會導通，第二 P占Γ日之電*壓仍會維持在低位準電壓（Vss)狀態。 :時’因為第二節點N2之電壓為低位準電壓㈣， ^ 一電晶體T3、第八電晶體吖 時脈此時為低位準電射',、 ㈣X㈣第一 ,义咕 ^l(Vss)，所以第九電晶體T9會截 止，但第九電晶體T9夕、m J ^ 之源極編接至的第一時脈端CK此時 為馬位準電壓_，所以第九電㈣了9此時之問-源極 13 1284881 電壓（Vgs9)的偏壓條件為負偏壓（NegatiVe Bias)。 因為此階段剛開始時，第一節點N1的初始電壓為 (Vdd-Vthl)，但由於第一電晶體τι、第二電晶體:第 二電晶體Τ3皆為截止狀態，使得第一節點N1此時呈現浮 接狀態（Floating)，再加上第八電晶體T8、第九電晶體 T9也截止，因此，當第一時脈端CK由低位準電壓（yss) 變為高位準電壓（Vdd)時，輸出端OUT輸出之電壓會因為 第七電晶體T7導通而由低位準電壓（Vss)開始升高，同 輸出端OUT電壓之升高會透過電容C1，使第一節點Μ〗的 電壓也升高，而使第七電晶體T7持續保持導通之狀態， 此即為自舉升壓（bootstrap)效應，這可使輪出端〇υτ輪 出之電壓由低位準電壓（Vss)升高至高位準電壓（Vdd) ^Because, at this time, the input terminal IN becomes a low level voltage (Vss), so the first transistor τ1 is turned off because the input terminal IN is a low level voltage (Vss); and the second transistor T2 is because the reset terminal RT is When the low level voltage (Vss) is turned off, the sixth transistor T6 is turned off because the second clock terminal (10) is low (Vss), and the fourth transistor T4 is high because the first clock terminal α is high. The voltage (Vdd) is turned on; and the fifth transistor Τ5_ is turned on at this time = the voltage of one point Ν1 is (10)-cut + AVp), but since the component size W/L of the electric μ body T5 is higher than the fourth The transistor has 4 components and W/L is much larger. Therefore, even if the fourth transistor is turned on, the second P will remain in the low level voltage (Vss) state. : When 'the voltage of the second node N2 is the low level voltage (4), ^ a transistor T3, the eighth transistor 吖 clock is now low level quasi-electricity', (4) X (four) first, 咕 咕 ^l (Vss) Therefore, the ninth transistor T9 will be turned off, but the first clock terminal CK to which the source of the ninth transistor T9 and m J ^ is coupled is now the horse level voltage _, so the ninth power (four) is 9 At this time, the bias condition of the source 13 1284881 voltage (Vgs9) is a negative bias (NegatiVe Bias). Since the initial voltage of the first node N1 is (Vdd-Vthl) at the beginning of this phase, since the first transistor τι, the second transistor: the second transistor Τ3 are all turned off, the first node N1 is The floating state is floated, and the eighth transistor T8 and the ninth transistor T9 are also turned off. Therefore, when the first clock terminal CK is changed from the low level voltage (yss) to the high level voltage (Vdd). When the output voltage of the output terminal OUT is turned on, the low voltage (Vss) starts to rise due to the conduction of the seventh transistor T7, and the voltage of the output terminal OUT rises through the capacitor C1, so that the voltage of the first node is also Raising, and keeping the seventh transistor T7 in a continuous state, this is the bootstrap boosting effect, which can raise the voltage of the wheel-out terminal 〇υτ from the low level voltage (Vss) to the high level. Level voltage (Vdd) ^
而不會有位準之損失。第一節點N1電壓也會升高為 (Vdd-Vthl + AVp)(其中 AVp=〔C1/ (CHCni)〕X (Vdd-Vss)，Cni為第一節點Ni之寄生電容）。 階段c:當第一時脈端CK變為低位準電壓（Vss)， 第二時脈端CKB變為高位準電壓（Vdd)時，且輪入端= 續為低位準電壓（Vss)，此時第一節點N1之電壓會由、 (vdd—vthi+?p)變為低位準電壓(Vss)，輸出端_輸出 之電壓會由南位準電壓（Vdd)降低變為低位準電壓 (V^s)。此時重置端RT之電壓會由次一階輸出端之輸 出峨得到，因為此時次—階之輸出端衝電壓為高位準 電壓⑽）’所以重置端RT會由低位準電壓（VSS)升高變 1284881 為高位準電壓（Vdd)。 第-電低位準電壓（Vss)，所以 m 為重㉔rt升高為高位準電壓 (Vdd)而導通；第四電晶體T4會因為第—時脈端 位準=壓（VS_截止；第六電晶體T6也因為第二時脈端 準電壓(Vdd)而導通’此時第一時脈端CK為低 =電£ Vss) ’所以第二節點N2之電齡轉在低位準 =(，)，而第五電晶體T5、第七電晶體T7會因為此時 第一即點Ν1之電壓為低位準電壓（Vss)而截止。 同時，因為第二節點N2之電壓為低位準電壓（Vss)， 所以第二電晶體T3會截止，且，由於第三電晶體τ3之源 極端接至第二時脈端CKB，而第二時脈端CKB此時為高位 準電壓（Vdd)，所以第三電晶體了3此時之閘-源極電壓 (Vgs3)的偏壓條件為一負偏壓（NegatiVe Bias)。相同的， 因為第二節點N2之電壓為低位準電壓（vss)，所以第八電 晶體T8會截止，且由於第八電晶體T8之源極端接至第二 時脈端CKB，而第二時脈端CKB此時為高位準電壓（Vdd)， 所以第八電晶體T8此時之閘-源極電壓（Vgs8)的偏壓條件 為負偏壓（Negative Bias)。 第九電晶體T9會導通，因為第二時脈端CKB為高位 準電壓（Vdd)，又，第一時脈端CK為低位準電壓（Vss)， 所以此時輸出端OUT的電壓會由高位準電壓（vdd)降低變 為低位準電壓（Vss)。電容C1也因為輸出端OUT的電壓與 15 1284881 第一節點N1之電壓皆為低位準電壓 壓差變為0。 (Vss)，而使其兩端 電 々匕#又d . §第一日π脈端CKB變為低位準電壓（Vss)，而 第：時脈端CK變為高位準電壓(Vdd)時’輸入端IN電壓 ，續為-低位準電壓（Vss)，第一節點N1之電壓將維持為 低位準電壓(Vss)，同時輸出端ουτ輸出之電壓也會維持 為低位準電壓（Vss) ’而重置端RT會由高位準電壓（Vdd) 降低變為低位準電壓（Vss)。 、因為，此階段輸入端IN持續為低位準電壓（Vss)，所 乂第電晶體T1會因為輸入端IN為低位準電壓（Vss)而 戴止，第二電晶體T2也會因為重置端打降低變為低位準 ^壓（vss)而截止；第四電晶體74會因為第—時脈端CK 為向位準電壓⑽）而導通，所以第二節點N2之電壓會由 盔準電壓（Vss)上升至（Vdd_Vth4);第六電晶體T6會因 ”、、一時脈端CKB為低位準電壓（Vss)而截止。 一卽點N2之電壓為（vdd-Vth4)，戶斤以第二θ = τ3、第八電晶體T8會被導通，且由於第三電^ 第^端接至第二時脈端CKB為低位準電壓（Vss)，所^ 電晶：：N1電，維持為低位準電壓(VSS);且由於第 (v二 <源極端接至第二時脈端CKB為低位準電壓 CVss)’所以輸出端0UT輸出 千电铿 (vss);而第五電曰曰辦會維持為低位準電層 -節點m之電壓Z第七電晶體17也會因為此時 之電£為低位準電壓（Vss)而截止。 16 1284881 而第九電晶體T9會因為第二時脈端ckb為低位準電 ^ 而截止，且由於第九電晶體T9源極端接至第一 時脈端CK為高位準電壓（Vdd)， 之間-源極=壓_)的偏壓條件為負偏壓=1 此時 Bias)。電各C1兩端電屋差維持為〇。 階段當第一時脈端心電壓由 電壓⑽）變為低位準電壓（Vss)，而第二時脈端== 變為高位準電壓⑽）時，且輸人端1 電塾 電屋（Vss)，第-郎點N1之電壓將維持為低位準電壓 同=輸出端OUT輸出之電壓也會維持為低 麼（Vss)，重置端RT也會維持在低位準電壓（vss)。 因為，此時輸入端IN電壓持續為低位 所以第-電晶體T1會因為輸人端低電壓（Vss) ’ 而截止；第二電晶體T2也會因為重置 (vf而截止;第四電晶㈣會因為第_時脈二率電壓 位準電壓如）而截止；而第六電晶體Τ6會因=為低 端CKB為南位準電壓⑽)而導通， -:脈 端ck為低位準電壓（Vss)所以第二節點脈 ⑽-觸降低為低位準電壓(Vss)由 第七電晶體Π也會因為第—節點則 ^體T5、 電壓（Vss)而截止。 寬3"維持為低位準 同時’因為第二節點N2之電壓 所以第三電晶體73會 · ^壓（VSS)， 於第二電晶體T3之源極 17 1284881 端接至第二時脈端，而馀一 _ 弟二時脈端CKB此時為高位準 的^條件^第三電晶體T3此時之閘一源極電壓(Vgs3)There will be no loss of position. The voltage at the first node N1 also rises to (Vdd - Vthl + AVp) (where AVp = [C1/ (CHCni)] X (Vdd - Vss), and Cni is the parasitic capacitance of the first node Ni). Stage c: when the first clock terminal CK becomes a low level voltage (Vss), the second clock terminal CKB becomes a high level voltage (Vdd), and the wheel terminal = continues to a low level voltage (Vss), When the voltage of the first node N1 is changed from (vdd_vthi+?p) to a low level voltage (Vss), the voltage of the output terminal_output will be changed from the south level voltage (Vdd) to the low level voltage (V^). s). At this time, the voltage of the reset terminal RT will be obtained from the output 次 of the second-order output terminal, because the output voltage of the secondary-stage is the high level voltage (10))', so the reset terminal RT will be low-level voltage (VSS). The rise becomes 1284881 to a high level voltage (Vdd). The first-electric low level voltage (Vss), so m is 24 volts to rise to a high level voltage (Vdd) and turned on; the fourth transistor T4 will be due to the first-clock end level = pressure (VS_ cutoff; sixth The crystal T6 is also turned on because of the second clock terminal voltage (Vdd) 'At this time, the first clock terminal CK is low = electricity £ Vss) 'so the second node N2 is turned to the low level = (,), The fifth transistor T5 and the seventh transistor T7 are turned off because the voltage of the first point Ν1 is a low level voltage (Vss). Meanwhile, since the voltage of the second node N2 is a low level voltage (Vss), the second transistor T3 is turned off, and since the source terminal of the third transistor τ3 is connected to the second clock terminal CKB, and the second time The pulse terminal CKB is now at a high level voltage (Vdd), so the bias condition of the gate-source voltage (Vgs3) of the third transistor 3 is a negative bias (NegatiVe Bias). Similarly, because the voltage of the second node N2 is a low level voltage (vss), the eighth transistor T8 is turned off, and since the source terminal of the eighth transistor T8 is connected to the second clock terminal CKB, and the second time At this time, the pulse terminal CKB is a high level voltage (Vdd), so the bias condition of the gate-source voltage (Vgs8) of the eighth transistor T8 at this time is a negative bias (Negative Bias). The ninth transistor T9 will be turned on because the second clock terminal CKB is a high level voltage (Vdd), and the first clock terminal CK is a low level voltage (Vss), so the voltage at the output terminal OUT will be high. The quasi-voltage (vdd) decreases to a low level voltage (Vss). Capacitor C1 also has a low level voltage difference of 0 due to the voltage at the output terminal OUT and the voltage at the first node N1 of 15 1284881. (Vss), and its both ends are electrically 々匕#又d. § The first day π pulse end CKB becomes the low level voltage (Vss), and the first: when the clock terminal CK becomes the high level voltage (Vdd) 'input The voltage at the terminal IN continues to be the low-level voltage (Vss). The voltage at the first node N1 will remain at the low level voltage (Vss), and the voltage at the output terminal ουτ will also remain at the low level voltage (Vss). The set terminal RT is changed from a high level voltage (Vdd) to a low level voltage (Vss). Because, at this stage, the input terminal IN continues to be a low level voltage (Vss), and the first transistor T1 is worn because the input terminal IN is a low level voltage (Vss), and the second transistor T2 is also reset because of the reset terminal. The lowering is changed to a lower level (vss) and turned off; the fourth transistor 74 is turned on because the first-clock end CK is a leveling voltage (10), so the voltage of the second node N2 is controlled by the helmet standard voltage ( Vss) rises to (Vdd_Vth4); the sixth transistor T6 is turned off due to ", and the clock terminal CKB is a low level voltage (Vss). The voltage at one point N2 is (vdd-Vth4), and the second is the second. θ = τ3, the eighth transistor T8 is turned on, and since the third terminal is connected to the second clock terminal CKB is a low level voltage (Vss), the transistor: N1 is maintained at a low level. Quasi-voltage (VSS); and since the (v second < source terminal is connected to the second clock terminal CKB is a low level voltage CVss) 'the output terminal OUT outputs kilowatts (vss); Will remain as the low level of the quasi-electrical layer - the voltage of the node m. The seventh transistor 17 will also be cut off because of the low voltage (Vss) at this time. 16 1284881 and the ninth The crystal T9 is turned off because the second clock terminal ckb is low level, and since the source terminal of the ninth transistor T9 is connected to the first clock terminal CK is a high level voltage (Vdd), the source-source = voltage The bias condition of _) is negative bias = 1 at this time Bias). The electric house difference between the two ends of C1 is maintained as 〇. When the first clock center voltage changes from voltage (10)) to low level voltage (Vss) When the second clock terminal == becomes the high level voltage (10)), and the input terminal 1 is electrically connected to the electric house (Vss), the voltage of the first-point N1 will be maintained at the low level voltage and the output terminal OUT output. The voltage will also remain low (Vss), and the reset terminal RT will also remain at the low level voltage (vss). Because the input terminal IN voltage continues to be low at this time, the first transistor T1 will be low due to the input terminal. The voltage (Vss) ' is turned off; the second transistor T2 is also turned off due to reset (vf; the fourth transistor (4) is turned off due to the _clock second rate voltage level voltage); and the sixth transistor Τ6 will be turned on because = low-end CKB is the south-level voltage (10)), -: pulse-side ck is low-level voltage (Vss), so the second node pulse (10)-touch is reduced to low level (Vss) by the seventh transistor Π will also be cut off due to the first node, the body T5, the voltage (Vss). The width 3 " maintains the low level and simultaneously 'because of the voltage of the second node N2, the third transistor 73 will · ^voltage (VSS), the source 17 1284881 of the second transistor T3 is terminated to the second clock terminal, and the second clock terminal CKB is at a high level ^ condition ^ third transistor T3 gate-source voltage (Vgs3)
Bias)〇^^， 二且由於曰準電壓(VSS)’所以第八電晶體T8 曰 ^人電晶體T8之源極端接至第三時脈$ CKB，而第二時脈端CKB此眛 乐于胍麵 、雪曰I* T8 «·吐 時為兩位準電壓（_)，所以第 ⑽)第而九^ ^ Τ9 # _二時脈端G〇為高位準電魔 k，此時第一時脈端以為低位準電壓 所=此時輸出端_的電麗會維持為低 而電容C1兩端電壓差轉為0。 由上述之說明，可以了解本發明電路於單一階移 作原理’本發明電路根據輸 二時脈端 輸出“為輸人端IN之位移（Shi⑴，其各階依 接在，並將輪出訊號G1、G2、G3、α ^mcgate iines), 動信號位移的功能。 囬极所而之驅 此外’由於本發明之位移電路在運作時，配 :時耻第端1、第二時脈端CKB相位相反的第一時::號 了8 /二 ⑽’使第三電晶體T3、第八電晶體 第九電晶體T9是處於正負偏愿交替的驅動條件，如 18 1284881 「第4圖」所示’尤其是第八電晶體T8、第九電晶體T9， 除了在階段b外’其餘各階段兩電晶體是呈現一種相位相 反的正負偏雇父替的驅動樣悲。而不是如美國專利us 6, 690, 347所述，5亥專利電路中電晶體NT2與電晶體NT4 只有2個脈衝波（pulse)的時間，其閘—源極電壓Vgs2 與Vgs4電壓偏壓值才為零，其餘所有時間電晶體NT2與 電晶體NT4之閘-源極電壓Vgs2與Vgs4電壓偏壓值將長 時間維持在正偏壓的狀態，如「第7圖」所示。 所以本發明使第 ^ ％日日菔Μ興弟九 電晶體T9的Vgs偏壓為正負偏屋交替的驅動條件，「藉此 抑制第三電晶㈣、第八電晶體T8、第九電晶體τ9曰之臨 ^電壓位移現象，使其臨界電壓不隨使用時間增加而過度 立曰加，如「第5圖」所示。 (a-Si T n： m)4產纽界電綠移躲以路動 進而=掃描卿電路之穩紐（stabimy)，也可提古’ =i m 的*命⑴fe time)，延μ ^ =避免㈣抓因臨_位移現mu 器電路之掃描信號。 P胃位移暫存 淮上述僅為本發明之較佳 、 本發明實施之範圍。即凡* ’並非用來限定 等變化與修飾，料太 x U利範圍所做的均 白為本發明專利範圍所涵蓋。 19 1284881 【圖式簡單說明】 第1圖，係本發明之位移暫存器方塊圖。 第2圖，係第1圖之各輸出、入訊號時序圖。 第3圖，係本發明之電路示意圖。 第4圖，係第3圖之時序圖。 第5圖，係本發明之電晶體T3、T8及T9之臨界電壓隨使 用時間的變化。 第6圖，係美國專利US 6, 690, 347之電路示意圖。 第7圖，係第6圖之時序圖。 第8圖，係第6圖之電晶體NT2與NT4之臨界電壓隨使用 時間的變化。 【主要元件符號說明】 STV :啟動信號 RT :重置端 CK :第一時脈端 CKB :第二時脈端 CLK :第一時脈訊號 CLKB :第二時脈訊號Bias)〇^^, and because of the voltage (VSS), the source of the eighth transistor T8 人^ human transistor T8 is connected to the third clock $ CKB, and the second clock terminal CKB is happy.胍面,雪曰I* T8 «·Take time is two quasi-voltage (_), so the first (10)) and nine ^ ^ Τ9 # _ two-clock end G〇 is the high level quasi-electric magic k, this time first The clock terminal considers the low level voltage = the current level of the output terminal _ will remain low and the voltage difference across the capacitor C1 will turn to zero. From the above description, it can be understood that the circuit of the present invention is based on a single-order shift principle. The circuit of the present invention outputs "the displacement of the input terminal IN (Shi(1), the respective stages are connected, and the signal G1 is rotated according to the output of the second clock terminal. , G2, G3, α ^mcgate iines), the function of the displacement of the moving signal. In addition, because the displacement circuit of the present invention is in operation, it is equipped with: the first end of the shame and the second phase of the CKB phase. The opposite first time:: number 8 / 2 (10) ' makes the third transistor T3, the eighth transistor ninth transistor T9 is in a driving condition of positive and negative bias alternately, as shown in Fig. 18 1284881 "Fig. 4" 'Especially the eighth transistor T8, the ninth transistor T9, except for the stage b, the other two phases of the two transistors are presented with a phase opposite positive and negative biased by the father. Rather than the time of transistor NT2 and transistor NT4 having only 2 pulse pulses, the gate-source voltage Vgs2 and Vgs4 voltage bias values are as described in U.S. Patent No. 6,690,347. It is zero, and the gate-source voltages Vgs2 and Vgs4 voltage bias values of the transistor NT2 and the transistor NT4 remain at a positive bias for a long time, as shown in Fig. 7. Therefore, the present invention makes the Vgs bias of the first day of the Xingdian Jiudian T9 to be a positive and negative partial housing alternate driving condition, "by which the third electro-crystal (4), the eighth transistor T8, and the ninth transistor are suppressed. The voltage displacement phenomenon of τ9曰 is such that its threshold voltage does not increase excessively with the increase of the use time, as shown in Figure 5. (a-Si T n: m) 4 production of the New Territories electricity green to hide the road to move = scan the stability of the circuit (stabimy), can also mention the ancient ' = im * life (1) fe time), delay μ ^ = Avoid (four) catching the scanning signal of the current-disappearing mu circuit. The P gastric dislocation temporary storage is only preferred of the present invention and the scope of the present invention. That is, where *' is not used to limit changes and modifications, it is covered by the scope of the invention. 19 1284881 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a displacement register of the present invention. Fig. 2 is a timing chart of each output and input signal of Fig. 1. Figure 3 is a schematic diagram of the circuit of the present invention. Figure 4 is a timing diagram of Figure 3. Fig. 5 is a graph showing changes in the threshold voltage of the transistors T3, T8 and T9 of the present invention as a function of time of use. Figure 6 is a schematic diagram of the circuit of U.S. Patent No. 6,690,347. Figure 7 is a timing diagram of Figure 6. Fig. 8 is a graph showing the variation of the threshold voltage of the transistors NT2 and NT4 of Fig. 6 with the use time. [Main component symbol description] STV: Start signal RT: Reset terminal CK: First clock terminal CKB: Second clock terminal CLK: First clock signal CLKB: Second clock signal
Vdd :高位準供應電壓Vdd: high level supply voltage
Vss :低位準供應電壓 IN 輸入端 N1 第一節點 N2 第二節點 20 1284881 ΤΙ ·· 第 一 電 晶 體 Τ2 第 二 電 晶 體 Τ3 第 三 電 晶 體 Τ4 第 四 電 晶 體 Τ5 第 五 電 晶 體 Τ6 第 六 電 晶 體 Τ7 第 七 電 晶 體 Τ8 第 八 電 晶 體 T9 ••第九 電 晶 體Vss: low level supply voltage IN input terminal N1 first node N2 second node 20 1284881 ΤΙ · · first transistor Τ 2 second transistor Τ 3 third transistor Τ 4 fourth transistor Τ 5 fifth transistor Τ 6 sixth Crystal Τ7 seventh transistor Τ8 eighth transistor T9 •• ninth transistor