WO2015098990A1 - 積層型電子部品およびその実装構造体 - Google Patents
積層型電子部品およびその実装構造体 Download PDFInfo
- Publication number
- WO2015098990A1 WO2015098990A1 PCT/JP2014/084199 JP2014084199W WO2015098990A1 WO 2015098990 A1 WO2015098990 A1 WO 2015098990A1 JP 2014084199 W JP2014084199 W JP 2014084199W WO 2015098990 A1 WO2015098990 A1 WO 2015098990A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electronic component
- bonding member
- main body
- multilayer electronic
- pair
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims abstract description 113
- 238000005304 joining Methods 0.000 claims abstract description 92
- 239000003985 ceramic capacitor Substances 0.000 claims description 18
- 238000003475 lamination Methods 0.000 abstract 1
- 238000011156 evaluation Methods 0.000 description 31
- 229910000679 solder Inorganic materials 0.000 description 31
- 238000004088 simulation Methods 0.000 description 27
- 238000012986 modification Methods 0.000 description 26
- 230000004048 modification Effects 0.000 description 26
- 239000000463 material Substances 0.000 description 23
- 239000004020 conductor Substances 0.000 description 17
- 230000000694 effects Effects 0.000 description 11
- 238000007747 plating Methods 0.000 description 7
- 229910017944 Ag—Cu Inorganic materials 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 230000005496 eutectics Effects 0.000 description 5
- 238000005259 measurement Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000004743 Polypropylene Substances 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 4
- 238000005219 brazing Methods 0.000 description 4
- 229920001155 polypropylene Polymers 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 3
- 229910002113 barium titanate Inorganic materials 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 239000005038 ethylene vinyl acetate Substances 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- -1 polypropylene Polymers 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- RNFJDJUURJAICM-UHFFFAOYSA-N 2,2,4,4,6,6-hexaphenoxy-1,3,5-triaza-2$l^{5},4$l^{5},6$l^{5}-triphosphacyclohexa-1,3,5-triene Chemical compound N=1P(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP=1(OC=1C=CC=CC=1)OC1=CC=CC=C1 RNFJDJUURJAICM-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000003063 flame retardant Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002847 impedance measurement Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
- H01G2/02—Mountings
- H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09418—Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10015—Non-printed capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to a multilayer electronic component and its mounting structure.
- Patent Document 1 discloses that a conductive material, which is a propagation medium of capacitor vibration, has a mounting structure that is farthest from the most vibrating portion of the capacitor, so that vibration is less likely to propagate to the circuit board. Yes.
- the present invention has been made in view of the above problems, and an object of the present invention is to provide a multilayer electronic component that can reduce noise when mounted on a substrate and a mounting structure thereof.
- the multilayer electronic component of the present invention includes a laminate in which dielectric layers and internal electrode layers are alternately laminated, and an external electrode provided on the outer surface of the laminate and electrically connected to the internal electrode layer A pair of first surfaces positioned opposite to each other in a stacking direction of the dielectric layer and the internal electrode layer, and It has a second surface and four side surfaces, and the joining member is opposed to the center of at least one of the four sides constituting the first surface and the four sides. It is located in the area
- the multilayer electronic component of the present invention is provided with a laminate in which dielectric layers and internal electrode layers are alternately laminated, and provided on the outer surface of the laminate, and is electrically connected to the internal electrode layer.
- the first side surface has a first side surface and a second side surface, and the side forming the first side surface is a first side, a second side facing the first side, and the first side. And a pair of third sides adjacent to the second side, wherein the joining member is at least one of the first side and a region adjacent to the first side in the first surface.
- the first joining member located in the crab, the second side, and the first surface A second joining member located at least in any of the regions adjacent to the two sides, and adjacent to the center of the first side surface, the pair of third sides, and the third side
- the region to be provided is not provided with the joining member.
- the multilayer electronic component mounting structure of the present invention is formed by joining the joint member of the multilayer electronic component described above to a mounting surface of a substrate, and the first surface or the first side surface of the main body is It faces the mounting surface.
- FIG. 1 illustrates a multilayer electronic component according to a first embodiment, in which (a) is an exploded perspective view, (b) is a perspective view, and (c) is a plan view seen from the first surface side.
- FIG. FIG. 2 is a cross-sectional view taken along line A1-A1 of FIG. 1C, showing a mounting structure in which the multilayer electronic component according to the first embodiment is mounted on a substrate. It is a top view which shows the dimension of each part which looked at the multilayer electronic component in 1st Embodiment from the 1st surface side.
- FIG. 5 is a cross-sectional view taken along line A2-A2 of FIG. 4B, showing a mounting structure in which the multilayer electronic component according to the modification of the first embodiment is mounted on a substrate.
- 2A and 2B show a multilayer electronic component according to a second embodiment, in which FIG. 1A is a perspective view, FIG. 2B is a plan view seen from the first surface side, and FIG. 2C is a dimension of each part seen from the first surface side.
- FIG. 1A is a perspective view
- FIG. 2B is a plan view seen from the first surface side
- FIG. 2C is a dimension of each part seen from the first surface side.
- FIG. 6 shows a mounting structure in which a multilayer electronic component according to a second embodiment is mounted on a substrate, where (a) is a cross-sectional view taken along line A3-A3 of FIG. 6 (b), and (b) is B3 of FIG. 6 (b).
- FIG. The multilayer electronic component in the modification of 2nd Embodiment is shown, (a) is a perspective view, (b) is the top view seen from the 1st surface side, (c) is seen from the 1st surface side. It is a top view which shows the dimension of each part.
- FIGS. 8A and 8B show a mounting structure in which a multilayer electronic component according to a modification of the second embodiment is mounted on a substrate, where FIG.
- FIG. 8A is a cross-sectional view taken along line A4-A4 in FIG. 8B
- FIG. 2 is a sectional view taken along line B4-B4.
- 3A and 3B show a multilayer electronic component according to a third embodiment, in which FIG. 3A is a perspective view
- FIG. 3B is a plan view seen from the first side surface
- FIG. 3C is a dimension of each part seen from the first side surface side.
- FIG. 10 shows a mounting structure in which a multilayer electronic component according to a third embodiment is mounted on a substrate, where (a) is a cross-sectional view taken along line A5-A5 of FIG. 10 (b), and (b) is B5 of FIG. 10 (b).
- FIG. 9 shows a mounting structure in which a multilayer electronic component according to a fourth embodiment is mounted on a substrate, where (a) is a cross-sectional view taken along line A6-C6-D6-A6 ′ of FIG. 12 (b), and (b) is FIG.
- FIG. 6B is a sectional view taken along line B6-B6 in FIG.
- the laminated type electronic component in the modification of 4th Embodiment is shown, (a) is a perspective view, (b) is the top view seen from the 1st surface side, (c) is seen from the 1st surface side. It is a top view which shows the dimension of each part.
- 14 shows a mounting structure in which multilayer electronic components according to a modification of the fourth embodiment are mounted on a substrate, where (a) is a cross-sectional view taken along line A7-C7-D7-A7 ′ of FIG. 14 (b), and (b).
- FIG. 15 is a sectional view taken along line B7-B7 of FIG.
- FIG. 16 shows a mounting structure in which a multilayer electronic component according to a fifth embodiment is mounted on a substrate, where (a) is a sectional view taken along line A8-A8 in FIG. 16 (c), and (b) is B8 in FIG. 16 (c). -B8 sectional view.
- FIG. 18 shows a mounting structure in which a multilayer electronic component according to a sixth embodiment is mounted on a substrate, where (a) is a cross-sectional view taken along line A9-A9 in FIG. 19 (c), and (b) is B9 in FIG.
- FIG. 18 shows a mounting structure in which a multilayer electronic component according to a sixth embodiment is mounted on a substrate, where (a) is a cross-sectional view taken along line A9-A9 in FIG. 19 (c), and (b) is B9 in FIG.
- the conventional multilayer electronic component is shown, (a) is a perspective view, (b) is a plan view seen from the z-axis direction of the coordinate axis, (c) is a mounting structure in which the multilayer electronic component is mounted on a substrate, FIG. 6B is a cross-sectional view taken along line A10-A10 in (b). It is the schematic of the measuring apparatus of a sound pressure level. It is a graph which shows the sound pressure level of the sound of the conventional multilayer ceramic capacitor, Comprising: (a) is a graph which shows the actually measured sound pressure level, (b) is a graph which shows the sound pressure level obtained by simulation.
- the multilayer electronic component according to the first embodiment includes a multilayer body 2 and external electrodes 3 provided on the outer surfaces of both ends thereof. Further, a first joining member 4 and a second joining member 5 are provided. As shown in FIG. 2, the laminate 2 is obtained by alternately laminating dielectric layers 6 and internal electrode layers 7. The internal electrode layer 7 is electrically connected to the external electrode 3 at either one of both end portions of the multilayer body 2. The internal electrode layers 7 are electrically connected to different external electrodes 3 for each layer, and are sandwiched between a pair of internal electrode layers 7 connected to different external electrodes 3 by applying a voltage to the external electrodes 3. A capacitance is generated in the dielectric layer 6.
- the stacking direction of the dielectric layer 6 and the internal electrode layer 7 (hereinafter sometimes simply referred to as the stacking direction) is assumed to coincide with the z-axis direction of the coordinate axis.
- the main body 1 has a rectangular parallelepiped shape as in the conventional multilayer electronic component, and has a pair of first and second surfaces 8 and 9 that face each other in the stacking direction, and four side surfaces. ing.
- first and second surfaces 8 and 9 that face each other in the stacking direction, and four side surfaces. ing.
- the main body 1 is viewed from the first surface 8 side, there are a surface of the rectangular laminate 2 and surfaces of the external electrodes 3 provided at both ends thereof, and the external electrode 3 is a laminate in the y-axis direction.
- the amount of protrusion is sufficiently smaller than the width of the laminate 2 in the y-axis direction.
- the main body 1 having such a shape is assumed to have a rectangular parallelepiped shape.
- FIG. 1C is a plan view of the multilayer electronic component of the present embodiment as viewed from the first surface 8 side.
- FIG. 2 shows the multilayer electronic component of the present embodiment mounted on the substrate 21, and is a cross-sectional view taken along line A1-A1 of FIG. 1 (c).
- the multilayer body 2 is formed by alternately laminating dielectric layers 6 and internal electrode layers 7.
- the structure of the dielectric layer 6 and the internal electrode layer 7 shown in FIG. 2 is a schematic structure, and actually, several to several hundreds of dielectric layers 6 and the internal electrode layer 7 are laminated. Many things are used. The same applies to other examples described later.
- the first joining member 4 is provided over the first side 11 constituting the first surface 8 and the two surfaces adjacent thereto, and the first side 11 It is located in the site
- the second bonding member 5 is provided over the second side 12 constituting the first surface 8 and two adjacent surfaces, includes the center 12c of the second side 12, and includes the vertex V of the main body 1. Located in no part. And the 3rd edge
- the center 11c of the first side 11 is a bisection point that bisects the length of the first side 11, and the center 12c of the second side 12 is the center of the second side 12. This is a bisection point that divides the length into two equal parts.
- the first side 11 and the second side 12 face each other.
- the length of the first side 11 is E1
- the length of the second side 12 is E2
- the length of the third side 13 is E3, E1 ⁇ E3 and E2 ⁇ E3 It is.
- E1, E2, and E3 are all the length of the main body 1 including the external electrode 3.
- L1 is the length of the first joining member 4 in the length direction of the first side 11, and L2 is the second length in the length direction of the second side 12. This is the length of the joining member 5.
- P1 is the length of the first surface 8 in the direction perpendicular to the first side 11 of the first bonding member 4 extending from the first side 11 to the center side of the first surface 8.
- P2 is the length of the first surface 8 in the direction perpendicular to the second side 12 of the second bonding member 5 extending from the second side 12 to the center side of the first surface 8. .
- H0 is the height of the main body 1 in the stacking direction
- H1 is the length of the first bonding member 4 in the stacking direction on the side surface of the main body 1 adjacent to the first surface 8. It is.
- H2 is the length in the stacking direction of the second bonding member 5 on the side surface of the main body 1 adjacent to the first surface 8.
- C is the distance between the mounting surface of the substrate 21 and the main body 1.
- the first bonding member 4 and the second bonding member 5 are formed on the surfaces of the different external electrodes 3 and have electrical conductivity.
- materials for the first bonding member 4 and the second bonding member 5 for example, eutectic solder, brazing material such as lead-free solder (Sn—Ag—Cu), a conductive adhesive, or the like can be used.
- FIG. 4 is a plan view of the multilayer electronic component of Modification 1 as viewed from the first surface 8 side.
- FIG. 5 shows the multilayer electronic component of Modification 1 mounted on the substrate 21, and is a cross-sectional view taken along line A2-A2 of FIG. 4 (b).
- the first joining member 4 is provided on the first surface 8 and in a region adjacent to the first side 11.
- the second bonding member 5 is provided in a region on the first surface 8 and adjacent to the second side 12.
- side which comprises the 1st surface 8 is not provided with the joining member. The range of the area adjacent to the first side 11, the second side 12, and the third side 13 on the first surface 8 will be described later.
- first bonding member 4 and the second bonding member 5 are separated from the first side 11 and the second side 12, respectively. 11 and the second side 12 may be in contact with each other.
- a solder paste may be printed on a predetermined portion of the main body 1, heat-treated at the melting temperature of the solder, and then cooled.
- the solder ball may be bonded to a predetermined portion of the main body 1 using a flux, low melting point solder or the like.
- the solid solder bonded to the main body 1 as the first bonding member 4 and the second bonding member 5 is referred to as a solid solder for convenience regardless of the shape.
- the 1st joining member 4 and the 2nd joining member 5 can be formed by printing on the main body 1 by screen printing etc., and drying and heat-processing. it can.
- the main body 1 and the land pattern 22 on the substrate 21 are connected to the first bonding member 4 and the second bonding. It is joined via the member 5.
- the first surface 8 of the main body 1 and the mounting surface of the substrate 21 face each other.
- the first bonding member 4 and the second bonding member 5 in the present embodiment serve to bond the main body 1 to the substrate 21 and electrically connect the external electrode 3 of the main body 1 and a circuit (not shown) of the substrate 21. Also has a role to connect to.
- the stacked electronic component When the stacked electronic component is mounted on the substrate 21, it may be directly bonded to the land pattern 22 of the substrate 21 by the first bonding member 4 and the second bonding member 5.
- a conductive material such as solder may be applied on the land pattern 22 of the substrate 21, and the multilayer electronic component may be mounted on the substrate 21 through the conductive material.
- a conductive layer 23 such as solder applied on the land pattern 22 is formed between the first bonding member 4 and the second bonding member 5 and the land pattern 22.
- the conductive layer 23 is formed so as to be in contact with the first bonding member 4 and the second bonding member 5 or to cover the first bonding member 4 and the second bonding member 5.
- the conductive layer 23 and the main body 1 are bonded via the first bonding member 4 and the second bonding member 5, and the conductive layer 23 and the main body 1 are not in direct contact.
- the conductive layer 23 and the main body 1 are bonded to each other through the first bonding member 4 and the second bonding member 5, so that the main body 1 is bonded to the land pattern 22 of the substrate 21. It can join in the site
- the conductive material to be used may be the same kind of material as the first bonding member 4 and the second bonding member 5. Although it is preferable, there is no particular limitation as long as the wettability with the first bonding member 4 and the second bonding member 5 is good.
- the conventional multilayer electronic component includes a rectangular parallelepiped laminate 102 and external electrodes 103 provided on the outer surfaces of both ends thereof as shown in FIG.
- FIG. 22B is a plan view seen from the z-axis direction of FIG.
- FIG. 22 (c) shows a conventional multilayer electronic component mounted on the substrate 21, and is a cross-sectional view taken along line A10-A10 of FIG. 22 (b).
- the laminate 102 is obtained by alternately laminating dielectric layers 106 and internal electrode layers 107.
- the internal electrode layer 107 is electrically connected to the external electrode 103 at one of both end portions of the multilayer body 102.
- a multilayer ceramic capacitor which is one of multilayer electronic components uses a ferroelectric material such as barium titanate as the dielectric layer 106 and a metal material such as Ni as the internal electrode layer 107.
- the external electrode 103 is usually made by baking a Cu paste as a base electrode and performing Ni and Sn plating on the surface thereof.
- the external electrode 103 and the land pattern 22 on the substrate 21 are fixed in a state of being electrically connected via the solder 114.
- the solder 114 fills the gap between the external electrode 103 and the land pattern 22 and further covers the external electrode 103 that covers the side surfaces and part of the upper and lower surfaces, which are the end portions of the multilayer body 102. That is, the solder 114 is also provided on the vertex V of the multilayer electronic component.
- the sound produced when a multilayer ceramic capacitor, which is a conventional multilayer electronic component, was mounted on the substrate 21 was measured.
- a 1005 type monolithic ceramic capacitor (capacitance 10 ⁇ F, rated voltage 4 V, hereinafter also referred to as an evaluation part) is used as the monolithic ceramic capacitor, and FR4 (Flame Retardant Type 4) is 100 ⁇ 40 mm and the thickness is 0.8 mm as the substrate 21.
- a glass epoxy substrate made of a material was used.
- the multilayer ceramic capacitor was mounted on the center of the substrate 21 using Sn—Ag—Cu (SAC) solder. After mounting the evaluation component on the substrate 21, the mounting state was observed with a microscope, and it was confirmed that the fillet height of the solder 114 was 460 ⁇ m and the distance C between the substrate 21 and the evaluation component was 45 ⁇ m.
- FIG. 24 shows the sounding measurement results when a DC voltage of 4V (DC bias) and an AC voltage of 20 Hz to 20 kHz and 1 Vp-p are applied to the multilayer ceramic capacitor.
- the sound pressure level is indicated by an A characteristic sound pressure level (dBA).
- a characteristic sound pressure level of 0 dBA corresponds to the lowest sound pressure level that humans can hear as sound.
- the A-weighted sound pressure level is a sound pressure level weighted for each frequency so as to be close to human hearing, and is described in the standard of a sound level meter (sound level meter) (JISC 1509-1: 2005).
- FIG. 26 schematically shows a finite element method model used for impedance simulation. This is a 1/8 model considering symmetry, and the two cross sections appearing on the front surface of FIG. 26 and the lower cross section are symmetry planes.
- Table 1 shows the parameters (elastic stiffness c ij and piezoelectric constant e ij ) of the dielectric layer 106 obtained by the fitting. From Table 1, it can be seen that the material properties of the dielectric layer 106 of the evaluation part have anisotropy (c 11 > c 33 , c 22 > c 33 ). This is considered due to the compressive stress caused by the internal electrode layer 107.
- FIG. 24B is a graph showing the result of converting the vibration amplitude of the mounting board 31 obtained by the simulation into an A characteristic sound pressure level. Since the frequency characteristic of the sound depends on the vibration characteristic of the evaluation component and the resonance mode of the mounting substrate 31, the simulation results shown in FIG. 24B show that the sound pressure is particularly low in a low frequency region of 10 kHz or less. Both the sound pressure level and the frequency characteristics were in good agreement with the measured values shown in FIG. Therefore, by performing a simulation using this parameter, it is possible to confirm the effect of the mounting structure on the sound produced when the mounting structure is changed.
- FIG. 27A is a view from the inside (symmetry plane side) of the 1/8 model
- FIG. 27B is the opposite side of FIG. 27A, that is, the outside of the 1/8 model. Viewed from the side (surface side).
- the broken line indicates the shape of the evaluation component in a state where no AC voltage is applied
- the solid line indicates the shape of the evaluation component that is displaced to the maximum by the AC voltage. From this result, as shown in FIG.
- the vibration amplitude is at the center of each side constituting the surface. It can be seen that there is a small region 24 (hereinafter referred to as a nodal portion) that can be said to be a vibration node. Since the main body 1 of the present embodiment is equivalent to the evaluation part, such a node-like portion 24 exists in the main body 1 of the present embodiment as well as the evaluation part. Therefore, by fixing the main body 1 to the substrate 21 in the node-like portion 24, it is considered that the propagation of the piezoelectric vibration of the main body 1 to the substrate 21 is suppressed and the noise can be reduced.
- the body 1 since the first joining member 4 and the second joining member 5 are provided in such a node-like portion 24 existing in the body 1, the body 1 is attached to the substrate 21 in the node-like portion 24. It can be fixed.
- Modification 1 in which the first bonding member 4 and the second bonding member 5 are provided only on the first surface 8, when the multilayer electronic component is bonded to the substrate 21, The protrusion of the bonding material (the first bonding member 4, the second bonding member 5, and the solder used for bonding) is reduced, and the mounting density of the multilayer electronic component can be improved.
- the simulation of sound generation was performed using the following models of the first embodiment and the first modification.
- L1 and L2 are both 310 ⁇ m
- P1 and P2 are both 142 ⁇ m
- H1 and H2 in the first embodiment are both 78 ⁇ m.
- C in the mounting structure was 140 ⁇ m.
- Other conditions related to the main body 1 were the same as those of the simulation of sound generation in the evaluation part described above.
- the average value of the sound pressure level in this embodiment is reduced by 13 dBA in the first embodiment compared to the above-described evaluation component, that is, the conventional mounting structure.
- the result was reduced by 15 dBA.
- L1 and L2 are set to 0.5 (L1 / E1, L2 / E2) with respect to E1 and E2 (620 ⁇ m), respectively. Even if the sound pressure level is 8, the sound pressure level can be reduced by about 10 dBA.
- L1 / E1 and L2 / E2 are preferably 0.4 or more from the viewpoint of mountability.
- the vibration amplitude is large near the center of each surface constituting the evaluation part and near the center of the side where the side surfaces are in contact with each other. Therefore, it is preferable not to provide the first bonding member 4 and the second bonding member 5 in the vicinity of the center of each surface of the main body 1 and in the vicinity of the center of the side where the side surfaces contact each other.
- the ratio of H1 to H0 (H1 / H0) and the ratio of H2 to H0 (H2 / H0) are both preferably 0.4 or less.
- P1 and P2 are 0.25 or less in the ratio (P1 / E3, P2 / E3) to E3.
- the region adjacent to the first side is a region whose distance from the first side 11 is not more than 0.25 times E3.
- the region adjacent to the second side 12 is a region whose distance from the second side 12 is not more than 0.25 times E3.
- the region adjacent to the third side 13 is a region whose distance from the third side 13 is less than 0.1 times E1 or E2.
- the first joining member 4 and the second joining member 5 are in the region adjacent to the first side 11 and the region adjacent to the second side 12, respectively, and the third side 13 It is provided in the site
- the main body 1 is not in direct contact with the mounting surface of the substrate 21.
- the ratio of C to H0 (C / H0), which is the distance between the main body 1 and the mounting surface of the substrate 21, is preferably 0.1 or more.
- the multilayer electronic component including the first bonding member 4 and the second bonding member 5 on the main body 1 has been described as being mounted on the substrate 21. Even when the first joining member 4 and the second joining member 5 and the other joining members are not provided, the main body 1 mounted on the substrate 21 is the first joining member 4 and the second joining described above. Any component that is bonded to the substrate 21 at the site where the member 5 is to be provided is included in the mounting structure of the present embodiment.
- the conductive layer 23 such as solder for joining the main body 1 to the substrate 21 corresponds to the first joining member 4 and the second joining member 5.
- a multilayer ceramic capacitor using a ferroelectric material such as barium titanate for the dielectric layer and a metal material such as Ni, Cu, Ag, or Ag—Pd for the internal electrode layer is used as the main body 1.
- a ferroelectric material such as barium titanate for the dielectric layer
- a metal material such as Ni, Cu, Ag, or Ag—Pd for the internal electrode layer
- it is particularly preferably used.
- the present embodiment can exert a remarkable effect particularly in a multilayer electronic component of a 1005 type or more type.
- the form of the main body 1 in this embodiment is essentially the same as that of a conventional multilayer electronic component, and it is not necessary to change the design greatly. Therefore, the present embodiment can be applied to various existing multilayer electronic components. There is also an advantage that no special jig is required for mounting on the substrate.
- a multilayer ceramic capacitor having a general structure having the external electrodes 3 at both ends in the longitudinal direction has been described as an example of the main body 1.
- a thin type a so-called LW reverse type, multi-terminal
- a multilayer electronic component having various structures such as a mold can be applied as the main body 1.
- the first joining member 4 and the second joining member 5 having insulating properties as will be described later.
- many multilayer ceramic capacitors use an external electrode 3 in which a base electrode made of Cu is plated with Ni and Sn.
- the external electrode is composed of only a plated electrode without using the base electrode.
- the present invention can also be suitably applied to those having the electrode 3.
- the external electrode 3 having the base electrode is directly bonded to the land pattern 22 of the substrate 21 via solder or the like, so the base electrode made of Cu is relatively soft, so the base electrode absorbs the piezoelectric vibration of the laminate 2 to some extent. Attenuates and suppresses noise.
- the external electrode 3 is composed only of a plating electrode, the piezoelectric vibration of the multilayer body 2 is not attenuated by the external electrode 3 and the sounding becomes noticeable. Therefore, when this embodiment is applied to what has the external electrode 3 comprised only by the plating electrode, the bigger noise reduction effect is acquired.
- the Sn plating of the external electrode 3 has a role of improving the wettability between the external electrode 3 and the solder when the multilayer electronic component is mounted on the substrate 21.
- the main body 1 is the first. Since it joins with the land pattern 22 of the board
- the first bonding member 4 and the second bonding member 5 are not only on the first surface 8 side of the main body 1 but also on the side opposite to the first surface 8. It can also be provided on the second surface 9 side. In other words, both of the pair of first surface 8 and second surface 9 that face each other in the stacking direction are configured by the first side 11, the second side 12, and the third side 13. As described above, a plurality of first joining members 4 and a plurality of second joining members 5 can be provided on the main body 1.
- first joining member 4 and the second joining member 5 may be insulative.
- the external electrode 3 may be electrically connected to the electric circuit of the substrate 21 by wire bonding or the like.
- thermoplastic resins such as ethylene vinyl acetate (EVA) and polypropylene (PP) are suitable.
- the first bonding member 4 and the second bonding member 5 are provided on the first surface 8 side of the main body 1.
- the difference from the first embodiment is that, as shown in FIG. 6C, the length E1 of the first side 11 provided with the first bonding member 4 and the second bonding member 5 are provided.
- the relational expressions E3 ⁇ E1 and E3 ⁇ E2 are satisfied.
- 7 shows the multilayer electronic component of the present embodiment mounted on the substrate 21, FIG. 7 (a) is a cross-sectional view taken along line A3-A3 of FIG. 6 (b), and FIG. 7 (b) is FIG. 6 (b).
- FIG. 3 is a sectional view taken along line B3-B3.
- first bonding member 4 and the second bonding member 5 are formed on the surface of the laminate 2 so as to be separated from the external electrode 3, and both have electrical conductivity.
- a pair of conductors 25 is further formed on the surface of the laminate 2.
- One conductor 25 electrically joins the first joining member 4 and one external electrode 3, and the other conductor 25. Electrically joins the second joining member 5 and the other external electrode 3.
- the conductor 25 is formed by, for example, plating or conductive paste.
- a brazing material such as eutectic solder, lead-free solder (Sn—Ag—Cu), and conductive adhesive Etc. can be used.
- FIG. 8 is a plan view of the multilayer electronic component of Modification 2 as viewed from the first surface 8 side.
- FIG. 9 shows a multilayer electronic component of Modification 2 mounted on the substrate 21.
- FIG. 9A is a cross-sectional view taken along line A4-A4 of FIG. 8B
- FIG. 9B is FIG. It is B4-B4 sectional view taken on the line of b).
- first bonding member 4 and the second bonding member 5 are separated from the first side 11 and the second side 12, respectively. 11 and the second side 12 may be in contact with each other.
- the mounting structure of the multilayer electronic component of the present embodiment includes the main body 1 and the land pattern 22 on the substrate 21 as shown in FIG.
- the first surface 8 and the mounting surface of the substrate 21 are bonded through the second bonding member 5 so as to face each other.
- the first bonding member 4 and the second bonding member 5 serve to bond the main body 1 to the substrate 21 and to connect the external electrode 3 of the main body 1 and a circuit (not shown) of the substrate 21. It also plays the role of electrical connection.
- a sounding simulation was performed using the following model.
- L1 and L2 are both 220 ⁇ m
- P1 and P2 are both 142 ⁇ m.
- H1 and H2 are both 78 ⁇ m.
- C in the mounting structure of the present embodiment was 140 ⁇ m.
- Other conditions related to the main body 1 were the same as those of the above-described sound simulation of the evaluation component.
- the average value of the sound pressure level in this embodiment is reduced by 20 dBA in the second embodiment compared to the conventional mounting structure, and is reduced by 22 dBA in the second modification.
- the sound reduction effect is greater than the simulation result of the first embodiment. This is because the first bonding member 4 and the second bonding member 5 of the main body 1 are provided because the distance between the first bonding member 4 and the second bonding member 5 is smaller than that in the first embodiment. It is considered that the propagation of the piezoelectric vibration of the main body 1 to the substrate 21 is further suppressed as a result of the difference in vibration displacement at the obtained portion being smaller than in the case of the first embodiment.
- L1 and L2 (220 ⁇ m) are set to 0.2 (L1 / E1, L2 / E2) with respect to E1 and E2 (1100 ⁇ m).
- L1 / E1 and L2 / E2 are preferably 0.1 to 0.5, and more preferably 0.4 to 0.5, from the viewpoint of mountability.
- the thickness T1 of the first bonding member 4 and the second bonding member 5 on the first surface 8 side is important.
- the external electrode 3 normally protrudes outside the multilayer body 2 from each surface constituting the multilayer body 2. Therefore, on the first surface 8 side, it is preferable to make the thickness T1 of the first bonding member 4 and the second bonding member 5 thicker than the thickness T0 of the protruding portion of the external electrode 3.
- H1, H2, P1, P2, and C are preferably in the same range as in the first embodiment.
- first bonding member 4 and the second bonding member 5 are formed on the surface of the multilayer body 2 so as to be separated from the external electrode 3, and are electrically connected to the different external electrodes 3 by the conductor 25.
- first bonding member 4 and the second bonding member 5 may be directly connected to different external electrodes 3 and separated only from the other external electrode 3.
- the third embodiment has a rectangular parallelepiped main body 1 similar to the first embodiment, and is perpendicular to the stacking direction of the dielectric layer 6 and the internal electrode layer 7 as shown in FIGS.
- the 1st junction member 4 and the 2nd junction member 5 are each provided in the 1st side 10 which uses the 1st edge 11 and the 2nd edge 16 as a component.
- the first side 11 is the side where the first side surface 10 and the first surface 8 are in contact
- the second side 16 is the side where the first side surface 10 and the second surface 9 are in contact
- the side 17 is a side where the first side surface 10 and the other side surface are in contact with each other.
- a side adjacent to the first side 11 in the first surface 8 is referred to as a fourth side 14.
- the side adjacent to the second side 16 in the second surface 9 may be the fourth side 14.
- FIG. 11 shows the multilayer electronic component according to the third embodiment mounted on the substrate 21,
- FIG. 11 (a) is a cross-sectional view taken along the line A5-A5 of FIG. 10 (b)
- FIG. FIG. 10B is a cross-sectional view taken along line B5-B5.
- the stacking direction coincides with the y-axis direction of the coordinate axis.
- E1, L1, L2, and C are the same as the other examples, but the definitions of E2, E3, P1, P2, H0, H1, and H2 are different from those of the other examples. That is, in the third embodiment, as shown in FIG. 10C, E2 is the length of the second side 16, E3 is the length of the third side 17, and P1 is the first side In the side surface 10, the length in the direction perpendicular to the first side 11 of the first bonding member 4 extending from the first side 11 to the center side of the first side surface 10.
- P ⁇ b> 2 is a length in a direction perpendicular to the second side 16 of the second bonding member 5 that extends from the second side 16 to the center side of the first side surface 10 in the first side surface 10.
- H0 is the length of the fourth side 14, in other words, the height of the main body 1 in the z-axis direction of the coordinate axis.
- H1 is the length in the z-axis direction of the first bonding member 4 on the first surface 8 adjacent to the first side surface 10
- H2 is the second surface 9 adjacent to the first side surface 10. This is the length of the second bonding member 5 in the z-axis direction.
- simulation of sound generation was performed using the following model.
- L1 and L2 are both 200 ⁇ m
- H1 and H2 are both 78 ⁇ m
- P1 and P2 are both 140 ⁇ m.
- C in the mounting structure of the third embodiment is 140 ⁇ m.
- Other conditions related to the main body 1 were the same as those of the above-described sound simulation of the evaluation component.
- the average value of the sound pressure level in the third embodiment was reduced by 20 dB relative to the conventional mounting structure.
- the ratio of L1 and L2 (200 ⁇ m) to E1 and E2 (1100 ⁇ m) (L1 / E1, L2 / E2) is set to 0.18. 10 dBA can be reduced.
- the conductor 25 may be disposed in a region where the first bonding member 4 and the second bonding member 5 described above can be provided.
- the first bonding member 4 and the second bonding member 5 are not only the first side surface 10 of the main body 1 but also the first side surface. 10 can also be provided on the second side opposite to 10.
- first bonding member 4 and the second bonding member 5 may have insulating properties.
- the external electrode 3 may be electrically connected to the electric circuit of the substrate by wire bonding or the like.
- the first bonding member 4 and the second bonding member 5 are arranged on the first surface 8 side of the main body 1. Is provided.
- the second side 12 is a pair of sides that are adjacent to the first side 11 and face each other.
- the pair of second joining members 5 provided on the side 12 is located at portions of the pair of second sides 12 facing each other.
- E1 ⁇ E2 in the length E1 of the first side 11, the length E2 of the second side 12, and the length E3 of the third side 13, E1 ⁇ E2 and The relational expression of E3 ⁇ E2 is satisfied.
- FIG. 12C in the length E1 of the first side 11, the length E2 of the second side 12, and the length E3 of the third side 13, E1 ⁇ E2 and The relational expression of E3 ⁇ E2 is satisfied.
- FIG. 13 shows the multilayer electronic component of the present embodiment mounted on the substrate 21.
- FIG. 13 (a) is a cross-sectional view taken along line A6-C6-D6-A6 ′ of FIG. 12 (b), and
- FIG. ) Is a cross-sectional view taken along line B6-B6 of FIG.
- the first bonding member 4 is formed on the surface of the external electrode 3 located on the first side 11 side.
- Each of the pair of second bonding members 5 is formed on the surface of the multilayer body 2 so as to be separated from the external electrode 3. Both the first joining member 4 and the second joining member 5 have electrical conductivity.
- the pair of second bonding members 5 are electrically connected to the external electrode 3 located on the third side 13 side by a conductor 25.
- the conductor 25 is formed by, for example, plating or conductive paste.
- first joining member 4 and the second joining member 5 for example, eutectic solder, lead-free solder (Sn—Ag—Cu) brazing material, conductive An adhesive or the like can be used.
- FIG. 14 is a plan view of the multilayer electronic component of the present embodiment as viewed from the first main surface 8 side.
- FIG. 15 shows the multilayer electronic component of Modification 4 mounted on the substrate 21,
- FIG. 15 (a) is a cross-sectional view taken along line A7-C7-D7-A7 ′ of FIG. 14 (b), and
- FIG. FIG. 15 is a cross-sectional view taken along line B7-B7 of FIG.
- first bonding member 4 and the second bonding member 5 are separated from the first side 11 and the second side 12, respectively. 11 and the second side 12 may be in contact with each other.
- the multilayer electronic component mounting structure includes a main body 1 and a land pattern 22 on a substrate 21 via a first bonding member 4 and a second bonding member 5.
- the first surface 8 and the mounting surface of the substrate 21 are joined so as to face each other.
- the first bonding member 4 and the second bonding member 5 serve to bond the main body 1 to the substrate 21 and to connect the external electrode 3 of the main body 1 and a circuit (not shown) of the substrate 21. It also plays the role of electrical connection.
- a sounding simulation was performed using the following model.
- L1 and L2 were 310 ⁇ m and 142 ⁇ m, respectively, and P1 and P2 were both 142 ⁇ m.
- H1 of the 1st joining member 4 in 4th Embodiment was 78 micrometers.
- C in the mounting structure was 140 ⁇ m.
- Other conditions related to the main body 1 were the same as those of the above-described sound simulation of the evaluation component.
- the average value of the sound pressure level in the present embodiment is reduced by 24 dBA in the fourth embodiment compared to the conventional mounting structure, and is reduced by 26 dBA in the modified example.
- L1 is 310 ⁇ m and the ratio (L1 / E1) to E1 (620 ⁇ m) is 0.5, but even if this is 0.8, the sound pressure level can be reduced by about 10 dBA compared to the prior art. it can.
- L1 / E1 is preferably 0.4 or more from the viewpoint of mountability.
- L2 is 142 ⁇ m, and the ratio (L2 / E2) to E2 (1100 ⁇ m) is 0.13. However, even if this is 0.2, the sound pressure level can be reduced by 10 dBA compared to the conventional case.
- H1, H2, P1, P2, and C are preferably set in the same range as in the first and second embodiments.
- the thickness T1 of the second bonding member 5 of the present embodiment is made thicker than the height T0 from the first main surface 8 of the protruding portion of the external electrode 3 as in the second embodiment. Is preferred.
- H1, H2, and C are preferably set in the same range as in the first and second embodiments.
- a pair of second bonding members 5 are formed on the surface of the laminate 2 so as to be spaced apart from the external electrode 3, and the conductor is connected to the external electrode 3 positioned on the third side 13 side. 25, but only one of the pair of second bonding members 5 is electrically connected to the external electrode 3 located on the third side 13 side, and the other is connected. It does not have to be.
- the pair of second bonding members 5 may be directly connected to the external electrode 3 located on the third side 13 side and separated from only the external electrode 3 located on the first side 11 side.
- first bonding member 4 only serves to fix the main body 1 and the substrate 21, and the pair of second bonding members 5 are electrically connected to different external electrodes 3, respectively.
- the main body 1 may be connected to the electric circuit of the substrate 21 only through the second bonding member 5.
- the first bonding member 4 and the second bonding member 5 are not only the first surface 8 side of the main body 1 but also the first.
- the second surface 9 side opposite to the surface 8 can also be provided.
- first bonding member 4 and the second bonding member 5 may have insulating properties.
- the external electrode 3 may be electrically connected to the electric circuit of the substrate by wire bonding or the like.
- the first joining member 4 is provided on the first surface 8 side of the main body 1.
- the first joining member 4 is on a line 15 connecting the center 11c of the first side 11 that is one of the two pairs of opposite sides constituting the first surface 8, and In a region including the center 8 c of the surface 8, the surface 8 is provided so as to have an elongated shape along the line 15.
- the center 11 c of the first side 11 is a bisection point that bisects the length of the first side 11, and the center 8 c of the first surface 8 is the center of the first surface 8.
- the center of gravity of the surface is not limited to bea bisection point that bisects the length of the first side 11, and the center 8 c of the first surface 8 is the center of the first surface 8.
- the length of the first side 11 is E1, and the length of the other pair of sides adjacent to the first side 11 on the first surface 8 side of the main body 1. Is E2, E2 ⁇ E1. Note that E1 and E2 are the lengths of the main body 1 including the external electrodes 3.
- L1 is the length of the first joining member 4 in the length direction of the first side 11
- P1 is the length of the first joining member 4 on the line 15.
- H0 is the height of the main body 1 in the stacking direction
- C is the distance between the mounting surface of the substrate 21 and the main body 1.
- the first bonding member 4 is formed on the surface of the laminate 2 so as to be separated from the external electrode 3.
- the first bonding member 4 has electrical conductivity and is electrically connected to one of the external electrodes 3 by a conductor 25.
- a brazing material such as eutectic solder or lead-free solder (Sn—Ag—Cu), a conductive adhesive, or the like is used, as in the first to third embodiments. Can do.
- the mounting structure of the multilayer electronic component of this embodiment will be described.
- the main body 1 and the land pattern 22 on the substrate 21 are connected to the first surface via the first bonding member 4. 8 and the mounting surface of the substrate 21 are joined so as to face each other.
- the first joining member 4 has a role of joining the main body 1 to the substrate 21 and also electrically connecting one of the external electrodes 3 of the main body 1 to an electric circuit (not shown) of the substrate 21.
- the other of the external electrodes 3 (one not electrically connected to the first bonding member 4) is electrically connected to the electric circuit of the substrate 21 by wire bonding or the like, for example.
- the central portion of the two surfaces positioned opposite to the stacking direction of the evaluation component that is, the vicinity of the center 8c of the first surface 8 Vibrates only in the stacking direction, and does not vibrate in the plane direction of the stacking.
- the length of the line itself is shorter than the line connecting the centers of the sides, and the difference in vibration displacement between the center part (center 8c of the first surface) and the end part (11c, node-like part 24) is small. Therefore, by fixing the main body 1 to the substrate 21 on the line connecting the centers of the longer pair of sides, the propagation of the piezoelectric vibration of the main body 1 to the substrate 21 is further suppressed, and the noise can be reduced. .
- the main body 1 can be fixed to the substrate 21 at a site that vibrates only in the stacking direction.
- the first bonding member 4 had L1 of 200 ⁇ m and P1 of 620 ⁇ m. Further, C in the mounting structure of the present embodiment was 210 ⁇ m. Other conditions related to the main body 1 were the same as those in the simulation of the sound of the evaluation component described above. When the obtained results are averaged over the frequency range of 5 Hz to 20 kHz, the average value of the sound pressure level in the present embodiment is reduced by 22 dBA in the case of the aforementioned evaluation component, that is, the conventional mounting structure. .
- L1 (200 ⁇ m) is set to 0.18 as a ratio (L1 / E1) to E1 (1100 ⁇ m), but even if this is set to 0.45, the sound pressure level can be reduced by about 10 dBA compared to the conventional case. it can. Further, as L1 / E1 becomes smaller, the inclination of the main body 1 with respect to the substrate 21 is more likely to occur at the time of mounting. Therefore, L1 / E1 is preferably set to 0.10 to 0.45 from the viewpoint of mountability. P1 is preferably 0.5 or more in terms of E2 (P1 / E2) from the viewpoint of mountability.
- the first bonding member 4 is larger than the thickness T0 of the protruding portion on the first surface 8 side. It is preferable to increase the thickness T1 on the first surface 8 side.
- the length of the first side 11 is E1
- the length of a pair of sides adjacent to the first side 11 on the first surface 8 side of the main body 1 is E2.
- E1 is longer than E2 (E2 ⁇ E1)
- E1 ⁇ E2 the difference in vibration displacement of the main body 1 increases on the line 15 on which the first bonding member 4 is provided, so that the noise reduction effect is reduced. Therefore, when the lengths of the two pairs of sides on the first surface 8 side of the main body 1 are different, it is preferable that the pair of longer sides be the first sides 11.
- the ratio of C to H0 (C / H0), which is the distance between the mounting surface of the substrate 21 and the external electrode 3 of the main body 1, is preferably 0.1 or more.
- C is approximately equal to L1 in terms of facilitating mounting of the multilayer electronic component on the substrate 21 and improving mounting reliability.
- the first bonding member 4 may be provided not only on the first surface 8 side of the main body 1 but also on the second surface 9 side opposite to the first surface 8. it can.
- the first bonding member 4 can also have insulating properties. In that case, it is not necessary to provide the conductor 25, and all the external electrodes 3 may be electrically connected to the electric circuit of the substrate 21 by wire bonding or the like. Further, the first bonding member 4 and the external electrode 3 may be in direct contact.
- the insulating material for example, thermoplastic resins such as ethylene vinyl acetate (EVA) and polypropylene (PP) are suitable.
- a second joining member 5 is provided in addition to the first joining member 4 in the fifth embodiment.
- the second bonding member 5 is provided on the first side 8 of the main body 1 over the second side 12 that is one of the pair of sides adjacent to the first side 11 and the two sides adjacent thereto. It has been.
- the second bonding member 5 may be provided only on the first surface 8, and may be further away from the second side 12.
- L ⁇ b> 2 is the length of the second joining member 5 in the length direction of the second side 12, and P ⁇ b> 2 is from the second side 12 on the first surface 8 of the main body 1. This is the length in the direction perpendicular to the second side 12 of the second bonding member 5 extending to the center side of the first surface 8.
- H2 is the length in the stacking direction of the second bonding member 5 on the side surface of the main body 1 adjacent to the first surface 8.
- the second bonding member 5 is formed on the surface of the external electrode 3 located on the second side 12 side. Both the first joining member 4 and the second joining member 5 have electrical conductivity.
- first joining member 4 and the second joining member 5 for example, eutectic solder, lead-free solder (Sn—Ag—Cu), conductive adhesive, etc., as in the first to fourth embodiments. Can be used.
- the main body 1 and the land pattern 22 on the substrate 21 are interposed via the first bonding member 4 and the second bonding member 5.
- the first surface 8 and the mounting surface of the substrate 21 are opposed to each other.
- the first joining member 4 and the second joining member 5 serve to join the main body 1 to the substrate 21 and electrically connect the external electrode 3 of the main body 1 and an electric circuit (not shown) of the substrate 21. It also has a role.
- a sound simulation was performed using the following model.
- the first bonding member 4 had L1 of 200 ⁇ m and P1 of 620 ⁇ m
- the second bonding member 5 had L2 of 620 ⁇ m, H2 of 0 ⁇ m, and P2 of 200 ⁇ m.
- C in the mounting structure of the present embodiment was 210 ⁇ m.
- Other conditions related to the main body 1 were the same as those of the above-described sound simulation of the evaluation component.
- the average value of the sound pressure level in the present embodiment was reduced by 17 dBA compared to the conventional mounting structure.
- L1 (200 ⁇ m) is set to 0.18 as a ratio (L1 / E1) to E1 (1100 ⁇ m), but 0.10 to 0.43 is preferable from the viewpoint of mountability.
- a center line parallel to the line 15 of the first joining member 4 (a line passing through the center of gravity of the first joining member 4 in the plan view, hereinafter referred to as a first line).
- the center line of the bonding member 4 may not coincide with the line 15. Even if the deviation between the center line of the first joining member 4 and the line 15 is about 0.2 times E1, a significant noise reduction effect can be obtained.
- L2 (620 ⁇ m) is set to 1.0 as a ratio (L2 / E2) to E2 (620 ⁇ m), but when this is set to 0.5, the sound pressure level can be reduced by about 20 dBA from the conventional level.
- L2 / E2 is preferably set to 0.4 or more.
- the second joining member 5 is preferably located in the region including the above-described nodal portion 24, that is, the center 12 c of the second side 12.
- the vibration amplitude in the vicinity of the center of each surface constituting the evaluation part and in the vicinity of the center where the side faces contact each other is large. Therefore, P2 is preferably 0.25 or less in terms of E1 (P1 / E1).
- the ratio of H2 to H0 (H2 / H0) is preferably 0.4 or less.
- C it is preferable to set it as the same range as 4th Embodiment.
- first bonding member 4 and the second bonding member 5 are not only the first surface 8 side of the main body 1 but also the second surface opposite to the first surface 8. It can also be provided on the 9 side.
- first joining member 4 and the second joining member 5 may be insulative.
- the external electrode 3 may be electrically connected to the electric circuit of the substrate 21 by wire bonding or the like.
- the shapes of the first bonding member 4 and the second bonding member 5 are mainly rectangular, and preferred ranges of dimensions and ratios have been described based on the shapes. However, this does not limit the shapes of the first bonding member 4 and the second bonding member 5 to a rectangular shape, and may be various other shapes and irregular shapes. In addition, various changes and modifications can be made without departing from the gist of the present invention based on the description of the vibration mode of the multilayer electronic component and the nodal portion 24 confirmed by the above simulation.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
第1の実施形態である積層型電子部品は、図1(a)~(c)に示すように積層体2と、その両端部の外表面に設けられた外部電極3とを備える本体1に、さらに第1の接合部材4および第2の接合部材5を備えている。積層体2は、図2に示すように、誘電体層6と内部電極層7とが交互に積層されたものである。内部電極層7は、積層体2の両端部のいずれか一方において外部電極3と電気的に接続している。内部電極層7は、1層毎に異なる外部電極3に電気的に接続しており、外部電極3に電圧が印加されることにより、異なる外部電極3に接続した一対の内部電極層7に挟まれた誘電体層6において静電容量が発生する。以下、特に明記しない限り誘電体層6および内部電極層7の積層方向(以下、単に積層方向という場合もある)は、座標軸のz軸方向と一致するものとする。
第1の実施形態の変形例として、第1の接合部材4および第2の接合部材5をそれぞれ、第1の辺11および第2の辺12から離間して、第1の面8上にのみ配置したものを図4に示す(変形例1)。図4(b)は、変形例1の積層型電子部品を第1の面8側からみた平面図である。
第2の実施形態においては、第1の実施形態と同様、第1の接合部材4および第2の接合部材5が、本体1の第1の面8側に設けられている。第1の実施形態と異なるのは、図6(c)に示すように、第1の接合部材4が設けられた第1の辺11の長さE1、第2の接合部材5が設けられた第2の辺12の長さE2および接合部材が設けられていない第3の辺13の長さE3において、E3<E1かつE3<E2という関係式を満たしているという点である。図7は、基板21に実装した本実施形態の積層型電子部品を示し、図7(a)は図6(b)のA3-A3線断面図、図7(b)は図6(b)のB3-B3線断面図である。
第2の実施形態の変形例として、第1の接合部材4および第2の接合部材5をそれぞれ、第1の辺11および第2の辺12から離間して、第1の面8上にのみ配置したものを図8に示す(変形例2)。図8(b)は、変形例2の積層型電子部品を第1の面8側からみた平面図である。
第3の実施形態について説明する。第3の実施形態は、第1の実施形態と同様の直方体形状の本体1を有しており、図10、11に示すように、誘電体層6および内部電極層7の積層方向に垂直な方向に対向して位置する一対の第1の側面10および第2の側面(図示せず)を有しており、第1の側面10を構成する辺が、第1の辺11、該第1の辺11と対向する第2の辺16、および第1の辺11および第2の辺16に隣接する一対の第3の辺17を含んでいる。
第4の実施形態においては、図12に示すように、第1、第2の実施形態と同様、第1の接合部材4および第2の接合部材5が、本体1の第1の面8側に設けられている。第1、第2の実施形態と異なるのは、図12に示すように、第2の辺12が、第1の辺11に隣接するとともに互いに対向する一対の辺であり、一対の第2の辺12に設けられた一対の第2の接合部材5が、一対の第2の辺12の互いに対向する部位に位置しているという点である。本実施形態では、図12(c)に示すように、第1の辺11の長さE1、第2の辺12の長さE2および第3の辺13の長さE3において、E1<E2かつE3<E2の関係式を満たしている。図13は、基板21に実装した本実施形態の積層型電子部品を示すもので、図13(a)は図12(b)のA6-C6-D6-A6’線断面図、図13(b)は図12(b)のB6-B6線断面図である。
第4の実施形態の変形例として、第1の接合部材4および第2の接合部材5をそれぞれ、第1の辺11および第2の辺12から離間して、第1の面8上にのみ配置したものを図14に示す(変形例4)。図14(b)は、本実施形態の積層型電子部品を第1の主面8側からみた平面図である。
第5の実施形態においては、図16(c)に示すように、第1の接合部材4のみが本体1の第1の面8側に設けられている。第1の接合部材4は、第1の面8を構成する互いに対向する二対の辺のうち、いずれか一対である第1の辺11の中央11cを結ぶ線15上であって、第1の面8の中心8cを含む領域に、線15に沿った細長い形状を有するように設けられている。なお、第1の辺11の中央11cとは、第1の辺11の長さを2等分する2等分点であり、第1の面8の中心8cとは、第1の面8の面重心である。
第6の実施形態においては、図19に示すように、第5の実施形態における第1の接合部材4に加え、第2の接合部材5が設けられている。第2の接合部材5は、本体1の第1の面8において第1の辺11に隣接する一対の辺のうち、いずれか一方である第2の辺12とそれに隣接する2つの面にかけて設けられている。第2の接合部材5は、第1の面8のみに設けられていてもよく、さらに第2の辺12から離間していてもよい。
2、102 積層体
3、103 外部電極
4 第1の接合部材
5 第2の接合部材
6、106 誘電体層
7、107 内部電極層
8 第1の面
9 第2の面
10 第1の側面
11 第1の辺
11c 第1の辺の中央部
12、16 第2の辺
12c、16c 第2の辺の中央部
13、17 第3の辺
14 第4の辺
15 一対の第1の辺の中央を結ぶ線
21 基板
22 ランドパターン
23 導電層
24 節状部
25 導電体
31 実装基板
32 無響箱
33 集音マイク
34 アンプ
35 FETアナライザ
114 半田
V 本体の頂点
Claims (15)
- 誘電体層と内部電極層とが交互に積層された積層体と、該積層体の外表面に設けられ、前記内部電極層と電気的に接続された外部電極と、により構成される本体と、接合部材と、を備え、前記本体は直方体形状であり、前記誘電体層および前記内部電極層の積層方向に対向して位置する一対の第1の面および第2の面を有しており、前記接合部材は、前記第1の面を構成する4つの辺のうち少なくとも1つの辺の中央、および前記4つの辺のうち対向するいずれか一対の前記辺の中央を結ぶ線上のうち少なくともいずれかであって、かつ前記本体の頂点を含まない領域に位置していることを特徴とする積層型電子部品。
- 前記本体が、積層セラミックコンデンサであることを特徴とする請求項1に記載の積層型電子部品。
- 前記第1の面を構成する辺が、第1の辺、該第1の辺と対向する第2の辺、および前記第1の辺および前記第2の辺に隣接する第3の辺を含み、前記接合部材は、前記第1の辺、および前記第1の面における前記第1の辺に隣接する領域のうち、少なくともいずれかに位置する第1の接合部材と、前記第2の辺、および前記第1の面における前記第2の辺に隣接する領域のうち、少なくともいずれかに位置する第2の接合部材と、を有し、前記第1の面の中心、前記第3の辺、および前記第1の面における前記第3の辺に隣接する領域には前記接合部材を備えていないことを特徴とする請求項1または2に記載の積層型電子部品。
- 前記第1の辺の長さをE1、前記第2の辺の長さをE2、前記第3の辺の長さをE3としたとき、E1<E3かつE2<E3であることを特徴とする請求項3に記載の積層型電子部品。
- 前記第1の辺の長さをE1、前記第2の辺の長さをE2、前記第3の辺の長さをE3としたとき、E3<E1かつE3<E2であることを特徴とする請求項3に記載の積層型電子部品。
- 前記第1の面を構成する辺が、第1の辺、該第1の辺に隣接するとともに互いに対向する一対の第2の辺、および前記第1の辺と対向する第3の辺を含み、前記接合部材は、前記第1の辺、および前記第1の面における前記第1の辺に隣接する領域のうち、少なくともいずれかに位置する第1の接合部材と、前記一対の第2の辺、および前記第1の面における前記第2の辺に隣接する領域のうち、少なくともいずれかに位置する一対の第2の接合部材と、を有し、該一対の第2の接合部材は対向する部位に位置しており、前記第1の面の中心、前記第3の辺、および前記第1の面における前記第3の辺に隣接する領域には前記接合部材を備えていないことを特徴とする請求項1または2に記載の積層型電子部品。
- 前記第1の面において互いに対向する2対の前記辺のうちいずれか一対を第1の辺とし、前記接合部材は、一対の前記第1の辺の中央を結ぶ線上であって、前記第1の面の中心を含む領域に、前記一対の第1の辺の中央を結ぶ線に沿った細長い第1の接合部材を有することを特徴とする請求項1または2に記載の積層型電子部品。
- 前記接合部材は、さらに第2の接合部材を有し、前記第1の面において前記第1の辺に隣接する他の一対の前記辺のうち、いずれか一方を第2の辺としたとき、前記第2の接合部材が、前記第2の辺、および前記第1の面における前記第2の辺に隣接する領域のうち少なくともいずれかに位置することを特徴とする請求項7に記載の積層型電子部品。
- 前記第1の辺の長さをE1、前記第1の面において前記第1の辺に隣接する他の一対の辺の長さをE2としたとき、E2<E1であることを特徴とする請求項7または8に記載の積層型電子部品。
- 誘電体層と内部電極層とが交互に積層された積層体と、該積層体の外表面に設けられ、前記内部電極層と電気的に接続された外部電極と、により構成される本体と、
接合部材と、を備え、
前記本体は直方体形状であり、前記誘電体層および前記内部電極層の積層方向に垂直な方向に対向して位置する一対の第1の側面および第2の側面を有しており、
前記第1の側面を構成する辺が、第1の辺、該第1の辺と対向する第2の辺、および前記第1の辺および前記第2の辺に隣接する一対の第3の辺を含み、
前記接合部材は、前記第1の辺、および前記第1の側面における前記第1の辺に隣接する領域のうち、少なくともいずれかに位置する第1の接合部材と、
前記第2の辺、および前記第1の側面における前記第2の辺に隣接する領域のうち、少なくともいずれかに位置する第2の接合部材と、を有し、
前記第1の側面の中心、前記一対の第3の辺および該第3の辺に隣接する領域には前記接合部材を備えていないことを特徴とする積層型電子部品。 - 前記第1の辺の長さをE1、前記第2の辺の長さをE2、前記第3の辺の長さをE3としたとき、E3<E1かつE3<E2であることを特徴とする請求項10に記載の積層型電子部品。
- 前記本体は、前記誘電体層および前記内部電極層の積層方向に対向して位置する一対の第1の面および第2の面を有しており、
前記第1の辺の長さをE1、前記第2の辺の長さをE2とし、
前記第1の面における前記第1の辺に隣接する辺を第4の辺とし、該第4の辺の長さをH0としたとき、H0<E1かつH0<E2であることを特徴とする請求項10または11に記載の積層型電子部品。 - 基板の実装面に請求項1乃至9のいずれかに記載の積層型電子部品の前記接合部材を接合してなり、前記本体の前記第1の面が、前記実装面に対向していることを特徴とする積層型電子部品の実装構造体。
- 基板の実装面に請求項10乃至12のいずれかに記載の積層型電子部品の前記接合部材を接合してなり、前記本体の前記第1の側面が、前記実装面に対向していることを特徴とする積層型電子部品の実装構造体。
- 前記本体と前記基板の実装面との間に間隙を有することを特徴とする請求項13または14に記載の積層型電子部品の実装構造体。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015554973A JP6392784B2 (ja) | 2013-12-24 | 2014-12-24 | 積層型電子部品およびその実装構造体 |
US15/107,175 US9877393B2 (en) | 2013-12-24 | 2014-12-24 | Laminated electronic component and laminated electronic component mounting structure |
CN201480070375.3A CN105849835B (zh) | 2013-12-24 | 2014-12-24 | 层叠型电子部件及其安装结构体 |
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013265494 | 2013-12-24 | ||
JP2013-265494 | 2013-12-24 | ||
JP2013-267388 | 2013-12-25 | ||
JP2013267388 | 2013-12-25 | ||
JP2014014433 | 2014-01-29 | ||
JP2014-014433 | 2014-01-29 | ||
JP2014027602 | 2014-02-17 | ||
JP2014-027602 | 2014-02-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015098990A1 true WO2015098990A1 (ja) | 2015-07-02 |
Family
ID=53478837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2014/084199 WO2015098990A1 (ja) | 2013-12-24 | 2014-12-24 | 積層型電子部品およびその実装構造体 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9877393B2 (ja) |
JP (2) | JP6392784B2 (ja) |
CN (1) | CN105849835B (ja) |
WO (1) | WO2015098990A1 (ja) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018186283A (ja) * | 2013-12-24 | 2018-11-22 | 京セラ株式会社 | 積層型電子部品およびその実装構造体 |
KR20190059972A (ko) | 2016-12-01 | 2019-05-31 | 가부시키가이샤 무라타 세이사쿠쇼 | 칩형 전자 부품 |
JP2020181962A (ja) * | 2019-04-26 | 2020-11-05 | 株式会社村田製作所 | チップ型電子部品および電子部品の実装構造体 |
CN114664566A (zh) * | 2020-12-22 | 2022-06-24 | 株式会社村田制作所 | 层叠陶瓷电容器以及层叠陶瓷电容器的制造方法 |
US11657977B2 (en) | 2020-10-07 | 2023-05-23 | Murata Manufacturing Co., Ltd. | Method of manufacturing multilayer ceramic capacitor |
US11670458B2 (en) | 2020-10-07 | 2023-06-06 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
US11705284B2 (en) | 2020-10-07 | 2023-07-18 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
US11735370B2 (en) | 2020-10-07 | 2023-08-22 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
US11749461B2 (en) | 2020-10-07 | 2023-09-05 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
US11756735B2 (en) | 2020-10-07 | 2023-09-12 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
US11848155B2 (en) | 2021-05-18 | 2023-12-19 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
US12009155B2 (en) | 2020-10-07 | 2024-06-11 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10204737B2 (en) * | 2014-06-11 | 2019-02-12 | Avx Corporation | Low noise capacitors |
JP6524734B2 (ja) * | 2015-03-19 | 2019-06-05 | 株式会社村田製作所 | 電子部品およびこれを備えた電子部品連 |
DE102017109712A1 (de) * | 2017-05-05 | 2018-11-08 | Avl Software And Functions Gmbh | Bestimmung akustischer Störsignale in elektrischen Schaltungen |
US10658118B2 (en) * | 2018-02-13 | 2020-05-19 | Samsung Electro-Mechanics Co., Ltd. | Electronic component and board having the same |
CN110312359A (zh) * | 2018-03-27 | 2019-10-08 | 联发科技股份有限公司 | 用来降低电容器噪音的装置与方法 |
JP7089426B2 (ja) | 2018-07-23 | 2022-06-22 | 太陽誘電株式会社 | 積層セラミック電子部品、積層セラミック電子部品の製造方法及び電子部品内蔵基板 |
JP7451103B2 (ja) * | 2019-07-31 | 2024-03-18 | 株式会社村田製作所 | チップ型電子部品、電子部品の実装構造体および電子部品連 |
JP2023044006A (ja) | 2021-09-17 | 2023-03-30 | 株式会社村田製作所 | 電子部品 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62135426U (ja) * | 1986-02-21 | 1987-08-26 | ||
JPH11162780A (ja) * | 1997-11-21 | 1999-06-18 | Tokin Ceramics Kk | 積層セラミックコンデンサー結合体とその製造方法 |
JP2007103496A (ja) * | 2005-09-30 | 2007-04-19 | Tdk Corp | コンデンサおよび基板アセンブリ |
JP2007194313A (ja) * | 2006-01-18 | 2007-08-02 | Matsushita Electric Ind Co Ltd | 積層セラミックコンデンサ |
WO2007105395A1 (ja) * | 2006-03-14 | 2007-09-20 | Murata Manufacturing Co., Ltd. | 積層型電子部品の製造方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54105774A (en) * | 1978-02-08 | 1979-08-20 | Hitachi Ltd | Method of forming pattern on thin film hybrid integrated circuit |
JPS61288409A (ja) * | 1985-06-17 | 1986-12-18 | 株式会社日立製作所 | チツプ型電気部品 |
JPH03209806A (ja) * | 1990-01-12 | 1991-09-12 | Murata Mfg Co Ltd | 積層セラミックコンデンサ |
US5639010A (en) * | 1995-08-31 | 1997-06-17 | Ford Motor Company | Simultaneous process for surface mount adhesive cure and solder paste reflow for surface mount technology devices |
CN1289443A (zh) * | 1998-12-03 | 2001-03-28 | 株式会社东金 | 具有用于中断异常电流的薄膜电极的叠层式电子器件 |
JP4958363B2 (ja) * | 2000-03-10 | 2012-06-20 | スタッツ・チップパック・インコーポレイテッド | パッケージング構造及び方法 |
JP2002237429A (ja) * | 2000-12-08 | 2002-08-23 | Murata Mfg Co Ltd | 積層型貫通コンデンサおよび積層型貫通コンデンサアレイ |
JP3498711B2 (ja) * | 2001-02-05 | 2004-02-16 | 三菱マテリアル株式会社 | 塩化第一銅の製造方法 |
JP4736225B2 (ja) * | 2001-04-16 | 2011-07-27 | パナソニック株式会社 | コンデンサ |
CN100354995C (zh) * | 2002-09-27 | 2007-12-12 | 京瓷株式会社 | 电容器、布线基板、去耦电路及高频电路 |
JP2006295076A (ja) * | 2005-04-14 | 2006-10-26 | Rohm Co Ltd | セラミック製チップ型電子部品とその製造方法 |
KR100925603B1 (ko) | 2007-09-28 | 2009-11-06 | 삼성전기주식회사 | 적층형 캐패시터 |
KR100994172B1 (ko) * | 2008-07-23 | 2010-11-15 | 삼화콘덴서공업주식회사 | 커패시터 모듈 |
JP5810706B2 (ja) * | 2010-09-06 | 2015-11-11 | 株式会社村田製作所 | 電子部品 |
JP5884653B2 (ja) | 2011-09-01 | 2016-03-15 | 株式会社村田製作所 | 実装構造 |
JP5589994B2 (ja) * | 2011-09-01 | 2014-09-17 | 株式会社村田製作所 | 選択方法 |
JP5678919B2 (ja) * | 2012-05-02 | 2015-03-04 | 株式会社村田製作所 | 電子部品 |
JP5725062B2 (ja) | 2013-03-15 | 2015-05-27 | 株式会社村田製作所 | 電子部品、それに含まれる基板型の端子、および、電子部品の実装構造 |
JP6392784B2 (ja) * | 2013-12-24 | 2018-09-19 | 京セラ株式会社 | 積層型電子部品およびその実装構造体 |
-
2014
- 2014-12-24 JP JP2015554973A patent/JP6392784B2/ja active Active
- 2014-12-24 WO PCT/JP2014/084199 patent/WO2015098990A1/ja active Application Filing
- 2014-12-24 CN CN201480070375.3A patent/CN105849835B/zh active Active
- 2014-12-24 US US15/107,175 patent/US9877393B2/en active Active
-
2018
- 2018-06-27 JP JP2018122445A patent/JP2018186283A/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62135426U (ja) * | 1986-02-21 | 1987-08-26 | ||
JPH11162780A (ja) * | 1997-11-21 | 1999-06-18 | Tokin Ceramics Kk | 積層セラミックコンデンサー結合体とその製造方法 |
JP2007103496A (ja) * | 2005-09-30 | 2007-04-19 | Tdk Corp | コンデンサおよび基板アセンブリ |
JP2007194313A (ja) * | 2006-01-18 | 2007-08-02 | Matsushita Electric Ind Co Ltd | 積層セラミックコンデンサ |
WO2007105395A1 (ja) * | 2006-03-14 | 2007-09-20 | Murata Manufacturing Co., Ltd. | 積層型電子部品の製造方法 |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018186283A (ja) * | 2013-12-24 | 2018-11-22 | 京セラ株式会社 | 積層型電子部品およびその実装構造体 |
KR20190059972A (ko) | 2016-12-01 | 2019-05-31 | 가부시키가이샤 무라타 세이사쿠쇼 | 칩형 전자 부품 |
US10971301B2 (en) | 2016-12-01 | 2021-04-06 | Murata Manufacturing Co., Ltd. | Chip electronic component |
KR20210107171A (ko) | 2016-12-01 | 2021-08-31 | 가부시키가이샤 무라타 세이사쿠쇼 | 칩형 전자 부품 |
JP2020181962A (ja) * | 2019-04-26 | 2020-11-05 | 株式会社村田製作所 | チップ型電子部品および電子部品の実装構造体 |
JP7292958B2 (ja) | 2019-04-26 | 2023-06-19 | 株式会社村田製作所 | 電子部品の実装構造体 |
US11670458B2 (en) | 2020-10-07 | 2023-06-06 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
US11657977B2 (en) | 2020-10-07 | 2023-05-23 | Murata Manufacturing Co., Ltd. | Method of manufacturing multilayer ceramic capacitor |
US11705284B2 (en) | 2020-10-07 | 2023-07-18 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
US11735370B2 (en) | 2020-10-07 | 2023-08-22 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
US11749461B2 (en) | 2020-10-07 | 2023-09-05 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
US11756735B2 (en) | 2020-10-07 | 2023-09-12 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
US12009155B2 (en) | 2020-10-07 | 2024-06-11 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
KR20220090433A (ko) | 2020-12-22 | 2022-06-29 | 가부시키가이샤 무라타 세이사쿠쇼 | 적층 세라믹 콘덴서 및 적층 세라믹 콘덴서의 제조 방법 |
CN114664566A (zh) * | 2020-12-22 | 2022-06-24 | 株式会社村田制作所 | 层叠陶瓷电容器以及层叠陶瓷电容器的制造方法 |
US11923142B2 (en) | 2020-12-22 | 2024-03-05 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor and method of manufacturing multilayer ceramic capacitor |
CN114664566B (zh) * | 2020-12-22 | 2024-05-14 | 株式会社村田制作所 | 层叠陶瓷电容器以及层叠陶瓷电容器的制造方法 |
US11848155B2 (en) | 2021-05-18 | 2023-12-19 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
Also Published As
Publication number | Publication date |
---|---|
CN105849835A (zh) | 2016-08-10 |
US20170042029A1 (en) | 2017-02-09 |
CN105849835B (zh) | 2019-05-07 |
US9877393B2 (en) | 2018-01-23 |
JP2018186283A (ja) | 2018-11-22 |
JPWO2015098990A1 (ja) | 2017-03-23 |
JP6392784B2 (ja) | 2018-09-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6392784B2 (ja) | 積層型電子部品およびその実装構造体 | |
JP6220898B2 (ja) | 積層型電子部品およびその実装構造体 | |
JP5126379B2 (ja) | チップ部品構造体 | |
KR100586863B1 (ko) | 전자 부품 | |
JP2012033654A (ja) | セラミックコンデンサ | |
JP5532087B2 (ja) | 実装構造 | |
JP2012033655A (ja) | セラミックコンデンサ | |
JP2012033651A (ja) | セラミックコンデンサ | |
JP2012099538A (ja) | 電子部品 | |
JP5459368B2 (ja) | チップ部品構造体 | |
JP2014187315A (ja) | 電子部品 | |
JP2012033659A (ja) | セラミックコンデンサ | |
JP6549712B2 (ja) | 積層型コンデンサおよびその実装構造体 | |
JP6239764B2 (ja) | 積層型電子部品およびその実装構造体 | |
JP6585340B2 (ja) | 積層型電子部品およびその実装構造体 | |
JP2012094785A (ja) | 電子部品 | |
JP6400924B2 (ja) | 電子部品の実装構造 | |
JP2016219624A (ja) | 積層型コンデンサおよびその実装構造体 | |
JP6137069B2 (ja) | コンデンサの実装構造体及びコンデンサ | |
WO2016171261A1 (ja) | 積層セラミックコンデンサおよび実装構造体 | |
JP2003257779A (ja) | 電子部品 | |
JP2020038983A (ja) | 積層型コンデンサおよびその実装構造 | |
JP2012099529A (ja) | 電子部品 | |
JP2016207718A (ja) | 積層型コンデンサおよびその実装構造 | |
JP2016219741A (ja) | 積層型コンデンサおよびその実装構造体 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14873195 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2015554973 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 15107175 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 14873195 Country of ref document: EP Kind code of ref document: A1 |