WO2015093097A1 - 表示装置およびその駆動方法 - Google Patents
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- WO2015093097A1 WO2015093097A1 PCT/JP2014/071721 JP2014071721W WO2015093097A1 WO 2015093097 A1 WO2015093097 A1 WO 2015093097A1 JP 2014071721 W JP2014071721 W JP 2014071721W WO 2015093097 A1 WO2015093097 A1 WO 2015093097A1
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
- G09G3/3283—Details of drivers for data electrodes in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
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- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
- G09G3/325—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
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Definitions
- the present invention relates to a display device and a driving method thereof, and more particularly to a display device including a pixel circuit including an electro-optical element such as an organic EL (Electro-Luminescence) element and a driving method thereof.
- a display device including a pixel circuit including an electro-optical element such as an organic EL (Electro-Luminescence) element and a driving method thereof.
- an electro-optical element such as an organic EL (Electro-Luminescence) element
- organic EL display devices that use organic EL elements, which are self-luminous electro-optic elements, can be easily reduced in thickness, power consumption, brightness, etc., compared to liquid crystal display devices that require backlights and color filters. Can be achieved. Accordingly, in recent years, organic EL display devices have been actively developed.
- an organic EL display device As a driving method of an organic EL display device, a passive matrix method (also called a simple matrix method) and an active matrix method are known.
- An organic EL display device adopting a passive matrix system has a simple structure but is difficult to increase in size and definition.
- an organic EL display device adopting an active matrix method hereinafter referred to as an “active matrix type organic EL display device” is larger and has higher definition than an organic EL display device employing a passive matrix method. Can be easily realized.
- a pixel circuit of an active matrix organic EL display device typically includes an input transistor that selects a pixel and a drive transistor that controls the supply of current to the organic EL element.
- the current flowing from the drive transistor to the organic EL element may be referred to as “drive current”.
- FIG. 32 is a circuit diagram showing a configuration of a conventional general pixel circuit 91.
- the pixel circuit 91 is provided corresponding to each intersection of the plurality of data signal lines S and the plurality of scanning lines G provided in the display unit.
- the pixel circuit 91 includes two transistors T1 and T2, one capacitor Cst, and one organic EL element OLED.
- the transistor T1 is an input transistor
- the transistor T2 is a drive transistor.
- the transistor T1 is provided between the data signal line S and the gate terminal of the transistor T2.
- a gate terminal is connected to the scanning line G, and a source terminal is connected to the data signal line S.
- the transistor T2 is provided in series with the organic EL element OLED.
- a drain terminal is connected to a power supply line that supplies a high-level power supply voltage ELVDD, and a source terminal is connected to an anode terminal of the organic EL element OLED.
- a power supply line that supplies the high-level power supply voltage ELVDD is hereinafter referred to as a “high-level power supply line”, and the high-level power supply line is given the same sign ELVDD as the high-level power supply voltage.
- the capacitor Cst one end is connected to the gate terminal of the transistor T2, and the other end is connected to the source terminal of the transistor T2.
- the cathode terminal of the organic EL element OLED is connected to a power supply line that supplies a low level power supply voltage ELVSS.
- the power supply line that supplies the low-level power supply voltage ELVSS is hereinafter referred to as “low-level power supply line”, and the same sign ELVSS as the low-level power supply voltage is attached to the low-level power supply line.
- a connection point between the gate terminal of the transistor T2, one end of the capacitor Cst, and the drain terminal of the transistor T1 is referred to as a “gate node VG” for convenience.
- the higher of the drain and the source is called the drain, but in the description of this specification, one is defined as the drain and the other is defined as the source. Therefore, the source potential is higher than the drain potential. May be higher.
- FIG. 33 is a timing chart for explaining the operation of the pixel circuit 91 shown in FIG.
- the scanning line G Prior to time t1, the scanning line G is in a non-selected state. Therefore, before the time t1, the transistor T1 is in an off state, and the potential of the gate node VG maintains an initial level (for example, a level corresponding to writing in the previous frame).
- the scanning line G is selected and the transistor T1 is turned on. Thereby, the data voltage Vdata corresponding to the luminance of the pixel (sub-pixel) formed by the pixel circuit 91 is supplied to the gate node VG via the data signal line S and the transistor T1.
- the potential of the gate node VG changes according to the data voltage Vdata.
- the capacitor Cst is charged to the gate-source voltage Vgs which is the difference between the potential of the gate node VG and the source potential of the transistor T2.
- the scanning line G is in a non-selected state.
- the transistor T1 is turned off, and the gate-source voltage Vgs held by the capacitor Cst is determined.
- the transistor T2 supplies a drive current to the organic EL element OLED according to the gate-source voltage Vgs held by the capacitor Cst. As a result, the organic EL element OLED emits light with a luminance corresponding to the drive current.
- a thin film transistor (TFT) is typically employed as a drive transistor.
- the threshold voltage tends to vary for the thin film transistor.
- a technique for suppressing deterioration in display quality in an organic EL display device has been conventionally proposed.
- Japanese Unexamined Patent Application Publication No. 2005-31630 discloses a technique for compensating for variations in threshold voltage of drive transistors.
- 2007-128103 disclose a technique for making the current flowing from the pixel circuit to the organic EL element OLED constant. Furthermore, Japanese Unexamined Patent Application Publication No. 2007-233326 discloses a technique for displaying an image with uniform brightness regardless of the threshold voltage and electron mobility of a driving transistor.
- Japanese Patent Publication No. 2008-523448 discloses a technique for correcting data based on the characteristics of the organic EL element OLED in addition to the technique for correcting data based on the characteristics of the driving transistor.
- Japanese Unexamined Patent Publication No. 2005-31630 Japanese Unexamined Patent Publication No. 2003-195810 Japanese Unexamined Patent Publication No. 2007-128103 Japanese Unexamined Patent Publication No. 2007-233326 Japanese Special Table 2008-523448
- the circuit scale does not increase as much as possible. This is because an increase in circuit scale is disadvantageous, for example, in reducing power consumption and size.
- the characteristic detection is performed in addition to the data signal line VDATA for supplying the data signal to the pixel circuit. Current detection monitor line MONITOR is provided. For this reason, the degree of increase in circuit scale is large.
- the present invention provides a display device capable of compensating for deterioration of circuit elements while suppressing an increase in circuit scale (particularly, a display device capable of simultaneously compensating for both deterioration of drive transistors and deterioration of organic EL elements). ).
- a first aspect of the present invention is an active matrix display device,
- the pixel circuit includes n ⁇ m pixel circuits (n and m are integers of 2 or more) each including an electro-optical element whose luminance is controlled by a current and a drive transistor for controlling a current to be supplied to the electro-optical element.
- a display unit having data signal lines provided to correspond to the columns;
- a characteristic detection process for detecting a characteristic of a characteristic detection target circuit element including at least one of the electro-optical element or the driving transistor is performed in a frame period, and each electro-optical element emits light according to a target luminance.
- a pixel circuit driver for driving the scanning line, the monitor control line, and the data signal line;
- Correction data storage unit that stores characteristic data obtained based on the result of the characteristic detection processing as correction data for correcting a video signal;
- a video signal correction unit that corrects the video signal based on correction data stored in the correction data storage unit and generates a data signal to be supplied to the n ⁇ m pixel circuits;
- Each pixel circuit The electro-optic element;
- An input transistor having a control terminal connected to the scan line, a first conduction terminal connected to the control terminal of the drive transistor, and a second conduction terminal connected to the data signal line;
- the drive transistor having a drive power supply potential applied to the first conduction terminal;
- Monitor control in which a control terminal is connected to the monitor control line, a first conduction terminal is connected to the second conduction terminal of the drive transistor and the anode of the electro-optic element, and a second conduction terminal is connected to the data signal line
- a transistor A first capacitor connected at one
- the current measurement period includes a drive transistor characteristic detection period in which current measurement for detecting the characteristic of the drive transistor is performed, and an electro-optical element characteristic detection period in which current measurement for detecting the characteristic of the electro-optical element is performed. It is characterized by comprising.
- the output / current monitor circuit further includes a third control switch having one end connected to the data signal line and the other end connected to a predetermined control line, In the drive transistor characteristic detection period of the current measurement period, the data signal line and the control line are electrically connected by turning on the third control switch during the AD conversion period. Further, the control line is supplied with a potential having a magnitude equal to that of the potential applied to the data signal line during the data signal line charging period.
- the third control switch In the electro-optical element characteristic detection period of the current measurement period, the third control switch is in an off state and the monitor control is performed so that the data signal line is in a high impedance state during the AD conversion period.
- the transistor is turned off.
- the data signal line and the control line are electrically connected by turning on the third control switch during the AD conversion period. And a potential having a magnitude substantially equal to the magnitude of the potential applied to the data signal line during the data signal line charging period is applied to the control line.
- the data signal line and the control line are electrically connected by turning on the third control switch during the AD conversion period. And a potential having a constant magnitude close to a potential to be applied to the data signal line during the data signal line charging period is applied to the control line.
- Vmg the potential applied to the data signal line during the drive transistor characteristic detection period
- Vm_TFT the potential applied to the data signal line during the electro-optical element characteristic detection period.
- Vm_TFT Vmg ⁇ Vth (T2)
- Vm_TFT ⁇ ELVSS + Vth (oled)
- ELVSS ELVSS + Vth (oled)
- Vth (T2) is a threshold voltage of the driving transistor
- Vth (oled) is a light emission threshold voltage of the electro-optical element
- ELVSS is a cathode potential of the electro-optical element.
- the characteristic detection processing period is provided within a vertical blanking period.
- a ninth aspect of the present invention is the eighth aspect of the present invention,
- the pixel circuit driving unit when the target electro-optical element is included in the monitor row, the data to the pixel circuit included in the monitor row.
- the potential of the data signal corresponding to a grayscale voltage higher than the grayscale voltage when the electro-optical element of interest is included in the non-monitor row is the data signal. It is given to a line.
- the characteristic detection processing period is provided within a vertical scanning period.
- a cycle including the data signal line charging period, the monitoring period, and the AD conversion period is repeated a plurality of times.
- the characteristic detection process is performed for only one of the electro-optic element and the driving transistor per frame period.
- n ⁇ m electro-optic elements whose luminance is controlled by current and driving transistors for controlling the current to be supplied to the electro-optic elements (n and m are 2).
- a display device comprising: a control line; a data signal line provided so as to correspond to each column of the pixel matrix; and a scanning circuit, the monitor control line, and a pixel circuit driving unit that drives the data signal line Driving method,
- a pixel circuit including an electro-optical element (for example, an organic EL element) whose luminance is controlled by a current and a driving transistor for controlling a current to be supplied to the electro-optical element.
- an electro-optical element for example, an organic EL element
- a driving transistor for controlling a current to be supplied to the electro-optical element.
- the characteristic of the circuit element is detected by measuring the current flowing through the data signal line. That is, the data signal line is used not only as a signal line for transmitting a signal for causing the electro-optic element in each pixel circuit to emit light with a desired luminance, but also as a signal line for characteristic detection. For this reason, it is not necessary to provide a new signal line in the display unit in order to detect the characteristics of the circuit element. Therefore, it is possible to compensate for the deterioration of the circuit element while suppressing an increase in circuit scale.
- the second switch is turned off, so that the analog data acquired in the monitor period is held in the output / current monitor circuit.
- the AD conversion circuit is shared by a plurality of columns. As a result, an increase in circuit scale associated with a configuration capable of detecting the characteristics of the circuit elements is effectively suppressed.
- the characteristics of the electro-optic element and the drive transistor are detected during the frame period. For this reason, it is possible to compensate both the deterioration of the electro-optic element and the deterioration of the driving transistor while effectively suppressing an increase in circuit scale.
- the data signal line and the internal data line are electrically disconnected, and the data signal line immediately before the AD conversion period is A potential equal to the potential is applied from the control line to the data signal line. For this reason, the potential of the data signal line is prevented from fluctuating during AD conversion due to sharing of the AD conversion circuit.
- the data signal line is recharged in a very short time, current measurement for characteristic detection can be repeatedly performed. As a result, it is possible to ensure a sufficient S / N ratio at the time of current measurement for detecting the characteristics of the drive transistor.
- the data signal line is in a high impedance state during the AD conversion period within the electro-optic element characteristic detection period. For this reason, the potential of the data signal line is prevented from fluctuating during AD conversion due to sharing of the AD conversion circuit.
- the data signal line is recharged in a very short time, current measurement for characteristic detection can be repeatedly performed. As a result, it is possible to ensure a sufficient S / N ratio at the time of current measurement for detecting the characteristics of the electro-optical element.
- the data signal line and the internal data line are electrically disconnected, and the data signal line immediately before the AD conversion period Is supplied from the control line to the data signal line. For this reason, the potential of the data signal line is prevented from fluctuating during AD conversion due to sharing of the AD conversion circuit.
- the data signal line is recharged in a very short time, current measurement for characteristic detection can be repeatedly performed. As a result, it is possible to ensure a sufficient S / N ratio at the time of current measurement for detecting the characteristics of the electro-optical element.
- the sixth aspect of the present invention as in the fifth aspect of the present invention, it is possible to ensure a sufficient S / N ratio at the time of current measurement for detecting the characteristics of the electro-optic element. .
- the drive transistor during the drive transistor characteristic detection period, the drive transistor is reliably turned on and the electro-optic element is reliably turned off. In the electro-optical element characteristic detection period, the drive transistor is surely turned off and the electro-optical element is reliably turned on.
- the monitor row is written again in the light emission preparation period in the vertical blanking period after writing in the vertical scanning period.
- the increase in memory capacity is slight.
- a line memory for several tens of lines may be required. As described above, the required memory capacity is reduced as compared with the configuration in which the characteristic detection processing period is provided in the vertical scanning period.
- the potential of the data signal is adjusted in consideration of the fact that the electro-optic element is temporarily turned off during the vertical blanking period. For this reason, deterioration of display quality is suppressed.
- writing according to the target luminance in the monitor row is performed only once per frame period. It ’s fine.
- the current measurement is repeated a plurality of times in each current measurement period for detecting the characteristic of the characteristic detection target circuit element. For this reason, sufficient S / N ratio is securable.
- the characteristic detection processing is performed for only one of the electro-optic element and the driving transistor per frame period, thereby transferring data obtained by AD conversion after AD conversion. Enough time is secured.
- the same effect as that of the first aspect of the present invention can be achieved in the invention of the display device driving method.
- FIG. 3 is a circuit diagram illustrating detailed configurations of a pixel circuit, an output / current monitor circuit, and a signal conversion circuit in an embodiment of the present invention. It is a block diagram which shows the whole structure of the active matrix type organic electroluminescent display apparatus which concerns on the said embodiment.
- 5 is a timing chart for explaining an operation of a gate driver in the embodiment. 5 is a timing chart for explaining an operation of a gate driver in the embodiment. 5 is a timing chart for explaining an operation of a gate driver in the embodiment. In the said embodiment, it is a figure for demonstrating the input / output signal of the output / current monitor circuit in an output part.
- FIG. 6 is a diagram for explaining adjustment of the length of integration time by control of a control clock signal CLK1 in the embodiment.
- the said embodiment it is a figure for demonstrating sharing of an A / D converter. In the said embodiment, it is a figure for demonstrating transition of operation
- 5 is a timing chart for explaining an operation of a pixel circuit (i-row and j-column pixel circuit) included in a monitor row in the embodiment.
- it is a figure for demonstrating the flow of an electric current when normal operation
- it is a timing chart for demonstrating the detail of 1 horizontal scanning period about a monitor line.
- FIG. 6 is a diagram for describing a circuit state in a period Tb3 within a TFT characteristic detection period in the embodiment.
- it is a figure for demonstrating the flow of the electric current of the period Tc2 in an OLED characteristic detection period.
- it is a figure for demonstrating the flow of the electric current in the light emission preparation period.
- it is a figure for demonstrating the flow of the electric current in the light emission period.
- it is the figure which compared 1 frame period in a monitor line with 1 frame period in a non-monitoring line.
- the said embodiment is a flowchart for demonstrating the procedure of the update of the correction data in a correction data storage part.
- it is a figure for demonstrating correction
- it is a flowchart for demonstrating the outline of the operation
- 14 is a timing chart for explaining the operation of a pixel circuit (pixel circuit of i rows and j columns) included in a monitor row in the second modification of the embodiment.
- FIG. 10 is a circuit diagram showing a configuration in which a control line CL and a switch 335 are deleted from the configuration shown in FIG. 1 in the second modification of the embodiment. It is a figure for demonstrating the structure of 1 frame period. 12 is a timing chart for explaining an operation during a vertical blanking period of a pixel circuit (a pixel circuit of i rows and j columns) included in a monitor row in the third modification of the embodiment. In the 3rd modification of the said embodiment, it is a timing chart for demonstrating the detail of a vertical blanking period.
- FIG. 10 is a circuit diagram showing a configuration in which a control line CL and a switch 335 are deleted from the configuration shown in FIG. 1 in the second modification of the embodiment. It is a figure for demonstrating the structure of 1 frame period. 12 is a timing chart for explaining an operation during a vertical blanking period of a pixel circuit (a pixel circuit of i rows and j columns) included in a monitor row in the third modification of the embodiment. In the 3r
- FIG. 15 is a timing chart for explaining an operation during one frame period of a pixel circuit (referred to as a pixel circuit of i rows and j columns) included in a monitor row in the third modification of the embodiment. It is a circuit diagram which shows the structure of the conventional general pixel circuit. 33 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 32. It is a figure for demonstrating the case where no compensation is performed with respect to deterioration of a drive transistor and deterioration of an organic EL element. It is a figure for demonstrating the case where compensation is performed only with respect to deterioration of a drive transistor. It is FIG. 14 of Japanese special table 2008-523448.
- TFT characteristic the characteristic of the driving transistor provided in the pixel circuit
- OLED characteristic the characteristic of the organic EL element provided in the pixel circuit
- FIG. 2 is a block diagram showing the overall configuration of an active matrix organic EL display device 1 according to an embodiment of the present invention.
- the organic EL display device 1 includes a display unit 10, a control circuit 20, a source driver (data signal line driving circuit) 30, a gate driver (scanning line driving circuit) 40, and a correction data storage unit 50.
- a pixel circuit driving unit is realized by the source driver 30 and the gate driver 40. Note that one or both of the source driver 30 and the gate driver 40 may be formed integrally with the display unit 10.
- the display unit 10 is provided with m data signal lines S (1) to S (m) and n scanning lines G1 (1) to G1 (n) orthogonal thereto.
- the extending direction of the data signal lines is defined as the Y direction
- the extending direction of the scanning lines is defined as the X direction.
- Components along the Y direction may be referred to as “columns”
- components along the X direction may be referred to as “rows”.
- the display unit 10 is provided with n monitor control lines G2 (1) to G2 (n) so as to correspond to the n scanning lines G1 (1) to G1 (n) on a one-to-one basis. Has been.
- the scanning lines G1 (1) to G1 (n) and the monitor control lines G2 (1) to G2 (n) are parallel to each other. Further, the display unit 10 has n ⁇ m so as to correspond to the intersections of the n scanning lines G1 (1) to G1 (n) and the m data signal lines S (1) to S (m). Pixel circuits 11 are provided. By providing n ⁇ m pixel circuits 11 in this manner, a pixel matrix of n rows ⁇ m columns is formed in the display unit 10.
- the display unit 10 is provided with a high level power supply line for supplying a high level power supply voltage and a low level power supply line for supplying a low level power supply voltage.
- the data signal line is simply represented by a symbol S.
- the scanning lines are simply denoted by reference numeral G1
- the n monitor control lines G2 (1) to G2 (n) When it is not necessary to distinguish them from each other, the monitor control line is simply represented by the symbol G2.
- the data signal line S in the present embodiment is not only used as a signal line for transmitting a luminance signal for causing the organic EL element in the pixel circuit 11 to emit light with a desired luminance, but also for detecting TFT characteristics and OLED characteristics. It is also used as a signal line for applying a control potential to the pixel circuit 11 and a signal line serving as a current path that can be measured by an output / current monitor circuit 330 to be described later, which is a current representing TFT characteristics and OLED characteristics.
- the control circuit 20 controls the operation of the source driver 30 by supplying the data signal DA and the source control signal SCTL to the source driver 30, and controls the operation of the gate driver 40 by supplying the gate control signal GCTL to the gate driver 40.
- the source control signal SCTL includes, for example, control clock signals CLK1, CLK2, and the like for controlling the operation of the output / current monitor circuit 330 in addition to the conventionally used source start pulse, source clock, and latch strobe signal. CLK2B is included.
- the gate control signal GCTL includes, for example, a gate start pulse, a gate clock, and an output enable signal.
- the control circuit 20 also receives the monitor data MO given from the source driver 30 and updates the correction data stored in the correction data storage unit 50. Note that the monitor data MO is data measured for obtaining TFT characteristics and OLED characteristics.
- the gate driver 40 is connected to n scanning lines G1 (1) to G1 (n) and n monitor control lines G2 (1) to G2 (n).
- the gate driver 40 includes a shift register and a logic circuit.
- Detection of TFT characteristics and OLED characteristics for the third row is performed. In this way, detection of TFT characteristics and OLED characteristics for n rows is performed over an n frame period.
- a row in which TFT characteristics and OLED characteristics are detected when attention is paid to an arbitrary frame is referred to as a “monitor row”, and a row other than the monitor row is referred to as “non-monitoring”. Line ".
- n scanning lines G1 (1) to G1 (n) and n monitor control lines G2 (1) to G2 (n) are driven as shown in FIG. 3 at the (k + 1) th frame, driven at the (k + 2) th frame as shown in FIG. 4, and at the (k + n) th frame.
- the high level state is an active state.
- one horizontal scanning period for the monitor row is represented by a symbol THm
- one horizontal scanning period for a non-monitor row is represented by a symbol THn.
- the length of one horizontal scanning period is different between the monitor row and the non-monitor row. Specifically, the length of one horizontal scanning period for the monitor row is longer than the length of one horizontal scanning period for the non-monitor row.
- there is one selection period in one frame period as in a general organic EL display device.
- a monitor row unlike a general organic EL display device, there are two selection periods in one frame period. A more detailed description of one horizontal scanning period THm for the monitor row will be described later.
- the monitor control line G2 corresponding to the non-monitor row is maintained in an inactive state.
- the monitor control line G2 corresponding to the monitor row is maintained in an active state during a period other than the selection period in one horizontal scanning period THm (a period in which the scanning line G1 is in an inactive state).
- the gate driver 40 is driven so that the n scanning lines G1 (1) to G1 (n) and the n monitor control lines G2 (1) to G2 (n) are driven as described above. It is configured.
- the waveform of the output enable signal sent from the control circuit 20 to the gate driver 40 is controlled using a known method. It ’s fine.
- the source driver 30 is connected to m data signal lines S (1) to S (m).
- the source driver 30 includes a drive signal generation circuit 31, a signal conversion circuit 32, and an output unit 33 including m output / current monitor circuits 330 (see FIG. 2).
- the m output / current monitor circuits 330 in the output unit 33 are connected to corresponding data signal lines S among the m data signal lines S (1) to S (m), respectively.
- the drive signal generation circuit 31 includes a shift register, a sampling circuit, and a latch circuit.
- the shift register sequentially transfers the source start pulse from the input end to the output end in synchronization with the source clock.
- a sampling pulse corresponding to each data signal line S is output from the shift register.
- the sampling circuit sequentially stores the data signals DA for one row according to the timing of the sampling pulse.
- the latch circuit fetches and holds the data signal DA for one row stored in the sampling circuit according to the latch strobe signal.
- the data signal DA controls the luminance signal for causing the organic EL element of each pixel to emit light with a desired luminance, and the operation of the pixel circuit 11 when detecting TFT characteristics and OLED characteristics. And a monitor control signal.
- the signal conversion circuit 32 includes a D / A converter and an A / D converter.
- the data signal DA for one row held in the latch circuit in the drive signal generation circuit 31 as described above is converted into an analog voltage by the D / A converter in the signal conversion circuit 32.
- the converted analog voltage is supplied to the output / current monitor circuit 330 in the output unit 33.
- the signal conversion circuit 32 is supplied with monitor data MO from the output / current monitor circuit 330 in the output unit 33.
- the monitor data MO is converted from an analog voltage to a digital signal by an A / D converter in the signal conversion circuit 32.
- the monitor data MO converted into a digital signal is given to the control circuit 20 via the drive signal generation circuit 31.
- FIG. 6 is a diagram for explaining input / output signals of the output / current monitor circuit 330 in the output unit 33.
- the output / current monitor circuit 330 is supplied with the analog voltage Vs as the data signal DA from the signal conversion circuit 32.
- the analog voltage Vs is applied to the data signal line S via a buffer in the output / current monitor circuit 330.
- the output / current monitor circuit 330 has a function of acquiring the magnitude of the current flowing through the data signal line S as analog data (analog voltage) and AD conversion of the value of the analog data acquired at a certain timing. It has a function of holding over a certain period (that is, a sample hold function).
- the data acquired by the output / current monitor circuit 330 is given to the signal conversion circuit 32 as monitor data MO.
- the detailed configuration of the output / current monitor circuit 330 will be described later (see FIG. 1).
- the correction data storage unit 50 includes a TFT offset memory 51a, an OLED offset memory 51b, a TFT gain memory 52a, and an OLED gain memory 52b (see FIG. 2). These four memories may be physically one memory or physically different memories.
- the correction data storage unit 50 stores correction data used for correcting a video signal sent from the outside.
- the TFT offset memory 51a stores an offset value based on the detection result of the TFT characteristics as correction data.
- the OLED offset memory 51b stores an offset value based on the detection result of the OLED characteristic as correction data.
- the TFT gain memory 52a stores a gain value based on the detection result of the TFT characteristics as correction data.
- the OLED gain memory 52b stores a deterioration correction coefficient based on the detection result of the OLED characteristic as correction data.
- the number of offset values and gain values equal to the number of pixels in the display unit 10 are respectively stored in the TFT offset memory 51a and the TFT gain memory 52a as correction data based on the detection result of the TFT characteristics.
- offset values and deterioration correction coefficients equal to the number of pixels in the display unit 10 are used as correction data based on the detection results of the OLED characteristics, respectively, and an OLED offset memory 51b and an OLED gain memory 52b. Is remembered.
- one value may be stored in each memory for each of a plurality of pixels.
- the control circuit 20 Based on the monitor data MO given from the source driver 30, the control circuit 20 sets the offset value in the TFT offset memory 51a, the offset value in the OLED offset memory 51b, the gain value in the TFT gain memory 52a, and the OLED. The deterioration correction coefficient in the gain memory 52b is updated. Further, the control circuit 20 reads the offset value in the TFT offset memory 51a, the offset value in the OLED offset memory 51b, the gain value in the TFT gain memory 52a, and the deterioration correction coefficient in the OLED gain memory 52b. To correct the video signal. Data obtained by the correction is sent to the source driver 30 as a data signal DA.
- FIG. 1 is a circuit diagram showing the detailed configuration of the pixel circuit 11, the output / current monitor circuit 330, and the signal conversion circuit 32.
- the configuration and operation of these circuits will be described in detail.
- a pixel circuit 11 shown in FIG. 1 is a pixel circuit 11 of i rows and j columns.
- the pixel circuit 11 includes one organic EL element OLED, three transistors T1 to T3, and one capacitor Cst.
- the transistor T1 functions as an input transistor for selecting a pixel
- the transistor T2 functions as a drive transistor for controlling supply of current to the organic EL element OLED
- the transistor T3 controls whether to detect TFT characteristics or OLED characteristics. Functions as a monitor control transistor.
- the transistor T2 and the organic EL element OLED correspond to the characteristic detection target circuit element.
- the gate terminal corresponds to the control terminal
- the drain terminal corresponds to the first conduction terminal
- the source terminal corresponds to the second conduction terminal.
- the transistor T1 is provided between the data signal line S (j) and the gate terminal of the transistor T2.
- a gate terminal is connected to the scanning line G1 (i), and a source terminal is connected to the data signal line S (j).
- the transistor T2 is provided in series with the organic EL element OLED.
- the gate terminal is connected to the drain terminal of the transistor T1
- the drain terminal is connected to the high-level power supply line ELVDD
- the source terminal is connected to the anode terminal of the organic EL element OLED.
- the gate terminal is connected to the monitor control line G2 (i)
- the drain terminal is connected to the anode terminal of the organic EL element OLED
- the source terminal is connected to the data signal line S (j).
- capacitor Cst one end is connected to the gate terminal of the transistor T2, and the other end is connected to the drain terminal of the transistor T2.
- a first capacitor is realized by the capacitor Cst.
- the cathode terminal of the organic EL element OLED is connected to the low level power line ELVSS.
- the capacitor Cst is provided between the gate and the source of the transistor T2.
- the capacitor Cst is provided between the gate and the drain of the transistor T2.
- control for changing the potential of the data signal line S (j) is performed in a state in which the transistor T3 is turned on during one frame period. If the capacitor Cst is provided between the gate and source of the transistor T2, the gate potential of the transistor T2 also varies according to the variation of the potential of the data signal line S (j). Then, the on / off state of the transistor T2 may not be a desired state. Therefore, in the present embodiment, as shown in FIG. 1, a capacitor is connected between the gate and the drain of the transistor T2 so that the gate potential of the transistor T2 does not vary according to the variation in the potential of the data signal line S (j). Cst is provided.
- the transistors T1 to T3 in the pixel circuit 11 are all n-channel type.
- oxide TFTs thin film transistors using an oxide semiconductor as a channel layer are employed for the transistors T1 to T3.
- the oxide semiconductor layer is, for example, an In—Ga—Zn—O-based semiconductor layer.
- the oxide semiconductor layer includes, for example, an In—Ga—Zn—O-based semiconductor.
- An In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc).
- a TFT having an In—Ga—Zn—O-based semiconductor layer has high mobility (mobility more than 20 times that of an amorphous silicon TFT) and low leakage current (leakage less than 1/100 that of an amorphous silicon TFT). Therefore, it is suitably used as a driving TFT (the transistor T2) and a switching TFT (the transistor T1) in the pixel circuit.
- a driving TFT the transistor T2
- a switching TFT the transistor T1 in the pixel circuit.
- the In—Ga—Zn—O-based semiconductor may be amorphous, may include a crystalline portion, and may have crystallinity.
- a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
- Such a crystal structure of an In—Ga—Zn—O-based semiconductor is disclosed, for example, in Japanese Unexamined Patent Publication No. 2012-134475.
- the oxide semiconductor layer may include another oxide semiconductor instead of the In—Ga—Zn—O-based semiconductor.
- Zn—O based semiconductor ZnO
- In—Zn—O based semiconductor IZO (registered trademark)
- Zn—Ti—O based semiconductor ZTO
- Cd—Ge—O based semiconductor Cd—Pb—O based
- CdO cadmium oxide
- Mg—Zn—O based semiconductors In—Sn—Zn—O based semiconductors (eg, In 2 O 3 —SnO 2 —ZnO), In—Ga—Sn—O based semiconductors, etc. You may go out.
- the output / current monitor circuit 330 includes an operational amplifier 331, a capacitor 332, and three switches (switches 333, 334, and 335).
- the internal data line Sin (j) of the output / current monitor circuit 330 is connected to the data signal line S (j) via the switch 334.
- the operational amplifier 331 the inverting input terminal is connected to the internal data line Sin (j), and the non-inverting input terminal is supplied with the analog voltage Vs as the data signal DA.
- the capacitor 332 and the switch 333 are provided between the output terminal of the operational amplifier 331 and the internal data line Sin (j).
- the switch 333 is supplied with a control clock signal CLK1.
- the operational amplifier 331, the capacitor 332, and the switch 333 constitute an integrating circuit. Here, the operation of this integration circuit will be described.
- the switch 333 When the switch 333 is switched from the off state to the on state by the control clock signal CLK1, the charge accumulated in the capacitor 332 is discharged. Thereafter, when the switch 333 is switched from the on state to the off state, the capacitor 332 is charged based on the current flowing through the internal data line Sin (j). That is, the time integral value of the current flowing through the internal data line Sin (j) is accumulated in the capacitor 332. Thereby, the potential of the output terminal of the operational amplifier 331 changes according to the magnitude of the current flowing through the internal data line Sin (j). The output from the operational amplifier 331 is sent to the signal conversion circuit 32 as monitor data MO.
- the switch 334 is provided between the data signal line S (j) and the internal data line Sin (j).
- the switch 334 is supplied with a control clock signal CLK2.
- CLK2 By switching the state of the switch 334 based on the control clock signal CLK2, the electrical connection state between the data signal line S (j) and the internal data line Sin (j) is controlled.
- the control clock signal CKL2 if the control clock signal CKL2 is high level, the data signal line S (j) and the internal data line Sin (j) are electrically connected, and the control clock signal CKL2 is low level. If so, the data signal line S (j) and the internal data line Sin (j) are electrically disconnected.
- the switch 335 is provided between the data signal line S (j) and a predetermined control line CL.
- the switch 335 is supplied with the control clock signal CLK2B.
- the electrical connection state between the data signal line S (j) and the control line CL is controlled.
- the control clock signal CKL2B is at a high level, the data signal line S (j) and the control line CL are electrically connected. If the control clock signal CKL2B is at a low level, The data signal line S (j) and the control line CL are electrically disconnected.
- the switch 334 when the switch 334 is turned off, the data signal line S (j) and the internal data line Sin (j) are electrically disconnected. At this time, if the switch 333 is off, the potential of the internal data line Sin (j) is maintained.
- AD conversion is performed by the A / D converter 324 in the signal conversion circuit 32 while the potential of the internal data line Sin (j) is maintained in this way.
- a first control switch is realized by the switch 333
- a second control switch is realized by the switch 334
- a third control switch is realized by the switch 335.
- a second capacitor is realized by the capacitor 332.
- the signal conversion circuit 32 includes a D / A converter 321, a selector 322, an offset circuit 323, and an A / D converter 324.
- the D / A converter 321 converts the data signal DA that is a digital signal output from the drive signal generation circuit 31 into an analog voltage Vs.
- the A / D converter 324 is shared by a plurality of columns.
- a selector 322 is provided in the signal conversion circuit 32. The selector 322 receives monitor data MO from a plurality of output / current monitor circuits 330.
- the selector 322 sequentially outputs a plurality of given monitor data MO in a time division manner.
- the offset circuit 323 has a function (offset adjustment function) for making the input level to the A / D converter 324 the same when detecting the TFT characteristics and when detecting the OLED characteristics.
- the reason why the offset circuit 323 is provided is that Vm_TFT, which is a reference potential when detecting TFT characteristics, and Vm_oled, which is a reference potential when detecting OLED characteristics, are different potentials.
- the A / D converter 324 converts the analog voltage output from the offset circuit 323 into a digital signal. Note that the offset value used for offset adjustment is preferably made to depend on the value of Vm_TFT and the value of Vm_oled. As described above, regarding the components in the signal conversion circuit 32, one D / A converter 321 is provided for each column, and one selector 322, offset circuit 323, and A / D converter 324 are provided for each column. Is provided.
- Vm_TFT and Vm_oled have different sizes and countermeasures. Since Vm_TFT and Vm_oled are different in potential, if the offset circuit 323 is not provided, the input DC level to the A / D converter 324 changes between when the TFT characteristics are detected and when the OLED characteristics are detected. . For this reason, the resolution of AD conversion by the A / D converter 324 is wasted (not effectively used). Therefore, in the present embodiment, the above-described offset circuit 323 is provided. In the offset circuit 323, the input DC level to the A / D converter 324 is adjusted by Voffset1 when the TFT characteristics are detected and Voffset2 when the OLED characteristics are detected.
- the DC level at the time of AD conversion by the A / D converter 324 can be made substantially constant, and the resolution of AD conversion is effectively utilized.
- the case where there are two types of offset levels is described as an example, but the present invention is not limited to this.
- three types of offset levels may be prepared for OLED characteristic detection, and these may be switched and used.
- the control clock signal CLK1 applied to the switch 333 is controlled as shown in FIG. 7, for example, to change the length of the integration time (the OFF time of the control clock signal CLK1).
- the resolution of conversion can be used effectively. Thereby, it is possible to ensure a sufficient S / N ratio even when the measurement current is small.
- the A / D converter 324 is shared by a plurality of columns. This will be described in detail with reference to FIG. FIG. 8 shows an example where the source driver 30 has the output unit 33 of 1440 channels (that is, when 1440 data signal lines S are provided).
- one A / D converter 324 is shared by 144 columns. Therefore, one selector 322 is provided for every 144 columns. Each selector 322 is supplied with monitor data MO from 144 output / current monitor circuits 330. Each selector 322 sequentially provides 144 monitor data MOs to the offset circuit 323 in time division.
- the monitor data MO given to the offset circuit 323 is given to the A / D converter 324 after adjusting the input level.
- the value of analog data is held throughout the period during which AD conversion is performed by the above-described sample hold function.
- analog data values acquired at the same timing in all columns are sequentially supplied to the A / D converter 324.
- the monitor data MO after AD conversion is sent to the control circuit 20 via the logic unit 311 in the drive signal generation circuit 31.
- one A / D converter 324 is shared by 144 columns, but the present invention is not limited to this.
- the number of columns sharing one A / D converter 324 may be determined according to the capability of the A / D converter 324, that is, the sampling frequency of the A / D converter 324. The greater the sampling frequency of the A / D converter 324, the greater the number of columns sharing one A / D converter 324.
- driving method> ⁇ 3.1 Overview> Next, a driving method in the present embodiment will be described.
- detection of TFT characteristics and OLED characteristics in one row is performed for each frame.
- an operation for detecting the TFT characteristic and the OLED characteristic (hereinafter referred to as “characteristic detection operation”) is performed for the monitor row, and a normal operation is performed for the non-monitor row. That is, when the frame in which the TFT characteristic and the OLED characteristic for the first row are detected is defined as the (k + 1) th frame, the operation of each row changes as shown in FIG.
- the correction data in the correction data storage unit 50 is updated using the detection results. Then, the video signal is corrected using the correction data stored in the correction data storage unit 50.
- FIG. 10 is a timing chart for explaining the operation of the pixel circuit 11 included in the monitor row (the pixel circuit 11 in the i row and j column).
- “one frame period” is represented with reference to the starting point of the first selection period of the i-th row in a frame in which the i-th row is a monitor row.
- a period other than one horizontal scanning period THm in the monitor row in one frame period is referred to as “light emission period”.
- the light emission period is denoted by reference sign TL. As shown in FIG.
- one horizontal scanning period THm for a monitor row is a period during which preparation for detecting TFT characteristics and OLED characteristics is performed in the monitor row (hereinafter referred to as “detection preparation period”) Ta, and TFT characteristics.
- a period during which current measurement for detecting the current (hereinafter referred to as “TFT characteristic detection period”) Tb and a period during which current measurement for detecting the OLED characteristic is performed (hereinafter referred to as “OLED characteristic detection period”). ) Tc and a period (hereinafter, referred to as “light emission preparation period”) Td in which the organic EL element OLED is prepared to emit light in the monitor row.
- TFT characteristic detection period A period during which current measurement for detecting the current
- OLED characteristic detection period a period during which current measurement for detecting the OLED characteristic is performed
- Tc and a period (hereinafter, referred to as “light emission preparation period”) Td in which the organic EL element OLED is prepared to emit light in the monitor row.
- the scanning line G1 (i) is in an active state
- the monitor control line G2 (i) is in an inactive state
- the potential Vmg is applied to the data signal line S (j).
- the scanning line G1 (i) is in an inactive state
- the monitor control line G2 (i) is in an active state
- the potential Vm_TFT is applied to the data signal line S (j).
- the OLED characteristic detection period Tc the scanning line G1 (i) is in an inactive state
- the monitor control line G2 (i) is in an active state
- the potential Vm_oled is applied to the data signal line S (j).
- the scanning line G1 (i) is in an active state
- the monitor control line G2 (i) is in an inactive state
- the data signal line S (j) is included in the monitor row.
- a data potential D (i, j) corresponding to the target luminance of the EL element OLED is applied.
- the scanning line G1 (i) and the monitor control line G2 (i) are inactive.
- the potential Vm_TFT is applied from the power supply circuit to the control line CL
- the potential Vm_oled is applied from the power supply circuit to the control line CL.
- FIG. 12 is a timing chart for explaining details of one horizontal scanning period THm for the monitor row.
- the characteristic detection processing period is realized by this one horizontal scanning period THm.
- the TFT characteristic detection period Tb is composed of periods Tb1 to Tb6, and the OLED characteristic detection period Tc is composed of periods Tc1 to Tc6.
- the data signal line charging period is realized by the periods Tb1, Tb4, Tc1, and Tc4, and the monitoring period is realized by the periods Tb2, Tb5, Tc2, and Tc5, and the periods Tb3, Tb6, Tc3,
- And AD conversion period is realized by Tc6.
- the scanning line G1 (i) is in an active state, and the monitor control line G2 (i) is maintained in an inactive state.
- the transistor T1 is turned on, and the transistor T3 is maintained in the off state.
- the control clock signals CLK1, CLK2, and CLK2B are at a high level, a high level, and an off level, respectively. Therefore, the switches 333, 334, and 335 are turned on, on, and off, respectively.
- the potential Vmg is applied to the data signal line S (j) via the operational amplifier 331.
- the capacitor Cst is charged by writing based on the potential Vmg, and the transistor T2 is turned on.
- the drive current is supplied to the organic EL element OLED through the transistor T2, as indicated by the arrow 72 in FIG.
- the organic EL element OLED emits light with a luminance corresponding to the drive current.
- the organic EL element OLED emits light for a very short time.
- the scanning line G1 (i) is in an inactive state, and the monitor control line G2 (i) is in an active state.
- the transistor T1 is turned off and the transistor T3 is turned on. Note that the transistor T1 is maintained in the off state and the transistor T3 is maintained in the on state throughout the TFT characteristic detection period Tb.
- the potential Vm_TFT is applied to the data signal line S (j) through the operational amplifier 331. As described above, in the period Tb1, charging is performed so that the potential of the data signal line S (j) becomes Vm_TFT. As will be described later, in the period Tc1 within the OLED characteristic detection period Tc, charging is performed so that the potential of the data signal line S (j) becomes Vm_oled.
- the control clock signal CLK1 changes from the high level to the low level.
- the switch 333 is turned off.
- the threshold voltage of the transistor T2 obtained based on the offset value stored in the TFT offset memory 51a is Vth (T2)
- the potential Vmg is established so that the following expressions (1) and (2) are satisfied.
- the value of the potential Vm_TFT, and the value of the potential Vm_oled are set.
- the above expressions (1), (3), and ( A potential Vm_TFT that satisfies 4) is applied to the data signal line S (j). From the above equation (1), the transistor T2 is turned on in the period Tb2. Further, from the above formulas (3) and (4), no current flows through the organic EL element OLED in the period Tb2.
- the current flowing through the transistor T2 is output to the data signal line S (j) via the transistor T3.
- the switch 334 is on.
- electric charge is accumulated in the capacitor 332 according to the magnitude (time integration value) of the current (sink current) output to the data signal line S (j) in the period Tb2, and the potential of the output terminal of the operational amplifier 331 is Change.
- the control clock signal CLK2 changes from high level to low level.
- the switch 334 is turned off, and the data signal line S (j) and the internal data line Sin (j) are electrically disconnected.
- analog data indicating the magnitude of the current of the data signal line S (j) at the end of the period Tb2 is held in the output / current monitor circuit 330.
- the selector 322 sequentially outputs analog data (monitor data MO) of a plurality of columns, so that each A / D converter 324 sequentially performs AD conversion on the analog data of the plurality of columns. Is called.
- the control clock signal CLK2B changes from the low level to the high level.
- the switch 335 is turned on, and the data signal line S (j) and the control line CL are electrically connected.
- charging is performed so that the potential of the data signal line S (j) becomes Vm_TFT. In this manner, the data signal line S (j) is charged through the control line CL during the period during which AD conversion is performed.
- the control clock signal CLK1 changes from low level to high level
- the control clock signal CLK2 changes from low level to high level
- the control clock signal CLK2B changes from high level to low level.
- the switches 333, 334, and 335 are turned on, on, and off, respectively.
- the switch 333 and the switch 334 are turned on, and the potential Vm_TFT is applied to the data signal line S (j) through the operational amplifier 331.
- recharging is performed so that the potential of the data signal line S (j) becomes Vm_TFT.
- the data signal line S (j) is charged through the control line CL in the period Tb3. Therefore, the period Tb4 may be a very short period.
- the same operation as in the period Tb2 is performed.
- the period Tb6 (AD conversion period) an operation similar to that in the period Tb3 is performed.
- the magnitude of the current flowing between the drain and the source of the transistor T2 is repeatedly measured in a state where the voltage between the gate and the source of the transistor T2 is set to a predetermined magnitude (Vmg ⁇ Vm_TFT). Is detected.
- the control clock signal CLK1 changes from low level to high level
- the control clock signal CLK2 changes from low level to high level
- the control clock signal CLK2B changes from high level to low level.
- the switches 333, 334, and 335 are turned on, on, and off, respectively.
- the transistor T1 is maintained in the off state and the transistor T3 is maintained in the on state through the OLED characteristic detection period Tc.
- the potential Vm_oled is supplied to the data signal line S (j) through the operational amplifier 331. As described above, in the period Tc1, charging is performed so that the potential of the data signal line S (j) becomes Vm_oled.
- the control clock signal CLK1 changes from the high level to the low level.
- the switch 333 is turned off.
- the value of the potential Vm_oled is set so that the above equation (2) and the following equation (5) are satisfied.
- the value of the potential Vm_oled is set so that the following expression (6) is established.
- the potential Vm_oled satisfying the above equations (2), (5), and (6) is applied to the data signal line S (j). From the above equations (2) and (6), the transistor T2 is turned off in the period Tc2. From the above equation (5), a current flows through the organic EL element OLED in the period Tc2.
- the control clock signal CLK2 changes from the high level to the low level.
- the switch 334 is turned off, and the data signal line S (j) and the internal data line Sin (j) are electrically disconnected.
- analog data indicating the magnitude of the current of the data signal line S (j) at the end of the period Tc2 is held in the output / current monitor circuit 330.
- the selector 322 sequentially outputs analog data (monitor data MO) of a plurality of columns, so that each A / D converter 324 sequentially performs AD conversion on the analog data of the plurality of columns. Is called.
- the control clock signal CLK2B changes from the low level to the high level. Accordingly, as in the period Tb3, the switch 335 is turned on, and the data signal line S (j) and the control line CL are electrically connected. As a result, in the period Tc3, charging is performed so that the potential of the data signal line S (j) becomes Vm_oled. In this manner, the data signal line S (j) is charged through the control line CL during the period during which AD conversion is performed.
- the control clock signal CLK1 changes from low level to high level
- the control clock signal CLK2 changes from low level to high level
- the control clock signal CLK2B changes from high level to low level.
- the switches 333, 334, and 335 are turned on, on, and off, respectively.
- the switch 333 and the switch 334 are turned on, and the potential Vm_oled is applied to the data signal line S (j) through the operational amplifier 331.
- recharging is performed so that the potential of the data signal line S (j) becomes Vm_oled.
- the data signal line S (j) is charged through the control line CL in the period Tc3.
- the period Tc4 may be a very short period.
- the same operation as in the period Tc2 is performed.
- the period Tc6 (AD conversion period) an operation similar to that in the period Tc3 is performed.
- the magnitude of the current flowing through the organic EL element OLED is repeated with the voltage between the anode (anode) and the cathode (cathode) of the organic EL element OLED set to a predetermined level (Vm_oled-ELVSS). Measured and OLED characteristics are detected.
- the current measurable range in the output / current monitor circuit 330, etc. Is also determined.
- the scanning line G1 (i) is activated, and the monitor control line G2 (i) is deactivated. Accordingly, the transistor T1 is turned on and the transistor T3 is turned off.
- the control clock signal CLK1 changes from low level to high level
- the control clock signal CLK2 changes from low level to high level
- the control clock signal CLK2B changes from high level to low level.
- the switches 333, 334, and 335 are turned on, on, and off, respectively.
- the data potential D (i, j) corresponding to the target luminance is applied to the data signal line S (j) via the operational amplifier 331.
- the capacitor Cst is charged by writing based on the data potential D (i, j), and the transistor T2 is turned on.
- the drive current is supplied to the organic EL element OLED via the transistor T2.
- the organic EL element OLED emits light with a luminance corresponding to the drive current.
- the scanning line G1 (i) is in an inactive state, and the monitor control line G2 (i) is maintained in an inactive state. Accordingly, the transistor T1 is turned off, and the transistor T3 is maintained in the off state. Although the transistor T1 is turned off, since the capacitor Cst is charged by writing based on the data potential D (i, j) corresponding to the target luminance during the light emission preparation period Td, the transistor T2 is maintained in the on state.
- a drive current is supplied to the organic EL element OLED via the transistor T2, as indicated by an arrow 76 in FIG.
- the organic EL element OLED emits light with a luminance corresponding to the drive current. That is, in the light emission period TL, the organic EL element OLED emits light according to the target luminance.
- the gate potential of the transistor T2 is ideally held. However, actually, the gate potential of the transistor T2 varies from the written potential due to secondary effects such as charge injection by the transistor T1, feedthrough of the scanning line G1 (i), and charge sharing with the parasitic capacitance. Arise.
- the process of causing the organic EL element OLED to emit light is performed in the same manner as a general organic EL display device.
- the monitor row processing for detecting TFT characteristics and OLED characteristics is performed, and then processing for causing the organic EL element OLED to emit light is performed. Accordingly, as can be understood from FIG. 19, the length of the light emission period in the monitor row is shorter than the length of the light emission period in the non-monitor row. For this reason, with respect to the magnitude of the data potential D (i, j) applied to the data signal line S (j) during the light emission preparation period Td, the integrated luminance within the frame period becomes equal to the luminance appearing in the non-monitor row.
- a data potential corresponding to a gradation voltage slightly higher than the gradation voltage in the non-monitor row is supplied to the data signal line S (j) in the light emission preparation period Td.
- the target organic EL element is set to the non-monitor row in the light emission preparation period Td.
- a data potential corresponding to a gradation voltage higher than the gradation voltage in the case of being included is applied to the data signal line S (j) by the source driver 30. Thereby, the deterioration of display quality is suppressed.
- current measurement for detecting TFT characteristics is performed twice during the TFT characteristic detection period Tb, and current measurement for detecting OLED characteristics is performed twice during the OLED characteristic detection period Tc.
- the present invention is not limited to this.
- the current measurement for detecting the TFT characteristic and the current measurement for detecting the OLED characteristic may be performed once each, or three times or more each. It may be done.
- the number of times of current measurement for detecting TFT characteristics may be different from the number of times of current measurement for detecting OLED characteristics.
- the potential Vm_TFT is applied to the data signal line S (j) through the period indicated by Tb to Tc in FIG. 10, and in the frame period in which the OLED characteristic is detected. , The potential Vm_oled is applied to the data signal line S (j) through a period indicated by Tb to Tc in FIG. By doing so, sufficient time is secured for transferring the monitor data MO obtained by AD conversion to the control circuit 20 after AD conversion.
- the monitor row changes every time the frame changes as shown in FIG. 9, but the present invention is not limited to this.
- the same line may be used as a monitor line over a plurality of frames. For example, it is the same over a total of four frames including two frames for detecting characteristics of the transistor T2 (driving transistor) with two types of Vm_TFT and two frames for detecting characteristics of the organic EL element OLED (electro-optical element) with two types of Vm_oled.
- the line can be a monitor line.
- the same row may be used as a monitor row over a plurality of frames with the same monitor voltage (Vm_TFT, Vm_oled).
- the present invention is not limited to this.
- multiple lines may be set as monitor lines in each frame, and the characteristics of all lines may be set immediately after the panel power is turned on, at any time during the power-off period, or during the non-display period. Detection may be performed continuously.
- FIG. 20 is a flowchart for explaining a procedure for updating correction data in the correction data storage unit 50. Here, attention is focused on correction data corresponding to one pixel.
- a TFT characteristic is detected during the TFT characteristic detection period Tb (step S110).
- an offset value and a gain value for correcting the video signal are obtained.
- the offset value obtained in step S110 is stored in the TFT offset memory 51a as a new offset value (step S120).
- the gain value obtained in step S110 is stored as a new gain value in the TFT gain memory 52a (step S130).
- the OLED characteristic is detected in the OLED characteristic detection period Tc (step S140).
- an offset value and a deterioration correction coefficient for correcting the video signal are obtained.
- the offset value obtained in step S140 is stored in the OLED offset memory 51b as a new offset value (step S150).
- the deterioration correction coefficient obtained in step S140 is stored in the OLED gain memory 52b as a new deterioration correction coefficient (step S160).
- the correction data corresponding to one pixel is updated.
- detection of TFT characteristics and OLED characteristics for one row in each frame is performed. Therefore, m offset values in the TFT offset memory 51a, and in the TFT gain memory 52a per frame period. M gain values, m offset values in the OLED offset memory 51b, and m deterioration correction coefficients in the OLED gain memory 52b are updated.
- the characteristic data is realized by data (offset value, gain value, deterioration correction coefficient) obtained based on the detection results in step S110 and step S140.
- the magnitude of the current flowing through the organic EL element OLED is measured based on a constant voltage (Vm_oled-ELVSS).
- Vm_oled-ELVSS a constant voltage
- the data in the OLED offset memory 51b and the OLED gain memory 52b are updated so that the smaller the detected current is, the larger the offset value is and the larger the deterioration correction coefficient is.
- the control circuit 20 is provided with an LUT 211, a multiplier 212, a multiplier 213, an adder 214, an adder 215, and a multiplier 216 as components for correcting the video signal. Yes. Further, the control circuit 20 is provided with a multiplier 221 and an adder 222 as components for correcting the potential Vm_oled applied to the data signal line S during the OLED characteristic detection period Tc.
- the CPU 230 in the control circuit 20 controls the operation of each of the above components, and each memory in the correction data storage unit 50 (TFT offset memory 51a, TFT gain memory 52a, OLED offset memory 51b, and OLED gain memory). 52b), update / read data to / from the non-volatile memory 70, exchange data with the source driver 30, and the like.
- the video signal sent from the outside is corrected as follows.
- gamma correction is performed on a video signal transmitted from the outside using the LUT 211. That is, the gradation P indicated by the video signal is converted to the control voltage Vc by gamma correction.
- the multiplier 212 receives the control voltage Vc and the gain value B1 read from the TFT gain memory 52a, and outputs a value “Vc ⁇ B1” obtained by multiplying them.
- the multiplier 213 receives the value “Vc ⁇ B1” output from the multiplier 212 and the deterioration correction coefficient B2 read from the OLED gain memory 52b and multiplies them to obtain the value “Vc ⁇ B1 ⁇ B2”. "Is output.
- the adder 214 receives the value “Vc ⁇ B1 ⁇ B2” output from the multiplier 213 and the offset value Vt1 read from the TFT offset memory 51a, and adds the values “Vc ⁇ B1 ⁇ B2”.
- B1 ⁇ B2 + Vt1 ′′ is output.
- the adder 215 receives the value “Vc ⁇ B1 ⁇ B2 + Vt1” output from the adder 214 and the offset value Vt2 read from the OLED offset memory 51b and adds the values “Vc ⁇ B1 ⁇ B2 + Vt1 + Vt2 ′′ is output.
- the multiplier 216 receives the value “Vc ⁇ B1 ⁇ B2 + Vt1 + Vt2” output from the adder 215 and the coefficient Z for compensating for the attenuation of the data potential caused by the parasitic capacitance in the pixel circuit 11, and multiplies them.
- the obtained value “Z (Vc ⁇ B1 ⁇ B2 + Vt1 + Vt2)” is output.
- the value “Z (Vc ⁇ B1 ⁇ B2 + Vt1 + Vt2)” obtained as described above is sent from the control circuit 20 to the source driver 30 as the data signal DA.
- the potential Vmg applied to the data signal line S during the detection preparation period Ta is also corrected by the same process as that for the video signal. Note that the multiplication unit 216 that multiplies the value output from the addition unit 215 by the coefficient Z for compensating for the attenuation of the data potential is not necessarily provided.
- the potential Vm_oled applied to the data signal line S in the OLED characteristic detection period Tc is corrected as follows.
- the multiplier 221 receives pre_Vm_oled (Vm_oled before correction) and the deterioration correction coefficient B2 read from the OLED gain memory 52b, and outputs a value “pre_Vm_oled ⁇ B2” obtained by multiplying them.
- the adder 222 receives the value “pre_Vm_oled ⁇ B2” output from the multiplier 221 and the offset value Vt2 read from the OLED offset memory 51b, and adds the values “pre_Vm_oled ⁇ B2 + Vt2”. Is output.
- the value “pre_Vm_oled ⁇ B2 + Vt2” obtained as described above is sent from the control circuit 20 to the source driver 30 as data indicating the potential Vm_oled of the data signal line S during the OLED characteristic detection period Tc.
- FIG. 22 is a flowchart for explaining an outline of operations related to detection of TFT characteristics and OLED characteristics.
- the TFT characteristic is detected during the TFT characteristic detection period Tb (step S210).
- the TFT offset memory 51a and the TFT gain memory 52a are updated using the detection result in step S210 (step S220).
- the OLED characteristic is detected during the OLED characteristic detection period Tc (step S230).
- the OLED offset memory 51b and the OLED gain memory 52b are updated (step S240).
- the video signal sent from the outside is corrected using the correction data stored in the TFT offset memory 51a, TFT gain memory 52a, OLED offset memory 51b, and OLED gain memory 52b (step). S250).
- the characteristic detection step is realized by steps S210 and S230
- the correction data storage step is realized by steps S220 and S240
- the video signal correction step is realized by step S250.
- the data potential based on the video signal corrected in this way is applied to the data signal line S, when the organic EL element OLED in each pixel circuit 11 is caused to emit light, the deterioration of the driving transistor (transistor T2) and organic A drive current having such a magnitude as to compensate for the deterioration of the EL element OLED is supplied to the organic EL element OLED (see FIG. 23). Further, as shown in FIG. 24, it is possible to compensate for burn-in by increasing the current in accordance with the deterioration level of the pixel with the least deterioration.
- the data signal line S in the present embodiment is not only used as a signal line for transmitting a luminance signal for causing the organic EL element OLED in each pixel circuit 11 to emit light with a desired luminance, but also for detecting characteristics.
- a signal line (a signal line that gives control potentials (Vmg, Vm_TFT, Vm_oled) for characteristic detection to the pixel circuit 11 and a signal line that is a current that represents the characteristic and that can be measured by the output / current monitor circuit 330) Also used as That is, it is not necessary to provide a new signal line in the display unit 10 in order to detect TFT characteristics and OLED characteristics. Therefore, it is possible to simultaneously compensate for both the deterioration of the drive transistor (transistor T2) and the deterioration of the organic EL element OLED while suppressing an increase in circuit scale.
- the output / current monitor circuit 330 provided in each column has a function (sample hold function) for holding analog data representing TFT characteristics and OLED characteristics.
- An A / D converter 324 for converting the analog data into digital data using the sample and hold function is shared by a plurality of columns.
- the output / current monitor circuit 330 also has a switch 334 for controlling the connection state between the data signal line S and the internal data line Sin and the connection state between the data signal line S and the predetermined control line CL. Switch 335 is provided.
- the data signal line S and the internal data line Sin are electrically disconnected, and a predetermined potential (from the control line CL to the data signal line S is set). Vm_TFT or Vm_oled). This prevents the potential of the data signal line S from fluctuating during AD conversion due to sharing of the A / D converter 324.
- the data signal line S is recharged in a very short time, it is possible to repeatedly perform current measurement for characteristic detection. Thereby, the effect that a sufficient S / N ratio can be secured is obtained.
- oxide TFTs are employed for the transistors T1 to T3 in the pixel circuit 11. Also from this viewpoint, an effect that a sufficient S / N ratio can be secured is obtained. This will be described below.
- a TFT having an In—Ga—Zn—O-based semiconductor layer is referred to as an “In—Ga—Zn—O—TFT” here.
- In-Ga-Zn-O-TFT and LTPS (Low Temperature-Polysilicon) -TFT are compared, In-Ga-Zn-O-TFT has much smaller off-current than LTPS-TFT.
- the off-current is about 1 pA at maximum.
- an In—Ga—Zn—O—TFT is used for the transistor T3 in the pixel circuit 11
- the off-current is about 10 fA at maximum. Therefore, for example, the off-current for 1000 rows is about 1 nA at the maximum when LTPS-TFT is employed, and is about 10 pA at the maximum when In—Ga—Zn—O-TFT is employed.
- the detected current is about 10 to 100 nA in any case.
- each data signal line S is connected to the transistors T3 in the pixel circuits 11 in all rows of the corresponding column.
- the S / N ratio of the data signal line S when the characteristic detection is performed depends on the total leakage current of the transistors T3 in the non-monitoring row.
- the S / N ratio of the data signal line S when the characteristic detection is performed is represented by “detection current / (leakage current ⁇ number of non-monitor rows)”. From the above, for example, in the organic EL display device having the “Landscape FHD” display unit 10, the S / N ratio is about 10 when the LTPS-TFT is employed, whereas the In— When Ga—Zn—O—TFT is employed, the S / N ratio is about 1000. Thus, in the present embodiment, a sufficient S / N ratio can be ensured when performing current detection.
- the potential Vm_oled determined for each pixel does not necessarily need to be supplied from the control line CL to the data signal line S. Therefore, in this modification, a constant potential close to the potential Vm_oled is applied from the power supply circuit to the control line CL during the OLED characteristic detection period Tc. Thus, the constant potential is applied from the control line CL to the data signal line S during the OLED characteristic detection period Tc.
- the potential applied to the control line CL during the OLED characteristic detection period Tc may be exactly the same as the potential Vm_oled as long as it is substantially equal to the potential Vm_oled determined for each pixel. However, it may be a potential close to the potential Vm_oled.
- the potential Vm_oled is applied from the control line CL to the data signal line S in the period (period Tc3 and period Tc6) in which AD conversion is performed within the OLED characteristic detection period Tc.
- the present invention is not limited to this.
- a configuration in which the data signal line S is in a high impedance state during the AD conversion period within the OLED characteristic detection period Tc (the configuration of this modification) can also be employed.
- the driving method in this modification will be described focusing on differences from the above embodiment.
- FIG. 25 is a timing chart for explaining the operation of the pixel circuit 11 (referred to as the pixel circuit 11 of i rows and j columns) included in the monitor row in this modification.
- the waveform of the monitor control line G2 (i) in the OLED characteristic detection period Tc is different between the above embodiment and the present modification.
- FIG. 26 is a timing chart for explaining details of one horizontal scanning period THm for a monitor row in the present modification.
- the characteristic detection operation in the present modification will be described with reference to FIG.
- the detection preparation period Ta, the TFT characteristic detection period Tb, and the light emission preparation period Td are the same as those in the above-described embodiment, and thus the description thereof is omitted.
- the OLED characteristic detection period Tc is composed of periods Tc1 to Tc6.
- the period Tc1 data signal line charging period
- the period Tc2 monitoring period
- the same operation as in the above embodiment is performed.
- the control clock signal CLK2 changes from the high level to the low level.
- the switch 334 is turned off, and the data signal line S (j) and the internal data line Sin (j) are electrically disconnected.
- each A / D converter 324 sequentially performs AD conversion on a plurality of columns of analog data.
- the control clock signal CLK2B is maintained at a low level, and the monitor control line G2 (i) is inactive. Accordingly, the switch 335 is maintained in the off state, and the transistor T3 is also in the off state. As described above, in the period Tc3, the data signal line S (j) is in a high impedance state. In this manner, in the period Tc3, the outflow of charges from the data signal line S (j) is prevented, and the potential of the data signal line S (j) is maintained at a potential close to Vm_oled.
- the data signal line S (j) is recharged in the same manner as in the above embodiment.
- the data signal line S (j) is in a high impedance state, and the potential of the data signal line S (j) is maintained at a potential close to Vm_oled. Therefore, in the period Tc4, recharging is performed in a very short time so that the potential of the data signal line S (j) becomes Vm_oled.
- Tc5 monitoring period
- an operation similar to that in the period Tc2 is performed
- the period Tc6 AD conversion period
- the data signal line S is in a high impedance state during the AD conversion performed by the A / D converter 324 in the OLED characteristic detection period Tc. Further, during the period during which AD conversion is performed by the A / D converter 324 in the TFT characteristic detection period Tb, a predetermined potential (Vm_TFT) is applied from the control line CL to the data signal line S as in the above embodiment. .
- Vm_TFT a predetermined potential
- recharge of the data signal line S is performed in a very short time. Therefore, current measurement for characteristic detection can be repeatedly performed, and a sufficient S / N ratio can be ensured.
- the transistor T3 can be turned off and the data signal line S (j) can be in a high-impedance state even during a period during which AD conversion is performed within the TFT characteristic detection period Tb (period Tb3 and period Tb6).
- the circuit configuration in this case is a configuration in which the control line CL and the switch 335 are deleted from the configuration shown in FIG. 1 (see FIG. 27).
- the transistor T2 since the transistor T2 is in the on state, a current is supplied to the organic EL element OLED and the organic EL element OLED emits light.
- the source potential of the transistor T2 varies greatly, it is necessary to lengthen the recharge period after AD conversion.
- the potential Vm_TFT is applied from the control line CL to the data signal line S (j) while maintaining the transistor T3 as in the above embodiment. It is preferable to give.
- adopted is acquired.
- one frame period includes a vertical scanning period in which video signals are sequentially written to pixels in the order from the first row to the last row, and video signal writing is performed on the last row.
- a vertical blanking period vertical synchronization period which is a period provided for returning to the first row.
- the vertical scanning period Tv and the vertical blanking period Tf are alternately repeated.
- the detection of the TFT characteristic and the detection of the OLED characteristic are performed during the vertical scanning period Tv.
- the present invention is not limited to this, and a configuration in which the detection of the TFT characteristics and the detection of the OLED characteristics are performed during the vertical blanking period Tf (the configuration of this modification) can also be adopted.
- the vertical blanking period Tf of the (k + 1) frame is Detection of TFT characteristics and OLED characteristics for the second row is performed, and detection of TFT characteristics and OLED characteristics for the third row is performed in the vertical blanking period Tf of the (k + 3) frame, and (k + n)
- the TFT characteristic and the OLED characteristic for the nth row are detected. That is, the monitor row changes every time the frame changes.
- the vertical scanning period Tv an operation similar to that of a general organic EL display device is performed.
- FIG. 29 is a timing chart for explaining the operation during the vertical blanking period Tf of the pixel circuit 11 (referred to as the pixel circuit 11 of i rows and j columns) included in the monitor row in this modification.
- a part of the vertical blanking period Tf includes a detection preparation period Ta, a TFT characteristic detection period Tb, an OLED characteristic detection period Tc, and a light emission preparation period Td. It is a characteristic detection processing period.
- FIG. 30 is a timing chart for explaining the details of the vertical blanking period Tf in this modification.
- the detection preparation period Ta, the TFT characteristic detection period Tb (Tb1 to Tb6), and the light emission preparation period Td in the vertical blanking period Tf in this modification are respectively detected in the above embodiment. Operations similar to those in the preparation period Ta, the TFT characteristic detection period Tb (Tb1 to Tb6), and the light emission preparation period Td are performed (the same applies to the second modified example).
- the OLED characteristic detection period Tc (Tc1 to Tc6) in the vertical blanking period Tf in the present modification an operation similar to that in the OLED characteristic detection period Tc (Tc1 to Tc6) in the second modification is performed.
- writing according to the target luminance is performed in the selection period in the vertical scanning period Tv, and the light emission of the organic EL element OLED based on the writing is continued for almost one frame period.
- the monitor row writing is performed during the selection period in the vertical scanning period Tv, but light emission of the organic EL element OLED is temporarily interrupted when the vertical blanking period Tf is reached. Therefore, writing based on the data potential D (i, j) is performed in the light emission preparation period Td in the vertical blanking period Tf so that the organic EL element OLED emits light in the monitor row after the vertical blanking period Tf ends.
- the organic EL element OLED emits light based on writing in the selection period in the vertical scanning period Tv of the preceding frame. Thereafter, the organic EL element OLED is temporarily turned off during the vertical blanking period Tf. Thereafter, the organic EL element OLED emits light based on writing in the light emission preparation period Td in the vertical blanking period Tf.
- the increase in memory capacity is slight.
- the light emission of the organic EL elements OLED in the monitor row is temporarily interrupted during the vertical blanking period Tf, during the selection period (the period indicated by Tz in FIG. 31) during the vertical scanning period Tv.
- a data potential corresponding to a gradation voltage larger than the original gradation voltage may be applied to the data signal line S in advance.
- the target organic EL element is not included in the selection period in the vertical scanning period Tv.
- a data potential corresponding to a gradation voltage higher than the gradation voltage in the case of being included in a non-monitor row may be applied to the data signal line S (j) by the source driver 30. Thereby, the deterioration of display quality is suppressed.
- the organic EL display device to which the present invention is applicable is not limited to the one provided with the pixel circuit 11 exemplified in the above embodiment.
- the pixel circuit may have a configuration other than the configuration illustrated in the above embodiment as long as it includes at least an electro-optical element (organic EL element OLED) controlled by current, transistors T1 to T3, and a capacitor Cst. .
Abstract
Description
電流によって輝度が制御される電気光学素子および前記電気光学素子に供給すべき電流を制御するための駆動トランジスタをそれぞれが含むn×m個(nおよびmは2以上の整数)の画素回路からなるn行×m列の画素マトリクスと、前記画素マトリクスの各行に対応するように設けられた走査線と、前記画素マトリクスの各行に対応するように設けられたモニタ制御線と、前記画素マトリクスの各列に対応するように設けられたデータ信号線とを有する表示部と、
フレーム期間に前記電気光学素子または前記駆動トランジスタの少なくとも一方を含む特性検出対象回路素子の特性を検出する特性検出処理が行われるよう、かつ、各電気光学素子が目標輝度に応じて発光するよう、前記走査線,前記モニタ制御線,および前記データ信号線を駆動する画素回路駆動部と、
前記特性検出処理の結果に基づいて得られる特性データを、映像信号を補正するための補正データとして記憶する補正データ記憶部と、
前記補正データ記憶部に記憶されている補正データに基づいて前記映像信号を補正して、前記n×m個の画素回路に供給すべきデータ信号を生成する映像信号補正部と
を備え、
各画素回路は、
前記電気光学素子と、
前記走査線に制御端子が接続され、前記駆動トランジスタの制御端子に第1導通端子が接続され、前記データ信号線に第2導通端子が接続された入力トランジスタと、
駆動電源電位が第1導通端子に与えられた前記駆動トランジスタと、
前記モニタ制御線に制御端子が接続され、前記駆動トランジスタの第2導通端子および前記電気光学素子の陽極に第1導通端子が接続され、前記データ信号線に第2導通端子が接続されたモニタ制御トランジスタと、
前記駆動トランジスタの制御端子の電位を保持するため、一端が前記駆動トランジスタの制御端子に接続された第1のコンデンサと
を含み、
前記画素回路駆動部は、
前記データ信号を前記データ信号線に印加する機能および前記データ信号線に流れている電流の大きさに応じたデータを前記特性データの元となるモニタデータとして取得する機能を有する出力/電流モニタ回路と、
前記モニタデータをアナログ値からデジタル値に変換するAD変換回路と
を含み、
前記出力/電流モニタ回路は、
前記データ信号線に接続された内部データ線と、
前記データ信号が非反転入力端子に与えられ、前記内部データ線に反転入力端子が接続されたオペアンプと、
前記内部データ線に一旦が接続され、前記オペアンプの出力端子に他端が接続された第2のコンデンサと、
前記内部データ線に一旦が接続され、前記オペアンプの出力端子に他端が接続された第1の制御スイッチと、
前記データ信号線に一端が接続され、前記内部データ線に他端が接続された第2の制御スイッチと
を含み、
前記AD変換回路は、複数個の前記出力/電流モニタ回路につき1個設けられ、
フレーム期間において前記特性検出処理が行われる行をモニタ行と定義し、前記モニタ行以外の行を非モニタ行と定義したとき、フレーム期間には、前記モニタ行において前記特性検出対象回路素子の特性を検出する準備が行われる検出準備期間と、前記データ信号線に流れている電流を測定することによって前記特性検出対象回路素子の特性を検出する電流測定期間と、前記モニタ行において前記電気光学素子を発光させる準備が行われる発光準備期間とからなる特性検出処理期間が含まれ、
前記電流測定期間には、前記特性検出対象回路素子の特性に応じた大きさの電流が前記データ信号線に流れるように前記データ信号線を充電するデータ信号線充電期間と、前記データ信号線に流れている電流の時間積分値を前記第2のコンデンサに蓄積することによって前記モニタデータを取得するモニタ期間と、前記AD変換回路が前記モニタデータをアナログ値からデジタル値に変換するAD変換期間とが含まれ、
前記AD変換期間には、
前記第2の制御スイッチがオフ状態とされることによって、前記データ信号線と前記内部データ線とが電気的に切り離され、
前記AD変換回路において、対応する複数個の前記出力/電流モニタ回路によってそれぞれ取得された複数個の前記モニタデータが順次にアナログ値からデジタル値に変換されることを特徴とする。
前記電流測定期間は、前記駆動トランジスタの特性を検出するための電流測定が行われる駆動トランジスタ特性検出期間と前記電気光学素子の特性を検出するための電流測定が行われる電気光学素子特性検出期間とからなることを特徴とする。
前記出力/電流モニタ回路は、前記データ信号線に一端が接続され、所定の制御線に他端が接続された第3の制御スイッチを更に含み、
前記電流測定期間のうちの前記駆動トランジスタ特性検出期間においては、前記AD変換期間には、前記第3の制御スイッチがオン状態とされることによって前記データ信号線と前記制御線とが電気的に接続され、かつ、前記制御線には前記データ信号線充電期間に前記データ信号線に与えられた電位の大きさに等しい大きさの電位が与えられることを特徴とする。
前記電流測定期間のうちの前記電気光学素子特性検出期間においては、前記AD変換期間には、前記データ信号線がハイインピーダンスの状態となるよう、前記第3の制御スイッチがオフ状態かつ前記モニタ制御トランジスタがオフ状態とされることを特徴とする。
前記電流測定期間のうちの前記電気光学素子特性検出期間においては、前記AD変換期間には、前記第3の制御スイッチがオン状態とされることによって前記データ信号線と前記制御線とが電気的に接続され、かつ、前記制御線には前記データ信号線充電期間に前記データ信号線に与えられた電位の大きさに実質的に等しい大きさの電位が与えられることを特徴とする。
前記電流測定期間のうちの前記電気光学素子特性検出期間においては、前記AD変換期間には、前記第3の制御スイッチがオン状態とされることによって前記データ信号線と前記制御線とが電気的に接続され、かつ、前記制御線には前記データ信号線充電期間に前記データ信号線に与えられるべき電位に近い一定の大きさの電位が与えられることを特徴とする。
前記検出準備期間に前記データ信号線に与える電位をVmgとし、前記駆動トランジスタ特性検出期間に前記データ信号線に与える電位をVm_TFTとし、前記電気光学素子特性検出期間に前記データ信号線に与える電位をVm_oledとしたとき、以下の関係を満たすようにVmg,Vm_TFT,およびVm_oledの値が定められていることを特徴とする。
Vm_TFT<Vmg-Vth(T2)
Vm_TFT<ELVSS+Vth(oled)
Vm_oled>Vmg-Vth(T2)
Vm_oled>ELVSS+Vth(oled)
ここで、Vth(T2)は前記駆動トランジスタの閾値電圧であって、Vth(oled)は前記電気光学素子の発光閾値電圧であって、ELVSSは前記電気光学素子の陰極の電位である。
前記特性検出処理期間は、垂直帰線期間内に設けられていることを特徴とする。
任意の電気光学素子を着目電気光学素子と定義したとき、前記画素回路駆動部は、前記着目電気光学素子が前記モニタ行に含まれている場合、前記モニタ行に含まれる画素回路への前記データ信号の書き込みを垂直走査期間に行う際には、前記着目電気光学素子が前記非モニタ行に含まれている場合における階調電圧よりも大きい階調電圧に相当するデータ信号の電位を前記データ信号線に与えることを特徴とする。
前記特性検出処理期間は、垂直走査期間内に設けられていることを特徴とする。
1つの前記特性検出対象回路素子の特性を検出するための電流測定期間において、前記データ信号線充電期間と前記モニタ期間と前記AD変換期間とからなるサイクルが複数回繰り返されることを特徴とする。
1フレーム期間につき前記電気光学素子または前記駆動トランジスタのいずれか一方のみについての前記特性検出処理が行われることを特徴とする。
フレーム期間に前記電気光学素子または前記駆動トランジスタの少なくとも一方を含む特性検出対象回路素子の特性を検出する特性検出ステップと、
前記特性検出ステップでの検出結果に基づいて得られる特性データを、映像信号を補正するための補正データとして、予め用意された補正データ記憶部に記憶させる補正データ記憶ステップと、
前記補正データ記憶部に記憶されている補正データに基づいて前記映像信号を補正して、前記n×m個の画素回路に供給すべきデータ信号を生成する映像信号補正ステップと
を含み、
各画素回路は、
前記電気光学素子と、
前記走査線に制御端子が接続され、前記駆動トランジスタの制御端子に第1導通端子が接続され、前記データ信号線に第2導通端子が接続された入力トランジスタと、
駆動電源電位が第1導通端子に与えられた前記駆動トランジスタと、
前記モニタ制御線に制御端子が接続され、前記駆動トランジスタの第2導通端子および前記電気光学素子の陽極に第1導通端子が接続され、前記データ信号線に第2導通端子が接続されたモニタ制御トランジスタと、
前記駆動トランジスタの制御端子の電位を保持するため、一端が前記駆動トランジスタの制御端子に接続された第1のコンデンサと
を含み、
前記画素回路駆動部は、
前記データ信号を前記データ信号線に印加する機能および前記データ信号線に流れている電流の大きさに応じたデータを前記特性データの元となるモニタデータとして取得する機能を有する出力/電流モニタ回路と、
前記モニタデータをアナログ値からデジタル値に変換するAD変換回路と
を含み、
前記出力/電流モニタ回路は、
前記データ信号線に接続された内部データ線と、
前記データ信号が非反転入力端子に与えられ、前記内部データ線に反転入力端子が接続されたオペアンプと、
前記内部データ線に一旦が接続され、前記オペアンプの出力端子に他端が接続された第2のコンデンサと、
前記内部データ線に一旦が接続され、前記オペアンプの出力端子に他端が接続された第1の制御スイッチと、
前記データ信号線に一端が接続され、前記内部データ線に他端が接続された第2の制御スイッチと
を含み、
前記AD変換回路は、複数個の前記出力/電流モニタ回路につき1個設けられ、
フレーム期間において前記特性検出処理が行われる行をモニタ行と定義し、前記モニタ行以外の行を非モニタ行と定義したとき、
前記特性検出ステップは、
前記モニタ行において前記特性検出対象回路素子の特性を検出する準備を行う検出準備ステップと、
前記データ信号線に流れている電流を測定することによって前記特性検出対象回路素子の特性を検出する電流測定ステップと、
前記モニタ行において前記電気光学素子を発光させる準備を行う発光準備ステップと
を含み、
前記電流測定ステップは、
前記特性検出対象回路素子の特性に応じた大きさの電流が前記データ信号線に流れるように前記データ信号線を充電するデータ信号線充電ステップと、
前記データ信号線に流れている電流の時間積分値を前記第2のコンデンサに蓄積することによって前記モニタデータを取得するモニタステップと、
前記AD変換回路によって前記モニタデータをアナログ値からデジタル値に変換するためのAD変換ステップと
を含み、
前記AD変換ステップでは、
前記第2の制御スイッチがオフ状態とされることによって、前記データ信号線と前記内部データ線とが電気的に切り離され、
前記AD変換回路において、対応する複数個の前記出力/電流モニタ回路によってそれぞれ取得された複数個の前記モニタデータが順次にアナログ値からデジタル値に変換されることを特徴とする。
図2は、本発明の一実施形態に係るアクティブマトリクス型の有機EL表示装置1の全体構成を示すブロック図である。この有機EL表示装置1は、表示部10,コントロール回路20,ソースドライバ(データ信号線駆動回路)30,ゲートドライバ(走査線駆動回路)40,および補正データ記憶部50を備えている。本実施形態においては、ソースドライバ30およびゲートドライバ40によって画素回路駆動部が実現されている。なお、ソースドライバ30およびゲートドライバ40の一方または双方が表示部10と一体的に形成された構成であっても良い。
次に、本実施形態における要部の詳細な構成について説明する。図1は、画素回路11,出力/電流モニタ回路330,および信号変換回路32の詳細な構成を示す回路図である。以下、これらの回路の構成および動作について詳しく説明する。
図1に示す画素回路11は、i行j列の画素回路11である。この画素回路11は、1個の有機EL素子OLED,3個のトランジスタT1~T3,および1個のコンデンサCstを備えている。トランジスタT1は画素を選択する入力トランジスタとして機能し、トランジスタT2は有機EL素子OLEDへの電流の供給を制御する駆動トランジスタとして機能し、トランジスタT3はTFT特性やOLED特性を検出するか否かを制御するモニタ制御トランジスタとして機能する。なお、本実施形態においては、トランジスタT2および有機EL素子OLEDが特性検出対象回路素子に相当する。また、各トランジスタに関し、ゲート端子が制御端子に相当し、ドレイン端子が第1導通端子に相当し、ソース端子が第2導通端子に相当する。
本実施形態においては、画素回路11内のトランジスタT1~T3はすべてnチャネル型である。また、本実施形態においては、トランジスタT1~T3には、酸化物TFT(酸化物半導体をチャネル層に用いた薄膜トランジスタ)が採用されている。
図1を参照しつつ、本実施形態における出力/電流モニタ回路330の構成および動作について詳しく説明する。出力/電流モニタ回路330には、オペアンプ331とコンデンサ332と3つのスイッチ(スイッチ333,334,および335)とが含まれている。
図1を参照しつつ、本実施形態における信号変換回路32の構成および動作について詳しく説明する。この信号変換回路32には、D/Aコンバータ321とセレクタ322とオフセット回路323とA/Dコンバータ324とが含まれている。D/Aコンバータ321は、駆動信号発生回路31から出力されたデジタル信号であるデータ信号DAをアナログ電圧Vsに変換する。本実施形態においては、複数の列でA/Dコンバータ324が共有される。これを実現するために、信号変換回路32内にセレクタ322が設けられている。セレクタ322には、複数個の出力/電流モニタ回路330からモニタデータMOが与えられる。セレクタ322は、与えられた複数個のモニタデータMOを時分割で順次に出力する。オフセット回路323は、TFT特性検出の際とOLED特性検出の際とでA/Dコンバータ324への入力レベルを同じにする機能(オフセット調整機能)を有している。このオフセット回路323が設けられている理由は、TFT特性検出の際の基準電位であるVm_TFTとOLED特性検出の際の基準電位であるVm_oledとが異なる電位であるためである。A/Dコンバータ324は、オフセット回路323から出力されたアナログ電圧をデジタル信号に変換する。なお、オフセット調整に用いるオフセット値は、Vm_TFTの値およびVm_oledの値に依存させると良い。以上より、信号変換回路32内の構成要素に関しては、D/Aコンバータ321については各列につき1個設けられ、セレクタ322,オフセット回路323,およびA/Dコンバータ324については複数の列につき1個設けられている。
上述したように、本実施形態においては、複数の列でA/Dコンバータ324が共有される。これについて、図8を参照しつつ、詳しく説明する。なお、図8には、ソースドライバ30が1440チャネルの出力部33を有している場合(すなわち、1440本のデータ信号線Sが設けられている場合)の例を示している。図8に示す例では、144列で1個のA/Dコンバータ324が共有されている。従って、144列毎に1個のセレクタ322が設けられている。各セレクタ322には、144個の出力/電流モニタ回路330からモニタデータMOが与えられる。そして、各セレクタ322は、144個のモニタデータMOを時分割で順次にオフセット回路323に与える。オフセット回路323に与えられたモニタデータMOは、入力レベルの調整後、A/Dコンバータ324に与えられる。ところで、上述したように、出力/電流モニタ回路330では、上述したサンプルホールド機能によって、AD変換が行われている期間を通じてアナログデータの値が保持される。これにより、全ての列で同じタイミングで取得されたアナログデータの値が順次にA/Dコンバータ324に与えられる。なお、AD変換後のモニタデータMOは、駆動信号発生回路31内のロジック部311を介してコントロール回路20に送られる。
<3.1 概要>
次に、本実施形態における駆動方法について説明する。上述したように、本実施形態においては、各フレームに1つの行のTFT特性およびOLED特性の検出が行われる。各フレームにおいて、モニタ行についてはTFT特性およびOLED特性の検出を行うための動作(以下、「特性検出動作」という。)が行われ、非モニタ行については通常動作が行われる。すなわち、1行目についてのTFT特性およびOLED特性の検出が行われるフレームを(k+1)フレーム目と定義すると、図9に示すように、各行の動作は推移する。また、TFT特性およびOLED特性の検出が行われると、その検出結果を用いて、補正データ記憶部50内の補正データの更新が行われる。そして、補正データ記憶部50に記憶されている補正データを用いて映像信号の補正が行われる。
<3.2.1 通常動作>
各フレームにおいて、非モニタ行では、通常動作が行われる。非モニタ行に含まれる画素回路11では、目標輝度に対応するデータ電位Vdataに基づく書き込みが選択期間に行われた後、トランジスタT1はオフ状態で維持される。データ電位Vdataに基づく書き込みによってトランジスタT2はオン状態となる。トランジスタT3についてはオフ状態で維持される。以上より、図11で符号71で示す矢印のように、トランジスタT2を介して有機EL素子OLEDに駆動電流が供給される。これにより、駆動電流に応じた輝度で有機EL素子OLEDが発光する。
各フレームにおいて、モニタ行では、特性検出動作が行われる。図12は、モニタ行についての1水平走査期間THmの詳細を説明するためのタイミングチャートである。なお、この1水平走査期間THmによって特性検出処理期間が実現されている。図12に示すように、本実施形態においては、TFT特性検出期間Tbは、期間Tb1~Tb6によって構成されており、OLED特性検出期間Tcは、期間Tc1~Tc6によって構成されている。なお、本実施形態においては、期間Tb1,Tb4,Tc1,およびTc4によってデータ信号線充電期間が実現され、期間Tb2,Tb5,Tc2,およびTc5によってモニタ期間が実現され、期間Tb3,Tb6,Tc3,およびTc6によってAD変換期間が実現されている。
Vm_TFT+Vth(T2)<Vmg ・・・(1)
Vmg<Vm_oled+Vth(T2) ・・・(2)
また、OLED用オフセットメモリ51bに格納されているオフセット値に基づいて求められる有機EL素子OLEDの発光閾値電圧をVth(oled)とすると、次式(3)が成立するように電位Vm_TFTの値が設定されている。
Vm_TFT<ELVSS+Vth(oled) ・・・(3)
さらに、有機EL素子OLEDの降伏電圧をVbr(oled)とすると、次式(4)が成立するように電位Vm_TFTの値が設定されている。
Vm_TFT>ELVSS-Vbr(oled) ・・・(4)
ELVSS+Vth(oled)<Vm_oled ・・・(5)
また、トランジスタT2の降伏電圧をVbr(T2)とすると、次式(6)が成立するように電位Vm_oledの値が設定されている。
Vm_oled<Vmg+Vbr(T2) ・・・(6)
次に、補正データ記憶部50に記憶されている補正データ(TFT用オフセットメモリ51aに記憶されているオフセット値,OLED用オフセットメモリ51bに記憶されているオフセット値,TFT用ゲインメモリ52aに記憶されているゲイン値,およびOLED用ゲインメモリ52bに記憶されている劣化補正係数)がどのように更新されるかについて説明する。図20は、補正データ記憶部50内の補正データの更新の手順を説明するためのフローチャートである。なお、ここでは1つの画素に対応する補正データに着目する。
本実施形態においては、駆動トランジスタの劣化および有機EL素子OLEDの劣化を補償するために、補正データ記憶部50に格納されている補正データを用いて、外部から送られる映像信号の補正が行われる。以下、映像信号のこの補正について図21を参照しつつ説明する。
図22は、TFT特性およびOLED特性の検出に関連する動作の概略を説明するためのフローチャートである。まず、TFT特性検出期間TbにTFT特性の検出が行われる(ステップS210)。そして、ステップS210での検出結果を用いて、TFT用オフセットメモリ51aおよびTFT用ゲインメモリ52aの更新が行われる(ステップS220)。次に、OLED特性検出期間TcにOLED特性の検出が行われる(ステップS230)。そして、ステップS230での検出結果を用いて、OLED用オフセットメモリ51bおよびOLED用ゲインメモリ52bの更新が行われる(ステップS240)。その後、TFT用オフセットメモリ51a,TFT用ゲインメモリ52a,OLED用オフセットメモリ51b,およびOLED用ゲインメモリ52bに格納されている補正データを用いて、外部から送られる映像信号の補正が行われる(ステップS250)。
本実施形態によれば、各フレームにおいて1つの行についてのTFT特性およびOLED特性の検出が行われる。モニタ行における1水平走査期間THmは非モニタ行における1水平走査期間THnよりも長くされ、モニタ行では、その1水平走査期間THm中にTFT特性の検出およびOLED特性の検出が行われる。そして、TFT特性の検出結果およびOLED特性の検出結果の双方を考慮して求められた補正データを用いて、外部から送られる映像信号が補正される。このようにして補正された映像信号に基づくデータ電位がデータ信号線Sに印加されるので、各画素回路11内の有機EL素子OLEDを発光させる際に、駆動トランジスタ(トランジスタT2)の劣化および有機EL素子OLEDの劣化が補償されるような大きさの駆動電流が有機EL素子OLEDに供給される(図23参照)。また、図24に示すように劣化の最も少ない画素の劣化レベルに合わせて電流を増加させることによって、焼き付きに対する補償を行うことが可能となる。ここで、本実施形態におけるデータ信号線Sは、各画素回路11内の有機EL素子OLEDを所望の輝度で発光させるための輝度信号を伝達する信号線として用いられるだけでなく、特性検出用の信号線(特性検出用の制御電位(Vmg,Vm_TFT,Vm_oled)を画素回路11に与える信号線、特性を表す電流であって出力/電流モニタ回路330で測定可能な電流の経路となる信号線)としても用いられる。すなわち、TFT特性やOLED特性を検出するために新たな信号線を表示部10内に設ける必要がない。従って、回路規模の増大を抑制しつつ、駆動トランジスタ(トランジスタT2)の劣化および有機EL素子OLEDの劣化の双方を同時に補償することが可能となる。
以下、上記実施形態の変形例について説明する。なお、以下においては、上記実施形態と異なる点についてのみ詳しく説明し、上記実施形態と同様の点については説明を省略する。
上記実施形態においては、OLED特性検出期間Tcにデータ信号線Sに与える電位については、OLED用オフセットメモリ51bに格納されているオフセット値Vt2およびOLED用ゲインメモリ52bに格納されている劣化補正係数B2に基づいて補正が施される(図21参照)。すなわち、電位Vm_oledの大きさは、画素毎に異なり得る。これに関し、上述したようにAD変換中にはスイッチ334がオフ状態となるので、仮に画素毎に異なる大きさの電位Vm_oledが制御線CLからデータ信号線Sに供給されるようにするためには、図1に示すD/Aコンバータ321とは別のD/Aコンバータを備える必要がある。
上記実施形態においては、OLED特性検出期間Tc内でAD変換が行われる期間(期間Tc3および期間Tc6)には制御ラインCLからデータ信号線Sに電位Vm_oledが与えられる構成となっていた。しかしながら、本発明はこれに限定されない。OLED特性検出期間Tc内でAD変換が行われる期間にはデータ信号線Sがハイインピーダンスの状態にされる構成(本変形例の構成)を採用することもできる。以下、本変形例における駆動方法について、上記実施形態と異なる点を中心に説明する。
一般に、有機EL表示装置においては、1フレーム期間は、先頭行から最終行への順番で順次に画素への映像信号の書き込みが行われる期間である垂直走査期間と、映像信号の書き込みを最終行から先頭行に戻すために設けられている期間である垂直帰線期間(垂直同期期間)とからなる。そして、有機EL表示装置の動作中、図28に示すように、垂直走査期間Tvと垂直帰線期間Tfとが交互に繰り返される。ところで、上記実施形態においては、垂直走査期間Tv中にTFT特性の検出およびOLED特性の検出が行われていた。しかしながら、本発明はこれに限定されず、垂直帰線期間Tf中にTFT特性の検出およびOLED特性の検出が行われる構成(本変形例の構成)を採用することもできる。
本発明は、上記実施形態および変形例に限定されるものではなく、本発明の趣旨を逸脱しない範囲で種々変形して実施することができる。例えば、本発明を適用可能な有機EL表示装置は、上記実施形態で例示した画素回路11を備えるものに限定されるものではない。画素回路は、少なくとも、電流によって制御される電気光学素子(有機EL素子OLED),トランジスタT1~T3,およびコンデンサCstを備えていれば、上記実施形態で例示した構成以外の構成であっても良い。
10…表示部
11…画素回路
20…コントロール回路
30…ソースドライバ
31…駆動信号発生回路
32…信号変換回路
33…出力部
40…ゲートドライバ
50…補正データ記憶部
51a…TFT用オフセットメモリ
51b…OLED用オフセットメモリ
52a…TFT用ゲインメモリ
52b…OLED用ゲインメモリ
321…D/Aコンバータ
322…セレクタ
323…オフセット回路
324…A/Dコンバータ
330…出力/電流モニタ回路
333~335…スイッチ
T1~T3…トランジスタ
Cst…コンデンサ
G1,G1(1)~G1(n)…走査線
G2,G2(1)~G2(n)…モニタ制御線
S,S(j),S(1)~S(m)…データ信号線
Sin,Sin(j),Sin(1)~Sin(m)…内部データ線
ELVDD…ハイレベル電源電圧,ハイレベル電源線
ELVSS…ローレベル電源電圧,ローレベル電源線
Ta…検出準備期間
Tb…TFT特性検出期間
Tc…OLED特性検出期間
Tb1,Tb4,Tc1,Tc4…データ信号線充電期間
Tb2,Tb5,Tc2,Tc5…モニタ期間
Tb3,Tb6,Tc3,Tc6…AD変換期間
Td…発光準備期間
TL…発光期間
Claims (13)
- アクティブマトリクス型の表示装置であって、
電流によって輝度が制御される電気光学素子および前記電気光学素子に供給すべき電流を制御するための駆動トランジスタをそれぞれが含むn×m個(nおよびmは2以上の整数)の画素回路からなるn行×m列の画素マトリクスと、前記画素マトリクスの各行に対応するように設けられた走査線と、前記画素マトリクスの各行に対応するように設けられたモニタ制御線と、前記画素マトリクスの各列に対応するように設けられたデータ信号線とを有する表示部と、
フレーム期間に前記電気光学素子または前記駆動トランジスタの少なくとも一方を含む特性検出対象回路素子の特性を検出する特性検出処理が行われるよう、かつ、各電気光学素子が目標輝度に応じて発光するよう、前記走査線,前記モニタ制御線,および前記データ信号線を駆動する画素回路駆動部と、
前記特性検出処理の結果に基づいて得られる特性データを、映像信号を補正するための補正データとして記憶する補正データ記憶部と、
前記補正データ記憶部に記憶されている補正データに基づいて前記映像信号を補正して、前記n×m個の画素回路に供給すべきデータ信号を生成する映像信号補正部と
を備え、
各画素回路は、
前記電気光学素子と、
前記走査線に制御端子が接続され、前記駆動トランジスタの制御端子に第1導通端子が接続され、前記データ信号線に第2導通端子が接続された入力トランジスタと、
駆動電源電位が第1導通端子に与えられた前記駆動トランジスタと、
前記モニタ制御線に制御端子が接続され、前記駆動トランジスタの第2導通端子および前記電気光学素子の陽極に第1導通端子が接続され、前記データ信号線に第2導通端子が接続されたモニタ制御トランジスタと、
前記駆動トランジスタの制御端子の電位を保持するため、一端が前記駆動トランジスタの制御端子に接続された第1のコンデンサと
を含み、
前記画素回路駆動部は、
前記データ信号を前記データ信号線に印加する機能および前記データ信号線に流れている電流の大きさに応じたデータを前記特性データの元となるモニタデータとして取得する機能を有する出力/電流モニタ回路と、
前記モニタデータをアナログ値からデジタル値に変換するAD変換回路と
を含み、
前記出力/電流モニタ回路は、
前記データ信号線に接続された内部データ線と、
前記データ信号が非反転入力端子に与えられ、前記内部データ線に反転入力端子が接続されたオペアンプと、
前記内部データ線に一旦が接続され、前記オペアンプの出力端子に他端が接続された第2のコンデンサと、
前記内部データ線に一旦が接続され、前記オペアンプの出力端子に他端が接続された第1の制御スイッチと、
前記データ信号線に一端が接続され、前記内部データ線に他端が接続された第2の制御スイッチと
を含み、
前記AD変換回路は、複数個の前記出力/電流モニタ回路につき1個設けられ、
フレーム期間において前記特性検出処理が行われる行をモニタ行と定義し、前記モニタ行以外の行を非モニタ行と定義したとき、フレーム期間には、前記モニタ行において前記特性検出対象回路素子の特性を検出する準備が行われる検出準備期間と、前記データ信号線に流れている電流を測定することによって前記特性検出対象回路素子の特性を検出する電流測定期間と、前記モニタ行において前記電気光学素子を発光させる準備が行われる発光準備期間とからなる特性検出処理期間が含まれ、
前記電流測定期間には、前記特性検出対象回路素子の特性に応じた大きさの電流が前記データ信号線に流れるように前記データ信号線を充電するデータ信号線充電期間と、前記データ信号線に流れている電流の時間積分値を前記第2のコンデンサに蓄積することによって前記モニタデータを取得するモニタ期間と、前記AD変換回路が前記モニタデータをアナログ値からデジタル値に変換するAD変換期間とが含まれ、
前記AD変換期間には、
前記第2の制御スイッチがオフ状態とされることによって、前記データ信号線と前記内部データ線とが電気的に切り離され、
前記AD変換回路において、対応する複数個の前記出力/電流モニタ回路によってそれぞれ取得された複数個の前記モニタデータが順次にアナログ値からデジタル値に変換されることを特徴とする、表示装置。 - 前記電流測定期間は、前記駆動トランジスタの特性を検出するための電流測定が行われる駆動トランジスタ特性検出期間と前記電気光学素子の特性を検出するための電流測定が行われる電気光学素子特性検出期間とからなることを特徴とする、請求項1に記載の表示装置。
- 前記出力/電流モニタ回路は、前記データ信号線に一端が接続され、所定の制御線に他端が接続された第3の制御スイッチを更に含み、
前記電流測定期間のうちの前記駆動トランジスタ特性検出期間においては、前記AD変換期間には、前記第3の制御スイッチがオン状態とされることによって前記データ信号線と前記制御線とが電気的に接続され、かつ、前記制御線には前記データ信号線充電期間に前記データ信号線に与えられた電位の大きさに等しい大きさの電位が与えられることを特徴とする、請求項2に記載の表示装置。 - 前記電流測定期間のうちの前記電気光学素子特性検出期間においては、前記AD変換期間には、前記データ信号線がハイインピーダンスの状態となるよう、前記第3の制御スイッチがオフ状態かつ前記モニタ制御トランジスタがオフ状態とされることを特徴とする、請求項3に記載の表示装置。
- 前記電流測定期間のうちの前記電気光学素子特性検出期間においては、前記AD変換期間には、前記第3の制御スイッチがオン状態とされることによって前記データ信号線と前記制御線とが電気的に接続され、かつ、前記制御線には前記データ信号線充電期間に前記データ信号線に与えられた電位の大きさに実質的に等しい大きさの電位が与えられることを特徴とする、請求項3に記載の表示装置。
- 前記電流測定期間のうちの前記電気光学素子特性検出期間においては、前記AD変換期間には、前記第3の制御スイッチがオン状態とされることによって前記データ信号線と前記制御線とが電気的に接続され、かつ、前記制御線には前記データ信号線充電期間に前記データ信号線に与えられるべき電位に近い一定の大きさの電位が与えられることを特徴とする、請求項3に記載の表示装置。
- 前記検出準備期間に前記データ信号線に与える電位をVmgとし、前記駆動トランジスタ特性検出期間に前記データ信号線に与える電位をVm_TFTとし、前記電気光学素子特性検出期間に前記データ信号線に与える電位をVm_oledとしたとき、以下の関係を満たすようにVmg,Vm_TFT,およびVm_oledの値が定められていることを特徴とする、請求項2に記載の表示装置:
Vm_TFT<Vmg-Vth(T2)
Vm_TFT<ELVSS+Vth(oled)
Vm_oled>Vmg-Vth(T2)
Vm_oled>ELVSS+Vth(oled)
ここで、Vth(T2)は前記駆動トランジスタの閾値電圧であって、Vth(oled)は前記電気光学素子の発光閾値電圧であって、ELVSSは前記電気光学素子の陰極の電位である。 - 前記特性検出処理期間は、垂直帰線期間内に設けられていることを特徴とする、請求項1に記載の表示装置。
- 任意の電気光学素子を着目電気光学素子と定義したとき、前記画素回路駆動部は、前記着目電気光学素子が前記モニタ行に含まれている場合、前記モニタ行に含まれる画素回路への前記データ信号の書き込みを垂直走査期間に行う際には、前記着目電気光学素子が前記非モニタ行に含まれている場合における階調電圧よりも大きい階調電圧に相当するデータ信号の電位を前記データ信号線に与えることを特徴とする、請求項8に記載の表示装置。
- 前記特性検出処理期間は、垂直走査期間内に設けられていることを特徴とする、請求項1に記載の表示装置。
- 1つの前記特性検出対象回路素子の特性を検出するための電流測定期間において、前記データ信号線充電期間と前記モニタ期間と前記AD変換期間とからなるサイクルが複数回繰り返されることを特徴とする、請求項1に記載の表示装置。
- 1フレーム期間につき前記電気光学素子または前記駆動トランジスタのいずれか一方のみについての前記特性検出処理が行われることを特徴とする、請求項1に記載の表示装置。
- 電流によって輝度が制御される電気光学素子および前記電気光学素子に供給すべき電流を制御するための駆動トランジスタをそれぞれが含むn×m個(nおよびmは2以上の整数)の画素回路からなるn行×m列の画素マトリクスと、前記画素マトリクスの各行に対応するように設けられた走査線と、前記画素マトリクスの各行に対応するように設けられたモニタ制御線と、前記画素マトリクスの各列に対応するように設けられたデータ信号線と、前記走査線,前記モニタ制御線,および前記データ信号線を駆動する画素回路駆動部とを備えた表示装置の駆動方法であって、
フレーム期間に前記電気光学素子または前記駆動トランジスタの少なくとも一方を含む特性検出対象回路素子の特性を検出する特性検出ステップと、
前記特性検出ステップでの検出結果に基づいて得られる特性データを、映像信号を補正するための補正データとして、予め用意された補正データ記憶部に記憶させる補正データ記憶ステップと、
前記補正データ記憶部に記憶されている補正データに基づいて前記映像信号を補正して、前記n×m個の画素回路に供給すべきデータ信号を生成する映像信号補正ステップと
を含み、
各画素回路は、
前記電気光学素子と、
前記走査線に制御端子が接続され、前記駆動トランジスタの制御端子に第1導通端子が接続され、前記データ信号線に第2導通端子が接続された入力トランジスタと、
駆動電源電位が第1導通端子に与えられた前記駆動トランジスタと、
前記モニタ制御線に制御端子が接続され、前記駆動トランジスタの第2導通端子および前記電気光学素子の陽極に第1導通端子が接続され、前記データ信号線に第2導通端子が接続されたモニタ制御トランジスタと、
前記駆動トランジスタの制御端子の電位を保持するため、一端が前記駆動トランジスタの制御端子に接続された第1のコンデンサと
を含み、
前記画素回路駆動部は、
前記データ信号を前記データ信号線に印加する機能および前記データ信号線に流れている電流の大きさに応じたデータを前記特性データの元となるモニタデータとして取得する機能を有する出力/電流モニタ回路と、
前記モニタデータをアナログ値からデジタル値に変換するAD変換回路と
を含み、
前記出力/電流モニタ回路は、
前記データ信号線に接続された内部データ線と、
前記データ信号が非反転入力端子に与えられ、前記内部データ線に反転入力端子が接続されたオペアンプと、
前記内部データ線に一旦が接続され、前記オペアンプの出力端子に他端が接続された第2のコンデンサと、
前記内部データ線に一旦が接続され、前記オペアンプの出力端子に他端が接続された第1の制御スイッチと、
前記データ信号線に一端が接続され、前記内部データ線に他端が接続された第2の制御スイッチと
を含み、
前記AD変換回路は、複数個の前記出力/電流モニタ回路につき1個設けられ、
フレーム期間において前記特性検出処理が行われる行をモニタ行と定義し、前記モニタ行以外の行を非モニタ行と定義したとき、
前記特性検出ステップは、
前記モニタ行において前記特性検出対象回路素子の特性を検出する準備を行う検出準備ステップと、
前記データ信号線に流れている電流を測定することによって前記特性検出対象回路素子の特性を検出する電流測定ステップと、
前記モニタ行において前記電気光学素子を発光させる準備を行う発光準備ステップと
を含み、
前記電流測定ステップは、
前記特性検出対象回路素子の特性に応じた大きさの電流が前記データ信号線に流れるように前記データ信号線を充電するデータ信号線充電ステップと、
前記データ信号線に流れている電流の時間積分値を前記第2のコンデンサに蓄積することによって前記モニタデータを取得するモニタステップと、
前記AD変換回路によって前記モニタデータをアナログ値からデジタル値に変換するためのAD変換ステップと
を含み、
前記AD変換ステップでは、
前記第2の制御スイッチがオフ状態とされることによって、前記データ信号線と前記内部データ線とが電気的に切り離され、
前記AD変換回路において、対応する複数個の前記出力/電流モニタ回路によってそれぞれ取得された複数個の前記モニタデータが順次にアナログ値からデジタル値に変換されることを特徴とする、駆動方法。
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Cited By (10)
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---|---|---|---|---|
WO2015190407A1 (ja) * | 2014-06-10 | 2015-12-17 | シャープ株式会社 | 表示装置およびその駆動方法 |
WO2016129463A1 (ja) * | 2015-02-10 | 2016-08-18 | シャープ株式会社 | 表示装置およびその駆動方法 |
WO2017010286A1 (ja) * | 2015-07-10 | 2017-01-19 | シャープ株式会社 | 画素回路ならびに表示装置およびその駆動方法 |
EP3188176A1 (en) * | 2015-12-30 | 2017-07-05 | LG Display Co., Ltd. | Pixel, display device comprising the same and driving method thereof |
JP2017198967A (ja) * | 2016-04-29 | 2017-11-02 | エルジー ディスプレイ カンパニー リミテッド | フレキシブル有機発光表示装置 |
CN113785349A (zh) * | 2019-05-14 | 2021-12-10 | 夏普株式会社 | 显示装置及其驱动方法 |
US11217169B2 (en) | 2019-01-30 | 2022-01-04 | Shenzhen Torey Microelectronic Technology Co. Ltd. | Display device with reference pixel circuit |
WO2022244220A1 (ja) * | 2021-05-21 | 2022-11-24 | シャープ株式会社 | 表示装置 |
WO2024003963A1 (ja) * | 2022-06-27 | 2024-01-04 | シャープ株式会社 | 表示パネルの制御装置、表示装置、および表示パネルの制御装置による制御方法 |
US11910671B2 (en) | 2019-03-28 | 2024-02-20 | Sharp Kabushiki Kaisha | Display device and method for driving same |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101560492B1 (ko) * | 2014-09-12 | 2015-10-15 | 엘지디스플레이 주식회사 | 구동소자의 전기적 특성을 센싱할 수 있는 유기발광 표시장치 |
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JP2018072653A (ja) * | 2016-11-01 | 2018-05-10 | セイコーエプソン株式会社 | 電気光学装置、電子機器および駆動方法 |
WO2018119650A1 (zh) | 2016-12-27 | 2018-07-05 | 深圳市柔宇科技有限公司 | 像素电路驱动方法、像素电路组及有机发光显示设备 |
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US20180254004A1 (en) * | 2017-03-06 | 2018-09-06 | Novatek Microelectronics Corp. | Integrated circuit for driving display panel and fan-out compensation method thereof |
US10839746B2 (en) * | 2017-06-07 | 2020-11-17 | Shenzhen Torey Microelectronic Technology Co. Ltd. | Display device and image data correction method |
KR102350396B1 (ko) * | 2017-07-27 | 2022-01-14 | 엘지디스플레이 주식회사 | 유기발광 표시장치와 그의 열화 센싱 방법 |
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WO2019123064A1 (ja) * | 2017-12-21 | 2019-06-27 | 株式会社半導体エネルギー研究所 | 表示装置、及び電子機器 |
US10643528B2 (en) * | 2018-01-23 | 2020-05-05 | Valve Corporation | Rolling burst illumination for a display |
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US10971078B2 (en) | 2018-02-12 | 2021-04-06 | Ignis Innovation Inc. | Pixel measurement through data line |
US11114031B2 (en) * | 2018-03-28 | 2021-09-07 | Sharp Kabushiki Kaisha | Display device and method for driving same |
WO2019186895A1 (ja) * | 2018-03-29 | 2019-10-03 | シャープ株式会社 | 駆動方法、及び、表示装置 |
CN108520718B (zh) * | 2018-04-18 | 2019-12-27 | 京东方科技集团股份有限公司 | 一种显示装置的像素数据补偿方法及装置、显示装置 |
US10997882B2 (en) * | 2018-07-23 | 2021-05-04 | Samsung Electronics Co., Ltd. | Short detection device, a short detection circuit and a display device using the same |
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CN109389946A (zh) * | 2018-12-14 | 2019-02-26 | 昆山国显光电有限公司 | 显示面板、像素电路及其驱动方法 |
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CN109616051A (zh) * | 2018-12-14 | 2019-04-12 | 昆山国显光电有限公司 | 显示面板、像素电路及其驱动方法 |
JP7345268B2 (ja) * | 2019-04-18 | 2023-09-15 | Tianma Japan株式会社 | 表示装置及びその制御方法 |
CN110491319B (zh) * | 2019-08-23 | 2022-09-27 | 深圳市华星光电半导体显示技术有限公司 | 发光二极管驱动电路及驱动晶体管电子迁移率检测方法 |
CN114450742A (zh) * | 2019-10-23 | 2022-05-06 | 夏普株式会社 | 显示装置及其驱动方法 |
US11874997B2 (en) * | 2020-11-27 | 2024-01-16 | Sharp Kabushiki Kaisha | Display device equipped with touch panel and control method therefor |
KR20220120806A (ko) * | 2021-02-23 | 2022-08-31 | 삼성디스플레이 주식회사 | 픽셀 회로, 이를 포함하는 표시 장치 및 이의 구동 방법 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006505816A (ja) * | 2002-11-06 | 2006-02-16 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Ledマトリクス表示器の検査方法及び装置 |
JP2007536585A (ja) * | 2004-05-06 | 2007-12-13 | トムソン ライセンシング | 発光ディスプレイのための回路および制御方法 |
JP2009069421A (ja) * | 2007-09-12 | 2009-04-02 | Hitachi Displays Ltd | 表示装置 |
JP2010281872A (ja) * | 2009-06-02 | 2010-12-16 | Casio Computer Co Ltd | 発光装置及びその駆動制御方法、並びに電子機器 |
JP2011095720A (ja) * | 2009-09-30 | 2011-05-12 | Casio Computer Co Ltd | 発光装置及びその駆動制御方法、並びに電子機器 |
JP2011221480A (ja) * | 2010-04-14 | 2011-11-04 | Samsung Mobile Display Co Ltd | 表示装置及びその駆動方法 |
JP2012519881A (ja) * | 2009-03-04 | 2012-08-30 | グローバル・オーエルイーディー・テクノロジー・リミテッド・ライアビリティ・カンパニー | エレクトロルミネッセントディスプレイ補償済み駆動信号 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003195810A (ja) | 2001-12-28 | 2003-07-09 | Casio Comput Co Ltd | 駆動回路、駆動装置及び光学要素の駆動方法 |
KR100560780B1 (ko) | 2003-07-07 | 2006-03-13 | 삼성에스디아이 주식회사 | 유기전계 발광표시장치의 화소회로 및 그의 구동방법 |
EP2383720B1 (en) | 2004-12-15 | 2018-02-14 | Ignis Innovation Inc. | Method and system for programming, calibrating and driving a light emitting device display |
WO2007037269A1 (ja) * | 2005-09-27 | 2007-04-05 | Casio Computer Co., Ltd. | 表示装置及び表示装置の駆動方法 |
KR100671669B1 (ko) | 2006-02-28 | 2007-01-19 | 삼성에스디아이 주식회사 | 데이터 구동부 및 이를 이용한 유기 발광 표시장치와 그의구동방법 |
US20080048951A1 (en) * | 2006-04-13 | 2008-02-28 | Naugler Walter E Jr | Method and apparatus for managing and uniformly maintaining pixel circuitry in a flat panel display |
JP4424346B2 (ja) | 2006-12-11 | 2010-03-03 | カシオ計算機株式会社 | 駆動回路及び駆動装置 |
EP2093748B1 (en) * | 2007-03-08 | 2013-01-16 | Sharp Kabushiki Kaisha | Display device and its driving method |
US8179343B2 (en) * | 2007-06-29 | 2012-05-15 | Canon Kabushiki Kaisha | Display apparatus and driving method of display apparatus |
US8004479B2 (en) * | 2007-11-28 | 2011-08-23 | Global Oled Technology Llc | Electroluminescent display with interleaved 3T1C compensation |
JP4956598B2 (ja) * | 2009-02-27 | 2012-06-20 | シャープ株式会社 | 不揮発性半導体記憶装置及びその製造方法 |
KR102110496B1 (ko) | 2010-12-03 | 2020-05-13 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 산화물 반도체막 및 반도체 장치 |
JP6129318B2 (ja) * | 2013-07-30 | 2017-05-17 | シャープ株式会社 | 表示装置およびその駆動方法 |
-
2014
- 2014-08-20 US US15/037,712 patent/US9842545B2/en active Active
- 2014-08-20 WO PCT/JP2014/071721 patent/WO2015093097A1/ja active Application Filing
- 2014-08-20 JP JP2015553393A patent/JP6169191B2/ja active Active
- 2014-08-20 CN CN201480069047.1A patent/CN105830144B/zh active Active
- 2014-08-27 TW TW103129605A patent/TWI581237B/zh not_active IP Right Cessation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006505816A (ja) * | 2002-11-06 | 2006-02-16 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Ledマトリクス表示器の検査方法及び装置 |
JP2007536585A (ja) * | 2004-05-06 | 2007-12-13 | トムソン ライセンシング | 発光ディスプレイのための回路および制御方法 |
JP2009069421A (ja) * | 2007-09-12 | 2009-04-02 | Hitachi Displays Ltd | 表示装置 |
JP2012519881A (ja) * | 2009-03-04 | 2012-08-30 | グローバル・オーエルイーディー・テクノロジー・リミテッド・ライアビリティ・カンパニー | エレクトロルミネッセントディスプレイ補償済み駆動信号 |
JP2010281872A (ja) * | 2009-06-02 | 2010-12-16 | Casio Computer Co Ltd | 発光装置及びその駆動制御方法、並びに電子機器 |
JP2011095720A (ja) * | 2009-09-30 | 2011-05-12 | Casio Computer Co Ltd | 発光装置及びその駆動制御方法、並びに電子機器 |
JP2011221480A (ja) * | 2010-04-14 | 2011-11-04 | Samsung Mobile Display Co Ltd | 表示装置及びその駆動方法 |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10074313B2 (en) | 2014-06-10 | 2018-09-11 | Sharp Kabushiki Kaisha | Display device and method for driving same |
WO2015190407A1 (ja) * | 2014-06-10 | 2015-12-17 | シャープ株式会社 | 表示装置およびその駆動方法 |
WO2016129463A1 (ja) * | 2015-02-10 | 2016-08-18 | シャープ株式会社 | 表示装置およびその駆動方法 |
US10319305B2 (en) | 2015-02-10 | 2019-06-11 | Sharp Kabushiki Kaisha | Display device and drive method therefor |
WO2017010286A1 (ja) * | 2015-07-10 | 2017-01-19 | シャープ株式会社 | 画素回路ならびに表示装置およびその駆動方法 |
CN107710318A (zh) * | 2015-07-10 | 2018-02-16 | 夏普株式会社 | 像素电路以及显示装置及其驱动方法 |
JPWO2017010286A1 (ja) * | 2015-07-10 | 2018-03-15 | シャープ株式会社 | 画素回路ならびに表示装置およびその駆動方法 |
US10262588B2 (en) | 2015-12-30 | 2019-04-16 | Lg Display Co., Ltd. | Pixel, display device including the same, and driving method thereof |
EP3188176A1 (en) * | 2015-12-30 | 2017-07-05 | LG Display Co., Ltd. | Pixel, display device comprising the same and driving method thereof |
KR20170080883A (ko) * | 2015-12-30 | 2017-07-11 | 엘지디스플레이 주식회사 | 화소, 이를 포함하는 표시 장치 및 그 제어 방법 |
KR102630078B1 (ko) | 2015-12-30 | 2024-01-26 | 엘지디스플레이 주식회사 | 화소, 이를 포함하는 표시 장치 및 그 제어 방법 |
JP2019045879A (ja) * | 2016-04-29 | 2019-03-22 | エルジー ディスプレイ カンパニー リミテッド | フレキシブル有機発光表示装置 |
KR20170123967A (ko) * | 2016-04-29 | 2017-11-09 | 엘지디스플레이 주식회사 | 플렉서블 유기발광 표시장치 |
KR102475589B1 (ko) * | 2016-04-29 | 2022-12-07 | 엘지디스플레이 주식회사 | 플렉서블 유기발광 표시장치 |
JP2017198967A (ja) * | 2016-04-29 | 2017-11-02 | エルジー ディスプレイ カンパニー リミテッド | フレキシブル有機発光表示装置 |
US11217169B2 (en) | 2019-01-30 | 2022-01-04 | Shenzhen Torey Microelectronic Technology Co. Ltd. | Display device with reference pixel circuit |
US11910671B2 (en) | 2019-03-28 | 2024-02-20 | Sharp Kabushiki Kaisha | Display device and method for driving same |
CN113785349A (zh) * | 2019-05-14 | 2021-12-10 | 夏普株式会社 | 显示装置及其驱动方法 |
CN113785349B (zh) * | 2019-05-14 | 2023-12-26 | 夏普株式会社 | 显示装置及其驱动方法 |
WO2022244220A1 (ja) * | 2021-05-21 | 2022-11-24 | シャープ株式会社 | 表示装置 |
WO2024003963A1 (ja) * | 2022-06-27 | 2024-01-04 | シャープ株式会社 | 表示パネルの制御装置、表示装置、および表示パネルの制御装置による制御方法 |
Also Published As
Publication number | Publication date |
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JP6169191B2 (ja) | 2017-07-26 |
TWI581237B (zh) | 2017-05-01 |
CN105830144A (zh) | 2016-08-03 |
US9842545B2 (en) | 2017-12-12 |
CN105830144B (zh) | 2018-09-11 |
JPWO2015093097A1 (ja) | 2017-03-16 |
TW201525966A (zh) | 2015-07-01 |
US20160300534A1 (en) | 2016-10-13 |
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