WO2015089914A1 - 用于液晶显示的goa电路及显示装置 - Google Patents

用于液晶显示的goa电路及显示装置 Download PDF

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Publication number
WO2015089914A1
WO2015089914A1 PCT/CN2014/070115 CN2014070115W WO2015089914A1 WO 2015089914 A1 WO2015089914 A1 WO 2015089914A1 CN 2014070115 W CN2014070115 W CN 2014070115W WO 2015089914 A1 WO2015089914 A1 WO 2015089914A1
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Prior art keywords
circuit
thin film
film transistor
clock signal
gate
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/070115
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English (en)
French (fr)
Inventor
虞晓江
李长晔
赖梓杰
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TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to GB1607005.4A priority Critical patent/GB2534755B/en
Priority to US14/345,759 priority patent/US9159280B1/en
Priority to JP2016533627A priority patent/JP6208872B2/ja
Priority to KR1020167014120A priority patent/KR101817027B1/ko
Publication of WO2015089914A1 publication Critical patent/WO2015089914A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the liquid crystal display has many advantages such as thin body, power saving, and no radiation, and has been widely used.
  • Most of the liquid crystal displays on the market today are backlight type liquid crystal displays, which include a liquid crystal panel and a backlight module.
  • the working principle of the liquid crystal panel is to place liquid crystal molecules in two parallel glass substrates, and apply driving voltages on the two glass substrates to control the rotation direction of the liquid crystal molecules to refract the light of the backlight module to produce a picture.
  • each pixel has a thin film transistor (TFT) whose gate (Gate) is connected to a horizontal scanning line, a drain (Drain) is connected to a vertical data line, and a source (Source) is connected to Pixel electrode.
  • TFT thin film transistor
  • the driving of the horizontal scanning line of the active liquid crystal display panel is mainly completed by the external IC of the panel, and the external IC can control the stepwise charging and discharging of the horizontal scanning lines of each level.
  • GO A technology that is, Gate Driver on Array technology, can use the original process of the liquid crystal display panel to make the horizontal scanning line driving circuit on the substrate around the display area, so that it can replace the external IC to complete The drive of the horizontal scan line.
  • GOA technology can reduce the bonding process of external ICs, which has the potential to increase productivity and reduce product cost, and can make LCD panels more suitable for narrow-frame or borderless display products.
  • the existing GOA circuit generally includes a plurality of cascaded GOA units, and each level of the GOA unit corresponds to driving a level one ice level scan line.
  • the main structure of the GOA unit includes a pull-up circuit (Pull- ⁇ ⁇ part), a pull-up control part, a transfer part, a key pull-down part, and a pull-down sustain circuit. (Pull-down Holding Part), and the bootstrap (Boast) capacitor responsible for potential lift.
  • the pull-up circuit is mainly responsible for outputting the clock signal (Clock) as a gate signal; the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit, and generally connecting the downlink signal or the Gate signal transmitted by the GOA circuit of the previous stage; The circuit is responsible for pulling Gate low to low level at the first time, that is, turning off the Gate letter.
  • the pull-down sustain circuit is responsible for maintaining the Gate output signal and the Gate signal of the pull-up circuit (commonly referred to as the Q point) in the off state (ie, the negative potential), usually with two pull-down sustain blocks alternately;
  • the capacitor (C boast is responsible for the secondary rise of the Q point, which is beneficial to the G(N) output of the pull-up circuit.
  • the purpose of the GOA circuit is to output the scan waveform of the integrated circuit output through circuit operation, so that the pixel switch is turned on to input a data signal to the indium tin oxide (ITO) electrode. After the data signal is input, the data signal content is held until the next frame is turned on.
  • the scanning circuit since the scanning circuit is turned off after being turned on for a frame, the scanning circuit is turned off (maintained) for a much longer time than the scanning time, and the specific requirements for the stability of the thin film transistor in the GOA circuit are high.
  • the voltage of the IGBT 'Pole Q(n) of the thin film transistor which affects the horizontal scanning line charging in the GOA circuit is required to obtain an accurate control solution. Summary of the invention
  • Another object of the present invention is to provide a liquid crystal display device using the above GOA circuit, which can accurately control the gate Q(ri) voltage of a thin film transistor which affects horizontal scanning line charging by a low frequency clock signal and a high frequency clock signal, thereby Guaranteed stable output of the GOA charging signal.
  • the present invention provides a GOA circuit for liquid crystal display, comprising a plurality of cascaded GOA units, and controlling charging of an nth horizontal scanning line of a display area according to a level II GOA unit, the nth stage
  • the GOA unit includes a pull-up circuit, a pull-down circuit, a pull-down sustain circuit, a pull-up control circuit, and a bootstrap capacitor, the pull-up circuit, the pull-down circuit, the pull-down sustain circuit, and the bootstrap capacitor respectively and the gate signal point and the nth level a scan line connection, the pull-up control circuit is connected to the gate signal point;
  • the pull-down maintenance circuit includes:
  • a first thin film transistor having a gate connected to the first circuit point, and a drain and a source respectively connected to the nth horizontal scanning line and the input DC low voltage;
  • a second thin film transistor having a gate connected to the second circuit point, a drain and a source respectively connected to the nth horizontal scanning line and inputting the DC low voltage;
  • a third thin film transistor having a gate connected to the gate signal point, a drain and a source respectively connected to the first circuit point and inputting the DC low voltage;
  • a fourth thin film transistor having a gate connected to the gate signal point, and a drain and a source respectively connected to the gate a second circuit point and inputting the DC low voltage
  • a fifth thin film transistor having a drain and a source respectively connected to the tree signal point and the nth stage water, wherein the drain and the source respectively input an nth clock signal and the second drain and the source are respectively connected to the drain
  • the pole and the source are respectively connected to the drain and the source respectively
  • a tenth thin film transistor having a gate inputting the second clock signal, and a drain and a source respectively inputting the second clock signal and a cabinet connected to the sixth thin film transistor;
  • the first clock signal and the second clock signal have a lower frequency than the nth-level clock signal, and the first clock signal charges the first circuit point and the second clock signal corresponds to the second circuit The charging of the points alternates.
  • the pull-up circuit includes: an eleventh thin film transistor having a gate connected to the gate signal point, and a drain and a source respectively inputting the nth-level clock signal and connecting the nth-level horizontal scan line.
  • the pull-down circuit includes: a twelfth thin film transistor having a gate connected to the 11th and 2nd horizontal scanning lines, a drain and a source respectively connected to the nth horizontal scanning line and inputting the DC low voltage;
  • the thin film transistor has a gate connected to the n+2th horizontal scan line, and a drain and a source respectively connected to the gate signal point and inputting the DC low voltage.
  • the pull-up control circuit comprises: a fourteenth thin film transistor having a gate connected to the n-th horizontal scanning line, and a drain and a source respectively connected to the n-th horizontal scanning line and the cabinet signal point.
  • the duty ratio of the nth clock signal is 40%.
  • the first clock signal is input to the cascaded plurality of GOA units through a common metal line.
  • the second clock signal is input to the cascaded plurality of GOAs by a common metal line.
  • the DC low voltage is input to the cascaded plurality of GOA units through a common metal line.
  • the present invention also provides a GOA circuit for liquid crystal display, comprising a plurality of cascaded GOA units, controlling charging of a level II horizontal scanning line of a display area according to an nth stage GOA unit
  • the nth stage GOA unit includes a pull-up circuit, a pull-down circuit, a pull-down sustain circuit, a pull-up control circuit, and a bootstrap capacitor, the pull-up circuit, the pull-down circuit, the pull-down sustain circuit, and the bootstrap capacitor respectively and the gate signal point and the An nth horizontal scanning line is connected, and the pull-up control circuit is connected to the cabinet signal point;
  • the pull-down maintenance circuit includes:
  • a first thin film transistor having a gate connected to the first circuit point, and a drain and a source respectively connected to the nth horizontal scanning line and the input DC low voltage;
  • a second thin film transistor having a gate connected to the second circuit point, and a drain and a source respectively connected to the nth horizontal scanning line and the input DC low voltage;
  • a third thin film transistor having a bridge connected to the gate signal point, a drain and a source respectively connected to the first circuit point and inputting the DC low voltage;
  • a fourth thin film transistor having a gate connected to the gate signal point, a drain and a source respectively connected to the second circuit point and inputting the DC low voltage
  • a fifth thin film transistor having a drain and a source connected to the tree signal signal point and the nth level horizontal scan line;
  • a sixth thin film transistor having a drain and a source respectively inputting an nth-level clock signal and a gate connected to the fifth thin film transistor;
  • a seventh thin film transistor having a gate inputting a first clock signal, a drain and a source being respectively connected to a gate of the sixth thin film transistor and the first circuit point;
  • An eighth thin film transistor having a gate inputting a second clock signal, and a drain and a source are respectively connected to a gate of the sixth thin film transistor and the second circuit point;
  • a ninth thin film transistor the gate thereof inputs the first clock signal, the drain and the source respectively input the first clock signal and the gate connected to the sixth thin film transistor;
  • a tenth thin film transistor wherein a tree clock inputs the second clock signal, and a drain and a source respectively input the second clock signal and connect to a gate of the sixth thin film transistor;
  • the first clock signal and the second clock signal have a lower frequency than the nth-level clock signal, and the first clock signal charges the first circuit point and the second clock signal corresponds to the second circuit Point charging alternates;
  • the pull-up circuit includes: an eleventh thin film transistor having a gate connected to the gate signal point, a drain and a source respectively inputting the nth clock signal and connecting the nth horizontal scan line; wherein
  • the pull-down circuit includes: a twelfth thin film transistor having a gate connected to the 11th + 2nd horizontal scanning line, a drain and a source respectively connected to the nth horizontal scanning line and inputting the DC low voltage; the thirteenth thin film transistor, The gate is connected to the n+2th horizontal scan line, and the drain and the source are respectively connected to the gate signal point and the DC low voltage is input.
  • the pull-up control circuit comprises: a fourteenth thin film transistor, the drain of which is connected to the nth-level horizontal scan line, and the drain and the source are respectively connected to the n-th level horizontal scan line and the cabinet signal point.
  • the duty cycle of the nth stage clock signal is 40%.
  • the first clock signal is input to the cascaded plurality of GOA units through a common metal line.
  • the second clock signal is input to the cascaded plurality of GOA units through a common metal line.
  • the DC low voltage is input to the cascaded plurality of GOA units through a common metal line.
  • the present invention also provides a display device comprising the GO A circuit for liquid crystal display as described above.
  • the GOA circuit and the display device for liquid crystal display of the present invention can accurately control the voltage of the thin film transistor bridge Q(n) which affects the horizontal scanning line charging during the charging period and the non-charging period by the low frequency clock signal and the high frequency clock signal. A stable output of the GOA charging signal is ensured; a low-cost narrow-frame or borderless liquid crystal display device can be fabricated by using the GOA circuit of the present invention.
  • FIG. 1 is a circuit diagram of an embodiment of a GOA circuit (single stage) for liquid crystal display of the present invention
  • FIG. 2 is a schematic diagram showing an output waveform of a GOA circuit for liquid crystal display at normal temperature according to the present invention
  • FIG. 3 is a schematic diagram showing a multi-stage architecture of a GOA circuit for liquid crystal display according to the present invention
  • Fig. 4 is a view showing the configuration of a liquid crystal display device to which a GOA circuit for liquid crystal display of the present invention is applied. Concrete real way
  • the GOA circuit of the present invention may include a plurality of cascaded GOA units, and control the charging of the nth horizontal scanning line G(n) in the display area according to the nth stage GOA unit, the first!
  • the stage GOA unit includes a pull-up circuit 100, a pull-down circuit 200, a pull-down sustain circuit 300, a pull-up control circuit 400, and a bootstrap capacitor Cb.
  • the pull-down sustain circuit 300 and the bootstrap capacitor Cb are respectively
  • the gate signal point Q(n) is connected to the 11th horizontal scanning line G(n)
  • the pull-up control circuit 400 is connected to the gate signal point Q(n).
  • the pull-up circuit 100 includes direct control for charging the second horizontal scanning line G(n) of the display area.
  • the thin film transistor T21 has a drain connected to the gate signal point Q (n), and the drain and the source of the T21 are input to the nth high frequency clock signal CK(n) and the nth horizontal scan line G, respectively. (n), the potential of the gate Q(n) of T21 can directly affect CK(n) charging G(n).
  • the pull-down circuit 200 includes a group of thin film transistors that discharge at the end of G(ii) charging, including T31 that discharges G(n) and T41 that discharges Q(rs); T31 gates are connected to the n+2th stage a horizontal scanning line G (ii--2), the drain and the source are respectively connected to the 11th horizontal scanning line G(n) and the DC low voltage VSS is input; the T41 gate is connected to the +2 horizontal scanning line G (n--2), the drain and source are connected to the gate signal point Q(n) and the input DC low voltage V.SS, respectively.
  • the pull-up control circuit 400 includes a thin film transistor T1 whose gate is connected to the n-th horizontal scanning line G (n-2), and the drain and the source are respectively connected to the n-2th horizontal scanning line G (n-2) And the gate signal point Q (11).
  • the thin film transistor Til can control the transfer of the n-th grade GOA signal to the nth stage GOA circuit, so that the GOA circuit can be charged and discharged step by step.
  • a capacitor Cb with a bootstrap function connected between (n) and G(n) can increase the Q(n) potential by the coupling effect of Cb when the G(n) potential is raised, thereby obtaining a higher Q.
  • the pull-down sustain circuit (300) includes a set of thin film transistors that can maintain the low potential of G(n) and Q(n) during the non-charging period of the GOA circuit.
  • the gate of the thin film transistor T32 is connected to the first circuit point P, the drain and the source are respectively connected to the nth horizontal scanning line G(n) and the input DC low voltage VSS;
  • the thin film transistor T33 is connected to the second circuit point K,
  • the drain and the source are respectively connected to the second horizontal scanning line G ( ⁇ ) and the input DC low voltage VSS;
  • the gate of the thin film transistor T52 is connected to the ⁇ -pole signal point Q ( ⁇ ), the drain and the source are respectively Connecting the first circuit point P and the input DC low voltage VSS;
  • the gate of the thin film transistor T62 is connected to the gate signal point Q (n ), and the drain and the source are respectively connected to the second circuit point K and the DC low voltage VSS;
  • the thin film transistor T43 The drain and the source are respectively connected
  • the first clock signal LC1 charges the first circuit point P and the second clock signal LC2 the second circuit point
  • the charging of K alternates.
  • the P and K points of the circuit are alternately charged by the low frequency clock signals LCI and LC2 to alternately control the opening of the thin film transistor T32 or T33 to maintain the low potential of G(n) during the non-charging period and avoid the film.
  • Transistor T32 or T33 is affected by the voltage stress of the cabinet for a long time.
  • Thin film transistor T52 is connected to P point and input DC low voltage VSS
  • thin film transistor T62 is connected to K point and input DC low voltage VSS
  • T52 and T62 can be turned on when Q(n) is high and P point is set.
  • the K point potential is turned off to turn off T32 and T33 so that it does not affect charging.
  • the thin film transistor ⁇ 2 & ⁇ 72 or T13 & T73 will be turned on, P point or K point will be at a high potential, so the gate of the thin film transistor T42 is at a high potential, and the high frequency clock signal CK(n) can periodically turn on the thin film transistor T43. Keep Q(n) at a low potential.
  • T52 or T62 is turned on, the gate potential of T42 is pulled low, and T42 is turned off, and T43 cannot be turned on, so the leakage of Q(n) through T43 is also reduced. The stability of the Q(n) voltage is improved.
  • the GOA circuit of the present invention can accurately control the voltage of the gate Q(ii) of the thin film transistor which affects the horizontal scanning line charging in the non-charging period and the charging period by the low frequency clock signal and the high frequency clock signal, thereby ensuring the GOA charging signal. Stable output. Specifically: 1. During the non-charging period, the high-frequency clock signal CK(n) and the thin film transistor T42 of the thin film transistor T43 are turned on, and the high-frequency clock signal CK(Ti) can periodically turn on the thin film transistor T43 to maintain Q. (n) is at a low potential; 2. During the charging period, after Q(n) is charged to a high potential, the thin film transistors T42 and T43 are turned off - and Q(n) is lowered by the leakage of T43.
  • FIG. 2 it is a schematic diagram of an output waveform of a GOA circuit for liquid crystal display at normal temperature, wherein a high frequency clock signal has a duty ratio of 40%.
  • tl to t3 are preparation times before G(ri) charging
  • t3 to t4 are charging times of G(n)
  • G(n) is discharged after t4.
  • the low frequency clock signals LC1 and LC2 can be selected to have the same frequency and opposite phases.
  • Figure 2 can be understood in conjunction with Figure 1.
  • tl the potential of CK(n 2) begins to rise, and the potential of G(n 2) also begins to rise.
  • the thin film transistor Ti l turns on to charge Q(n).
  • the thin film transistors T52 and T62 can be turned on, thereby turning off T32, ⁇ 42, ⁇ 33, and ⁇ 43 so as not to affect Q(n) and G(n) charging.
  • the potential of CK(n-2) begins to decrease, but the connection mode of the thin film transistor Ti1 prevents the leakage of Q(n), and the Q(ri) potential remains substantially unchanged.
  • the potential of CK(n) starts to rise, thin film transistor T21 turns on, Q(n) boots up to a higher potential and T21 charges G(n).
  • CK(n) begins to fall, and the Q(n) potential is not immediately pulled low.
  • the thin film transistor T21 remains on for a short time after 14 and pulls the G(n) potential low. After this, the G(n+2) potential rises, The thin film transistors T31 and T41 are turned on to ensure that G(n) and Q(n) are pulled to a low potential. T52 and T62 are turned off after the Q(ri) potential is pulled low, and T32, T33, T42, and T43 can be normally turned on to maintain the low potential of G(n) and Q(n) during the non-charging period.
  • the present invention can accurately control the Q(n) voltage through the low frequency clock signal and the high frequency clock signal, and can ensure the stable output of the GOA charging signal.
  • FIG. 3 there is shown a multi-level architectural schematic of a GOA circuit for liquid crystal display of the present invention.
  • Figure 3 shows a multi-stage architecture of the GOA circuit of the present invention, which is used to transfer the low frequency clock signals LC1 and LC2, the DC low voltage VSS, and the four high frequency clock signals of CKi ⁇ CK4.
  • the periphery of the GOA circuit (see Figure 1 for the specific connection method).
  • Low-frequency clock signal LC2 and dc low-voltage VSS can be input into multiple GOA units cascaded through their respective common metal lines.
  • the nth stage GOA circuit accepts ⁇ CK signals in LCL LC2, VSS, CK CK4, G(n-2) generated in the ⁇ -2 stage GO ⁇ circuit, and rH-2 level GO, respectively.
  • the A circuit generates G(rH-2) and produces a G(n) signal.
  • the connection method between the GOA circuits shown in Figure 3 ensures that the GOA signal can be transmitted step by step, so that the horizontal scanning lines of each level can be charged and discharged step by step. For the first.
  • the GOA unit cascaded at the end can replace the missing G(n) signal ⁇ m8 by means of an input activation signal.
  • the GOA circuit of the present invention can use the original process of the liquid crystal display panel to make the driving circuit of the horizontal scanning line of the panel on the substrate around the display area, so that it can replace the external IC to complete the driving of the horizontal scanning lines of the flat display panel.
  • the invention is particularly suitable for making narrow border or borderless liquid crystal display products.
  • FIG. 4 there is shown a schematic structural view of a liquid crystal display device to which a GOA circuit for liquid crystal display of the present invention is applied.
  • the liquid crystal display device has a display substrate 10, and a drive control panel 20 above the display substrate 10 provides driving and control signals for the display substrate 10.
  • the left side of the display substrate 10, the area 30 and the right area 40, are made of GOA circuits, which can be left.
  • the horizontal scanning line of the display area 50 is driven in the right direction.
  • the GOA circuit accepts the input signal of the drive control board 20 and generates control signals of the horizontal scan line step by step, and can control the pixels in the display area 50 to be turned on line by line.
  • the GOA circuit and the display device for liquid crystal display of the present invention can accurately control the gate of the thin film transistor Q(ri) which affects the charging of the horizontal scanning line by the low frequency clock signal and the high frequency clock signal during the charging period and The voltage during the charging period ensures the stable output of the GOA charging signal; the low-cost narrow-frame or borderless liquid crystal jUi F can be fabricated using the GOA circuit of the present invention.

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Abstract

一种用于液晶显示的GOA电路及显示装置。该GOA电路包括级联的多个GOA单元，第n级GOA单元包括上拉电路（100）、下拉电路（200）、下拉维持电路（300）、上拉控制电路（400）及自举电容（Cb）。工作时，分别输入第n级时钟信号（CK（n））、第一和第二时钟信号（LC1，LC2），该第一时钟信号（LC1）和该第二时钟信号（LC2）的频率低于该第n级时钟信号（CK（n）），并且该第一时钟信号（LC1）对第一电路点（P）的充电和第二时钟信号（LC2）对第二电路点（K）的充电交替进行。该GOA电路通过低频时钟信号和高频时钟信号来准确控制影响水平扫描线充电的栅极（Q（n））的电压，从而保证GOA充电信号的稳定输出。

Description

用于液晶显示的 GO A电路及显示装置
尤其涉及一种用于液晶显示的 GOA ) 电路及显示装置。
液晶显示器具有机身薄、 省电、 无辐射等众多优点， 得到了广泛的应 用。 现有市场上的液晶显示器大部分为背光型液晶显示器， 其包括液晶面 板及背光模组 ( backlight module ) 。 液晶面板的工作原理是在两片平行的 玻璃基板当中放置液晶分子， 并在两片玻璃基板上施加驱动电压来控制液 晶分子的旋转方向， 以将背光模组的光线折射出来产生画面。
主动式液晶显示器中， 每个像素具有一个薄膜晶体管 （TFT ) , 其柵 极（Gate )连接至水平扫描线， 漏极 ( Drain )连接至垂直方向的数据线, 源极 ( Source ) 则连接至像素电极。 在水平扫描线上施加足够的电压, 会 使^ 该条线上的所有 TFT打开， 此时该水平扫描线上的像素电极会与垂直 方向的数据线连接， 从而将数据线上的显示信号电压写入像素， 控制不同 液晶的透光度进而达到控制色彩的效果。 目前主动式液晶显示面板水平扫 描线的驱动主要由面板外接的 IC来完成， 外接的 IC可以控制各級水平扫 描线的逐级充电和放电。 GO A技术， 即 Gate Driver on Array (阵列基 板行驱动）技术， 可以运用液晶显示面板的原有制程将水平扫描线的驱动 电路制作在显示区周围的基板上， 使之能替代外接 IC 来完成水平扫描线 的驱动。 GOA技术能减少外接 IC的绑定（bonding )工序， 有机会提升产 能并降低产品成本， 而且可以使液晶显示面板更适合制作窄边框或无边框 的显示产品。
现有的 GOA电路， 通常包括级联的多个 GOA单元， 每一级 GOA单 元对应驱动一级氷平扫描线。 GOA单元的主要结构包括上拉电路（Pull- ιιΡ part ) ， 上拉控制电 （ Pull- up control part ) , 下传电路 (Transfer Part), 下 拉电路 ( Key Pull-down Part ) 和下拉维持电路 ( Pull-down Holding Part ) ， 以及负责电位抬升的自举 ( Boast ) 电容。 上拉电路主要负责将时 钟信号 （Clock )输出为柵极（Gate )信号； 上拉控制电路负责控制上拉电 路的打开时间， 一般连接前面级 GOA 电路传递过来的下传信号或者 Gate 信号； 下拉电路负责在第一时间将 Gate 拉低为低电位， 即关闭 Gate 信 号； 下拉维持电路則负责将 Gate输出信号和上拉电路的 Gate信号 （通常 称为 Q 点） 维持（Holding )在关闭状态 （即负电位） , 通常有两个下拉 维持模块交替作用； 自举电容（ C boast 則负责 Q点的二次抬升， 这样有 利于上拉电路的 G(N)输出。
GOA 电路的目的就是将集成电路输出的扫描波形通过电路操作的方 式输出， 使像素开关打开从而可以向氧化铟锡 ( ITO ) 电极输入数据信 号。 数据信号输入完后将数据信号内容保持住直到下一帧的开启。 在电路 操作过程中， 因一条扫描电路打开过后在一帧剩余的时间里都是关闭的 , 扫描电路关闭 （保持） 时间比扫描时间长很多， 对 GOA 电路中的薄膜晶 体管稳定特定要求很高。 为保证 GOA 电路充电信号的稳定输出， 亟需 GOA 电路中影响水平扫描线充电的薄膜晶体管的棚 '极 Q(n)的电压能够得 到准确控制的解决方案。 发明内容
因此， 本发明的目的在于提供一种用于液晶显示的 GOA 电路， 实现 通过低频时钟信号和高频时钟信号来准确控制影响水平扫描线充电的薄膜 晶体管的栅极 Q(n)电压， 从而保证 GOA充电信号的稳定输出。
本发明的另一目的在于提供一种应用上述 GOA 电路的液晶显示装 置， 实现通过低频时钟信号和高频时钟信号来准确控制影响水平扫描线充 电的薄膜晶体管的柵极 Q(ri)电压， 从而保证 GOA充电信号的稳定输出。
为实现上述目的， 本发明提供了一种用于液晶显示的 GOA 电路， 包 括级联的多个 GOA单元， 按照第 II级 GOA单元控制对显示区域第 n级水 平扫描线充电， 该第 n级 GOA单元包括上拉电路、 下拉电路、 下拉维持 电路、 上拉控制电路及自举电容， 该上拉电路、 下拉电路、 下拉维持电路 及自举电容分别与柵极信号点和该第 n级水平扫描线连接， 该上拉控制电 路与该柵极信号点连接；
该下拉维持电路包括：
第一薄膜晶体管， 其柵极连接第一电路点， 漏极和源极分别连接该第 n级水平扫描线和输入直流低电压；
第二薄膜晶体管， 其栅极连接第二电路点， 漏极和源极分别连接该第 n级水平扫描线和输入该直流低电压;
第三薄膜晶体管， 其柵极连接该栅极信号点， 漏极和源极分别连接该 第一电路点和输入该直流低电压；
第四薄膜晶体管， 其柵极连接该柵极信号点， 漏极和源极分别连接该 第二电路点和输入该直流低电压；
第五薄膜晶体管， 其漏极和源极分别连接该树极信号点和该第 n级水 其漏极和源极分别输入第 n级时钟信号和连接该第 漏极和源极分别连接该 漏极和源极分别连接该 漏极和源极分别输入
Figure imgf000005_0001
第十薄膜晶体管， 其柵极输入该第二时钟信号， 漏极和源极分别输入 该第二时钟信号和连接该第六薄膜晶体管的橱极；
工作时， 该第一时钟信号和该第二时钟信号的频率低于该第 n级时钟 信号， 并且该第一时钟信号对该第一电路点的充电和该第二时钟信号对该 第二电路点的充电交替进行。
其中， 该上拉电路包括： 第十一薄膜晶体管， 其柵极连接该柵极信号 点， 漏极和源极分别输入该第 n級时钟信号和连接该第 n级水平扫描线。
其中， 该下拉电路包括： 第十二薄膜晶体管， 其柵极连接第 11+2级水 平扫描线， 漏极和源极分别连接该第 n级水平扫描线和输入该直流低电 压； 第十三薄膜晶体管， 其栅极连接该第 n+2级水平扫描线， 漏极和源极 分别连接该栅极信号点和输入该直流低电压。
其中， 该上拉控制电路包括： 第十四薄膜晶体管， 其柵极连接第 n 2 级水平扫描线， 漏极和源极分别连接该第 n- 2 級水平扫描线和该櫥极信号 点。
其中， 该第 n级时钟信号的占空比为 40%。
其中， 该第一时钟信号通过^^共的金属线输入所述级联的多个 GOA 单元。
其中， 该第二时钟信号通过公共的金属线输入所述级联的多个 GOA 单'元„
其中， 该直流低电压通过公共的金属线输入所述级联的多个 GOA单 元。
本发明还提供一种用于液晶显示的 GOA电路， 包括级联的多个 GOA 单元， 按照第 η级 GOA单元控制对显示区域第 II级水平扫描线充电， 该 第 n级 GOA单元包括上拉电路、 下拉电路、 下拉维持电路、 上拉控制电 路及.自举电容， 该上拉电路、 下拉电路、 下拉维持电路及自举电容分别与 柵极信号点和该第 n级水平扫描线连接， 该上拉控制电路与该櫥极信号点 连接；
该下拉维持电路包括：
第一薄膜晶体管， 其柵极连接第一电路点， 漏极和源极分别连接该第 n級水平扫描线和输入直流低电压；
第二薄膜晶体管， 其栅极连接第二电路点， 漏极和源极分别连接该第 n级水平扫描线和输入直流低电压;
第三薄膜晶体管， 其橋极连接该栅极信号点， 漏极和源极分别连接该 第一电路点和输入该直流低电压；
第四薄膜晶体管， 其柵极连接该柵极信号点， 漏极和源极分别连接该 第二电路点和输入该直流低电压；
第五薄膜晶体管， 其漏极和源极分别连接该树极信号点和该第 n级水 平扫描线；
第六薄膜晶体管， 其漏极和源极分别输入第 n级时钟信号和连接该第 五薄膜晶体管的柵极；
第七薄膜晶体管， 其栅极输入第一时钟信号， 漏极和源极分别连接该 第六薄膜晶体管的栅极和该第一电路点；
第八薄膜晶体管， 其柵极输入第二时钟信号， 漏极和源极分别连接该 第六薄膜晶体管的栅极和该第二电路点；
第九薄膜晶体管， 其柵极输入该第一时钟信号， 漏极和源极分别输入 该第一时钟信号和连接该第六薄膜晶体管的栅^ I；
第十薄膜晶体管， 其树极输入该第二时钟信号， 漏极和源极分别输入 该第二时钟信号和连.接该第六薄膜晶体管的栅极；
工作时， 该第一时钟信号和该第二时钟信号的频率低于该第 n级时钟 信号， 并且该第一时钟信号对该第一电路点的充电和该第二时钟信号对该 第二电路点的充电交替进行；
其中， 该上拉电路包括： 第十一薄膜晶体管， 其柵极连接该柵极信号 点， 漏极和源极分别输入该第 n級时钟信号和连接该第 n级水平扫描线； 其中， 该下拉电路包括： 第十二薄膜晶体管， 其柵极连接第 11+2级水 平扫描线， 漏极和源极分别连接该第 n级水平扫描线和输入该直流低电 压； 第十三薄膜晶体管， 其栅极连接该第 n+2级水平扫描线， 漏极和源极 分别连接该栅极信号点和输入该直流低电压。 该上拉控制电路包括： 第十四薄膜晶体管， 其櫪极.连接第 n 2 级水平 扫描线， 漏极和源极分别连接该第 n- 2级水平扫描线和该櫥极信号点。
该第 n级时钟信号的占空比为 40%。
该第一时钟信号通过公共的金属线输入所述级联的多个 GOA单元。 该第二时钟信号通过公共的金属线输入所述级联的多个 GOA单元。 该直流低电压通过公共的金属线输入所述级联的多个 GOA单元。
本发明还提供了一种显示装置， 包括如上面所述的用于液晶显示的 GO A电路。
本发明的用于液晶显示的 GOA 电路及显示装置可以通过低频时钟信 号和高频时钟信号来准确控制影响水平扫描线充电的薄膜晶体管橋极 Q(n) 在充电时期及非充电时期的电压， 保证 GOA 充电信号的稳定输出； 运用 本发明的 GOA电路可以制作低成本的窄边框或无边框的液晶显示装置。 附图说明
下面结合附图， 通过对本发明的具体实施方式详细描述， 将使本发明 的技术方案及其他有益效果显而易见。
附图中，
图 1 为本发明用于液晶显示的 GOA 电路（单級） 一实施例的电路 图；
图 2 为本发明用于液晶显示的 GOA 电路在常温时的输出波形示意 图 3为本发明用于液晶显示的 GOA电路的多级架构示意图；
图 4为应用了本发明用于液晶显示的 GOA 电路的液晶显示装置的结 构示意图。 具体实族方式
参见图 , 其为本发明用于液晶显示的 GOA 电路（单级） 一实施例 的电路图。 本发明的 GOA电路可以包括级联的多个 GOA单元， 按照第 η 级 GOA单元控制对显示区域第 η级水平扫描线 G(n)充电， 第 ]！级 GOA 单元包括上拉电路 100 , 下拉电路 200、 下拉维持电路 300、 上拉控制电路 400及自举电容 Cb, 该上拉电路 100、 下拉电路 200. 下拉维持电路 300 及自举电容 Cb分别与柵极信号点 Q ( n )和第 11级水平扫描线 G ( n )连 接， 该上拉控制电路 400与该栅极信号点 Q ( n )连接。
上拉电路 100包括直接控制给显示区域第 II级水平扫描线 G(n)进行充 电的薄膜晶体管 T21, 其櫪极.连接该栅极信号点 Q (n) , T21的漏极和源 极分别输入第 n级高频时钟信号 CK(n)和连接第 n级水平扫描线 G (n) ， T21栅极 Q(n)的电位可直接影响 CK(n)对 G(n)充电。
下拉电路 200包含在 G(ii)充电结束时进行放电的一组薄膜晶体管， 包 括对 G(n)进行放电的 T31和对 Q(rs)进行放电的 T41; T31栅极连接第 n+2 级水平扫描线 G ( ii--2 ) , 漏极和源极分别连接该第 11 级水平扫描线 G (n)和输入该直流低电压 VSS; T41栅极连接该第 +2级水平扫描线 G ( n--2 ) , 漏极和源极分别连接栅极信号点 Q ( n) 和输入直流低电压 V.SS。
上拉控制电路 400 包括薄膜晶体管 ΊΊ1， 其栅极连接第 n- 2级水平扫 描线 G (n-2) ， 漏极和源极分别连接第 n-2级水平扫描线 G (n-2)和栅 极信号点 Q ( 11 ) 。 薄膜晶体管 Til可以控制将第 n- 2级 GOA信号传递给 第 n级 GOA电路， 使 GOA电路可以逐级充放电。
)(n)和 G(n)之间所连接的有自举功能的电容 Cb, 可在 G(n)电位提升 时通过 Cb的耦合效应使 Q(n)电位提升， 从而获得更高的 Q(ri)电位及更小 的 GOA充电信号的阻容延迟（ RC delay ) 。
下拉维持电路（300) 包括的一组薄膜晶体管可以在 GOA电路非充电 时期保持 G(n)和 Q(n)的低电位。 薄膜晶体管 T32栅极连接第一电路点 P， 漏极和源极分别连接第 n级水平扫描线 G (n)和输入直流低电压 VSS; 薄膜晶体管 T33櫥极连.接第二电路点 K, 漏极和源极分别连.接第 Ώ级水平 扫描线 G ( Ώ )和输入该直流低电压 VSS; 薄膜晶体管 T52栅极连接该楣- 极信号点 Q (η) ， 漏极和源极分别连接该第一电路点 P 和输入直流低电 压 VSS; 薄膜晶体管 T62栅极连接柵极信号点 Q (n ) ， 漏极和源极分别 连接第二电路点 K和直流低电压 VSS; 薄膜晶体管 T43 漏极和源极分别 连.接该栅极信号点 Q (n)和第 n級水平扫描线 G (n) ； 薄膜晶体管 T42 漏极和源极分别输入第 11级时钟信号 CK (n)和薄膜晶体管 T43的櫥极； 薄膜晶体管 T72橋极输入第一时钟信号 1X1， 漏极和源极分别连接薄膜晶 体管 T42的栅 和第一电路点 P; 薄膜晶体管 T73柵极输入第二时钟信号 LC2, 漏极和源极分别连接薄膜晶体管 T42 的柵极和第二电路点 K; 薄膜 晶体管 T12 *极输入第一时钟信号 LC1, 漏极和源极分别输入第一时钟信 号 LC1 和连接薄膜晶体管 T42的 *极； 薄膜晶体管 T13橱极输入第二时 钟信号 LC2, 漏极和源极分别输入第二时钟信号 LC2 和连接薄膜晶体管 T42的棚 ·极； 直流低电压 VSS可以为接低电平或接地。 工作时， 输入第 n 级时钟信号 CK (n) 、 第一时钟信号 LC1 和第二时钟信号 LC2, 第一时 钟信号 LCI和第二时钟信号 LC2的频率低于第 n级时钟信号 CK ( η ) , 并且第一时钟信号 LC1对第一电路点 P的充电和该第二时钟信号 LC2对 该第二电路点 K的充电交替进行。
电路的 P点和 K点交替受低频时钟信号 LCI和 LC2的充电而处于高 电位， 从而交替控制薄膜晶体管 T32或 T33的打开， 以维持 G(n)在非充电 时期的低电位， 并避免薄膜晶体管 T32或 T33长时间受櫥极电压应力的影 响。 薄膜晶体管 T52连接 P点和输入直流低电压 VSS, 薄膜晶体管 T62连 接 K点和输入直流低电压 VSS, T52和 T62可在 Q(n)处于高电位时打开 而将 P点。 K点电位 氏以关闭 T32和 T33使之不影响充电。 在非充电时 期， 薄膜晶体管 ΤΊ2&Τ72或 T13&T73会打开， P点或 K点会处于高电 位， 因此薄膜晶体管 T42 的栅极处于高电位， 高频时钟信号 CK(n)可周期 性打开薄膜晶体管 T43以维持 Q(n)处于低电位。 在充电时期， Q(n)充至高 电位后， T52或 T62打开， T42的栅极电位被拉低而导致 T42关闭， T43 也无法打开， 因此 Q(n)通过 T43的漏电也得以减小， Q(n)电压的稳定性得 以提升。
本发明的 GOA 电路可以通过低频时钟信号和高频时钟信号来准确控 制影响水平扫描线充电的薄膜晶体管的栅极 Q(ii)在非充电时期及充电时期 的电压， 因此能保证 GOA充电信号的稳定输出。 具体来讲： 1、 在非充电 时期， 连接高频时钟信号 CK(n)和薄膜晶体管 T43 的薄膜晶体管 T42 导 通， 高频时钟信号 CK(Ti)可以周期性的打开薄膜晶体管 T43以维持 Q(n)处 于低电位； 2、 在充电时期， Q(n)被充至高电位后， 薄膜晶体管 T42和 T43 被关闭 -, Q(n)通过 T43的漏电得以降'低。
参见图 2， 其为本发明用于液晶显示的 GOA 电路在常温时的输出波 形示意图， 其中高频时钟信号的占空比 （dirty ratio ) 为 40%。 图 2 中， tl〜t3为 G(ri)充电前的准备时间， t3〜t4为 G(n)的充电时间， t4后 G(n)被放 电。 低频时钟信号 LC1 和 LC2可以选择为频率相同， 相位相反。 可结合 图 1 来理解图 2, tl 时， CK(n 2)的电位开始抬升， G(n 2)的电位也跟着开 始抬升， 薄膜晶体管 Ti l打开给 Q(n)充电。 Q(n)电位抬升后， 可打开薄膜 晶体管 T52和 T62 , 从而关闭 T32、 Τ42、 Τ33和 Τ43使之不影响 Q(n)和 G(n)充电。 t2时， CK(n- 2)的电位开始下降， 但薄膜晶体管 Ti l的连接方式 会阻止 Q(n)的漏电， Q(ri)电位基本保持不变。 t3 时， CK(n)的电位开始抬 升， 薄膜晶体管 T21打开， Q(n)自举到更高电位并控制 T21给 G(n)充电。 t4 时， CK(n)开始下降， Q(n)电位并未立即被拉低， 薄膜晶体管 T21 在 14 后的短时间内仍保持导通， 将 G(n)电位拉低。 这之后， G(n+2)电位抬升， 薄膜晶体管 T31和 T41打开， 确保 G(n)和 Q(n)被拉至低电位。 T52和 T62 在 Q(ri)电位拉低后关闭， T32 , T33 , T42 , T43可正常打开， 以维持 G(n) 和 Q(n)在非充电时期的低电位。 综上所述， 本发明可以通过低频时钟信号 和高频时钟信号来准确控制 Q(n)电压， 能保证 GOA 充电信号的稳定输 出。
参见图 3， 其为本发明用于液晶显示的 GOA 电路的多级架构示意 图。 图 3给出了本发明的 GOA 电路的一种多级架构， 用于传递低频时钟 信号 LC1和 LC2、 直流低电压 VSS、 以及 CKi〜CK4的 4个高频时钟信号 的金属线放置于各级 GOA 电路（具体连接方法参见图 1 ) 的外围。 低频 时钟信号 LCL 低频时钟信号 LC2和直流低电压 VSS分别可以通过各自 的公共的金属线输入级联的多个 GOA单元中。 在此实施例中， 第 n级 GOA电路分别接受 LCL LC2、 VSS , CK CK4中的 ί 个 CK信号、 第 η- 2级 GO Α电路产生的 G(n- 2)、 第 rH- 2级 GO A电路产生的 G(rH- 2)， 并产 生 G(n)信号。 图 3所示的各级 GOA电路间的连接方法可保证 GOA信号 可以逐级传递， 使得各级水平扫描线可以被逐级充电和放.电。 对于首。 末 端级联的 GOA单元可以采用输入激活信号的方式来代替缺少的 G ( n )信 Ί m八。
本发明的 GOA 电路可以运用液晶显示面板的原有制程将面板水平扫 描线的驱动电路制作在显示区周围的基板上， 使之能替代外接 IC 来完成 平板显示面板各级水平扫描线的驱动。 本发明尤其适合制作窄边框或无边 框的液晶.显示产品。
参见图 4 , 其为应用了本发明用于液晶显示的 GOA 电路的液晶显示 装置的结构示意图。 图 4 中， 液晶显示装置具有显示基板 10， 显示基板 10 上方的驱动控制板 20 为显示基板 10提供驱动和控制信号， 显示基板 10左边.区域 30和右边区域 40制作了 GOA电路， 可从左边和右边两个方 向驱动显示区域 50的水平扫描线。 GOA 电路接受驱动控制板 20 的输入 信号并逐级产生水平扫描线的控制信号， 可以控制显示区域 50 中的像素 逐行打开。
综上所述， 本发明的用于液晶显示的 GOA 电路及显示装置可以通过 低频时钟信号和高频时钟信号来准确控制影响水平扫描线充电的薄膜晶体 管栅极 Q(ri)在充电时期及非充电时期的电压， 保证 GOA充电信号的稳定 输出； 运用本发明的 GOA 电路可以制作低成本的窄边框或无边框的液晶 jUi F衣直。
以上所述， 对于本领域的普通技术人员来说， 可以根据本发明的技术

Claims

】、 一种用于液晶显示的 GOA电路， 包括级联的多个 GOA单元， 按 照第 n级 GOA单元控制对显示区域第 n级水平扫描线充电， 该第 n级 GOA 单元包括上拉电路， 下拉电路、 下拉维持电路、 上拉控制电路及自 举电容， 该上拉电路、 下拉电路、 下拉维持电路及自举电容分别与 *极信 号点和该第 n级水平扫描线连接， 该上拉控制电路与该栅极信号点连接； 该下 4i维持电路包 ^舌：
第一薄膜晶体管， 其橋极连接第一电路点， 漏极和源极分别连接该第 n级水平扫描线和输入直流低电压;
第二薄膜晶体管， 其栅极连接第二电路点， 漏极和源极分别连接该第 n级水平扫描线和输入直流低电压；
第三薄膜晶体管， 其树极连接该 *极信号点， 漏极和源极分别连接该 第一电路点和输入该直流低电压；
第四薄膜晶体管， 其柵极连接该柵极信号点， 漏极和源极分别连接该 第二电路点和输入该直流低电压；
第五薄膜晶体管， 其漏极和源极分别连接该栅极信号点和该第 n级水 第六薄膜晶体管， 其漏极和源极分别输入第 n级时钟信号和连接该第 五薄膜晶体管的柵极；
第七薄膜晶体管， 其柵极输入第一时钟信号， 漏极和源极分别连接该 第六薄膜晶体管的栅极和该第一电路点；
第八薄膜晶体管， 其树极输入第二时钟信号， 漏极和源极分别连接该 第六薄膜晶体管的栅极和该第二电路点；
第九薄膜晶体管， 其栅极输入该第一时钟信号， 漏极和源极分别输入 该第一时钟信号和连接该第六薄膜晶体管的棚_极：
第十薄膜晶体管， 其柵极输入该第二时钟信号， 漏极和源极分别输入 该第二时钟信号和连接该第六薄膜晶体管的栅极；
工作时， 该第一时钟信号和该第二时钟信号的频率低于该第 n级时钟 信号， 并且该第一时钟信号对该第一电路点的充电和该第二时钟信号对该 第二电路点的充电交替进行。
2、 如权利要求 1所述的用于液晶显示的 GOA电路， 其中， 该上拉电 路包括： 第十一薄膜晶体管， 其櫥极连接该櫥极信号点， 漏极和源极分别 输入该第 n级时钟信号和连接该第 n级水平扫描线。
3、 如权利要求 i所述的用于液晶显示的 GOA电路， 其中， 该下拉电 路包括： 第十二薄膜晶体管， 其栅极连接第 ri+2級水平扫描线， 漏极和源 极分别连接该第 n级水平扫描线和输入该直流低电压； 第十三薄膜晶体 管， 其栅极连接该第 n+2级水平扫描线， 漏极和源极分别连接该栅 信号 点和输入该直流低电压。
4、 如权利要求 i所述的用于液晶显示的 GOA电路， 其中， 该上拉控 制电路包括： 第十四薄膜晶体管， 其栅极连接第 n- 2 级水平扫描线， 漏极 和源极分别连接该第 n 2级水平扫描线和该櫥极信号点。
5、 如权利要求 1所述的用于液晶显示的 GOA电路， 其中， 该第 n级 时钟信号的占空比为 40%。
6、 如权利要求 I所述的用于液晶显示的 GOA电路， 其中， 该第一时 钟信号通过公共的金属线输入所述级联的多个 GOA单元。
7、 如权利要求 i所述的用于液晶显示的 GOA电路， 其中， 该第二时 钟信号通过公共的金属线输入所述级联的多个 GOA单元。
8、 如权利要求 1所述的用于液晶显示的 GOA电路， 其中， 该直流低 电压通过公共的金属线输入所述级联的多个 GOA单元。
9、 一种用于液晶显示的 GOA电路， 包括级联的多个 GOA单元, 按 照第 n级 GOA单元控制对显示区域第 n级水平扫描线充电， 该第 Ώ级 GOA 单元包括上拉电路、 下拉电路、 下拉维持电路、 上拉控制电路及自 举电容， 该上拉电路、 下拉电路、 下拉维持电路及自举电容分别与柵极信 号点和该第 n级水平扫描线连接， 该上拉控制电路与该栅极信号点连接； 该下拉维持电路包括：
第一薄膜晶体管， 其树极连接第一电路点， 漏极和源极分别连接该第 n级水平扫描线和输入直流低电压；
第二薄膜晶体管， 其栅极连接第二电路点， 漏极和源极分别连接该第 n级水平扫描线和输入直流低电压；
第三薄膜晶体管， 其柵极连接该栅极信号点， 漏极和源极分别连接该 第一电路点和输入该直流低电压；
第四薄膜晶体管， 其栅极连接该栅极信号点， 漏极和源极分别连接该 第二电路点和输入该直流低电压；
第五薄膜晶体管， 其漏极和源极分别连接该柵极信号点和该第 n级水 第六薄膜晶体管， 其漏极和源极分别输入第 η级时钟信号和连接该第 五薄膜晶体管的栅极；
第七薄膜晶体管， 其树极输入第一时钟信号， 漏极和源极分别连接该 第六薄膜晶体管的柵极和该第一电路点；
第八薄膜晶体管， 其柵极输入第二时钟信号， 漏极和源极分别连接该 第六薄膜晶体管的楣-极和该第二电路点；
第九薄膜晶体管， 其柵极输入该第一时钟信号， 漏极和源极分别输入 该第一时钟信号和连接该第六薄膜晶体管的栅极；
第十薄膜晶体管， 其栅极输入该第二时钟信号， 漏极和源极分别输入 该第二时钟信号和连接该第六薄膜晶体管的栅极；
工作时， 该第一时钟信号和该第二时钟信号的频率低于该第 n级时钟
^号， 且， ^^中信 对该第一电路点的充电和该第二时钟信号对该 其中， 该上拉电路包括： 第十一薄膜晶体管， 其櫥极连接该 *极信号 点， 漏极和源极分别输入该第 n级时钟信号和连接该第 n级水平扫描线; 其中， 该下拉电路包括'： 第十二薄膜晶体管， 其櫥极连接第 n十 2级水 平扫描线， 漏极和源极分别连接该第 n 级水平扫描线和输入该直流低电 压； 第十三薄膜晶体管， 其柵极连接该第 η+·2级水平扫描线， 漏极和源极 分别连接该櫥极信号点和输入该直流低电压。
10, 如权利要求 9所述的用于液晶显示的 GOA 电路， 其中， 该上拉 控制电路包括： 第十 薄膜晶体管， 其柵极连接第 ri- 2 级水平扫描线， 漏 极和源极分别连接该第 η- 2级水平扫描线和该栅极信号点。
11 , 如权利要求 9 所述的用于液晶显示的 GOA 电路， 其中， 该第 n 级时钟信号的占空比为 40%。
12 , 如权利要求 9所述的用于液晶显示的 GOA电路， 其中， 该第一 时钟信号通过.公共的金属线输入所述级联的多个 GOA单元
13 , 如权利要求 9所述的用于液晶显示的 GOA 电路， 其中， 该第二 时钟信号通过公共的金属线输入所述级联的多个 GOA单元
14, 如权利要求 9所述的用于液晶显示的 GOA 电路， 其中， 该直流 低电压通过公共的金属线输入所述级联的多个 GOA单元。
15、 一种显示装置， 包括如权利要求 1 所述的用于液晶显示的 GOA 电路。
PCT/CN2014/070115 2013-12-18 2014-01-03 用于液晶显示的goa电路及显示装置 Ceased WO2015089914A1 (zh)

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JP2016533627A JP6208872B2 (ja) 2013-12-18 2014-01-03 液晶表示に用いられるｇｏａ回路及び表示装置
KR1020167014120A KR101817027B1 (ko) 2013-12-18 2014-01-03 액정 디스플레이용 goa회로 및 디스플레이 장치

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