WO2015083281A1 - 半導体装置 - Google Patents
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- WO2015083281A1 WO2015083281A1 PCT/JP2013/082793 JP2013082793W WO2015083281A1 WO 2015083281 A1 WO2015083281 A1 WO 2015083281A1 JP 2013082793 W JP2013082793 W JP 2013082793W WO 2015083281 A1 WO2015083281 A1 WO 2015083281A1
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- power supply
- supply voltage
- wiring
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 133
- 239000003990 capacitor Substances 0.000 claims abstract description 135
- 239000010410 layer Substances 0.000 claims description 110
- 229910052751 metal Inorganic materials 0.000 claims description 95
- 239000002184 metal Substances 0.000 claims description 95
- 238000000034 method Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 14
- 230000006870 function Effects 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 7
- 230000009467 reduction Effects 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 description 19
- 241000839426 Chlamydia virus Chp1 Species 0.000 description 18
- JPKJQBJPBRLVTM-OSLIGDBKSA-N (2s)-2-amino-n-[(2s,3r)-3-hydroxy-1-[[(2s)-1-[[(2s)-1-[[(2s)-1-[[(2r)-1-(1h-indol-3-yl)-3-oxopropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxobutan-2-yl]-6-iminohexanamide Chemical compound C([C@H](NC(=O)[C@@H](NC(=O)[C@@H](N)CCCC=N)[C@H](O)C)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@H](CC=1C2=CC=CC=C2NC=1)C=O)C1=CC=CC=C1 JPKJQBJPBRLVTM-OSLIGDBKSA-N 0.000 description 17
- 102100031277 Calcineurin B homologous protein 1 Human genes 0.000 description 17
- 101000777252 Homo sapiens Calcineurin B homologous protein 1 Proteins 0.000 description 17
- 101000943802 Homo sapiens Cysteine and histidine-rich domain-containing protein 1 Proteins 0.000 description 17
- 238000009792 diffusion process Methods 0.000 description 17
- 241001510512 Chlamydia phage 2 Species 0.000 description 13
- 102100031272 Calcineurin B homologous protein 2 Human genes 0.000 description 11
- 101000777239 Homo sapiens Calcineurin B homologous protein 2 Proteins 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 230000002093 peripheral effect Effects 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- 238000009825 accumulation Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 239000013256 coordination polymer Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 102100031077 Calcineurin B homologous protein 3 Human genes 0.000 description 2
- 101000777270 Homo sapiens Calcineurin B homologous protein 3 Proteins 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 102100025292 Stress-induced-phosphoprotein 1 Human genes 0.000 description 2
- 101710140918 Stress-induced-phosphoprotein 1 Proteins 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 101000658644 Homo sapiens Tetratricopeptide repeat protein 21A Proteins 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 102100034913 Tetratricopeptide repeat protein 21A Human genes 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/60—Peripheral circuit regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11868—Macro-architecture
- H01L2027/11874—Layout specification, i.e. inner core region
- H01L2027/11881—Power supply lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
Definitions
- the present invention relates to a semiconductor device, for example, a technology effective when applied to a semiconductor device such as a microcomputer.
- Patent Document 1 power supply potential wiring and ground potential wiring are arranged around each unit cell, and power supply noise is reduced by a decoupling capacitor including power supply potential wiring, ground potential wiring, and an insulating film therebetween. Techniques for reducing are described.
- Patent Document 2 includes an outer peripheral power supply wiring connected to the power supply terminal pad, and an internal circuit power supply wiring (for power supply potential and ground potential) provided between the internal circuit and the outer peripheral power supply wiring. The configuration in which the outer peripheral power supply wiring and the power supply wiring for the internal circuit are connected at only one place is shown. The power supply wiring (for power supply potential) and the power supply wiring (for ground potential) for the internal circuit are arranged close to each other to constitute an RC filter and attenuate EMI noise generated by the internal circuit.
- Patent Document 1 is a technique for reducing power supply noise in an internal circuit (core circuit) in a semiconductor device by using a power supply potential wiring and a ground potential wiring existing in the internal circuit.
- core circuit core circuit
- the required capacitance value cannot be sufficiently secured only by the inter-wiring capacitance in such an internal circuit.
- power supply noise caused by IR drop or the like cannot be sufficiently reduced on the power supply wiring from the power supply terminal to the internal circuit.
- Patent Document 2 is a technique for causing all sections of power supply wiring connecting a power supply terminal and an internal circuit (core circuit) to function as an RC filter.
- a long power supply wiring may be required between the power supply terminal and the internal circuit.
- EMI noise emission noise
- an IR drop tends to occur in the power supply voltage supplied from the power supply terminal to the internal circuit, and the power supply associated therewith
- the internal circuit may malfunction due to noise.
- a semiconductor device includes a single semiconductor substrate, and includes a first region, a first power supply voltage wiring, a power supply source node, a second power supply voltage wiring, and an on-chip capacitor.
- the first region is a region for forming a core circuit unit that executes predetermined processing.
- the first power supply voltage wiring is disposed in the first region and supplies a power supply voltage to the core circuit unit.
- the power supply source node is arranged outside the first region and serves as a power supply voltage supply source.
- the second power supply voltage line connects the power supply source node and the first power supply voltage line.
- the on-chip capacitor has a first electrode formed of a part of the second power supply voltage wiring and a second electrode to which a reference power supply voltage is supplied, and is configured by a unit cell.
- the power supply voltage from the power supply source node is supplied to the core circuit unit via the first electrode.
- noise can be reduced.
- FIG. 1 is a plan view showing an overall schematic configuration example of a semiconductor device according to a first embodiment of the present invention. It is a top view which shows the schematic structural example different from FIG. (A) is a top view which shows the schematic structural example of the wiring board which mounts the semiconductor device of FIG. 1, (b) is a top view which shows the schematic structural example of the wiring board which mounts the semiconductor device of FIG. is there.
- 2 is a circuit diagram showing an example of an equivalent circuit including the power regulator circuit and its periphery in the semiconductor device of FIG.
- FIG. 2 is a circuit block diagram illustrating an actual configuration example around the power regulator circuit in the semiconductor device of FIG. 1.
- FIG. 2 is a schematic diagram illustrating a schematic configuration example of a main part of the semiconductor device of FIG. 1.
- FIG. 3 is a schematic diagram illustrating a schematic configuration example of a main part of the semiconductor device of FIG. 2.
- (A) is a circuit symbol that schematically represents the on-chip capacitor in FIGS. 6 and 7, and
- (b) is a circuit symbol that is a comparative example of (a).
- FIG. 8 is a plan view showing a schematic arrangement example of the on-chip capacitor in the semiconductor device of FIGS. 6 and 7.
- FIG. 8 is a schematic view showing various structural examples of the on-chip capacitor in the semiconductor device of FIGS. 6 and 7.
- (A) is a top view which shows the example of schematic arrangement
- (b) is a part of (a).
- FIG. 11A is a cross-sectional view showing a structural example between AA ′ in FIG. 11B
- FIG. 11B is a cross-sectional view showing a structural example between BB ′ in FIG. is there.
- (A) is a figure which shows an example of the cross-section which represents FIG. 12 (a) simply, and its equivalent circuit
- (b) is the cross-section which becomes a comparative example of FIG. 13 (a), and its equivalent circuit
- FIG. 13 is a cross-sectional view showing a structural example of a metal gate used as a gate wiring in the on-chip capacitors of FIGS. 12 (a) and 12 (b).
- (A) is a top view which shows the schematic example of arrangement
- (b) is (a). It is a top view which shows the detailed layout structural example of the one part area
- (A) is a top view which shows the schematic example of an arrangement
- (A) is a plan view showing a detailed layout configuration example of each on-chip capacitor in FIG.
- FIG. 16 (b), and (b) is a cross-sectional view showing a structural example between CC ′ in (a). is there.
- FIG. 18 is a three-dimensional view schematically showing an example of a part of the structure of the on-chip capacitor shown in FIGS. (A)-(d) is the schematic which shows the structural example from which each principal part differs in the semiconductor device by Embodiment 5 of this invention.
- the constituent elements are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.
- the shapes, positional relationships, etc. of the components, etc. when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.
- each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor).
- CMOS complementary MOS transistor
- FIG. 1 is a plan view showing an overall schematic configuration example of a semiconductor device according to the first embodiment of the present invention.
- FIG. 1 shows a semiconductor chip CHP1 formed of one semiconductor substrate as an example of the semiconductor device.
- CHP1 is, for example, a microcomputer.
- the CHP1 includes an external input / output region (IO region) IOBK in the outer peripheral portion, and includes a core circuit portion CRBK, an analog circuit portion ANGBK, a power supply regulator circuit VREG, and a clock generation circuit portion CKBK.
- a plurality of pads PD are arranged on the IOBK.
- the PD includes a pad PDvcc for the power supply voltage VCC, a pad PDvss for the reference power supply voltage VSS (ground power supply voltage GND), and a pad PDvcl for the internal power supply voltage VDD.
- the analog circuit unit ANGBK includes, for example, various analog circuits represented by an analog / digital conversion circuit and a digital / analog conversion circuit. Although illustration is omitted, for example, ANGBK is directly supplied with power from the pad PD.
- the power supply regulator circuit VREG receives the power supply voltage VCC from the pad PDvcc and the reference power supply voltage VSS from the pad PDvss, and generates an internal power supply voltage VDD.
- VCC is 2.7 V to 5.5 V
- VDD is 1.1 V to 1.8 V.
- the clock generation circuit unit CKBK includes, for example, a crystal oscillation circuit, a PLL (phase locked loop) circuit, and the like, and generates various clock signals used in the semiconductor chip CHP1.
- the core circuit unit CRBK is a circuit unit that performs predetermined processing by the internal power supply voltage VDD supplied from the power supply regulator circuit VREG and applies process miniaturization.
- the CRBK includes a nonvolatile memory ROM such as a flash memory, a volatile memory RAM such as an SRAM (Static Random Access Memory), a processor circuit CPU, and various peripheral circuits PERI such as a timer circuit and a serial communication circuit.
- the CRBK also includes a main power supply voltage wiring MLVDM arranged along the outer periphery and sub power supply voltage wiring MLVDS branched from the MLVDM and arranged in a mesh pattern.
- the MLVDS is usually formed with a thinner wire than the MLVDM.
- the main power supply voltage wiring MLVDM is connected to the output of the power supply regulator circuit VREG and supplied with the internal power supply voltage VDD.
- Each circuit in the CRBK is appropriately connected to the MLVDS, and VDD is supplied from the VREG via the MLVDM and MLVDS.
- the MLVDM is connected to the pad PDvcl for the internal power supply voltage VDD.
- PDvcl is a pad for stabilizing VDD, and an external capacitor CE provided outside the semiconductor chip CHP1 is connected between PDvcl and the pad PDvss for the reference power supply voltage VSS.
- CE is, for example, a multilayer ceramic capacitor having a capacitance value of 0.1 ⁇ F to 1 ⁇ F.
- the CHP 1 is actually a reference power supply voltage line for VSS including a main reference power supply voltage line and a sub-reference power supply voltage line, similarly to the power supply voltage lines for VDD (MLVDM, MLVDS). Also equipped.
- the main reference power supply voltage wiring is connected to PDvss.
- FIG. 2 is a plan view showing a schematic configuration example different from FIG.
- the semiconductor chip CHP2 shown in FIG. 2 is different from the semiconductor chip CHP1 shown in FIG. 1 in that the power supply regulator circuit VREG is not provided. Therefore, in CHP2 of FIG. 2, the pad PDvcl for stabilizing the internal power supply voltage VDD in FIG. 1 is changed to a pad PDvdd for supplying VDD. The VDD generated outside the CHP 2 is supplied to the PDvdd.
- FIG. 3A is a plan view showing a schematic configuration example of the wiring board on which the semiconductor device of FIG. 1 is mounted
- FIG. 3B is a schematic configuration example of the wiring board on which the semiconductor device of FIG. 2 is mounted.
- FIG. On the wiring board BD1 shown in FIG. 3A a semiconductor package IC1 as an example of a semiconductor device is mounted.
- IC1 is obtained by packaging the semiconductor chip CHP1 of FIG.
- IC1 includes external terminals PNvcc, PNvss, and PNvcl connected to pads PDvcc, PDvss, and PDvcl of CHP1, respectively.
- the BD 1 includes an external capacitor CE mounted between the PNvcl wiring pattern and the PNvss wiring pattern in addition to the wiring patterns connected to the PNvcc, PNvss, and PNvcl.
- a semiconductor package IC2 as an example of a semiconductor device is mounted on the wiring board BD2 shown in FIG. IC2 is obtained by packaging the semiconductor chip CHP2 of FIG.
- the IC 2 includes external terminals PNvcc, PNvss, and PNvdd connected to the pads PDvcc, PDvss, and PDvdd of the CHP 2 respectively.
- the BD 2 includes wiring patterns connected to PNvcc, PNvss, and PNvdd.
- the internal power supply voltage VDD is being lowered, so that the semiconductor chip CHP1 (semiconductor package IC1) is included in the semiconductor chip CHP1 as shown in FIGS.
- a power supply regulator circuit VREG is provided.
- a semiconductor package provided with VREG may increase the amount of self-heating due to the thermal resistance of the package, which may cause a problem.
- a method of directly supplying VDD from the outside as shown in FIGS. 2 and 3B is used.
- FIG. 4 is a circuit diagram showing an example of an equivalent circuit including the power regulator circuit and its periphery in the semiconductor device of FIG.
- the power supply regulator circuit VREG shown in FIG. 4 is a linear regulator and includes an amplifier circuit AMPv and a PMOS transistor MPv.
- MPv the source voltage VCC is supplied to the source, and the internal voltage voltage VDD is output from the drain.
- AMPv a reference voltage Vref is applied to one of the two inputs, VDD (MPv drain) is fed back to the other of the two inputs, and the gate voltage of the MPv is controlled so that VDD matches Vref.
- the reference voltage Vref is generated by the reference voltage generation circuit VREFG.
- VREFG includes a band gap reference circuit BGR, an amplifier circuit AMPr, a PMOS transistor MPr, and a variable resistor RV.
- MPr the power supply voltage VCC is supplied to the source, and Vref is output from the drain.
- RV functions as a so-called trimming resistor that divides a resistance between a voltage (Vref) of the drain of MPr and a reference power supply voltage VSS (ground power supply voltage GND) at a predetermined ratio and corrects manufacturing variations in the process.
- the resistance voltage division ratio is stored in advance in, for example, the nonvolatile memory ROM of FIG.
- the output voltage of the BGR is applied to one of the two inputs, the voltage of the resistance voltage dividing node in the RV is fed back to the other of the two inputs, and the voltage of the resistance voltage dividing node matches the output voltage of the BGR.
- the gate voltage of MPr is controlled.
- FIG. 5 is a circuit block diagram showing an actual configuration example around the power regulator circuit in the semiconductor device of FIG.
- a plurality of power supply regulator circuits VREG as shown in FIG. 4 are actually arranged in a distributed manner in the semiconductor chip CHP1. That is, the plurality of VREGs receive the power supply voltage VCC and the reference voltage Vref from one reference voltage generation circuit VREFG, respectively generate the internal power supply VDD, and output the VDD to the common power supply voltage wiring LNVD.
- the number of VREGs is determined according to the current supply capability of each VREG and the current consumption of the core circuit unit CRBK. Moreover, each VREG is arrange
- the internal power supply voltage VDD generated by the power supply regulator circuit VREG is supplied to the core circuit unit CRBK and also output to the pad PDvcl.
- CRBK can be equivalently expressed as a current source CS connected between a power supply voltage line LNVD to which VDD is supplied and a reference power supply voltage line LNVS to which a reference power supply voltage VSS is supplied.
- the current value of CS frequently changes according to the processing content of CRBK.
- LVvdd and LNVS actually have a parasitic resistance component. For this reason, in VDD and VSS, power supply noise is generated according to the fluctuation of the current value of CS.
- EMI noise emission noise
- Such noise can be reduced to some extent by the parasitic capacitance CP existing between the power supply voltage wiring LNVD and the reference power supply voltage wiring LNVS and the external capacitor CE.
- CP mainly corresponds to the wiring capacitance between the mesh-like sub power supply voltage wiring MLVDS shown in FIG. 1 and a sub reference power supply voltage wiring (not shown), the capacitance of the diffusion layer of each transistor constituting the CRBK, and the like.
- CE is connected to the CRBK via a wiring having a certain distance, the parasitic resistance component of the wiring may not function effectively as a CRBK bypass capacitor.
- FIG. 6 is a schematic diagram showing a schematic configuration example of the main part of the semiconductor device of FIG.
- the semiconductor chip CHP1 shown in FIG. 6 includes an on-chip capacitor CC in addition to the power supply regulator circuit VREG and the core circuit unit CRBK.
- the CRBK includes a power supply voltage wiring (first power supply voltage wiring) LNVD1 that is arranged in the CRBK and supplies an internal voltage VDD to each circuit in the CRBK.
- the power supply voltage wiring (first power supply voltage wiring) LNVD1 corresponds to the main power supply voltage wiring MLVDM and the sub power supply voltage wiring MLVDS in FIG.
- the output node of the power regulator circuit VREG becomes the power supply source node Nvdd.
- Nvdd and the power supply voltage wiring (first power supply voltage wiring) LNVD1 are connected via a power supply voltage wiring (second power supply voltage wiring) LNVD2 arranged outside the core circuit unit CRBK.
- the on-chip capacitor CC has a lower electrode (second electrode) LWN to which a reference power supply voltage VSS (ground power supply voltage GND) is supplied and an upper electrode (first electrode) UPN.
- An insulating film IS is provided between LWN and UPN.
- CC sets UPN as a part of LNVD2.
- FIG. 7 is a schematic diagram showing a schematic configuration example of the main part of the semiconductor device of FIG.
- the semiconductor chip CHP2 shown in FIG. 7 has a configuration in which the power supply regulator circuit VREG is deleted compared to the semiconductor chip CHP1 shown in FIG. Therefore, the pad PDvdd becomes a power supply source node.
- Other configurations are the same as those in FIG. That is, in the CHP2 of FIG. 7, as in the case of the CHP1 of FIG. 6, the on-chip capacitor CC uses a part of the power supply voltage wiring (second power supply voltage wiring) LNVD2 as the upper electrode (first electrode) UPN. Yes.
- FIG. 8A is a circuit symbol that schematically represents the on-chip capacitor in FIGS. 6 and 7, and FIG. 8B is a circuit symbol that is a comparative example of FIG. 8A.
- the on-chip capacitor CC having the structure of FIGS. 6 and 7, the internal power supply voltage VDD from the power supply source node Nvdd is always supplied to the core circuit unit CRBK through the upper electrode (first electrode) UPN. Will be.
- This can be represented by a circuit symbol as shown in FIG.
- the CC shown in FIG. 8A has three nodes N1 to N3.
- N3 as a reference power supply voltage VSS (ground power supply voltage GND)
- VDD input from N1 is output from N2.
- UPN is a power supply voltage wiring of VDD from N1 to N2, and is also an electrode of a capacitor.
- the on-chip capacitor CC ′ which is a comparative example shown in FIG. 8B, has two nodes N3 and N4, N3 is a reference power supply voltage VSS (ground power supply voltage GND), and N4 is an internal circuit.
- the power supply voltage VDD is connected in parallel to the power supply voltage wiring.
- a resistance component exists at N4.
- the capacitance value that effectively functions as a bypass capacitor may be part of the capacitance value of CC ′.
- it is necessary to increase the capacitance value of CC ′ (for example, to increase the circuit area of CC ′).
- the on-chip capacitor CC of FIG. 8A when the on-chip capacitor CC of FIG. 8A is used, the internal power supply voltage VDD necessarily passes through the upper electrode (first electrode) UPN, so that the CC effectively functions as a bypass capacitor. To do.
- the capacitance value of the CC is equivalent to the effective capacitance value that functions as a bypass capacitor.
- the same effect as the on-chip capacitor CC ′ can be obtained with a capacitance value smaller than the capacitance value of CC ′.
- the on-chip capacitor CC shown in FIGS. 6 and 7 functions as a bypass capacitor.
- the bypass capacitor bypasses power supply noise having a predetermined frequency component generated in the internal power supply voltage VDD to the reference power supply voltage VSS side by using the impedance characteristic (1 / (frequency ⁇ capacitance value)) of the capacitor. With a function to reduce power supply noise.
- FIG. 9 is a plan view showing a schematic arrangement example of the on-chip capacitors in the semiconductor device of FIGS. 6 and 7.
- FIG. 9 the formation region (first region) of the core circuit part CRBK is arranged in the semiconductor chip CHP.
- a main power supply voltage wiring MLVDM is arranged along the outer periphery of the first region (CRBK).
- the MLVDM has a ring shape and is arranged so as to surround the CRBK.
- the sub power supply voltage wiring MLVDS branched from the MLVDM and arranged in a mesh pattern is arranged.
- a plurality of on-chip capacitors CC are arranged along the MLVDM.
- a plurality of on-chip capacitors CC are arranged so as to surround the CRBK.
- Each CC is composed of a unit cell, for example.
- a source power supply voltage wiring MLVDP connected to a power supply source node (not shown) (that is, the node Nvdd in FIG. 6 or the pad PDvdd in FIG. 7) is disposed outside the region surrounded by the main power supply voltage wiring MLVDM.
- the MLVDP has a ring shape surrounding the MLVDM, and is arranged so as to extend alongside the MLVDM.
- the plurality of on-chip capacitors CC are arranged in a region between the MLVDP and the MLVDM. In each CC, one end of the upper electrode (first electrode) UPN (node N1 in FIG. 8A) is connected to the MLVDP, and the other end of the UPN (node N2 in FIG. 8A) is connected to the MLVDM. .
- the supply of the internal power supply voltage VDD from the power supply source node to the core circuit unit CRBK is all performed via the upper electrode (first electrode) UPN of the on-chip capacitor CC.
- the upper electrode (first electrode) UPN of the on-chip capacitor CC Become. That is, it is possible to eliminate a power supply path through which the internal power supply voltage VDD passes as shown in FIG.
- the plurality of CCs are arranged so as to surround the CRBK along the main power supply voltage wiring MLVDM, it is possible to further enhance the effect of the CC as a bypass capacitor for the CRBK.
- an on-chip capacitor CC is formed using unit cells, instead of using a normal power supply voltage wiring as it is to form a capacitor. For this reason, it is possible to secure a sufficient capacitance value without unnecessarily lengthening the power supply voltage wiring (for example, LNVD2 in FIG. 6). That is, if the power supply voltage wiring is lengthened, the power supply noise may increase due to the IR drop, but such a situation can be prevented by using the unit cell. Furthermore, by using unit cells, layout design can be automatically performed, and the design can be facilitated.
- FIG. 10 is a schematic diagram showing various structural examples of the on-chip capacitor in the semiconductor device of FIGS.
- MOM type As the on-chip capacitor CC using the capacitance between the metal wirings, there are MOM type and MIM type.
- MOM type by disposing the metal wiring ML close to each other in the same metal wiring layer, the inter-metal wiring insulating film ISLm is used as a capacitor, and MLs are stacked in different metal wiring layers.
- the interlayer insulating film ISLy between them is used as a capacitor.
- the MIM type has a structure in which metal wiring ML is stacked via a thin insulating film ISL.
- the electrode is a part of the power supply voltage wiring, so that the IR drop of the power supply voltage wiring is reduced, or the current supply capability toward the core circuit unit CRBK. In order to ensure sufficient resistance, it is desirable that the electrode has as low resistance as possible. From this point, the MOM type and the MIM type have advantages. However, the MIM type can increase the capacitance value per unit area as compared with the MOM type, but cannot be realized by a normal CMOS process and requires a special process. It is preferable to use the MOM type.
- the PIP type has a structure in which an insulating film ISL is mounted on a lower polysilicon layer PSLl and an upper polysilicon layer PSLu is further mounted thereon. A silicide layer SC is formed on PSLu.
- the process structure is complicated, and the parasitic resistance of polysilicon (particularly the lower layer side) serving as an electrode increases. For this reason, the above-mentioned MOM type is preferable.
- an on-chip capacitor CC using a MOS capacitor there are a PMOS type and an NMOS type.
- a p-type diffusion layer DF (p +) serving as a source and a drain is formed in an n-type well WEL (n ⁇ ), and further a gate is formed on the WEL (n ⁇ ) via a gate insulating film GOX.
- the wiring GL is mounted.
- an n-type diffusion layer DF (n +) serving as a source and a drain is formed in a p-type well WEL (p ⁇ ), and further a gate is formed on the WEL (p ⁇ ) via a gate insulating film GOX.
- the wiring GL is mounted.
- GL is formed of, for example, polysilicon, and a silicide layer SC is formed on the GL.
- the PMOS type and NMOS type can increase the capacitance value per unit area, but have the disadvantage that the parasitic resistance of the electrode is large. That is, since one of the electrodes is the gate wiring GL (that is, polysilicon), the parasitic resistance increases, but the parasitic resistance can be lowered to some extent by the silicide layer SC. However, since the other electrode serves as a channel portion in the well WEL, it is not easy to reduce the parasitic resistance of the portion. For this reason, the above-mentioned MOM type is preferable.
- examples of the on-chip capacitor CC using the accumulation capacitance include a p-well type and an n-well type, and a type in which these are combined with a metal gate.
- a p-well type a p-type diffusion layer DF (p +) having a higher impurity concentration is formed in the p-type well WEL (p ⁇ ), and a gate insulating film GOX is further formed on the WEL (p ⁇ ).
- the gate wiring GL is mounted.
- an n-type diffusion layer DF (n +) having a higher impurity concentration is formed in the n-type well WEL (n ⁇ ), and a gate insulating film GOX is further formed on the WEL (n ⁇ ).
- the gate wiring GL is mounted.
- GL is formed of, for example, polysilicon, and a silicide layer SC is formed on the GL.
- the p-well type and the n-well type have a structure in which the polarity of the diffusion layer in the NMOS type and the PMOS type is changed. Such a structure is referred to as an accumulation capacity in this specification.
- the other one of the electrodes serves as the well WEL, so that the parasitic resistance is reduced by increasing the area of the WEL, for example. It becomes possible. Therefore, it is also beneficial to use the accumulation capacitance in addition to the MOM type described above as the on-chip capacitor CC.
- the accumulation capacitance as in the case of the PMOS type and NMOS type described above, there is some concern about the parasitic resistance in one of the electrodes (for example, the upper electrode UPN in FIG. 6). Therefore, it is more desirable to use a structure in which the gate wiring GL in the p well type and the n well type is replaced with the metal gate wiring MGL.
- the MGL is formed using a metal material such as titanium (Ti).
- noise power supply noise, EMI noise (emission noise)
- EMI noise emission noise
- FIG. 11A is a plan view showing a schematic arrangement example of on-chip capacitors in a semiconductor chip in the semiconductor device according to the second embodiment of the present invention, and FIG. It is a top view which shows the detailed layout structural example of the one part area
- FIG. 11A shows a schematic arrangement example of the on-chip capacitor CCa when the semiconductor chip CHP2 of FIG. 7 described above is used, for example.
- the formation region (first region) of the core circuit part CRBK is arranged.
- a main power supply voltage wiring MLVDM is arranged along the outer periphery of the first region (CRBK).
- the MLVDM has a ring shape and is arranged so as to surround the CRBK.
- the sub power supply voltage wiring MLVDS branched from the MLVDM and arranged in a mesh pattern is arranged inside the region surrounded by the MLVDM, as described in FIG. 1 and the like.
- the sub power supply voltage wiring MLVDS branched from the MLVDM and arranged in a mesh pattern is arranged.
- a plurality of on-chip capacitors CCa are arranged along the MLVDM.
- a plurality of on-chip capacitors CCa are arranged so as to surround the CRBK.
- Each CCa is composed of a unit cell, for example.
- the source power supply voltage wiring MLVDP is arranged outside the area surrounded by the main power supply voltage wiring MLVDM.
- the MLVDP is connected to a pad PDvdd serving as a power supply source node.
- the MLVDP has a ring shape surrounding the MLVDM, and is arranged so as to extend alongside the MLVDM.
- the PDvdd is disposed in the external input / output cell CL, and an ESD (Electro Static Static Discharge) protection element or the like is further formed in the CL.
- the plurality of on-chip capacitors CCa are arranged in a region between the MLVDP and the MLVDM.
- the well WEL region is formed so as to include the arrangement region of the on-chip capacitor CCa.
- the region of the well WEL is a river-like region.
- FIG. 11 (b) shows details of the area AR1 including the on-chip capacitor CCa in FIG. 11 (a).
- an n-type well WEL (n ⁇ ) that forms a river-like region by two sides extending side by side is arranged.
- two CCa are arranged at a predetermined interval along the extending direction of the region.
- Each CCa includes a rectangular gate wiring GL, two n-type diffusion layers (first semiconductor regions) DF1 (n +) having a higher impurity concentration than WEL (n ⁇ ), and WEL (n ⁇ ).
- GL includes a first side and a second side extending along two sides of the WEL (n ⁇ ) region, a third side extending along the direction intersecting the two sides of the WEL (n ⁇ ) region, and With 4th side.
- Two diffusion layers DF1 (n +) are formed in the well WEL (n ⁇ ) between the first and second sides of the gate wiring GL and the two sides of the WEL (n ⁇ ) region, respectively.
- the two diffusion layers DF2 (n +) are formed close to the third side and the fourth side in the GL, respectively.
- a plurality of contact layers CT are disposed on each of the two DF1 (n +) and the two DF2 (n +).
- a plurality of contact layers CT are disposed in the vicinity of the first side to the fourth side.
- FIG. 11B two reference power supply voltage wirings MLG, one source power supply voltage wiring MLVDP, and one main power supply voltage wiring MLVDM are arranged.
- Each of the two MLGs, MLVDP, and MLVDM extends in the same direction as the extension direction of the well WEL (n ⁇ ) region, and the two MLGs are arranged so as to sandwich the MLVDP and MLVDM.
- Each of the two MLGs is connected to a contact layer CT disposed in the two diffusion layers DF1 (n +).
- MLVDP and MLVDM are respectively connected to contact layers CT arranged in the vicinity of the first side and the second side in gate wiring GL.
- the reference power supply voltage wiring branched from MLG is connected to contact layer CT arrange
- FIG. 12A is a cross-sectional view showing a structural example between AA ′ in FIG. 11B, and FIG. 12B shows a structural example between BB ′ in FIG. 11B. It is sectional drawing shown.
- an n-type well WEL (n ⁇ ) is formed in the semiconductor substrate SUB.
- two n-type diffusion layers DF1 (n +) having an impurity concentration higher than that of WEL (n ⁇ ) are formed.
- two element isolation insulating films STI1 are disposed adjacent to each of the two DF1 (n +).
- a gate wiring GL is formed via a gate insulating film GOX above the region sandwiched between the two element isolation insulating films STI1.
- the GL is located in the gate layer GT and is formed, for example, with a stacked structure of a polysilicon layer and a silicide layer.
- GOX is made of, for example, silicon dioxide (SiO 2 ).
- the silicide layer is formed using, for example, tungsten (W), molybdenum (Mo), titanium (Ti), or the like.
- Both end portions of the gate wiring GL are respectively connected to two metal wirings in the first metal wiring layer M1 through the contact layer CTg, and the two metal wirings are respectively connected to the second metal wiring through the contact layer CT1. It is connected to two metal wirings in the two metal wiring layer M2.
- One of the two metal wirings in the M2 is a source power supply voltage wiring MLVDP, and the other is a main power supply voltage wiring MLVDM.
- the two diffusion layers DF1 (n +) are connected to the two metal wirings in M1 via the contact layer CTd, respectively. Both of the two metal wirings in M1 become the reference power supply voltage wiring MLG.
- the metal wiring is formed using, for example, copper (Cu).
- an n-type well WEL (n ⁇ ) is formed in the semiconductor substrate SUB.
- two n-type diffusion layers DF2 (n +) having an impurity concentration higher than that of WEL (n ⁇ ) are formed.
- two element isolation insulating films STI2 are arranged adjacent to the two DF2 (n +) so as to sandwich the two DF2 (n +).
- a gate wiring GL is formed above the region sandwiched between two DF2 (n +) in WEL (n ⁇ ) via a gate insulating film GOX.
- Two DF2 (n +) are respectively connected to two metal wirings in M1 through a contact layer CTd.
- the two metal wirings in M1 are omitted in FIG. 11B, but both serve as the reference power supply voltage wiring MLG.
- FIG. 13A is a diagram showing an example of a cross-sectional structure schematically representing FIG. 12A and an equivalent circuit thereof
- FIG. 13B is a cross-sectional structure serving as a comparative example of FIG. It is a figure which shows an example of the equivalent circuit.
- the well WEL (n ⁇ ) has a reference power supply voltage VSS via the reference power supply voltage wiring MLG and the diffusion layers DF1 (n +) and DF2 (n +). (Ground power supply voltage GND) is supplied. Therefore, in the on-chip capacitor CCa of FIG. 13A, the well WEL is connected to VSS.
- WEL in FIG. 13A becomes the lower electrode (second electrode) LWN of CCa, and the gate wiring GL in FIG. 1 electrode) UPN.
- the internal power supply voltage VDD supplied from the source power supply voltage wiring MLVDP reaches one end of the gate wiring GL via the contact layers CT1 and CTg, passes through the GL, and then passes through the GL.
- the other end reaches the main power supply voltage wiring MLVDM via CTg and CT1.
- CTg and CT1 have a certain amount of parasitic resistance component and parasitic inductor component, they are represented by a series circuit of an inductor and a resistor in the equivalent circuit.
- GL has a certain amount of parasitic resistance component, and is represented by a resistance in an equivalent circuit.
- the on-chip capacitor CCa ′ of FIG. 13B which is a comparative example, has two metal wirings in the first metal wiring layer M1 in FIG. 13A in common via the metal wiring ML1 in M1. It has a connected structure.
- Such a structure corresponds to a circuit symbol as shown in FIG. In this case, most of the internal power supply voltage VDD supplied from the source power supply voltage wiring MLVDP reaches the main power supply voltage wiring MLVDM through the supply path via the ML1. For this reason, CCa 'is less effective as a bypass capacitor than CCa.
- FIG. 14 is a cross-sectional view showing a structural example of a metal gate used as the gate wiring in the on-chip capacitors of FIGS. 12 (a) and 12 (b).
- the gate wiring GL is a capacitor electrode and also a power supply voltage wiring of the internal power supply voltage VDD. Therefore, for example, the gate wiring GL is more preferably formed with a metal gate structure as shown in FIG. 14 than a stacked structure of a polysilicon layer and a silicide layer.
- the gate wiring GL (metal gate wiring MGL) shown in FIG. 14 has a structure in which three layers (G1, G2, SC) are stacked in order from the gate insulating film GOX side.
- the layer G1 is formed of titanium nitride (TiN)
- the layer G2 is formed of polysilicon
- the silicide layer SC is formed using nickel platinum.
- the SC may be formed using any one of nickel (Ni), titanium (Ti), cobalt (Co), and platinum (Pt).
- GOX is formed of a high dielectric constant gate insulating film (so-called High-k). Specific examples include hafnium oxide (HfO 2 ) into which lanthanum oxide (La 2 O 3 ) is introduced, hafnium oxide silicate, hafnium oxynitride silicate, and the like.
- the semiconductor device of the second embodiment in addition to the effects described in the first embodiment, it is possible to realize an on-chip capacitor that efficiently operates as a bypass capacitor.
- the capacitance value of the insulating film is large in addition to the small parasitic resistance value of the electrode, the function as a bypass capacitor can be further enhanced.
- the on-chip capacitor is composed of unit cells, it is possible to efficiently arrange the on-chip capacitor around the core circuit portion CRBK by so-called automatic placement and wiring.
- FIG. 11B it is preferable to use a vertically long shape rather than a square shape, for example, from the viewpoint of reducing the parasitic resistance component of GL. That is, the distance through which the internal power supply voltage VDD flows in the GL (horizontal direction in the example of FIG. 11B) is shortened, and the width of flowing VDD (vertical direction in the example of FIG. 11B) is widened. Further, for example, in the example of FIG. 11B, an n-type well is used as a well, but a p-type well may be used in some cases. That is, the p-well structure shown in FIG. 10 can be used.
- the n-type well has a smaller parasitic resistance value than the p-type well, it is preferable to use the n-type well from the viewpoint of reducing the resistance of the electrode. From the viewpoint of reducing the resistance of the well, for example, in FIG. 11A, it is beneficial to widen the river width of the river-like region constituting the well WEL. That is, the outer peripheral side of the semiconductor chip CHP2 in the WEL is brought closer to the outer peripheral side of the CHP2.
- FIG. 15A is a plan view showing a schematic arrangement example of an on-chip capacitor and a power supply regulator circuit in a semiconductor chip in the semiconductor device according to the third embodiment of the present invention
- FIG. FIG. 16 is a plan view showing a detailed layout configuration example of a partial region in FIG.
- FIG. 15A shows a schematic arrangement example of the on-chip capacitor CCa and the power supply regulator circuit VREG when the semiconductor chip CHP1 of FIG. 6 described above is used, for example.
- the semiconductor chip CHP1 shown in FIG. 15 (a) has substantially the same arrangement configuration as the semiconductor chip CHP2 shown in FIG. 11 (a).
- the difference between CHP1 in FIG. 15A and CHP2 in FIG. 11A is that in FIG. 15A, the power supply path from the pad PDvdd in FIG. 11A to the source power supply voltage wiring MLVDP is deleted.
- a power regulator circuit VREG instead. This VREG is appropriately disposed between a plurality of on-chip capacitors CCa disposed along the extending direction of the well WEL region.
- FIG. 15 (b) shows details of the area AR2 including the on-chip capacitor CCa and the power supply regulator circuit VREG in FIG. 15 (a).
- the layout configuration of CCa is the same as in FIG. 11B.
- VREG is arranged between adjacent CCa, and the source power supply voltage wiring MLVDP extends from this VREG as a starting point.
- the contact layer CTvcc to which the power supply voltage VCC is supplied, the contact layer CTvdd1 for supplying the internal power supply voltage VDD toward one adjacent CCa, and the other adjacent And contact layer CTvdd2 for supplying VDD toward CCa.
- CTvcc is supplied with VCC via an external power supply voltage wiring MLVC extending in a direction crossing the extending direction of the well WEL region.
- VDD output from CTvdd1 and CTvdd2 is supplied to CCa via the source power supply voltage wiring MLVDP extending in the same direction as the extending direction of the WEL region.
- the source power supply voltage wiring MLVDP is divided at the position of the power supply regulator circuit VREG, but is connected inside the VREG via the contact layers CTvdd1 and CTvdd2.
- the layout configuration example is not limited to this, and a layout in which the MLVDP is not divided can be obtained by appropriately adjusting the metal wiring layer of the external power supply voltage wiring MLVC.
- the number of VREGs to be installed is set as appropriate. Therefore, the number of CCa sandwiched between the VREGs is determined so that the VREGs are arranged almost evenly around the core circuit unit CRBK according to the number.
- an efficient layout can be realized. More specifically, for example, when the power supply regulator circuit VREG is arranged at a location different from the arrangement area of the on-chip capacitor CCa, the distance from the VREG to the source power supply voltage wiring MLVDP may increase, or the area of the semiconductor chip increases. There is a fear. When the layouts as shown in FIGS. 15A and 15B are used, such a problem does not occur.
- the power regulator circuit VREG is arranged at a ratio of one to a plurality of on-chip capacitors CCa.
- One VREG usually has a sufficiently smaller circuit area than one CCa. Then, when the VREG is arranged at a location different from the CCa arrangement area, there is a possibility that a large step is further generated in the VREG arrangement area.
- a VREG is arranged between a plurality of CCa, since the circuit area of the VREG is sufficiently small compared to the CCa, two CCa adjacent to the VREG are arranged at a short distance. The level difference generated in the arrangement area is reduced.
- the PMOS transistor MPv shown in FIG. 4 is formed in the arrangement region of the power supply regulator circuit VREG shown in FIG. MPv occupies almost all the area in VREG.
- the amplifier circuit AMPv in FIG. 6 normally requires a p-type well in addition to an n-type well, and may be formed separately, for example, in a location close to the VREG arrangement region in FIG. . Since the area of AMPv is negligibly small compared with MPv, it is not particularly related to layout efficiency.
- FIG. 16A is a plan view showing a schematic arrangement example of on-chip capacitors in a semiconductor chip in the semiconductor device according to the third embodiment of the present invention, and FIG. It is a top view which shows the detailed layout structural example of the one part area
- the semiconductor chip CHP3 shown in FIG. 16A has the same arrangement configuration as the semiconductor chip CHP shown in FIG. 9 of the first embodiment. That is, a plurality of on-chip capacitors CCb are arranged in the region between the source power supply voltage wiring MLVDP and the main power supply voltage wiring MLVDM along the extending direction of MLVDP and MLVDM.
- FIG. 16 (b) shows details of the area AR3 including the on-chip capacitor CCb in FIG. 16 (a).
- CCb is arranged with a predetermined region SP in between along the extending direction of MLVDP and MLVDM.
- region SP for example, various signal wirings from the core circuit unit CRBK to the pads (not shown) of the semiconductor chip CHP3 are formed.
- CCb is formed by using most of the metal wiring layers, and therefore, in this example, a passing region for various signal wirings is secured by SP.
- each of the source power supply voltage wiring MLVDP and the main power supply voltage wiring MLVDM is divided between the on-chip capacitors CCb. In practice, however, they are connected using metal wiring layers as appropriate.
- FIG. 16A description regarding the power supply source node is omitted.
- the power supply source node is a pad
- the MLVDP is connected to the pad PDvdd as shown in FIG. 11A.
- the power supply regulator circuit VREG is appropriately arranged, and the output thereof is connected to the MLVDP.
- the VREG arrangement region may be the region SP in FIG. 16B, or may be a region near CCb other than SP.
- the on-chip capacitor CCb includes a source power supply voltage wiring MLVDP, a main power supply voltage wiring MLVDM, a reference power supply voltage wiring MLG, a plurality of branch power supply voltage wirings MLVB, and a plurality of branches.
- a reference power supply voltage wiring MLGB is provided.
- MLVDP, MLVDM, and MLG extend side by side in the same direction.
- the plurality of MLVBs and MLGBs extend side by side in a direction (first direction) intersecting with the extending direction of MLVDP, MLVDM, and MLG.
- One end of the plurality of branch power supply voltage lines (first metal lines) MLVB is commonly connected to the source power supply voltage line (first node) MLVDP, and the other end is commonly connected to the main power supply voltage line (second node) MLVDM. Connected.
- One end of each of the plurality of branch reference power supply voltage wirings (second metal wiring) MLGB is connected in common to the reference power supply voltage wiring MLG, and a plurality of MLVBs are sandwiched by an insulating film (not shown) at a predetermined interval. Be placed.
- MLG is arrange
- Each of the plurality of MLVBs and MLGBs is formed by, for example, a wiring thinner than MLVDP, MLVDM, and MLG.
- the on-chip capacitor CCb in FIG. 17A includes a plurality of metal wiring layers on a semiconductor substrate (not shown), and between each metal wiring in the same metal wiring layer. Are formed by using an inter-metal wiring insulating film that separates layers and an interlayer insulating film that separates different metal wiring layers.
- the same layout rule that is, the same rule for the minimum wiring width and the minimum pitch between wirings
- the CCb is formed using the M1 to M5, the inter-metal wiring insulating film ISLm, and the interlayer insulating film ISLy.
- Wiring) MLGB is alternately arranged with the inter-metal wiring insulating film ISLm interposed therebetween.
- each MLVB and each MLGB are alternately arranged with the interlayer insulating film ISLy interposed therebetween.
- the plurality of MLVBs constitute an upper electrode (first electrode) UPN
- the plurality of MLGBs constitute a lower electrode (second electrode) LWN.
- MLVB and MLGB are formed in the same metal wiring layer at the minimum wiring pitch on the layout rule.
- FIG. 18 is a three-dimensional view schematically showing an example of a part of the structure of the on-chip capacitor shown in FIGS. 17 (a) and 17 (b).
- the power supply voltage wiring in the first metal wiring layer M1, the main power supply voltage wiring MLVDM on the core circuit side is combed, and a plurality of branch power supply voltage wirings MLVBm1 are teeth. Comb-like power supply voltage wiring is arranged so that the teeth of the two branches.
- the second metal wiring layer M2 comb-like power supply voltage wirings having a source power supply voltage wiring MLVDP as a comb and a plurality of branch power supply voltage wirings MLVBm2 as teeth are arranged.
- power supply voltage wiring for interlayer connection having the same XY coordinates as MLVDM in M1 is arranged in M2.
- the comb-like power supply voltage wiring in the second metal wiring layer M2 is folded back symmetrically with respect to the Y axis in the comb-like power supply voltage wiring in the first metal wiring layer M1, and the XY coordinates of the teeth are further changed in the Y-axis direction. Is shifted by a predetermined pitch, and in addition, the length of the tooth in the X-axis direction is shorter than that of the tooth in M1.
- the predetermined pitch is defined as an interval between the branch power supply voltage wiring MLVB and the branch reference power supply voltage wiring MLGB which are adjacent to each other in the same metal wiring layer.
- one end of the contact layer CTvd2 is connected to the tip portions of a plurality of teeth branched from the comb, and the comb-shaped power supply in the second metal wiring layer M2 In the voltage wiring, the other end of CTvd2 is connected to an intermediate position between the branch point from the tooth comb and the branch point from the tooth adjacent to the tooth comb. Further, in the comb-like power supply voltage wiring in M1, one end of the contact layer CTvd1 is connected to a predetermined position on the comb (here, a plurality of tooth branch points), and in M2, the power supply voltage for interlayer connection The other end of CTvd1 is connected to the wiring.
- comb-like power supply voltage wirings having the same XY coordinates as the comb-like power supply voltage wirings in the first metal wiring layer M1 are arranged in the odd-numbered metal wiring layers.
- the even-numbered metal wiring layer includes a comb-shaped power supply voltage wiring and an inter-layer connection power supply having the same XY coordinates as the comb-shaped power supply voltage wiring and the interlayer connection power supply voltage wiring in the second metal wiring layer M2. Voltage wiring is arranged.
- These power supply voltage wirings are appropriately connected by CTvd1 and CTvd2 having the same XY coordinates as the contact layers CTvd1 and CTvd2 described above.
- the above-described comb-shaped power supply voltage wiring in the odd-numbered metal wiring layer is folded back symmetrically with respect to the Y-axis, and the XY coordinates of the teeth are A comb-like reference power supply voltage wiring having XY coordinates shifted by a predetermined pitch in the direction is arranged.
- the comb-like reference power supply voltage wiring includes the reference power supply voltage wiring MLG corresponding to the main power supply voltage wiring MLVDM and the source power supply voltage wiring MLVDP, and the branch reference power supply voltage wiring MLGB corresponding to the branch power supply voltage wiring MLVB. Consists of.
- the above-described power supply voltage wirings for the interdigitated and interlayer connections in the even-numbered metal wiring layer are folded back symmetrically with respect to the Y axis, and the XY coordinates of the teeth are set in the Y axis direction.
- Comb-like and XY reference power supply voltage wirings having XY coordinates shifted by a predetermined pitch are arranged.
- Each of these reference power supply voltage wirings is appropriately connected through contact layers CTvs1 and CTvs2 that are connected at different locations between even and odd metal wiring layers in the same manner as in the case of the contact layers CTvd1 and CTvd2.
- an on-chip capacitor CCb as shown in FIGS. 17A and 17B can be realized.
- the electrode of the on-chip capacitor can be formed with a metal wiring having a low resistance, and is somewhat large by using an inter-metal wiring insulating film ISLm in the same metal wiring layer and an interlayer insulating film ISLy between different metal wiring layers. Capacitance values can be obtained. Furthermore, since the on-chip capacitor is composed of unit cells, it is possible to efficiently arrange the on-chip capacitor around the core circuit portion CRBK by so-called automatic placement and routing.
- FIG. 19A shows an example in which the on-chip capacitor CC described with reference to FIG. 6 and the like is applied to a control signal CTLIGG such as a reset signal.
- FIG. 19B is an example in which CC is applied to the input data signal Din and the clock signal CLK
- FIG. 19C is an example in which CC is applied to the output data signal Dout.
- d) is an example in which CC is applied to the analog input signal Ain.
- the on-chip capacitor CC is provided, for example, in the vicinity of the pad PD of each signal, and in any case, bypasses a noise component having a frequency band sufficiently higher than the frequency band of each signal. Used for. As a result, for example, reduction of EMI noise (emission noise) generated in the PD, reduction of noise components included in a signal input from the PD, and the like can be realized.
- EMI noise emission noise
- the present invention made by the present inventor has been specifically described based on the embodiment.
- the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention.
- the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described.
- a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. .
- a microcomputer has been described as an example of a semiconductor device, but of course, the present invention is not limited to a microcomputer, and can be similarly applied to various semiconductor products that require countermeasures against noise.
- the on-chip capacitor CCa shown in FIG. 11B and the on-chip capacitor CCb shown in FIGS. 17A and 17B can be realized as discrete capacitor parts in some cases. is there.
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Abstract
Description
《半導体装置全体の概略構成》
図1は、本発明の実施の形態1による半導体装置において、その全体の概略構成例を示す平面図である。図1には、半導体装置の一例として、一つの半導体基板で構成される半導体チップCHP1が示される。CHP1は、例えば、マイクロコンピュータ等である。CHP1は、外周部に外部入出力領域(IO領域)IOBKを備え、その内部にコア回路部CRBKと、アナログ回路部ANGBKと、電源レギュレータ回路VREGと、クロック生成回路部CKBKを備える。IOBKには、複数のパッドPDが配置される。PDの中には、電源電圧VCC用のパッドPDvcc、基準電源電圧VSS(接地電源電圧GND)用のパッドPDvss、内部電源電圧VDD用のパッドPDvclが含まれる。
図4は、図1の半導体装置において、その電源レギュレータ回路およびその周辺を含めた等価回路の一例を示す回路図である。図4に示す電源レギュレータ回路VREGは、リニアレギュレータであり、アンプ回路AMPvとPMOSトランジスタMPvを備えている。MPvは、ソースに電源電圧VCCが供給され、ドレインから内部電圧電圧VDDを出力する。AMPvは、2入力の一方に参照電圧Vrefが印加され、2入力の他方にVDD(MPvのドレイン)が帰還され、VDDがVrefに一致するようにMPvのゲート電圧を制御する。
図6は、図1の半導体装置において、その主要部の概略構成例を示す模式図である。図6に示す半導体チップCHP1は、電源レギュレータ回路VREGとコア回路部CRBKに加えてオンチップコンデンサCCを備える。CRBKは、CRBK内に配置され、CRBK内の各回路に内部電圧VDDを供給するための電源電圧配線(第1電源電圧配線)LNVD1を備える。電源電圧配線(第1電源電圧配線)LNVD1は、図1におけるメイン電源電圧配線MLVDMおよびサブ電源電圧配線MLVDSに該当する。
図10は、図6および図7の半導体装置において、そのオンチップコンデンサの各種構造例を示す概略図である。図10において、まず、メタル配線間の容量を用いたオンチップコンデンサCCとして、MOM型とMIM型が挙げられる。MOM型は、同一メタル配線層内においてメタル配線MLを近接して配置することで、そのメタル配線間絶縁膜ISLmを容量として利用し、更に、異なるメタル配線層においてMLを重ねて配置することで、その間の層間絶縁膜ISLyを容量として利用する構造となる。MIM型は、メタル配線MLを薄い絶縁膜ISLを介して重ねる構造となる。
本実施の形態2では、実施の形態1で述べたオンチップコンデンサCCとしてアキミュレーション容量を用い、また、外部から内部電源電圧VDDが供給される場合を例として、その詳細について説明する。
図11(a)は、本発明の実施の形態2による半導体装置において、半導体チップ内でのオンチップコンデンサの概略的な配置例を示す平面図であり、図11(b)は、図11(a)における一部の領域の詳細なレイアウト構成例を示す平面図である。図11(a)には、例えば、前述した図7の半導体チップCHP2を用いた場合での、オンチップコンデンサCCaの概略的な配置例が示されている。
図13(a)は、図12(a)を簡略的に表す断面構造およびその等価回路の一例を示す図であり、図13(b)は、図13(a)の比較例となる断面構造およびその等価回路の一例を示す図である。図12(a)および図12(b)に示したように、ウエルWEL(n-)には、基準電源電圧配線MLGおよび拡散層DF1(n+),DF2(n+)を介して基準電源電圧VSS(接地電源電圧GND)が供給される。そこで、図13(a)のオンチップコンデンサCCaでは、ウエルWELをVSSに接続している。例えば、図8(a)を参照して、図13(a)におけるWELは、CCaの下部電極(第2電極)LWNとなり、図13(a)におけるゲート配線GLは、CCaの上部電極(第1電極)UPNとなる。
図14は、図12(a)および図12(b)のオンチップコンデンサにおいて、そのゲート配線として用いられるメタルゲートの構造例を示す断面図である。図13(a)等で述べたように、ゲート配線GLは、コンデンサの電極であると共に、内部電源電圧VDDの電源電圧配線でもあるため、寄生抵抗成分がより小さい方が望ましい。そこで、ゲート配線GLは、例えば、ポリシリコン層とシリサイド層の積層構造よりも、図14に示すようなメタルゲートの構造で形成される方がより望ましい。
本実施の形態3では、実施の形態1で述べたオンチップコンデンサCCとしてアキミュレーション容量を用い、また、内部の電源レギュレータ回路VREGで内部電源電圧VDDを生成する場合を例として、その詳細について説明する。以下では、実施の形態2との相違点となるVREGに着目した説明を行うが、実施の形態2で述べたオンチップコンデンサに関する説明は、本実施の形態3にも当てはまる。
図15(a)は、本発明の実施の形態3による半導体装置において、半導体チップ内でのオンチップコンデンサおよび電源レギュレータ回路の概略的な配置例を示す平面図であり、図15(b)は、図15(a)における一部の領域の詳細なレイアウト構成例を示す平面図である。図15(a)には、例えば、前述した図6の半導体チップCHP1を用いた場合での、オンチップコンデンサCCaおよび電源レギュレータ回路VREGの概略的な配置例が示されている。
本実施の形態4では、実施の形態1で述べたオンチップコンデンサCCとしてMOM型のメタル間容量を用いる場合を例として、その詳細について説明する。
図16(a)は、本発明の実施の形態3による半導体装置において、半導体チップ内でのオンチップコンデンサの概略的な配置例を示す平面図であり、図16(b)は、図16(a)における一部の領域の詳細なレイアウト構成例を示す平面図である。図16(a)に示す半導体チップCHP3は、実施の形態1の図9に示した半導体チップCHPと同様の配置構成を備えている。すなわち、ソース電源電圧配線MLVDPとメイン電源電圧配線MLVDMの間の領域に、MLVDP,MLVDMの延伸方向に沿って複数のオンチップコンデンサCCbが配置される。
本実施の形態5では、これまでに述べたオンチップコンデンサCCを電源電圧および基準電源電圧以外の箇所に適用する例について説明する。図19(a)~図19(d)は、本発明の実施の形態5による半導体装置において、その主要部のそれぞれ異なる構成例を示す概略図である。図19(a)は、前述した図6等で述べたオンチップコンデンサCCを、リセット信号等の制御信号CTLSIGに適用した例である。同様に、図19(b)は、CCを入力データ信号Dinやクロック信号CLKに適用した例であり、図19(c)は、CCを出力データ信号Doutに適用した例であり、図19(d)は、CCをアナログ入力信号Ainに適用した例である。
ANGBK アナログ回路部
Ain アナログ入力信号
BD 配線基板
BGR バンドギャップリファレンス回路
CC,CC’ オンチップコンデンサ
CE 外付けコンデンサ
CHP 半導体チップ
CKBK クロック生成回路部
CL セル
CLK クロック信号
CP 寄生容量
CPU プロセッサ回路
CRBK コア回路部
CS 電流源
CT コンタクト層
CTLSIG 制御信号
DF 拡散層
Din 入力データ信号
Dout 出力データ信号
G 層
GL ゲート配線
GOX ゲート絶縁膜
GT ゲート層
IC 半導体パッケージ
IOBK 外部入出力領域(IO領域)
IS 絶縁膜
ISL 絶縁膜
LNVD 電源電圧配線
LNVS 基準電源電圧配線
LWN 下部電極
M メタル配線層
MGL メタルゲート配線
ML メタル配線
MLG 基準電源電圧配線
MLGB 分岐用基準電源電圧配線
MLVC 外部電源電圧配線
MLVB 分岐用電源電圧配線
MLVDM メイン電源電圧配線
MLVDP ソース電源電圧配線
MLVDS サブ電源電圧配線
MP PMOSトランジスタ
N ノード
Nvdd 電源供給元ノード
PD パッド
PERI 各種周辺回路
PN 外部端子
PSL ポリシリコン層
RAM 揮発性メモリ
ROM 不揮発性メモリ
RV 可変抵抗
SC シリサイド層
SP 領域
STI 素子分離用絶縁膜
UPN 上部電極
VCC 電源電圧
VDD 内部電源電圧
VREFG 参照電圧生成回路
VREG 電源レギュレータ回路
VSS 基準電源電圧
Vref 参照電圧
WEL ウエル
Claims (20)
- 一つの半導体基板で構成される半導体装置であって、
所定の処理を実行するコア回路部を形成するための第1領域と、
前記第1領域内に配置され、前記コア回路部に電源電圧を供給するための第1電源電圧配線と、
前記第1領域外に配置され、前記電源電圧の供給元となる電源供給元ノードと、
前記電源供給元ノードと前記第1電源電圧配線とを接続する第2電源電圧配線と、
前記第2電源電圧配線の一部の区間よりなる第1電極と、基準電源電圧が供給される第2電極とを持ち、単位セルで構成されるオンチップコンデンサと、を有し、
前記電源供給元ノードからの前記電源電圧は、前記第1電極を経由して前記コア回路部に供給される半導体装置。 - 請求項1記載の半導体装置において、
前記オンチップコンデンサは、前記コア回路部のバイパスコンデンサとして機能する半導体装置。 - 請求項2記載の半導体装置において、
前記第1電源電圧配線は、
前記第1領域の外周部に沿って配置されるメイン電源電圧配線と、
前記メイン電源電圧配線から分岐して網目状に配置されるサブ電源電圧配線と、を備え、
前記オンチップコンデンサは、前記第1電極の一端が前記メイン電源電圧配線に接続され、前記第1電極の他端が前記電源供給元ノードに接続される半導体装置。 - 請求項3記載の半導体装置において、
前記電源供給元ノードから前記コア回路部に向けた前記電源電圧の供給は、全て前記第1電極を経由して行われる半導体装置。 - 請求項4記載の半導体装置において、
前記オンチップコンデンサは、前記メイン電源電圧配線に沿って複数配置される半導体装置。 - 請求項5記載の半導体装置において、
更に、前記電源供給元ノードに前記電源電圧を生成する電源レギュレータ回路を備え、
前記電源レギュレータ回路は、前記複数のオンチップコンデンサの合間に配置される半導体装置。 - 請求項5記載の半導体装置において、
前記電源供給元ノードは、外部端子である半導体装置。 - 請求項2記載の半導体装置において、
前記オンチップコンデンサは、
前記半導体基板内に形成され、前記第2電極となるウエルと、
前記ウエル上に形成される絶縁膜と、
前記絶縁膜上に形成され、前記第1電極となるゲート配線と、を備える半導体装置。 - 請求項2記載の半導体装置において、
前記オンチップコンデンサは、前記半導体基板上の複数層のメタル配線層と、同一のメタル配線層内で各メタル配線間を分離するメタル配線間絶縁膜と、異なるメタル配線層間を分離する層間絶縁膜とを用いて形成される半導体装置。 - 一つの半導体基板で構成される半導体装置であって、
所定の処理を実行するコア回路部を形成するための第1領域と、
前記第1領域内に配置され、前記コア回路部に電源電圧を供給するための第1電源電圧配線と、
前記第1領域外に配置され、前記電源電圧の供給元となる電源供給元ノードと、
前記電源供給元ノードと前記第1電源電圧配線とを接続する第2電源電圧配線と、
前記第2電源電圧配線の一部の区間よりなる第1電極と、基準電源電圧が供給される第2電極とを持ち、単位セルで構成されるオンチップコンデンサと、を有し、
前記オンチップコンデンサは、
前記半導体基板内に形成される第1導電型のウエルと、
前記ウエル内に形成され、前記ウエルよりも高い不純物濃度を持つ前記第1導電型の第1半導体領域と、
前記ウエル上に形成される絶縁膜と、
前記絶縁膜上に形成されるゲート配線と、
前記ゲート配線の両端部の上にそれぞれ形成される第1および第2コンタクト層と、を備え、
前記ゲート配線は、前記第1電極を構成し、
前記ウエルは、前記第1半導体領域に前記基準電源電圧が供給されることで前記第2電極を構成する半導体装置。 - 請求項10記載の半導体装置において、
前記ゲート配線は、メタルゲートで形成される半導体装置。 - 請求項11記載の半導体装置において、
前記第1電源電圧配線は、
前記第1領域の外周部に沿って配置されるメイン電源電圧配線と、
前記メイン電源電圧配線から分岐して網目状に配置されるサブ電源電圧配線と、を備え、
前記第1コンタクト層は、前記メイン電源電圧配線に接続され、
前記第2コンタクト層は、前記電源供給元ノードに接続される半導体装置。 - 請求項12記載の半導体装置において、
前記電源供給元ノードから前記コア回路部に向けた前記電源電圧の供給は、全て前記ゲート配線を経由して行われる半導体装置。 - 請求項13記載の半導体装置において、
前記オンチップコンデンサは、前記メイン電源電圧配線に沿って複数配置される半導体装置。 - 請求項14記載の半導体装置において、
前記第1導電型は、n型である半導体装置。 - 一つの半導体基板で構成される半導体装置であって、
所定の処理を実行するコア回路部を形成するための第1領域と、
前記第1領域内に配置され、前記コア回路部に電源電圧を供給するための第1電源電圧配線と、
前記第1領域外に配置され、前記電源電圧の供給元となる電源供給元ノードと、
前記電源供給元ノードと前記第1電源電圧配線とを接続する第2電源電圧配線と、
前記第2電源電圧配線の一部の区間よりなる第1電極と、基準電源電圧が供給される第2電極とを持ち、単位セルで構成されるオンチップコンデンサと、を備え、
前記第1および第2電極は、前記半導体基板上のメタル配線層で形成され、
前記第1電極は、前記第2電源電圧配線の一部の区間の両端となる第1および第2ノードの間で、並んで第1方向に延伸する複数の第1メタル配線を有し、
前記第2電極は、並んで前記第1方向に延伸し、前記複数の第1メタル配線に対して絶縁膜を挟んで所定の間隔で配置される複数の第2メタル配線を有する半導体装置。 - 請求項16記載の半導体装置において、
前記複数の第1および第2メタル配線は、前記半導体基板上の複数層のメタル配線層で形成され、
前記複数の第1および第2メタル配線を前記第1方向と直交する第2方向の断面で見た場合に、前記第1メタル配線と前記第2メタル配線は、前記複数層のメタル配線層の同じ層内において交互に配置され、前記複数層のメタル配線層の層方向において交互に配置される半導体装置。 - 請求項17記載の半導体装置において、
前記第1電源電圧配線は、
前記第1領域の外周部に沿って配置されるメイン電源電圧配線と、
前記メイン電源電圧配線から分岐して網目状に配置されるサブ電源電圧配線と、を備え、
前記第1ノードは、前記メイン電源電圧配線に接続され、
前記第2ノードは、前記電源供給元ノードに接続される半導体装置。 - 請求項18記載の半導体装置において、
前記電源供給元ノードから前記コア回路部に向けた前記電源電圧の供給は、全て前記複数の第1メタル配線を経由して行われる半導体装置。 - 請求項19記載の半導体装置において、
前記オンチップコンデンサは、前記メイン電源電圧配線に沿って複数配置される半導体装置。
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PCT/JP2013/082793 WO2015083281A1 (ja) | 2013-12-06 | 2013-12-06 | 半導体装置 |
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JP2016040814A (ja) * | 2014-08-13 | 2016-03-24 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US11189569B2 (en) * | 2016-09-23 | 2021-11-30 | Advanced Micro Devices, Inc. | Power grid layout designs for integrated circuits |
US10747931B2 (en) | 2017-07-28 | 2020-08-18 | Advanced Micro Devices, Inc. | Shift of circuit periphery layout to leverage optimal use of available metal tracks in periphery logic |
US11120190B2 (en) | 2017-11-21 | 2021-09-14 | Advanced Micro Devices, Inc. | Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level |
US10438937B1 (en) | 2018-04-27 | 2019-10-08 | Advanced Micro Devices, Inc. | Metal zero contact via redundancy on output nodes and inset power rail architecture |
US10818762B2 (en) | 2018-05-25 | 2020-10-27 | Advanced Micro Devices, Inc. | Gate contact over active region in cell |
KR102048319B1 (ko) * | 2018-07-20 | 2019-11-25 | 삼성전자주식회사 | 반도체 패키지 |
US10796061B1 (en) | 2019-08-29 | 2020-10-06 | Advanced Micro Devices, Inc. | Standard cell and power grid architectures with EUV lithography |
JP2021043786A (ja) * | 2019-09-12 | 2021-03-18 | キオクシア株式会社 | 半導体装置および電圧供給方法 |
CN112530933B (zh) * | 2019-09-18 | 2024-03-22 | 铠侠股份有限公司 | 半导体装置 |
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JP2007180087A (ja) * | 2005-12-27 | 2007-07-12 | Seiko Epson Corp | 集積回路装置 |
JP2007288028A (ja) * | 2006-04-19 | 2007-11-01 | Sony Corp | 信号遅延構造 |
JP2009283792A (ja) * | 2008-05-23 | 2009-12-03 | Mitsumi Electric Co Ltd | 半導体装置及び半導体集積回路装置 |
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2013
- 2013-12-06 US US14/381,482 patent/US20160276287A1/en not_active Abandoned
- 2013-12-06 JP JP2014539938A patent/JPWO2015083281A1/ja active Pending
- 2013-12-06 WO PCT/JP2013/082793 patent/WO2015083281A1/ja active Application Filing
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JP2009283792A (ja) * | 2008-05-23 | 2009-12-03 | Mitsumi Electric Co Ltd | 半導体装置及び半導体集積回路装置 |
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