WO2015078120A1 - 高一致性低功耗阻变存储器及制备方法 - Google Patents
高一致性低功耗阻变存储器及制备方法 Download PDFInfo
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- WO2015078120A1 WO2015078120A1 PCT/CN2014/074369 CN2014074369W WO2015078120A1 WO 2015078120 A1 WO2015078120 A1 WO 2015078120A1 CN 2014074369 W CN2014074369 W CN 2014074369W WO 2015078120 A1 WO2015078120 A1 WO 2015078120A1
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- Prior art keywords
- resistive switching
- layer
- resistive
- resistance value
- layer structure
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- 238000002360 preparation method Methods 0.000 title claims description 10
- 239000000463 material Substances 0.000 claims abstract description 53
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 48
- 239000001301 oxygen Substances 0.000 claims abstract description 48
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 35
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000001105 regulatory effect Effects 0.000 claims abstract description 8
- 230000007423 decrease Effects 0.000 claims abstract 2
- 150000004706 metal oxides Chemical class 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 15
- 238000004544 sputter deposition Methods 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 229910003070 TaOx Inorganic materials 0.000 claims description 8
- 238000005240 physical vapour deposition Methods 0.000 claims description 8
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
- 230000003247 decreasing effect Effects 0.000 claims description 5
- 229910000314 transition metal oxide Inorganic materials 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910003134 ZrOx Inorganic materials 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000010409 thin film Substances 0.000 abstract 3
- 239000010410 layer Substances 0.000 description 52
- 238000003860 storage Methods 0.000 description 9
- 101100022875 Mus musculus Meox1 gene Proteins 0.000 description 5
- 101150029117 meox2 gene Proteins 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- -1 oxygen ions Chemical class 0.000 description 3
- 102100026559 Filamin-B Human genes 0.000 description 2
- 101000913551 Homo sapiens Filamin-B Proteins 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000033228 biological regulation Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001491 hyper Rayleigh scattering spectroscopy Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000008261 resistance mechanism Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/023—Formation of switching materials, e.g. deposition of layers by chemical vapor deposition, e.g. MOCVD, ALD
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
Definitions
- the present application claims priority to Chinese Patent Application (201310618361.8) filed on Nov. 28, 2013, the entire content of BACKGROUND OF THE INVENTION 1.
- the present invention relates to a resistive memory (RRAM), and more particularly to a high-consistency, low-power 2-bit resistive memory cell design and a method for fabricating the same, which are non-volatile in CMOS Very Large Scale Integrated Circuit (ULSI) Nonvolatile memory performance optimization and its manufacturing technology.
- CMOS Very Large Scale Integrated Circuit
- CTM charge trap memory
- FeRAM ferroelectric memory
- MRAM magnetic memory
- PRAM phase change memory
- resistive memory resistive memory
- CTM charge trap memory
- FeRAM ferroelectric memory
- MRAM magnetic memory
- PRAM phase change memory
- resistive memory resistive memory
- the resistive memory structure is simple, mainly composed of a top electrode, a resistive material film and a bottom electrode three-layer structure (MIM); and the resistive material generally uses a metal oxide having a simple structure.
- the resistance mechanism it is generally considered to be caused by the movement of oxygen vacancies (or oxygen ions).
- the set operation is to generate oxygen vacancies in the resistive material film under the action of an electric field and to move and accumulate under the action of an electric field, and finally form a low-resistance conductive channel (CF) in the local area, and the device is converted into a low-resistance state (LRS).
- CF low-resistance conductive channel
- the reset process can be divided into two types, unipolar and bipolar, according to the action of heat or electric field: the unipolar reset is a combination of oxygen ions and oxygen vacancies around the CF under the action of heat, so that the channel is disconnected, and the device is transformed into High-impedance state (HRS); bipolar reset is mainly the effect of the electric field opposite to the set process The reverse movement of the oxygen ions is combined with the oxygen vacancies to break the CF (or create a gap) and convert to HRS.
- HRS High-impedance state
- bipolar reset is mainly the effect of the electric field opposite to the set process
- the reverse movement of the oxygen ions is combined with the oxygen vacancies to break the CF (or create a gap) and convert to HRS.
- people implement multi-value storage by regulating the set or reset process.
- one method is to adjust the thickness of the CF (or the oxygen vacancy concentration in CF) by adjusting the current limit (CC) during the set process to achieve different LRS resistance values; the other method is in the bipolar reset
- different HRS resistance values are realized by adjusting the stop voltage and then regulating the length of the gap.
- one HRS and three different resistance LRSs or one LRS and three different resistance HRSs can constitute 2-bit storage of a single device, and so on, 3-bit can be realized by appropriate regulation. Even higher density storage.
- the switching of CF in the ordinary resistive memory occurs in the single-layer resistive layer. Since the thickness of CF (or the oxygen vacancy concentration in CF) and the regulation of gap are large, the consistency problem is serious.
- the present invention can realize the complete on-off of the oxygen vacancy channel (CF) in each layer by dividing the film of the same metal oxide resistive material into four layers according to different oxygen concentrations, thereby accurately controlling the resistance. Value, to achieve high consistency 2-bit storage.
- the resistance of each layer in the 4-layer structure low-current operation can be performed, thereby achieving low power consumption.
- we can further realize 3-bit and higher density storage.
- a resistive memory structure comprising a substrate, an insulating layer, a bottom electrode, a resistive material film, and a top electrode in sequence from bottom to top, wherein the resistive material film is The four-layer structure consisting of the same metal oxide; the four-layer structure is sequentially increased by at least 10 times from the bottom-up resistance; the four-layer structure is sequentially increased from the bottom to the top, and the thickness is sequentially decreased.
- the resistive memory device is characterized in that: the four-layer structure, from bottom to top, the resistance of the first layer is
- the resistive memory is characterized in that the substrate is a Si substrate and a crossbar structure (or other common MIM structure) is used.
- the resistive memory device is characterized in that the bottom electrode and the top electrode material are conductive metals or metal nitrides.
- the resistive memory device is characterized in that the resistive material is made of a transition metal oxide material.
- the resistive memory device is characterized in that the transition metal oxide is HfOx, TaOx, ZrOx or WOx.
- step (2) Prepare and pattern the top electrode by PVD sputtering (or electron beam evaporation) on the resistive material film to define the device size.
- step (2) four layers of the resistive material are sequentially deposited by the sputtering method in the same chamber by adjusting the oxygen partial pressure to prepare a resistive material film.
- step (2) four layers of resistive materials are sequentially deposited by thermal oxidation to adjust the oxygen ratio, oxidation time, oxidation temperature and the like in the atmosphere to prepare a resistive material film.
- step (2) four layers of the resistive material are sequentially deposited by an ALD method to adjust the ratio of the reducing atmosphere, and a resistive material film is prepared.
- the resistive memory design proposed by the present invention has the following three advantages:
- the resistance values of MOx -3 and MOx -4 are Rl, R2, R3 and R4 respectively, where R1 «R2 «R3 «R4, then the resistance value of high resistance is determined by R4, that is, HRS R4; Small voltage, and set the current limit value to the current value corresponding to the R3 resistance of MOx -3, so that the conductive filament CF can be generated only in the uppermost layer MOx -4, as shown in Fig. 4, and thus after the set
- the resistance is determined by R3, that is, LRS3 R3; similarly, when the set is continued, and the current value corresponding to the R2 resistance of the current limit of MOx -2 is set, the conductive filament CF can continue in the third layer MOx -3.
- Figure 1 is a schematic cross-sectional view showing the structure of the RRAM of the present invention.
- Figure 2 is a top plan view of the crossbar structure of the device of the RRAM of the present invention.
- Figure 3 is a schematic diagram of a four-layer resistive film.
- Figure 4 - Figure 6 Schematic diagram of the 2-bit resistive process in sequence during electrical operation.
- 7 to FIG. 13 are schematic diagrams showing the structure of an RRAM assisted in the preparation process of the present invention.
- BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be further described with reference to the accompanying drawings, but the scope of the present invention is not limited thereto.
- the invention provides a resistive memory, the structure of which is shown in Figure 1, and the main resistance resistive memory structure
- the main difference of (MIM) is that the resistive material film is composed of four layers of metal oxide (MOx) having an oxygen concentration gradient, and the bottom four layers are abbreviated as MOx -1, MOx -2, and MOx -3, respectively.
- MOx -4 the oxygen concentration from MOx -1 to MOx -4 is sequentially increased, the thickness is sequentially decreased, and the gradient between the resistance values of each layer is realized by relevant experimental control (in experiments, the oxygen concentration or film thickness is adjusted every time) Then, measure the resistance once, and select the corresponding oxygen concentration range or film thickness according to the set resistance range.
- MOx -1 resistance is 10 3 ⁇ 10 4 ⁇
- MOx -2 resistance is about 10 5 ⁇ 10 6 ⁇
- MOx -3 resistance is about 10 7 ⁇ 10 8 ⁇
- MOx -4 resistance is about 10 9 ⁇ 10 10 ⁇ .
- the substrate is a Si substrate; a conventional crossbar structure is used as shown in Fig. 2; (2)
- the bottom electrode and the top electrode material are conductive metals or metal nitrides such as Pt, Al, Ti or TiN,
- the resistive material can be preferentially selected from the current mainstream transition metal oxide materials (such as HfOx, TaOx, ZrOx, WOx, etc.), and each oxide can select a suitable oxygen content gradient according to the respective resistance values of the respective oxygen contents, and then press The oxygen content is sequentially increased, and the thickness is sequentially decreased to sequentially deposit 4 layers; the preparation process of the resistive memory of the present invention is as follows:
- bottom electrode preparation PVD sputtering (or electron beam evaporation) on the substrate, metal Ti/M, wherein Ti is used as an adhesion layer, M is a bottom electrode, and a bottom electrode is patterned by a stripping or etching process;
- Preparation method of resistive film By sputtering method, four layers of resistive materials are sequentially deposited by adjusting oxygen partial pressure in the same chamber (according to the commonly used experimental parameters of the RRAM device according to the material, the film is first tested, Then, the resistance is measured. If the resistance of the experimental film is smaller than the set resistance range, the oxygen concentration is increased, or the thickness is slightly increased.
- the experimental conditions for the four layers are set to prepare a film of the resistive material; Two: through the thermal oxidation method, adjusting the oxygen ratio, oxidation time, oxidation temperature, etc.
- Method 3 depositing four layers of resistive materials by ALD method, adjusting the proportion of the reducing atmosphere (the same method, the experimental conditions corresponding to different resistance values are to be debugged in advance), and preparing a film of the resistive material;
- Top electrode preparation PVD sputtering (or electron beam evaporation) Prepare and pattern the top electrode to define the device dimensions.
- Embodiment 1 The following is a detailed description of the present invention by taking a TaOx resistive memory as an example, in conjunction with the accompanying drawings and specific embodiments.
- the process for preparing a high-consistent and low-power 2-bit resistive memory cell of the present invention is as follows:
- a first layer of resistive material film Preparation of the first layer of TaOx resistive material by PVD magnetron sputtering Film 4-1, thickness 30nm, oxygen partial pressure 3%, film resistance about 10 3 ⁇ (here given oxygen partial pressure and thickness are reference values, the corresponding corresponding thickness and oxygen partial pressure corresponding resistance needs to be determined experimentally in advance
- the following three steps are the same; the experiment includes: adjusting the oxygen concentration and the film thickness, and then measuring the resistance, according to the resistance ratio set to a larger or smaller resistance range, and then adjusting the oxygen concentration and thickness, for example, if the experimental film The resistance value is smaller than the set resistance range, and the oxygen concentration is increased, or the film thickness is increased, as shown in FIG. 9;
- the oxygen partial pressure is regulated in the sputtering chamber, and the fourth layer of TaOx resistive material film 4-4 is further prepared, having a thickness of 5 nm and an oxygen partial pressure of 50%. (ibid., oxygen partial pressure and thickness are reference values)
- the sheet resistance is about 10 9 ⁇ , as shown in Figure 12;
- the top electrode is prepared. Prepare and pattern the top electrode 5 by PVD sputtering to define the device size range (2 ⁇ > ⁇ 2 ⁇
- the invention directly prepares a four-layer resistive material film by adjusting the oxygen component of the sputtering process without adding an additional process step, thereby preparing a 2-bit resistive memory with high consistency and low power consumption.
- the process is simple and the performance is improved significantly.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/916,950 US9525133B2 (en) | 2013-11-28 | 2014-03-31 | Resistive random access memory with high uniformity and low power consumption and method for fabricating the same |
DE112014002344.2T DE112014002344T5 (de) | 2013-11-28 | 2014-03-31 | Hochkonsistenter und energiesparender resistiver speicher und verfahren zu dessen herstellung |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310618361.8A CN103606625B (zh) | 2013-11-28 | 2013-11-28 | 高一致性低功耗阻变存储器及制备方法 |
CN201310618361.8 | 2013-11-28 |
Publications (1)
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WO2015078120A1 true WO2015078120A1 (zh) | 2015-06-04 |
Family
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Application Number | Title | Priority Date | Filing Date |
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PCT/CN2014/074369 WO2015078120A1 (zh) | 2013-11-28 | 2014-03-31 | 高一致性低功耗阻变存储器及制备方法 |
Country Status (4)
Country | Link |
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US (1) | US9525133B2 (zh) |
CN (1) | CN103606625B (zh) |
DE (1) | DE112014002344T5 (zh) |
WO (1) | WO2015078120A1 (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103606625B (zh) * | 2013-11-28 | 2016-04-06 | 北京大学 | 高一致性低功耗阻变存储器及制备方法 |
WO2016105407A1 (en) * | 2014-12-24 | 2016-06-30 | Intel Corporation | Resistive memory cells and precursors thereof, methods of making the same, and devices including the same |
CN106571289B (zh) * | 2015-10-13 | 2020-01-03 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制备方法、电子装置 |
CN108807668B (zh) * | 2018-06-25 | 2020-07-10 | 华中科技大学 | 基于金属氧化物氧浓度梯度的高性能忆阻器件及其制备 |
CN109935685B (zh) * | 2019-01-31 | 2020-08-18 | 华中科技大学 | 一种调控材料中空位缺陷的方法 |
CN109888092B (zh) * | 2019-03-06 | 2023-05-02 | 天津理工大学 | 一种基于氧化钽/二维黒砷磷/氧化钽的三层异质阻变存储器及其制备方法 |
KR20210083933A (ko) * | 2019-12-27 | 2021-07-07 | 삼성전자주식회사 | 가변 저항 메모리 소자 |
CN113611722A (zh) | 2020-05-12 | 2021-11-05 | 联芯集成电路制造(厦门)有限公司 | 电阻式存储装置以及其制作方法 |
CN111564555B (zh) * | 2020-05-20 | 2022-04-12 | 浙江大学 | 一种改善工作稳定性及存储窗口的阻变存储器及制备方法 |
CN112331768B (zh) * | 2020-11-13 | 2023-02-03 | 上海华力集成电路制造有限公司 | 制造rram器件及制备渐变绝缘层结构的方法 |
CN113346016A (zh) * | 2021-05-20 | 2021-09-03 | 华中科技大学 | 一种忆阻器及其制备方法 |
CN113363382A (zh) * | 2021-05-31 | 2021-09-07 | 中国科学院微电子研究所 | 一种射频开关器件、射频电路及电子设备 |
CN114068808A (zh) * | 2021-11-03 | 2022-02-18 | 厦门半导体工业技术研发有限公司 | 一种半导体集成电路器件及其制造方法 |
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- 2013-11-28 CN CN201310618361.8A patent/CN103606625B/zh active Active
-
2014
- 2014-03-31 WO PCT/CN2014/074369 patent/WO2015078120A1/zh active Application Filing
- 2014-03-31 US US14/916,950 patent/US9525133B2/en not_active Expired - Fee Related
- 2014-03-31 DE DE112014002344.2T patent/DE112014002344T5/de not_active Withdrawn
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CN101960595A (zh) * | 2009-02-04 | 2011-01-26 | 松下电器产业株式会社 | 非易失性存储元件 |
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CN202308073U (zh) * | 2010-10-08 | 2012-07-04 | 松下电器产业株式会社 | 非易失性存储元件 |
CN102194995A (zh) * | 2011-05-10 | 2011-09-21 | 天津理工大学 | 一种基于氧化锌的极性可控阻变存储器及其制备方法 |
CN103348472A (zh) * | 2011-12-02 | 2013-10-09 | 松下电器产业株式会社 | 非易失性存储元件和非易失性存储装置 |
CN103606625A (zh) * | 2013-11-28 | 2014-02-26 | 北京大学 | 高一致性低功耗阻变存储器及制备方法 |
Also Published As
Publication number | Publication date |
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CN103606625A (zh) | 2014-02-26 |
CN103606625B (zh) | 2016-04-06 |
US9525133B2 (en) | 2016-12-20 |
DE112014002344T5 (de) | 2016-01-21 |
US20160225987A1 (en) | 2016-08-04 |
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