WO2014121618A1 - 一种高可靠性非挥发存储器及其制备方法 - Google Patents

一种高可靠性非挥发存储器及其制备方法 Download PDF

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WO2014121618A1
WO2014121618A1 PCT/CN2013/084761 CN2013084761W WO2014121618A1 WO 2014121618 A1 WO2014121618 A1 WO 2014121618A1 CN 2013084761 W CN2013084761 W CN 2013084761W WO 2014121618 A1 WO2014121618 A1 WO 2014121618A1
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metal
oxide
resistive material
volatile memory
electrode
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PCT/CN2013/084761
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English (en)
French (fr)
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黄如
余牧溪
蔡一茂
白文亮
黄英龙
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北京大学
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Priority to US14/759,624 priority Critical patent/US9379322B2/en
Publication of WO2014121618A1 publication Critical patent/WO2014121618A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8416—Electrodes adapted for supplying ionic species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8418—Electrodes adapted for focusing electric field or current, e.g. tip-shaped
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element

Definitions

  • the invention relates to a resistive memory (RRAM), in particular to a high reliability and high consistency memory structure and a preparation method thereof, and belongs to a nonvolatile memory performance optimization in a CMOS Very Large Scale Integrated Circuit (ULSI) and Manufacturing technology.
  • RRAM resistive memory
  • ULSI Very Large Scale Integrated Circuit
  • Semiconductor memory is one of the core pillars of semiconductor technology development and has an irreplaceable position in various IT fields.
  • Current mainstream semiconductor memories mainly include volatile dynamic random access memory (DRAM) and static random access memory (SRAM), as well as non-volatile flash memory (Flash).
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • Flash non-volatile flash memory
  • CTM charge trap memory
  • FeRAM ferroelectric memory
  • MRAM magnetic memory
  • PRAM Phase change memory
  • RRAM resistive memory
  • the resistive memory is based on the resistive property of the storage medium to realize information storage.
  • the resistive change property is the property that some dielectric materials can reversibly change between high and low resistance states under the action of an applied electric field.
  • the resistive memory can be further divided into an inorganic resistive memory and an organic resistive memory according to different resistive materials, wherein a memory based on excessive metal oxide (TMO) in the inorganic resistive memory in the prior art is used.
  • TMO excessive metal oxide
  • the voltage between the two plates is V.
  • the resistive memory In the initial state, the resistive memory is in a high-impedance state.
  • the device state changes from a high-impedance state to a low-resistance state.
  • This process is called forming, and the corresponding voltage V Vform; the low-resistance state can be maintained for a long time after power-off, until after the voltage is applied and reaches a certain value, the device returns to a high-resistance state, the process is reset, and the corresponding voltage V is Vreset; likewise, The high-resistance state can be maintained for a long time after the power is turned off. Until the voltage V reaches a certain value, the resistive material changes back to low resistance. The process is set, and the corresponding voltage V is Vset. At present, the mainstream view believes that The reason for the resistance change of the metal oxide resistive memory is mainly the filament conductive mechanism.
  • the high resistance state and the low resistance state of the device correspond to the formation and fracture processes of the conductive filaments, respectively.
  • the electric field acts to orient the metal ions or oxygen vacancies, thereby forming a conductive channel connecting the upper and lower electrodes in a local region, corresponding to the low resistance state of the device; when the voltage is v reset , due to the electric field and heat The combined effect of the channel is blown and the device becomes high impedance.
  • the present invention mainly proposes a solution to the above two problems. SUMMARY OF THE INVENTION Based on the above problems, the present invention aims to improve the consistency of a device and solve the reliability problem existing in a resistive memory. The combination of a doping technique and a two-layer resistive material can effectively improve device consistency and reliability. Sex.
  • a highly reliable non-volatile memory comprising an upper electrode, a lower electrode and a resistive material between the upper and lower electrodes, wherein the upper electrode is on the top of the device and the lower electrode is on the substrate, in the metal oxide of the resistive material The metal is doped, and a metal oxygen storage layer is added between the upper electrode and the resistive material.
  • metal M1 and the doping metal M2 corresponding to the metal oxide in the resistive material satisfy any of the following conditions:
  • the Gibbs free energy ⁇ Ml of M1 reacting with oxygen to form oxide is lower than the Gibbs free energy ⁇ corresponding to M2
  • the corresponding metal M3 of the metal oxygen storage layer satisfies the following conditions:
  • the Gibbs free energy ⁇ Ml of M1 reacting with oxygen to form an oxide is higher than the ⁇ ⁇ 3 corresponding to M3. Further, the electrode is patterned to form a series of parallel strip-shaped sawtooth structures on the surface of the substrate and the metal oxygen storage layer, the cross section of which is " ⁇ ".
  • the substrate uses Si as a supporting substrate, and the upper and lower electrode materials are selected from a conductive metal or a metal nitride, and one or more of Pt, Al, Ti, and TiN may be selected.
  • Transition material selection transition The metal oxide may be one or more selected from the group consisting of HfOx, TaOx, ZrOx, and WOx.
  • the upper electrode is patterned on the metal oxygen storage thin layer to complete the preparation.
  • the metal Ti and Pt are sputtered on the substrate in a thickness range of 100 to 200 nm, and the lower electrode is patterned by a lift-off process, wherein Ti is an adhesion layer and Pt is a lower electrode.
  • metal M1 and the doping metal M2 corresponding to the metal oxide in the resistive material satisfy any of the following conditions:
  • the Gibbs free energy ⁇ Ml of M1 reacting with oxygen to form oxide is lower than the Gibbs free energy ⁇ corresponding to M2
  • the corresponding metal M3 of the metal oxygen storage layer satisfies the following conditions:
  • the thickness of the resistive material obtained by the PVD sputtering method ranges from 20 to 50 nm, and metal impurities are doped into the resistive material by ion implantation, and the metal oxygen storage thin layer is passed through a PVD sputtering method, and the thickness ranges from 5 to 10 nm.
  • the resistive memory design proposed by the present invention has the following three advantages:
  • the fabrication process is compatible with CMOS processes and is easy to implement.
  • the doping can effectively improve the consistency of the device:
  • the two conditions mentioned above for the doping metal M2 can effectively increase the concentration of oxygen vacancies around the M2, thereby making the oxygen vacancy conductive path along the doping path. Formed to avoid the problem of poor consistency due to random formation of conductive filaments.
  • the Gibbs free energy ⁇ ⁇ 1 of the reaction of M1 with oxygen to form an oxide is lower than the ⁇ ⁇ 2 corresponding to M2, that is, the metal M1 corresponding to the resistive material is more likely to react with oxygen and oxygen, and vice versa.
  • FIG. 1 is a schematic view of a prior art excessive metal oxide resistive memory
  • FIG. 2 is a schematic diagram of a resistive memory according to an embodiment of the present invention, wherein: 1-substrate, 2-lower electrode, 3-metal doped resistive material, 4-thin metal storage layer, 5-upper electrode
  • FIG. 3 to FIG. 9 are schematic diagrams showing processes for preparing various parts in a method for preparing a resistive memory according to an embodiment of the present invention
  • Figure 3 is a schematic view of a substrate for preparing an insulating layer
  • FIG. 4 is a schematic view of a lower electrode prepared by sputtering a metal on a substrate;
  • FIG. 5 is a schematic view showing a method of preparing a metal oxide resistive material film to cover a bottom electrode by a sputtering method;
  • FIG. 6 is a schematic view of metal impurity doping into a resistive material;
  • 7 is a schematic view of preparing a corresponding metal oxygen storage thin layer by a sputtering or evaporation method on a resistive material;
  • FIG. 8 is a schematic view of an electrode draining hole under etching;
  • FIG. 9 is a schematic diagram of preparing an upper electrode resistive memory.
  • a highly reliable non-volatile memory including a 1-substrate, a 2-lower electrode, a 3-metal doped resistive material, and a 4-thin metal storage oxygen layer from bottom to top. , 5-upper electrode.
  • the detailed description of the structure of the diagram is as follows:
  • the substrate 1 is made of Si or other supporting substrate
  • the upper and lower electrode materials 1, 5 are conductive metals or metal nitrides (defining the upper and lower electrodes are M01 and M0 2 , respectively), such as Pt, Al, Ti, and TiN; (3) the resistive material 3 can be preferentially used now.
  • conductive metals or metal nitrides defining the upper and lower electrodes are M01 and M0 2 , respectively
  • the resistive material 3 can be preferentially used now.
  • Excessive metal oxide materials eg HfOx, TaOx,
  • the metal doped into the resistive material 3 shall meet one of the following two basic requirements (the metal corresponding to the metal oxide in the resistive material is defined as M1 and the doped metal is M2): 1) M1 reacts with oxygen The Gibbs free energy ⁇ Ml of the generated oxide is lower than the Gibbs free energy ⁇ M2 corresponding to M2, 2) the valence state of M2 in the corresponding oxide is lower than the valence state of M1 in the corresponding oxide;
  • the metal oxygen storage layer 4 should satisfy the following conditions (the metal corresponding to the metal oxygen storage layer is defined as M3):
  • the Gibbs free energy ⁇ Ml of M1 reacting with oxygen to form an oxide is higher than the ⁇ ⁇ 3 corresponding to M3.
  • 3 to 9 are schematic diagrams showing the preparation process of the high reliability non-volatile resistive memory of the present invention.
  • the preparation process of the resistive memory of the present invention is as follows:
  • Si0 2 is grown on the substrate silicon wafer as an insulating layer (101), as shown in FIG. 3;
  • a metal Ti/Pt (thickness of about 100 to 200 nm) is sputtered on the substrate 101, wherein Ti serves as an adhesion layer and Pt is a lower electrode, and the lower electrode 201 is patterned by a lift-off process, and the lower electrode 201 is formed on the substrate insulating layer.
  • a series of parallel arranged strip sawtooth structures as shown in Figure 4;
  • the metal impurity A1 (302) is implanted into the TaOx film by ion implantation, as shown in Fig. 6; the metal M1 and the doping metal M2 corresponding to the metal oxide in the resistive material satisfy any of the following conditions:
  • the Gibbs free energy ⁇ Ml of M1 reacting with oxygen to form oxide is lower than the Gibbs free energy ⁇ corresponding to M2
  • a thin layer of metal Ti (401) (having a thickness of about 5 to 10 nm) is prepared by PVD sputtering, and a metal oxygen storage layer 401 is coated on the resistive material 301, as shown in FIG. 7; 6) etching the lower electrode lead-out hole 502, As shown in Figure 8, the upper electrode was prepared and patterned by PVD sputtering.
  • a voltage can be applied between the upper and lower electrodes to define a device size range (2 ⁇ 2 ⁇ ⁇ 100 ⁇ 100 ⁇ ).
  • the lower electrode is on the substrate, and the metal oxide of the resistive material is doped with metal.
  • a metal oxygen storage layer is added between the upper electrode and the resistive material.
  • the invention adopts a combination method of doping and double layer, and finally selects a resistive material, a doping material and an intermediate layer material which meet certain conditions, and selects a suitable process method, thereby finally preparing a high reliability and high consistency resistive memory. , better improve the performance of the resistive memory.

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Abstract

本发明涉及高可靠性非挥发阻变存储器及其制备方法，储器包括上电极、下电极和位于上下电极之间的阻变材料，其中，上电极位于器件顶部，下电极位于衬底上，在阻变材料的金属氧化物中掺杂金属，在上电极和阻变材料之间有增设一金属储氧层。其制备方法采用掺杂和双层相结合的方法，可制备高可靠性高一致性阻变存储器，较好提高阻变存储器的性能。

Description

一种高可靠性非挥发存储器及其制备方法 技术领域
本发明涉及阻变存储器（RRAM)， 具体涉及一种高可靠性高一致性的存储器结 构及其制备方法， 属于 CMOS 超大规模集成电路 （ULSI ) 中的非挥发存储器 (Nonvolatile memory) 性能优化及其制造技术领域。 背景技术
半导体存储器是半导体技术发展的核心支柱之一， 在各个 IT领域都具有不可替 代的地位。 目前主流的半导体存储器主要包括挥发性的动态随机存储器（DRAM)和 静态随机存储器（SRAM)， 以及非挥发性的快闪存储器（Flash)。但是随着技术进步， 当特征尺寸不断缩小， 集成密度不断提高， 尤其是进入纳米尺寸节点后， DRAM、 SRAM和 Flash的缩小能力都将达到极限。尤其是非挥发性存储器的性能等参数随机 涨落显著增加， 可靠性问题日益严峻。 为此， 人们通过研究新材料、 新结构和新功能 等多种技术解决方案， 提出了新型非挥发性存储器技术， 包括电荷陷阱存储器 (CTM)、 铁电存储器 （FeRAM)、 磁存储器 (MRAM)、 相变存储器 (PRAM), 阻变存 储器（RRAM)等。 其中， 阻变存储器凭借其各方面的优异性能， 获得了人们的广泛 关注， 并成为下一代主流存储器的研究热点。 阻变存储器是基于存储介质的阻变特性实现信息存储的， 阻变特性即某些电介 质材料在外加电场作用下电阻发生高低阻态间可逆变化的性质。阻变存储器根据其阻 变材料的不同又可分为无机阻变存储器和有机阻变存储器，其中，在现有技术中无机 阻变存储器中基于过度金属氧化物 （TMO) 制作而成的存储器因为其工艺简单、 成 本低等优势而占据主流， TMO-RRAM 结构如图 1 所示。 两极板间电压为 V， 初始 状态下， 阻变存储器呈高阻态， 当电压增加到一定值时， 器件状态由高阻态变为低阻 态， 该过程被称为 forming, 对应的电压 V为 Vform; 该低阻态在断电后能长期保持， 直到当继续施加电压并达到某一值后， 器件又变回高阻态， 该过程为 reset, 对应的 电压 V为 Vreset;同样， 其高阻态在断电后能长期保持， 直到当再施加电压 V达某一 值后， 阻变材料又变回低阻， 该过程为 set, 对应的电压 V为 Vset， 目前， 主流观点认为， 金属氧化物阻变存储器的阻变原因主要为细丝导电机制。 即器件的高阻态和低阻态分别对应导电细丝的形成和断裂过程。 当 v=vset时， 电场 作用使金属离子或者氧空位定向移动，从而在局部区域内形成了连接上下电极的导电 通道， 对应器件的低阻态； 当电压为 vreset时， 由于电场和热的综合作用， 使通道熔 断， 器件变为高阻。
由于阻变存储器中导电通道的形成位置、 长度、 粗细都是随机的， 所以相对应 器件表现出来的各项参数都会在不同器件或者不同开关过程中有所波动，即存在器件 的一致性问题； 另外， 由于通道由金属离子或者氧空位移动形成， 在反复的读写操作 时， 金属离子或者氧空位有可能扩散到周围环境中而使器件特性退化，产生可靠性问 题。 本发明即主要针对以上两方面问题提出解决方案。 发明内容 基于以上问题， 本发明目的在于提高器件的一致性以及解决阻变存储器中存在 的可靠性问题，采用掺杂技术和双层阻变材料相结合的方法， 能有效提高器件一致性 和可靠性。
本发明的技术方案如下：
一种高可靠性非挥发存储器， 包括上电极、 下电极和位于上下电极之间的阻变 材料， 其中， 上电极位于器件顶部， 下电极位于衬底上， 在阻变材料的金属氧化物中 掺杂金属， 在上电极和阻变材料之间有增设一金属储氧层。
进一步的， 所述阻变材料中金属氧化物对应的金属 Ml和掺杂金属 M2， 满足如 下条件的任意一种：
Ml与氧反应生成氧化物的吉布斯自由能 Δ Ml低于 M2对应的吉布斯自由能 Δ
M2; 或者 M2在对应氧化物中的价态低于 Ml在相应氧化物中的价态。
进一步的， 金属储氧层相应金属 M3满足如下条件：
Ml与氧反应生成氧化物的吉布斯自由能 Δ Ml高于 M3对应的 Δ Μ3。 进一步的， 对电极进行图形化， 在衬底和金属储氧层表面形成一系列平行排列 的条状锯齿结构， 其截面为 "Λ"形。
可选的， 所述衬底采用 Si作为支撑性衬底， 所述上、 下电极材料选用导电金属 或金属氮化物， 可选择 Pt、 Al 、 Ti和 TiN中的一种或多种， 所述阻变材料选用过渡 金属氧化物， 可选择 HfOx， TaOx, ZrOx, WOx中的一种或多种。 本发明还提出一种高可靠性非挥发存储器制备方法， 其步骤包括：
1 ) 在衬底上溅射金属， 通过工艺图形化形成下电极；
2)通过溅射方法先制备金属氧化物阻变材料覆盖于底层电极， 再将相应的金属 杂质掺杂到阻变材料中；
3 ) 在阻变材料上通过溅射或蒸发方法制备相应的金属储氧薄层；
4) 在金属储氧薄层上图形化上电极， 完成制备。
可选的，制备下电极时，在衬底上溅射金属 Ti和 Pt，厚度范围为： 100〜200nm， 通过剥离工艺图形化下电极， 其中 Ti为粘附层， Pt为下电极。
进一步的， 阻变材料中金属氧化物对应的金属 Ml和掺杂金属 M2， 满足如下条 件的任意一种：
Ml与氧反应生成氧化物的吉布斯自由能 Δ Ml低于 M2对应的吉布斯自由能 Δ
M2; 或者 M2在对应氧化物中的价态低于 Ml在相应氧化物中的价态。
可选的， 金属储氧层相应金属 M3满足如下条件：
Ml与氧反应生成氧化物的吉布斯自由能 Δ Ml高于 M3对应的 Δ Μ3。 可选的， 通过 PVD溅射方法得到的阻变材料的厚度范围为 20〜50nm， 通过离 子注入将金属杂质掺杂到阻变材料中， 金属储氧薄层通过 PVD溅射方法， 厚度范围 为 5〜10nm。 本发明提出的阻变存储器设计主要有以下三点优势：
( 1 ) 制作工艺与 CMOS工艺兼容， 容易实现。
(2)通过掺杂可以有效提高器件的一致性： 上述提到的掺杂金属 M2应满足的 两个条件都能有效提高 M2周围氧空位的浓度，从而使氧空位导电通道沿着掺杂路径 形成，而避免了因导电细丝随机形成造成的一致性不好的问题。具体而言，对条件 1， Ml与氧反应生成氧化物的吉布斯自由能 Δ Μ1低于 M2对应的 Δ Μ2， 即阻变材料对 应的金属 Ml更易与氧发生反应与氧结合， 反之， M2周围则具有更高的氧空位浓度； 对条件 2， M2在对应氧化物中的价态低于 Ml在相应氧化物中的价态， 从而能有效 降低 M2周围氧空位的形成能， SP， 便 M2周围氧空位浓度更高。
(3 )通过在阻变材料和上电极间引入薄层金属储氧层， 可以有效的解决阻变存 储器中存在的可靠性问题。 因为 Ml与氧反应生成氧化物的吉布斯自由能 Δ Μ1高于 M3对应的 Δ Μ3， 即薄层金属 Μ3更容易和氧反应， 这样在 forming/set过程中， 会使 定向移动的氧离子在阻变材料和金属储氧层的界面处与 M3 反应并以氧化物的形式 存储起来，这样能有效防止氧离子延上电极金属扩散入环境中，而影响器件的耐久性。 附图说明
图 1是现有技术中过度金属氧化物阻变存储器的示意图；
图 2 是本发明一实施例中阻变存储器的示意图， 其中， 1-衬底、 2-下电极、 3- 金属掺杂的阻变材料、 4-薄层金属储氧层、 5-上电极； 图 3〜图 9是本发明一实施例中制备阻变存储器的方法中制备各部分的流程示意 图；
图 3是制备绝缘层的衬底示意图；
图 4是在衬底上溅射金属制备下电极示意图； 图 5是通过溅射方法先制备金属氧化物阻变材料薄膜覆盖于底层电极示意图； 图 6 金属杂质掺杂到阻变材料中示意图； 图 7是在阻变材料上通过溅射或蒸发方法制备相应的金属储氧薄层示意图； 图 8是刻蚀下电极引出孔示意图； 图 9 制备上电极阻变存储器示意图。 具体实施方式 下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 可以理解的是， 所描述的实施例仅仅是本发明一部分实施例， 而不是全 部的实施例。基于本发明中的实施例，本领域技术人员在没有做出创造性劳动前提下 所获得的所有其他实施例， 都属于本发明保护的范围。
一种高可靠性非挥发存储器， 其结构如图 2示， 从下到上依次包括 1-衬底、 2- 下电极、 3-金属掺杂的阻变材料、 4-薄层金属储氧层、 5-上电极。 图示结构的具体描述如下：
( 1 ) 衬底 1采用 Si或其他支撑性衬底；
(2)上下电极材料 1,5为导电金属或金属氮化物（定义上下电极分别为 M01和 M02)， 如 Pt、 Al 、 Ti和 TiN等； (3 )阻变材料 3可以优先选用现在主流的过度金属氧化物材料（如 HfOx， TaOx,
ZrOx, WOx等）；
(4) 向阻变材料 3中掺杂的金属应符合下列两项基本要求之一（定义阻变材料 中金属氧化物对应的金属为 Ml， 掺杂金属为 M2): 1 ) Ml与氧反应生成氧化物的吉 布斯自由能 Δ Ml低于 M2对应的吉布斯自由能 Δ M2， 2 ) M2在对应氧化物中的价态 低于 Ml在相应氧化物中的价态；
( 5 ) 金属储氧层 4应该满足以下条件 （定义金属储氧层相应的金属为 M3 ): Ml与氧反应生成氧化物的吉布斯自由能 Δ Ml高于 M3对应的 Δ Μ3。 如图 3~9是本发明的高可靠性非挥发阻变存储器制备过程示意图， 本发明的阻变存储器制备流程如下：
( 1 ) 下电极制备， 在衬底上溅射金属 Ti/M02， 其中 Ti作为粘附层， M02为下 电极， 通过剥离或腐蚀工艺图形化形成下电极；
(2) 阻变薄膜制备， 通过溅射方法制备阻变材料薄膜；
(3 ) 阻变材料掺杂， 通过离子注入掺杂相应的金属杂质；
(4) 薄层金属储氧层制备， 通过溅射或蒸发等方法制备相应的金属储氧薄层； (5) 上电极制备， 溅射制备并图形化上电极， 定义器件尺寸。 下面结合附图和具体实施方式对本发明作进一步详细描述：
本发明制备高可靠性高一致性阻变存储器的工艺结合附图描述如下：
1 ) 制备绝缘层。 在衬底硅片上生长 Si02作为绝缘层 （101 )， 如图 3所示；
2) 制备下电极。 在衬底 101 上溅射金属 Ti/Pt (厚度约 100~200nm)， 其中 Ti 作为粘附层， Pt为下电极， 通过剥离工艺图形化下电极 201， 下电极 201在衬底绝缘 层上形成一系列平行排列的条状锯齿结构， 如图 4所示；
3 ) 制备阻变材料。 通过 PVD溅射方法制备 TaOx阻变材料 301， （厚度大约在 20~50nm), 阻变材料 301覆盖于下电极条状锯齿结构上， 如图 5所示；
4)阻变材料掺杂。通过离子注入的方法在 TaOx薄膜中注入金属杂质 A1 (302), 如图 6所示； 阻变材料中金属氧化物对应的金属 Ml和掺杂金属 M2， 满足如下条件 的任意一种：
Ml与氧反应生成氧化物的吉布斯自由能 Δ Ml低于 M2对应的吉布斯自由能 Δ
M2; 或者 M2在对应氧化物中的价态低于 Ml在相应氧化物中的价态。
5 ) 制备薄层金属储氧层。 通过 PVD溅射制备薄层金属 Ti (401 ) (厚度大约在 5~10nm), 金属储氧层 401覆盖于阻变材料 301上， 如图 7所示； 6) 刻蚀下电极引出孔 502， 如图 8所示， 通过 PVD溅射制备并图形化上电极
501， 可在上下电极间施加电压， 定义器件尺寸范围 （2μιηΧ 2μιη ~100μιηΧ 100μιη)， 如图 9所示， 下电极位于衬底上， 在所述阻变材料的金属氧化物中掺杂金属， 在上电 极和阻变材料之间有增设一金属储氧层。
7) 制得高可靠性高一致性阻变存储器。 本发明采用掺杂和双层相结合的方法， 通过选择符合一定条件的阻变材料、 掺 杂材料和中间层材料， 并选用合适的工艺方法，最终可制备高可靠性高一致性阻变存 储器， 较好提高阻变存储器的性能。

Claims

权 利 要 求
1. 一种非挥发存储器， 包括上电极、 下电极和位于上下电极之间的阻变材 料， 其中， 上电极位于器件顶部， 其特征在于， 下电极位于衬底上， 在所述阻变 材料的金属氧化物中掺杂金属， 在上电极和阻变材料之间有增设一金属储氧层。
2. 如权利要求 1 所述的非挥发存储器， 其特征在于， 所述阻变材料中金属 氧化物对应的金属 Ml和掺杂金属 M2， 满足如下条件的任意一种：
Ml与氧反应生成氧化物的吉布斯自由能 Δ Ml低于 M2对应的吉布斯自由能 Δ Μ2;
或者 M2在对应氧化物中的价态低于 Ml在相应氧化物中的价态。
3. 如权利要求 1或 2述的非挥发存储器， 其特征在于， 金属储氧层相应金 属 M3满足如下条件：
Ml与氧反应生成氧化物的吉布斯自由能 Δ Ml高于 M3对应的 Δ Μ3。
4. 如权利要求 1 所述的非挥发存储器， 其特征在于， 所述电极为图形化电 极， 所述衬底和金属储氧层表面具有一系列平行排列的条状锯齿结构， 所述条状 锯齿结构的截面为 "Λ"形。
5. 如权利要求 1〜4任意一项所述的非挥发存储器， 其特征在于， 所述衬底 采用 Si作为支撑性衬底， 所述上、 下电极材料选用导电金属或金属氮化物， 可 选择 Pt、 Al 、 Ti和 TiN中的一种或多种， 所述阻变材料选用过渡金属氧化物， 可选择 HfOx， TaOx, ZrOx, WOx中的一种或多种。
6. 一种非挥发存储器制备方法， 其步骤包括：
1 ) 在衬底上溅射金属， 通过工艺图形化形成下电极；
2) 通过溅射方法先制备金属氧化物阻变材料覆盖于底层电极， 再将相应的 金属杂质掺杂到阻变材料中；
3 ) 在阻变材料上通过溅射或蒸发方法制备相应的金属储氧薄层；
4) 在金属储氧薄层上图形化上电极， 完成制备。
7. 如权利要求 6所述的非挥发存储器制备方法， 其特征在于， 制备下电极 时， 在衬底上溅射金属 Ti和 Pt， 厚度范围为： 100〜200nm， 通过剥离工艺图形 化下电极， 其中 Ti为粘附层， Pt为下电极。
8. 如权利要求 6所述的非挥发存储器制备方法， 其特征在于， 阻变材料中 金属氧化物对应的金属 Ml和掺杂金属 M2， 满足如下条件的任意一种：
Ml与氧反应生成氧化物的吉布斯自由能 Δ Ml低于 M2对应的吉布斯自由能 Δ Μ2;
或者 M2在对应氧化物中的价态低于 Ml在相应氧化物中的价态。
9. 如权利要求 6所述的非挥发存储器制备方法， 其特征在于， 金属储氧层 相应金属 M3满足如下条件：
Ml与氧反应生成氧化物的吉布斯自由能 Δ Ml高于 M3对应的 Δ Μ3。
10. 如权利要求 6所述的非挥发存储器制备方法， 其特征在于， 通过 PVD 溅射方法得到的阻变材料的厚度范围为 20〜50nm， 通过离子注入将金属杂质掺 杂到阻变材料中， 金属储氧薄层通过 PVD溅射方法， 厚度范围为 5〜10nm。
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