WO2015039381A1 - 阵列基板及其制备方法与显示装置 - Google Patents

阵列基板及其制备方法与显示装置 Download PDF

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Publication number
WO2015039381A1
WO2015039381A1 PCT/CN2013/088146 CN2013088146W WO2015039381A1 WO 2015039381 A1 WO2015039381 A1 WO 2015039381A1 CN 2013088146 W CN2013088146 W CN 2013088146W WO 2015039381 A1 WO2015039381 A1 WO 2015039381A1
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Prior art keywords
layer
array substrate
source
drain
base substrate
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Ceased
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PCT/CN2013/088146
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English (en)
French (fr)
Inventor
孙建
李成
安星俊
柳奉烈
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US14/364,024 priority Critical patent/US9922996B2/en
Publication of WO2015039381A1 publication Critical patent/WO2015039381A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/832—Electrodes characterised by their material
    • H10H20/833—Transparent materials
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • TFT Thin Film Transistor
  • LTPS Low Temperature Poly-silicon
  • the pixel pitch of the array substrate of the LTPS TFT display device is getting smaller as the resolution of the product and the aperture ratio become higher and higher. This in turn causes the storage capacitance of the array substrate to become smaller and smaller.
  • the LTPS TFT P ⁇ l substrate in the case of the same size leakage current, the smaller the storage capacitance, the lower the pixel voltage retention rate, which in turn leads to undesirable phenomena such as flicker, which is greatly reduced.
  • the quality of high-resolution products such as array substrates or TFT display devices. Therefore, how to increase the storage capacitance without affecting the aperture ratio of the array substrate has become an urgent problem in the industry. Summary of the invention
  • the embodiment of the invention provides an array substrate, a preparation method thereof and a display device, which are used to solve the problem of low quality of the array substrate or the display device caused by the small storage capacitance of the array substrate existing in the prior art.
  • One aspect of the present invention provides an array substrate including a base substrate, a buffer layer sequentially formed on the base substrate, a semiconductor layer, a gate insulating layer, a gate metal layer, and an interlayer dielectric a layer, a source/drain metal layer, and a pixel electrode layer, and a common electrode layer formed between the base substrate and the buffer layer.
  • a horizontal projection area of the common electrode layer on the base substrate and the image respectively The horizontal projection area of the element electrode layer on the substrate substrate and the horizontal projection area of the semiconductor layer on the substrate substrate overlap.
  • the semiconductor layer may be a polysilicon layer.
  • the source/drain metal layer includes a pattern of a source, a drain, and a data line, and the interlayer dielectric layer and the gate insulating layer are formed with a source, a drain, and the semiconductor, respectively.
  • the source is electrically connected to the source via and the drain via.
  • the common electrode layer is made of a transparent conductive material.
  • the transparent conductive material is ITO (indium tin oxide).
  • Another aspect of the present invention also provides a display device comprising the array substrate described in the embodiment of the present invention.
  • a still further aspect of the present invention provides a method for fabricating an array substrate, the method comprising: forming a common electrode layer on a substrate substrate; forming a buffer layer, a semiconductor layer, a gate insulating layer, and the gate electrode layer on the common electrode layer; a gate metal layer, an interlayer dielectric layer, a source/drain metal layer, and a pixel electrode layer.
  • a horizontal projection area of the common electrode layer on the substrate substrate and a horizontal projection area of the pixel electrode layer on the substrate substrate and a level of the semiconductor layer on the substrate substrate There is overlap in the projection area.
  • the semiconductor layer can be a polysilicon layer.
  • the source/drain metal layer includes a pattern of a source, a drain, and a data line; after forming the interlayer dielectric layer, and before forming the source/drain metal layer, the method further includes: Source vias and drain vias for electrically connecting the source and drain to the semiconductor layer are formed in the interlayer dielectric layer and the gate insulating layer.
  • the common electrode layer can not only form a storage capacitor with the pixel electrode layer, but also form a storage capacitor with the semiconductor layer, thereby increasing the storage capacitance of the array substrate and increasing the pixel voltage retention rate of the array substrate. And the effect of reducing the phenomenon of the flickering of the display device, and improving the quality of the array substrate and the display device.
  • the process of removing the subsequent protective layer and the passivation layer can be omitted. The process can also achieve the film structure of the cylindrical array substrate and the effect of the manufacturing process.
  • FIG. 1 is a schematic structural view of an array substrate according to Embodiment 1 of the present invention.
  • FIG. 2( a ) is a schematic diagram of a manufacturing process of the array substrate according to the first embodiment of the present invention
  • FIG. 2 ( b ) is a second schematic diagram of the manufacturing process of the array substrate according to the first embodiment of the present invention
  • (c) is a schematic diagram of the manufacturing process of the array substrate according to the first embodiment of the present invention
  • FIG. 2(d) is a schematic view showing the manufacturing process of the array substrate according to the first embodiment of the present invention
  • FIG. 2(f) is a schematic view showing the manufacturing process of the array substrate according to the first embodiment of the present invention
  • FIG. 2(g) is a schematic view of the manufacturing process of the array substrate according to the first embodiment of the present invention
  • FIG. 2( h ) is a schematic diagram of a manufacturing process of the array substrate according to the first embodiment of the present invention
  • FIG. 2 ( i ) is a schematic view of the manufacturing process of the array substrate according to the first embodiment of the present invention
  • FIG. 3 is a schematic view showing the planar structure of the array substrate according to the first embodiment of the present invention.
  • the array substrate provided in the first embodiment of the present invention includes: a base substrate 11, a buffer layer 12 sequentially formed on the base substrate 11, a semiconductor layer 13, a gate insulating layer 14, a gate metal layer 15, and an interlayer dielectric The layer 16, the source/drain metal layer 17, and the pixel electrode layer 18.
  • the array substrate further includes: a common electrode layer 19 formed between the base substrate 11 and the buffer layer 12.
  • the common electrode layer 19 may partially cover the base substrate 11 , and a horizontal projection area of the common electrode layer 19 on the base substrate 11 and the pixel electrode layer 11 respectively There is overlap in the horizontal projection area.
  • the common electrode layer 19 can be generally prepared from a transparent conductive material, which may be ITO (Indium Oxide), AZO (Aluminum Doped Oxide), etc., and the embodiment of the present invention does not make any limited.
  • the semiconductor layer 13 may be a polysilicon layer or a non-polysilicon layer.
  • the semiconductor layer 13 may be a polysilicon layer.
  • the source/drain metal layer 17 may generally include a pattern of a source, a drain, and a data line, which will not be described in detail in the embodiment of the present invention; accordingly, the interlayer dielectric layer 16 and the gate insulating layer 14 Source vias 161 and drain vias 162 for electrically connecting the source and drain of the source/drain metal layer 17 to the semiconductor layer 13 may also be formed therein, which is used in the embodiment of the present invention. Do not repeat them.
  • the common electrode layer 19 may be formed on the base substrate 11 before the buffer layer 12 is formed, so that the common electrode layer 19 can form not only a storage capacitor with the pixel electrode layer 18 but also a storage layer with the semiconductor layer 13. capacitance.
  • This structure has an effect of increasing the storage capacitance of the array substrate, increasing the pixel voltage holding ratio of the array substrate, and reducing the occurrence of flicker in the display device, thereby improving the quality of the array substrate and the display device.
  • the film layer structure of the protective layer, the common electrode layer, and the passivation layer is no longer disposed between the pixel electrode layer 18 and the source/drain metal layer 17, The process of preparing the subsequent protective layer and the passivation layer is performed, thereby achieving the film structure of the packaged array substrate and the effect of the fabrication process.
  • the first embodiment further provides a method for preparing an array substrate. Specifically, the method for preparing the array substrate described in the first embodiment will be described below with reference to FIGS. 2(a) to 2(i).
  • the array substrate preparation method can be carried out as follows.
  • Step 101 Forming the common electrode layer 19 on the base substrate 11, as shown in Fig. 2(a).
  • the substrate substrate 11 may be a glass substrate or a plastic substrate, etc., which is not limited in the embodiment of the present invention; further, before the common electrode layer 19 is formed on the base substrate 11, the The base substrate 11 is subjected to a pre-cleaning operation, and thereafter, a common electrode film layer is formed on the base substrate 11 by deposition, sputtering, or the like, and is coated, exposed, developed, etched, and light by including photoresist.
  • a patterning process of a process such as a stripping process is performed on the substrate substrate 11 to form a common electrode layer 19 having a pattern, which will not be described in detail in the embodiments of the present invention.
  • the pattern of the common electrode layer 19 may partially cover the base substrate 11. Moreover, in order to achieve the purpose of increasing the storage capacitance of the array substrate, in the embodiment of the present invention, the pattern of the common electrode layer 19 generally satisfies the following conditions: the common electrode layer 19 is on the base substrate 11. The horizontal projection areas overlap with the horizontal projection area of the pixel electrode layer 18 on the base substrate 11 and the horizontal projection area of the semiconductor layer 13 on the base substrate 11, respectively. This allows the common electrode layer 19 to form not only a storage capacitor with the pixel electrode layer 18 but also a storage capacitor with the semiconductor layer 13, thereby increasing the storage capacitance of the array substrate and improving the performance of the array substrate and the display device product.
  • the pattern of the common electrode layer 19 may also completely cover the base substrate 11, which may reduce one patterning process, but increase unnecessary parasitic capacitance. Therefore, preferably, the pattern portion of the common electrode layer 19 covers the base substrate, and the horizontal projection area on the base substrate 11 and the level of the pixel electrode layer 18 on the base substrate 11 and respectively The projection area and the horizontal projection area of the semiconductor layer 13 on the base substrate 11 overlap.
  • Step 102 Form a buffer layer 12 on the common electrode layer 19, as shown in Fig. 2(b).
  • the buffer layer 12 may be deposited on the common electrode layer 19 by a method such as CVD (Chemical Vapor Deposition); further, the buffer layer 12 may be nitrided.
  • the double-layered insulating layer structure of the silicon thin film layer and the silicon oxide thin film layer may also be a single-layer insulating layer structure such as a silicon nitride film layer or a silicon oxide film layer, which is not limited in the embodiment of the present invention.
  • Step 103 Forming a semiconductor layer 13 on the buffer layer 12 as shown in Fig. 2(c).
  • the semiconductor layer 13 may be a polysilicon layer or a non-polysilicon layer; when the semiconductor layer
  • an amorphous silicon layer may be deposited on the buffer layer 12 by a method such as CVD, and the amorphous silicon may be crystallized by excimer laser annealing (ELA) or solid phase crystallization (SPC).
  • ELA excimer laser annealing
  • SPC solid phase crystallization
  • a desired polysilicon pattern is formed by a patterning process including photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • Step 104 Forming a gate insulating layer 14 on the semiconductor layer 13 as shown in Fig. 2(d).
  • a gate insulating layer 14 may be deposited on the semiconductor layer 13 by a method such as CVD; further, the gate insulating layer 14 may be a silicon oxide layer, a silicon nitride layer, or a silicon oxide layer and a silicon nitride layer.
  • the composite insulating layer or the like composed of the layers is not limited in this embodiment of the present invention.
  • Step 105 forming a gate metal layer 15 on the gate insulating layer 14, as shown in FIG. 2(e)
  • the gate metal layer 15 may include a pattern of gate lines, gate lines, and common electrode lines, which will not be described in detail in the embodiment of the present invention; and when the gate metal layer 15 is formed on the gate insulating layer 14, Forming a metal layer on the gate insulating layer 14 by using a method such as PVD (Physical Vapor Deposition), and by a process including photoresist coating, exposure, development, etching, photoresist stripping, etc.
  • a patterning process forms a pattern of gate lines, gate lines, and common electrode lines on the gate insulating layer 14 at a time.
  • the metal layer may be an aluminum layer, a tungsten layer, a chromium layer or other metal and metal compound conductive layer, and the like, which is not limited in the embodiment of the present invention.
  • Step 106 forming an interlayer dielectric layer 16 on the gate metal layer 15 as shown in Fig. 2(f).
  • the interlayer dielectric layer 16 may be deposited on the gate metal layer 15 by a method such as CVD to protect the gate metal layer 15 and isolate the gate metal layer 15 and subsequent source/drain metal layers.
  • the purpose of the present invention is not limited by the embodiment of the present invention.
  • the interlayer dielectric layer 16 may be made of a material such as silicon oxide or silicon nitride.
  • Step 107 forming source vias and drain vias penetrating into the semiconductor layer 13 in the interlayer dielectric layer 16 and the gate insulating layer 14 as shown in FIG. 2( g ) .
  • one or more patterning processes may be used to form a source via 161 and a drain via 162 directly in the interlayer dielectric layer 16 and the gate insulating layer 14 to the semiconductor layer 13.
  • the embodiment of the present invention does not limit this.
  • Step 108 forming a source 171 and a drain 172 on the interlayer via 161, the drain via 162, and the interlayer dielectric layer 16 having the source via 161 and the drain via 162.
  • the source/drain metal layer 17 can be as shown in Fig. 2(h).
  • a conductive material may be deposited on the surface of the interlayer dielectric layer 16 having the source via 161 and the drain via 162, and coated, exposed, developed, and etched by including photoresist.
  • a patterning process of a process such as photoresist stripping to form a source/drain metal layer 17 including the source electrode 171 and the drain electrode 172.
  • the conductive material may be aluminum, tungsten, chromium or other metals and metal compounds, and the like, which is not limited in the embodiment of the invention.
  • the source/drain metal layer 17 may generally include a source, a drain, and a data line. Therefore, in this step 108, the data line (Data) can be formed at the same time as the source 171 and the drain 172 are formed, which will not be described in detail in the embodiment of the present invention.
  • Step 109 Form a pixel electrode layer 18 on the source/drain metal layer 17, as shown in Fig. 2(i).
  • a transparent conductive material layer may be deposited on the source/drain metal layer 17 by a method such as CVD, and may be obtained by a patterning process including photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • a pixel electrode layer 18 having a pattern is provided.
  • the obtained pixel electrode layer 18 can be electrically connected to the drain 172 of the source/drain metal layer 17, which will not be further described in the embodiment of the present invention.
  • the array substrate according to the embodiment of the present invention can be obtained.
  • a schematic diagram of the planar structure of the obtained array substrate can be shown in FIG.
  • the layers are transparent or translucent for clarity of illustration.
  • the gate line 100 and the data line 200 cross each other to define a plurality of pixel units, each of which includes a thin film transistor, a pixel electrode layer 18, a common electrode layer 19, and the like, each thin film transistor including a gate electrode and a semiconductor
  • the layer, the source and the drain, etc., for example, the gate is a part of the gate line 100, and the pixel electrode in the pixel electrode layer 18 is a comb electrode.
  • the common electrode layer (Vcom) 19 may be enlarged below the semiconductor layer 13 on the side of the pixel electrode layer 18, except that it may be located below the pixel electrode layer 18.
  • the common electrode layer 19 can not only form a storage capacitor with the pixel electrode layer 18, but also form a storage capacitor with the semiconductor layer 13.
  • the array is further increased.
  • the storage capacitor of the substrate the purpose of improving the performance of the array substrate and the display device product.
  • the array substrate includes a base substrate, a buffer layer sequentially formed on the base substrate, a semiconductor layer, a gate insulating layer, a gate metal layer, and an interlayer layer.
  • the dielectric layer, the source/drain metal layer, and the pixel electrode layer further include: a common electrode layer formed between the base substrate and the buffer layer.
  • the common electrode layer Since the common electrode layer is formed on the base substrate before the buffer layer is formed, the common electrode layer not only forms a storage capacitor with the pixel electrode layer, but also forms a storage capacitor with the semiconductor layer, thereby increasing the storage capacitance of the array substrate, The effect of improving the pixel voltage retention ratio of the array substrate and reducing the phenomenon such as flicker of the display device improves the quality of the array substrate and the display device; in addition, the preparation method can save subsequent protection as compared with the prior art. a process such as a layer and a passivation layer, thereby also achieving a film structure of the packaged array substrate And the effect of the production process.
  • the embodiment of the present invention is described by taking a top-gate TFT in which a semiconductor layer is a polysilicon layer as an example.
  • a TFT in which a semiconductor layer is an amorphous silicon layer or the like the embodiment of the present invention is also applicable, and is applicable to a bottom gate type.
  • TFTs or other structurally deformed TFTs, as long as the storage capacitors need to be increased by increasing the facing area, are also within the scope of protection of the embodiments of the present invention.
  • the second embodiment of the present invention provides a display device, which may be a liquid crystal display panel, an electronic paper, an OLED (Organic Light-Emitting Diode) panel, a mobile phone, a tablet computer, a television, a display, a notebook. Any of the products or components having a display function, such as a computer, a digital photo frame, a navigator, and the like, are not limited in this embodiment of the present invention.
  • the display device includes the array substrate according to the first embodiment of the present invention, which is not described in detail in the second embodiment of the present invention.
  • the display device described in the embodiment of the present invention may be a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, or an IPS (In-Plane Switching) mode.
  • the ADS (Advanced Super Dimension Switch) mode is not limited in this embodiment of the present invention.
  • the display device in the embodiment of the present invention is particularly applicable to the IPS mode and the ADS mode.

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板包括衬底基板（11），依次形成在衬底基板（11）上的缓冲层（12）、半导体层（13）、栅极绝缘层（14）、栅金属层（15）、层间介电层（16）、源漏金属层（17）以及像素电极层（18），以及形成在衬底基板（11）与缓冲层（12）之间的公共电极层（19）。该阵列基板具有增大的存储电容和提高的像素电压保持率，降低了显示装置的闪烁等不良现象。还涉及该阵列基板的制备方法与包括该阵列基板的显示装置。

Description

阵列基板及其制备方法与显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制备方法与显示装置。 背景技术
随着 TFT ( Thin Film Transistor,薄膜晶体管 )液晶显示技术的不断发展， 具备功耗低、 分辨率高、反应速度快以及开口率高等特点的基于 LTPS ( Low Temperature Poly-silicon, 低温多晶硅）技术的 TFT显示装置逐渐成为主流。 这样的显示装置已被广泛应用于各种电子设备如液晶电视、 智能手机、 平板 电脑以及数码相机等数字电子设备中。
但是， 在基于 LTPS技术的 TFT显示装置等高分辨率产品中， 随着产品 分辨率以及开口率的越来越高， LTPS TFT显示装置的阵列基板的像素间距 ( pixel pitch )也越来越小， 这进而导致阵列基板的存储电容越来越小。 由于 对于 LTPS TFT P车歹l基板来说， 在同样大小漏电流情况下， 存储电容越小则 像素电压的保持率越低， 这进而会导致闪烁 （Flicker )等不良现象的产生， 极大地降低了阵列基板或 TFT显示装置等高分辨率产品的品质。 因此， 如何 在不影响阵列基板开口率的同时提高其存储电容， 已成为业界亟需解决的问 题。 发明内容
本发明实施例提供了一种阵列基板及其制备方法与显示装置， 用以解决 现有技术中存在的阵列基板的存储电容较小所导致的阵列基板或显示装置品 质较低的问题。
本发明的一个方面提供了一种阵列基板， 所述阵列基板包括衬底基板、 依次形成在所述衬底基板上的緩沖层、 半导体层、 栅极绝缘层、 栅金属层、 层间介电层、 源漏金属层以及像素电极层， 以及形成在所述衬底基板与所述 緩沖层之间的公共电极层。
例如， 所述公共电极层在所述衬底基板上的水平投影区域分别与所述像 素电极层在所述村底基板上的水平投影区域以及所述半导体层在所述村底基 板上的水平投影区域存在重叠。
例如， 所述半导体层可以为多晶硅层。
例如， 所述源漏金属层包括源极、 漏极和数据线的图案， 所述层间介电 层以及栅极绝缘层内形成有分别用于将所述源极、 漏极与所述半导体层电连 接的源极过孔以及漏极过孔。
例如， 所述公共电极层由透明导电材料制备而成。 例如， 所述透明导电 材料为 ITO (氧化锡铟 ) 。
本发明的另一方面还提供了一种显示装置， 所述显示装置包括本发明实 施例中所述的阵列基板。
本发明的再一方面还提供了一种阵列基板制备方法， 所述方法包括： 在 村底基板上形成公共电极层； 在所述公共电极层上形成緩沖层、 半导体层、 栅极绝缘层、 栅金属层、 层间介电层、 源漏金属层以及像素电极层。
例如， 所述公共电极层在所述村底基板上的水平投影区域分别与所述像 素电极层在所述村底基板上的水平投影区域以及所述半导体层在所述村底基 板上的水平投影区域存在重叠。
例如， 所述半导体层可为多晶硅层。
例如， 所述源漏金属层包括源极、 漏极和数据线的图案； 在形成所述层 间介电层之后， 且在形成所述源漏金属层之前， 所述方法还包括： 在所述层 间介电层以及栅极绝缘层内形成分别用于将所述源极、 漏极与所述半导体层 电连接的源极过孔以及漏极过孔。
本发明实施例提供的阵列基板中， 公共电极层不仅可与像素电极层形成 存储电容，还可与半导体层形成存储电容，起到了增大阵列基板的存储电容、 提高阵列基板的像素电压保持率以及降低显示装置的闪烁等不良现象的效 果， 提高了阵列基板及显示装置的品质； 另外， 本发明实施例提供的阵列基 板的制备方法中， 由于可省去后续保护层及钝化层等工艺流程， 从而还可达 到筒化阵列基板的膜层结构以及制作工艺的效果。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1所示为本发明实施例一中所述阵列基板的结构示意图；
图 2 ( a )所示为本发明实施例一中所述阵列基板的制作工艺示意图一； 图 2 ( b )所示为本发明实施例一中所述阵列基板的制作工艺示意图二； 图 2 ( c )所示为本发明实施例一中所述阵列基板的制作工艺示意图三； 图 2 ( d )所示为本发明实施例一中所述阵列基板的制作工艺示意图四； 图 2 ( e )所示为本发明实施例一中所述阵列基板的制作工艺示意图五； 图 2 ( f)所示为本发明实施例一中所述阵列基板的制作工艺示意图六； 图 2 ( g )所示为本发明实施例一中所述阵列基板的制作工艺示意图七； 图 2 ( h )所示为本发明实施例一中所述阵列基板的制作工艺示意图八； 图 2 ( i )所示为本发明实施例一中所述阵列基板的制作工艺示意图九； 图 3所示为本发明实施例一中所述阵列基板的平面结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
实施例一
图 1为本发明实施例一的阵列基板的结构示意图。 本发明实施例一提供 的阵列基板包括：衬底基板 11、依次形成在所述衬底基板 11上的緩沖层 12、 半导体层 13、 栅极绝缘层 14、 栅金属层 15、 层间介电层 16、 源漏金属层 17 以及像素电极层 18。 所述阵列基板还包括： 形成在所述衬底基板 11与所述 緩沖层 12之间的公共电极层 19。
具体地， 所述公共电极层 19可部分覆盖所述衬底基板 11 , 并且， 所述 公共电极层 19在所述衬底基板 11上的水平投影区域分别与所述像素电极层 板 11上的水平投影区域存在重叠。 进一步地，所述公共电极层 19通常可由透明导电材料制备而成，所述透 明导电材料可为 ITO (氧化铟辞） 、 AZO (掺铝氧化辞）等材料， 本发明实 施例对此不作任何限定。
进一步地， 所述半导体层 13可为多晶硅层或非多晶硅层。 例如， 在本发 明所述实施例中， 所述半导体层 13通常可为多晶硅层。
进一步地， 所述源漏金属层 17通常可包括源极、 漏极和数据线的图案， 本发明实施例对此不作赘述； 相应地， 所述层间介电层 16 以及栅极绝缘层 14内还可形成有分别用于将所述源漏金属层 17中的源极、 漏极与所述半导 体层 13电连接的源极过孔 161以及漏极过孔 162,本发明实施例对此不作赘 述。
在本实施例中， 可在形成緩沖层 12之前， 在衬底基板 11上形成公共电 极层 19, 使得公共电极层 19不仅可与像素电极层 18形成存储电容， 还可与 半导体层 13形成存储电容。该结构起到了增大阵列基板的存储电容、提高阵 列基板的像素电压保持率以及降低显示装置的闪烁等不良现象的效果， 提高 了阵列基板及显示装置的品质。
另外， 与现有技术相比， 由于所述像素电极层 18与所述源漏金属层 17 之间不再设置有保护层、 公共电极层以及钝化层等膜层结构， 因此， 还可省 去后续保护层及钝化层等工艺制备流程， 从而还可达到筒化阵列基板的膜层 结构以及制作工艺的效果。
进一步地， 本实施例一还提供了一种阵列基板制备方法。 具体地， 下面 将结合图 2 ( a )〜图 2 ( i )对本实施例一中所述阵列基板的制备方法进行筒 要说明。 所述阵列基板制备方法可以如下进行。
步骤 101 : 在衬底基板 11上形成公共电极层 19, 可如图 2 ( a )所示。 例如，所述衬底基板 11可以为玻璃基板或塑料基板等，本发明实施例对 此不作任何限定；进一步地，在所述衬底基板 11上形成公共电极层 19之前， 还可对所述衬底基板 11进行预清洗操作，之后， 可采用沉积、 溅射等方式在 所述衬底基板 11上形成公共电极薄膜层， 并通过包括光刻胶涂敷、 曝光、显 影、刻蚀、光刻胶剥离等工艺的构图工艺在所述衬底基板 11上形成具备设定 图案的公共电极层 19, 本发明实施例对此不作赘述。
进一步地， 所述公共电极层 19的图案可以部分覆盖所述衬底基板 11。 并且， 为了达到增加阵列基板的存储电容的目的， 在本发明所述实施例中， 所述公共电极层 19的图案通常可满足以下条件： 所述公共电极层 19在所述 衬底基板 11上的水平投影区域分别与像素电极层 18在所述衬底基板 11上的 水平投影区域以及半导体层 13在所述衬底基板 11上的水平投影区域存在重 叠。 这使得所述公共电极层 19不仅可与像素电极层 18形成存储电容， 还可 与半导体层 13形成存储电容，进而达到增大阵列基板的存储电容、提高阵列 基板及显示装置产品性能的目的。
需要说明的是，所述公共电极层 19的图案还可以全部覆盖所述衬底基板 11 , 这样可以减少一次构图工艺， 但会增加一些不必要的寄生电容。 因此， 优选地，所述公共电极层 19的图案部分覆盖所述衬底基板，并且在所述衬底 基板 11上的水平投影区域分别与像素电极层 18在所述衬底基板 11上的水平 投影区域以及半导体层 13在所述衬底基板 11上的水平投影区域存在重叠。
步骤 102: 在所述公共电极层 19上形成緩沖层 12, 可如图 2 ( b )所示。 例如，在本发明所述实施例中，可采用 CVD( Chemical Vapor Deposition, 化学气相沉积）等方法在所述公共电极层 19上沉积緩沖层 12; 进一步地， 所述緩沖层 12 可以为氮化硅薄膜层和氧化硅薄膜层所组成的双层绝缘层结 构， 也可以为氮化硅薄膜层或氧化硅薄膜层等单层绝缘层结构， 本发明实施 例对此不作任何限定。
步骤 103: 在所述緩沖层 12上形成半导体层 13, 可如图 2 ( c )所示。 例如， 所述半导体层 13 可为多晶硅层或非多晶硅层； 当所述半导体层
13为多晶硅层时，可采用 CVD等方法在所述緩沖层 12上沉积非晶硅层， 并 采用准分子激光退火（ELA )或固相结晶 （SPC )等方法将所述非晶硅晶化 为多晶硅， 之后， 再通过包括光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离 等工艺的构图工艺形成所需的多晶硅图案。
步骤 104: 在所述半导体层 13上形成栅极绝缘层 14, 可如图 2 ( d )所 示。
例如， 可采用 CVD等方法在所述半导体层 13上沉积栅极绝缘层 14; 进 一步地，所述栅极绝缘层 14可为氧化硅层、氮化硅层或由氧化硅层和氮化硅 层所组成的复合绝缘层等， 本发明实施例对此不作任何限定。
步骤 105: 在所述栅极绝缘层 14上形成栅金属层 15, 可如图 2 ( e )所 例如， 所述栅金属层 15可包括栅极、栅线与公共电极线的图案， 本发明 实施例对此不作赘述； 并且， 在所述栅极绝缘层 14上形成栅金属层 15时， 可采用 PVD ( Physical Vapor Deposition, 物理气相沉积）等方法在所述栅极 绝缘层 14上形成一金属层， 并通过包括光刻胶涂敷、 曝光、 显影、 刻蚀、 光 刻胶剥离等工艺的构图工艺在所述栅极绝缘层 14上一次形成栅极、栅线与公 共电极线的图案。
例如， 所述金属层可以为铝层、 钨层、 铬层或其他金属及金属化合物导 电层等， 本发明实施例对此不作任何限定。
步骤 106: 在所述栅金属层 15上形成层间介电层 16, 可如图 2 ( f )所 示。
例如，可采用 CVD等方法在所述栅金属层 15上沉积所述层间介电层 16 , 以起到保护所述栅金属层 15、 并隔离所述栅金属层 15和后续源漏金属层 17 的目的； 所述层间介电层 16可由氧化硅、 氮化硅等材料制备而成， 本发明实 施例对此不作任何限定。
步骤 107: 在所述层间介电层 16及所述栅极绝缘层 14之内形成贯通至 所述半导体层 13的源极过孔与漏极过孔， 可如图 2 ( g )所示。
例如，可采用一次或多次构图工艺在所述层间介电层 16及所述栅极绝缘 层 14之内形成可直达所述半导体层 13的源极过孔 161、漏极过孔 162,本发 明实施例对此不作任何限定。
步骤 108:在所述源极过孔 161、漏极过孔 162内以及具备所述源极过孔 161、 漏极过孔 162的层间介电层 16上形成包括源极 171、 漏极 172的源漏 金属层 17, 可如图 2 ( h )所示。
例如， 在本步骤 108中， 可在具备源极过孔 161以及漏极过孔 162的层 间介电层 16表面沉积一导电材料， 并通过包括光刻胶涂敷、 曝光、 显影、 刻 蚀、 光刻胶剥离等工艺的构图工艺来形成包括所述源极 171、 漏极 172的源 漏金属层 17。
例如， 所述导电材料可以为铝、 钨、 铬或其他金属及金属化合物等， 本 发明实施例对此不作任何限定。
需要说明的是， 由于所述源漏金属层 17通常可包括源极、漏极和数据线 的图案， 因此， 在本步骤 108中， 在形成源极 171、 漏极 172的同时， 还可 以同时形成数据线（Data ) , 本发明实施例对此不作赘述。
步骤 109: 在所述源漏金属层 17上形成像素电极层 18, 可如图 2 ( i ) 所示。
例如， 可采用 CVD等方法在所述源漏金属层 17上沉积一透明导电材料 层， 并通过包括光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺的构图 工艺来得到具备设定图案的像素电极层 18。
需要说明的是， 所得到的像素电极层 18通常可与所述源漏金属层 17中 的漏极 172电连接， 本发明实施例对此不再进行赘述。
也就是说， 经过上述步骤 101〜步骤 109之后， 可得到本发明实施例中所 述的阵列基板。 所得到的阵列基板的平面结构示意图可如图 3所示。 在图 3 中， 为了图示清楚， 各层结构均是透明或半透明的样式。 如图 3所示， 栅线 100和数据线 200彼此交叉定义了多个像素单元， 每个像素单元包括薄膜晶 体管、 像素电极层 18、 公共电极层 19等， 每个薄膜晶体管包括栅极、 半导 体层、 源极和漏极等， 例如栅极为栅线 100的一部分，像素电极层 18中的像 素电极为梳状电极。 在每个像素单元中， 所述公共电极层 ( Vcom ) 19 除了 可以位于所述像素电极层 18之下外， 还可扩大范围至所述像素电极层 18一 侧的半导体层 13之下，从而使得所述公共电极层 19不仅可与像素电极层 18 形成存储电容，还可与半导体层 13形成存储电容，在达到筒化阵列基板制作 工艺、 膜层结构的基础上， 还达到了增大阵列基板的存储电容、 提高阵列基 板及显示装置产品性能的目的。
本实施例一提供的阵列基板及其制备方法中， 所述阵列基板包括衬底基 板、 依次形成在所述衬底基板上的緩沖层、 半导体层、 栅极绝缘层、 栅金属 层、 层间介电层、 源漏金属层以及像素电极层， 还包括： 形成在所述衬底基 板与所述緩沖层之间的公共电极层。 由于在形成緩沖层之前， 在衬底基板上 形成公共电极层， 该公共电极层不仅可与像素电极层形成存储电容， 还可与 半导体层形成存储电容， 起到了增大阵列基板的存储电容、 提高阵列基板的 像素电压保持率以及降低显示装置的闪烁等不良现象的效果， 提高了阵列基 板及显示装置的品质； 另外， 所述制备方法与现有技术相比， 由于还可省去 后续保护层及钝化层等工艺流程， 从而还可达到筒化阵列基板的膜层结构以 及制作工艺的效果。
需要说明的是，本发明实施例均以半导体层为多晶硅层的顶栅型 TFT为 例进行说明， 对于半导体层为非晶硅层等的 TFT, 本发明实施例同样适用， 且对于底栅型 TFT或者其他结构变形的 TFT,只要需要通过增加正对面积而 增大存储电容的方案， 也都属于本发明实施例的保护范围。
实施例二
本发明实施例二提供了一种显示装置， 所述显示装置可以为液晶显示面 板、 电子纸、 OLED ( Organic Light-Emitting Diode, 有机发光二极管）面板、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何 具备显示功能的产品或部件， 本发明实施例对此不作任何限定。 所述显示装 置包括本发明实施例一中所述的阵列基板， 本发明实施例二对此不再赘述。
需要说明的是， 本发明实施例中所述的显示装置可以为 TN ( Twisted Nematic, 扭曲向列 )模式、 VA ( Vertical Alignment, 垂直取向）模式、 IPS ( In-Plane Switching,平面转换技术 )模式或 ADS( Advanced Super Dimension Switch, 高级超维场转换技术）模式， 本发明实施例对此不作任何限定； 较 优地， 本发明实施例中所述的显示装置尤其适用于 IPS模式和 ADS模式。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种阵列基板，包括衬底基板、依次形成在所述衬底基板上的緩沖层、 半导体层、 栅极绝缘层、 栅金属层、 层间介电层、 源漏金属层以及像素电极 层， 以及形成在所述衬底基板与所述緩沖层之间的公共电极层。
2、如权利要求 1所述的阵列基板， 其中， 所述公共电极层在所述衬底基 板上的水平投影区域分别与所述像素电极层在所述衬底基板上的水平投影区 域以及所述半导体层在所述衬底基板上的水平投影区域存在重叠。
3、如权利要求 1或 2所述的阵列基板，其中，所述半导体层为多晶硅层。
4、 如权利要求 1-3任一所述的阵列基板， 其中， 所述源漏金属层包括源 极、 漏极和数据线的图案， 所述层间介电层以及栅极绝缘层内形成有分别用 于将所述源极、 漏极与所述半导体层电连接的源极过孔以及漏极过孔。
5、 如权利要求 1-4任一所述的阵列基板， 其中， 所述公共电极层由透明 导电材料制备而成。
6、如权利要求 5所述的阵列基板，其中，所述透明导电材料为氧化锡铟。
7、 一种显示装置， 包括权利要求 1-6任一所述的阵列基板。
8、 一种阵列基板制备方法， 包括：
在衬底基板上形成公共电极层；
在所述公共电极层上依次形成緩沖层、 半导体层、 栅极绝缘层、 栅金属 层、 层间介电层、 源漏金属层以及像素电极层。
9、如权利要求 8所述的阵列基板制备方法， 其中， 所述公共电极层在所 述衬底基板上的水平投影区域分别与所述像素电极层在所述衬底基板上的水 平投影区域以及所述半导体层在所述衬底基板上的水平投影区域存在重叠。
10、 如权利要求 8或 9所述的阵列基板制备方法， 其中， 所述半导体层 为多晶娃层。
11、 如权利要求 8-10任一所述的阵列基板制备方法， 其中， 所述源漏金 属层包括源极、 漏极和数据线的图案； 在形成所述层间介电层之后， 且在形 成所述源漏金属层之前， 所述方法还包括：
在所述层间介电层以及所述栅极绝缘层内形成分别用于将所述源极、 漏 极与所述半导体层电连接的源极过孔以及漏极过孔。
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