WO2015038328A1 - Accessing memory cells in parallel in a cross-point array - Google Patents

Accessing memory cells in parallel in a cross-point array Download PDF

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Publication number
WO2015038328A1
WO2015038328A1 PCT/US2014/052763 US2014052763W WO2015038328A1 WO 2015038328 A1 WO2015038328 A1 WO 2015038328A1 US 2014052763 W US2014052763 W US 2014052763W WO 2015038328 A1 WO2015038328 A1 WO 2015038328A1
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WIPO (PCT)
Prior art keywords
bias
memory
memory cell
cells
access
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PCT/US2014/052763
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English (en)
French (fr)
Inventor
Hernan Castro
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Micron Technology, Inc.
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Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to KR1020187022949A priority Critical patent/KR20180093104A/ko
Priority to CN201480049464.XA priority patent/CN105518789B/zh
Priority to EP14844632.1A priority patent/EP3044795B1/en
Priority to SG11201601195PA priority patent/SG11201601195PA/en
Priority to JP2016540276A priority patent/JP6201056B2/ja
Priority to KR1020197012214A priority patent/KR102349354B1/ko
Priority to KR1020167006101A priority patent/KR101890498B1/ko
Publication of WO2015038328A1 publication Critical patent/WO2015038328A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0061—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0097—Erasing, e.g. resetting, circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0088—Write with the simultaneous writing of a plurality of cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Definitions

  • FIG. 8A is a graphical illustration of voltage versus time evolution for memory cells in a cross-point array being accessed in parallel according to one embodiment.
  • phase change memory devices can be nonvolatile; i.e., physical and electrical states of the memory devices do not change substantially over a retention time (e.g., longer than one year) without any external power supplied thereto.
  • some phase change memory devices can provide fast read and write access time (e.g., faster than 10 nanoseconds) and/or high read and write access bandwidth (e.g., greater than 100 megabits per second).
  • some phase change memory device can be arranged in a very high density memory array, e.g., a cross-point array having greater than 1 million cells in the smallest memory array unit connected with local metallization. Chalcogenide materials can also be employed in ovonic threshold switch (OTS) devices that can also be used in memory arrays, and in particular in phase change memory cells as selector elements in series with phase change storage elements.
  • OTS ovonic threshold switch
  • OTS materials include Te-As-Ge-Si, Ge- Te-Pb, Ge-Se-Te, Al-As-Te, Se-As-Ge-Si, Se-As-Ge-C, Se-Te-Ge-Si, Ge-Sb-Te-Se, Ge-Bi- Te-Se, Ge-As-Sb-Se, Ge-As-Bi-Te, and Ge-As-Bi-Se, among others.
  • each one of the memory cells disposed at an intersection formed by any one of columns 20 and any one of rows 22 may be accessed by an access operation.
  • an access operation may refer to a write access operation, an erase access operation, or a read access operation.
  • a write access operation which for a phase change memory can also be referred to as a program operation or a RESET operation, changes the resistance state of the memory cell from a relatively low resistance state to a relatively high resistance state.
  • an erase operation which for a phase change memory can also be referred to as a SET operation, changes the resistance state of the memory cell from a relatively high resistance state to a relatively low resistance state.
  • RESET RESET
  • SET RESET
  • SET program or write operation
  • the target cell 52 can be accessed while inhibiting (i.e., preventing) the remaining cells from getting accessed.
  • This can be achieved, for example, by applying bias of VACCESS across the target cell 52 while applying biases substantially lower than VACCESS across the rest of the cells.
  • VCOL SEL can be applied to a selected column (20-n in this example) while applying VROW SEL to a selected row (22-m in this example).
  • a bias VCOL INHIBIT is applied across all remaining columns and a bias VROW INHIBIT is applied across all remaining rows. Under this configuration, when the bias between VCOL SEL and VROW SEL exceeds VACCESS, the target cell 52 can be accessed.
  • the phase change event can be a crystalline -to-amorphous transition which can occur in the storage node as a result of a RESET current IRESET flowing through the thresholded memory cell (or through an adjacent heater) that is sufficient to induce the crystalline -to-amorphous transition.
  • the resulting change in the resistance of the chalcogenide material can be from an LRS to a HRS.
  • FIG. 3 schematically illustrates a graph 60 illustrating current-voltage (I- V) curves of a memory cell incorporating a chalcogenide material undergoing access operations according to one embodiment.
  • the graph 60 illustrates an HRS I-V curve 70 of a phase change memory cell undergoing a RESET access operation and an LRS I-V curve 90 of a phase change memory cell undergoing a SET access operation.
  • the voltage drop across the memory cell in the HRS I-V curve 70 and the LRS I-V curve 90 can represent combined voltage drops across the storage node in the HRS state and the selector node, and across the storage node in the LRS state and the selector node, respectively.
  • the x-axis represents a bias applied across a phase change memory cell disposed between first and second electrodes and the y-axis represents the current measured in log scale across the phase change memory cell.
  • the HRS threshold region 74 is followed by a HRS snap back region 76 characterized by a rapid reduction in the bias across the memory cell, and the slope of the HRS I-V curve 70 has a negative value (i.e., the differential resistance is negative).
  • the HRS snap back region 76 is followed by a HRS hold region 78 at a voltage of about VH.
  • the HRS hold region 78 is followed by a HRS cell access region 80 at a voltage of about Vc RESET- Between the HRS hold region 78 and the HRS cell access region 80, the HRS I-V curve 70 has a very steep positive slope, which can exceed several decades of change in current over a fraction of a volt.
  • the access biases are less than about one half of the first and second threshold biases in magnitude. In another embodiment, the access biases are less than about one third of the first and second threshold biases in magnitude.
  • a particular value of the access bias may be chosen to be a convenient level that may already be available or desirable for the subsequent operation. [0053] In some embodiments, in both “capture and hold” and “capture and release” methods, mixed access operations are possible.
  • the voltage levels of inhibited columns 262a, 262c, and 262d and the voltage levels of inhibited rows 266a, 266b, and 266d are maintained at VCO L I N H and V R OW I N H , respectively.
  • the T cell bias 146 is applied across the target cell 270a.
  • the "capture and release" method of accessing memory cells in parallel further includes returning the second selected column 262c to the column inhibit voltage level V COL INH as illustrated in FIG. 7A by the falling edge of the second selected column voltage-time (V-T) curve 216b, and returning the selected row 266b to the row inhibit voltage level V ROW INH as illustrated in FIG. 7A by the falling (in absolute value of the magnitude) edge of the selected row voltage- time (V-T) curve 220b.
  • all cells are returned to having a C cell bias as illustrated in the cross-point array 240 in FIG. 7C.
  • the plurality of memory cells to be accessed include the Ti cell 270a and the T 2 cell 270b. These two target cells 270a, 270b do not share access lines, that is, are on adjacent row and column lines, such that they can be considered "diagonally" removed from one another. Because the two target cells 270a and 270b do not share access lines, the Ti cell 270a "sees" a C cell bias when T 2 cell 270b is being selected, and vice versa. This approach minimizes the impact of the previously selected cells when the subsequent cells are being accessed.
  • SET-accessing the plurality of memory cells 270a and 270b can additionally include increasing the voltage levels of the first and second selected columns 262b and 262c to VCO L A CC E SS (not shown).
  • Inhibiting A', B' and C cells in SET-accessing are similar to inhibiting A, B, and C cells in thresholding A, B, and C cells, except that the inhibit voltages applied to inhibited columns and rows are proportionally lower compared to the lowered V TH value as a result of thresholding the target cells.
  • accessing target cells 270a and 270b by providing an access bias to the target cells can result in the same access bias resulting across non-target cells T' adjacent the target cells 270a and 270b. While T cell receive the same bias compared to Ti and T 2 cells, however, unintended SET-accessing of T cells can be avoided because T cells have higher V TH compared to thresholded Ti and T 2 cells.
  • the cell access bias 160 is substantially smaller in magnitude compared to the threshold T cell bias 146, Ti and T 2 cells can be SET-accessed because the threshold voltages have been reduced in the wake of the snap back thresholding phenomenon.
  • the same cell access bias 160 is not sufficient to threshold non-target T' cells.
  • the voltage on the selected column 362b can be reduced to a column hold voltage level V COL HOLD (not shown).
  • V COL HOLD (not shown).
  • the resulting bias across the Ti cell 370a is a post-threshold target cell hold bias 164.
  • the post-threshold target cell hold bias 164 is sufficient to maintain the thresholded state of Ti cell 370a.
  • the T 2 cell 370b is selected from one of third inhibited memory (C) cells at the time the Ti cell 370a was selected for thresholding (i.e., a memory cell disposed between one of previously inhibited columns 362a, 362c, and 362d, and one of previously inhibited rows 366a, 366b, and 366d).
  • C third inhibited memory
  • the "capture and hold" method of accessing memory cells in parallel can include thresholding a suitable number of additional target cells.
  • third through Nth target memory cells T 3 -T N (not shown) can be “captured” by thresholding and “held” by applying post- threshold target cell hold bias 164.
  • the V TH of the "released" memory cell can take time to recover.
  • This behavior can be utilized in the "capture and release” method to access multiple cells in parallel by thresholding (i.e., “capturing”) multiple cells sequentially and subsequently accessing multiple cells in parallel at an access voltage lower than threshold voltages within the recovery period of the first thresholding event, or within the recovery period following a refresh event.
  • the non-thresholded cells retain their high V TH between thresholding and accessing target cells, and the access voltages of thresholded cells are substantially lower than the V TH of non-thresholded cells, the chances of unintentionally thresholding non-thresholded cells are minimized.
  • the above-described approaches of accessing multiple cells in parallel after sequentially thresholding can be particularly beneficial in a SET access operation, which can take longer (e.g., hundreds of nanoseconds to microseconds) than other access operations due to longer access bias portion (e.g.., a RESET access operation involving an amorphous to crystalline transition) in phase change memory technology.
  • a higher SET bandwidth can be achieved.

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PCT/US2014/052763 2013-09-10 2014-08-26 Accessing memory cells in parallel in a cross-point array WO2015038328A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1020187022949A KR20180093104A (ko) 2013-09-10 2014-08-26 크로스-포인트 어레이에서 병렬로 메모리 셀들을 액세스하는 방법
CN201480049464.XA CN105518789B (zh) 2013-09-10 2014-08-26 并行存取交叉点阵列中的存储器单元
EP14844632.1A EP3044795B1 (en) 2013-09-10 2014-08-26 Accessing memory cells in parallel in a cross-point array
SG11201601195PA SG11201601195PA (en) 2013-09-10 2014-08-26 Accessing memory cells in parallel in a cross-point array
JP2016540276A JP6201056B2 (ja) 2013-09-10 2014-08-26 クロスポイントアレイ内のメモリセルへの並列アクセス
KR1020197012214A KR102349354B1 (ko) 2013-09-10 2014-08-26 크로스-포인트 어레이에서 병렬로 메모리 셀들을 액세스하는 방법
KR1020167006101A KR101890498B1 (ko) 2013-09-10 2014-08-26 크로스-포인트 어레이에서 병렬로 메모리 셀들을 액세스하는 방법

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US14/023,112 US9312005B2 (en) 2013-09-10 2013-09-10 Accessing memory cells in parallel in a cross-point array
US14/023,112 2013-09-10

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US (5) US9312005B2 (zh)
EP (1) EP3044795B1 (zh)
JP (1) JP6201056B2 (zh)
KR (3) KR20180093104A (zh)
CN (2) CN109147856B (zh)
SG (1) SG11201601195PA (zh)
WO (1) WO2015038328A1 (zh)

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