WO2015035829A1 - Tft及其制作方法、阵列基板及其制作方法、x射线探测器和显示装置 - Google Patents

Tft及其制作方法、阵列基板及其制作方法、x射线探测器和显示装置 Download PDF

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WO2015035829A1
WO2015035829A1 PCT/CN2014/082411 CN2014082411W WO2015035829A1 WO 2015035829 A1 WO2015035829 A1 WO 2015035829A1 CN 2014082411 W CN2014082411 W CN 2014082411W WO 2015035829 A1 WO2015035829 A1 WO 2015035829A1
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passivation
film
layer
source
gate
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PCT/CN2014/082411
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English (en)
French (fr)
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高会朝
田宗民
李鹏
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US14/429,092 priority Critical patent/US9647019B2/en
Publication of WO2015035829A1 publication Critical patent/WO2015035829A1/zh
Priority to US15/462,105 priority patent/US10297635B2/en

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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
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    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/144—Devices controlled by radiation
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Definitions

  • TFT and manufacturing method thereof array substrate and manufacturing method thereof, X-ray detector and display device
  • Embodiments of the present invention relate to a TFT, a method of fabricating the same, an array substrate, and a method of fabricating the same,
  • the X-ray inspection devices are widely used in measurement medicine, electronics industry, aerospace industry and other fields.
  • the X-ray detecting device converts the X-ray into visible light
  • the photodiode receives the light and converts the optical signal into an electrical signal through a photovoltaic effect
  • the electrical signal is input to the control circuit of the X-ray detecting device through the switching control of the thin film transistor, thereby realizing detection Features.
  • a common X-ray detector is an X-ray detector centered on an amorphous silicon photodiode array, which includes an array substrate; the array substrate includes a thin film transistor (TFT) and a photodiode.
  • TFT thin film transistor
  • the scintillator layer or the phosphor layer of the detector converts the X-ray photons into visible light, and then converts the visible light into an electrical signal under the action of the photodiode, and the thin film transistor reads the electrical signal and outputs the electrical signal. Get the displayed image.
  • the turn-off and turn-on of the thin film transistor can separately control the storage and reading of electrical signals, so the performance of the thin film transistor is particularly important in the device.
  • the structure of a thin film transistor mainly includes a substrate, a gate, a source, a drain, a semiconductor layer (active layer), and a gate insulating layer, and a pattern of a gate, a gate insulating layer, and a semiconductor layer are sequentially formed on the substrate.
  • a source and a drain are formed on the semiconductor layer.
  • the way in which the source and drain are overlapped with the semiconductor layer is usually taken. Summary of the invention
  • Embodiments of the present invention provide a TFT and a method of fabricating the same, an array substrate and a method of fabricating the same, an X-ray detector, and a display device to reduce the number of patterning processes.
  • At least one embodiment of the present invention provides a thin film transistor including a gate, a source, a drain, and an active layer, the source and the drain being located at two of the active layers a side, and the source and the drain are in the same layer as the active layer.
  • At least one embodiment of the present invention provides a method of fabricating a thin film transistor, comprising: sequentially forming a gate insulating layer film, a semiconductor layer film, and a passivation shielding layer film; forming a pattern including a passivation shielding layer; a portion of the semiconductor layer film that is blocked by the passivation shielding layer forms a pattern of the active layer; and a portion of the semiconductor layer film that is not blocked by the passivation shielding layer is formed by an ion doping process including a source A pattern of poles and drains, the source and drain being located on opposite sides of the active layer.
  • At least one embodiment of the present invention further provides an array substrate including a substrate, a thin film transistor, a passivation layer, and a first pixel electrode.
  • the source and the drain of the thin film transistor are located on both sides of the active layer. And the source and the drain are in the same layer as the active layer, and the first pixel electrode is electrically connected to the drain.
  • At least one embodiment of the present invention provides a method for fabricating an array substrate, comprising: sequentially forming a gate insulating layer film, a semiconductor layer film, and a passivation shielding layer film; forming a pattern including a passivation shielding layer; a portion of the semiconductor layer film that is blocked by the passivation shielding layer forms a pattern of the active layer; a portion of the semiconductor layer film that is not blocked by the passivation shielding layer is formed by an ion doping process, including a source And a drain pattern, the source and the drain are located on both sides of the active layer; forming a passivation layer film to form a pattern including the first via; and forming a pixel electrode film, including forming the first a pattern of the pixel electrode, wherein the first pixel electrode is electrically connected to the drain through the first via.
  • At least one embodiment of the present invention provides an X-ray detector comprising the above-described thin film transistor or array substrate.
  • At least one embodiment of the present invention provides a display device comprising the above-described thin film transistor or array substrate.
  • FIG. 1 is a schematic flow chart of a method for fabricating a thin film transistor according to a second embodiment of the present invention
  • FIG. 2 is a schematic flowchart of a method for fabricating an array substrate according to Embodiment 4 of the present invention
  • FIG. 4 is a schematic structural diagram of a method for fabricating an array substrate according to Embodiment 4 of the present invention
  • FIG. 5 is a schematic structural diagram of an array substrate according to a sixth embodiment of the present invention.
  • the inventors of the present application have noticed that when the thin film transistor uses a source and a drain to overlap the active layer in the array substrate, the source, the drain and the active layer need to be fabricated by two patterning processes. This increases the number of patterning processes; and the positive facing area between the gate and the source and the drain is relatively large, which results in a large coupling capacitance between the gate and the source and the drain, thereby affecting the film. The performance of the transistor.
  • the manufacturing method thereof, the array substrate, the manufacturing method thereof, and the X-ray detector, the source, the drain, and the active layer are all formed on the same semiconductor layer film, so that the source and the drain are The pole is on the same layer as the active layer.
  • the patterns of the source, the drain, and the active layer are formed by one patterning process, which can reduce the number of patterning processes; and, since the source, the drain, and the active layer are disposed in the same layer, the layers are set differently than the three layers.
  • the active layer has the same width in the connection direction of the source and the drain
  • the opposing areas of the source, the drain and the gate are reduced, so that the coupling between the source, the drain and the gate
  • the capacitance is reduced, thereby improving the performance of the thin film transistor.
  • the present embodiment provides a thin film transistor including a gate, a source, a drain, an active layer, and a gate insulating layer, the source and the drain are located on both sides of the active layer, and the source and the drain are The active layers are on the same layer.
  • the bottom gate is taken as an example, and the gate is located below the active layer; of course, the embodiment of the present invention may also adopt the structure of the top gate, that is, the gate is located above the active layer, and the specific structure is not described herein again.
  • the present embodiment provides a thin film transistor including: a gate 2a', a source 4c', a drain 4b', an active layer 4a', and a gate insulating layer 3', a source 4c' and a drain 4b. ' is located on both sides of the active layer 4a' and is on the same layer as the active layer.
  • the patterns of the source, drain, and active layers are formed by a single patterning process (and thus are monolithic), which reduces the number of patterning processes, and There is only a gate insulating layer 3' between the source 4c', the drain 4b' and the gate 2a', and there is no semiconductor layer as an active layer, and a gate insulating layer is present between the source drain and the gate.
  • the structure of the semiconductor layer can reduce the dielectric constant between the source 4c', the drain 4c and the gate 2a', and reduce the coupling capacitance between the source, the drain and the gate, and improve the structure of the semiconductor layer.
  • the performance of thin film transistors can reduce the dielectric constant between the source 4c', the drain 4c and the gate 2a', and reduce the coupling capacitance between the source, the drain and the gate, and improve the structure of the semiconductor layer.
  • the source 4c', the drain 4b', and the active layer 4a' is disposed in the same layer, and the opposing area of the source 4c', the drain 4b' and the gate 2a' is reduced, which also reduces the coupling between the source, the drain and the gate. Capacitance, improving the performance of thin film transistors.
  • the width of the active layer 4a' and the width of the gate 2a' may be made uniform in the wiring direction of the source and the drain, In this way, there is no facing area between the source 4c' and the drain 4b' and the gate 2a', thereby further reducing the coupling capacitance between the source drain and the gate.
  • the source, the drain and the gate there is no semiconductor layer between the source, the drain and the gate such that the distance between them is reduced.
  • the change in the distance also causes a change in the capacitance between the two poles, but in spite of the fact, in the embodiment of the present invention, since the thickness of the thin film forming the semiconductor layer is extremely thin, the source, the drain and the gate are The distance between the electrodes is also very small, so that the influence on the coupling capacitance between the source, the drain and the gate is extremely small or negligible.
  • the present embodiment provides a method for fabricating a thin film transistor according to the first embodiment, comprising: sequentially forming a semiconductor layer film and a passivation shielding layer film; forming a pattern including a passivation shielding layer by a patterning process to form a semiconductor layer A portion of the film that is blocked by the passivation barrier layer forms a pattern of the active layer; and a portion of the semiconductor layer film that is not blocked by the passivation mask layer is formed by, for example, an ion doping process to form a pattern including a source and a drain.
  • the bottom gate is taken as an example, and the gate is located below the active layer.
  • the embodiment of the present invention may also adopt the structure of the top gate, that is, the gate is located above the active layer, and the specific structure is not described herein again.
  • the embodiment provides a method for fabricating the thin film transistor structure, including the following steps:
  • a gate metal film is formed on the substrate 1', and a pattern including the gate electrode 2a' is formed by a patterning process.
  • the formation of a thin film usually has various methods such as deposition, coating, sputtering, etc., and the patterning process usually includes photolithography. Glue coating, exposure, development, etching, photoresist stripping, etc.
  • a gate metal film may be deposited on the substrate by sputtering or thermal evaporation, and the substrate may be a transparent glass substrate or a quartz substrate.
  • the gate metal film may be a metal such as Cr, W, Ti, Ta, Mo, Al, or Cu or an alloy thereof.
  • the gate metal film may be composed of a plurality of metal thin films, which is not limited herein.
  • a photoresist is coated on the gate metal film, and exposed by a common mask, and a fully exposed region and a completely unexposed region are formed on the substrate V; the photoresist in the fully exposed region is removed by development, so that The gate metal film in the fully exposed area is exposed and remains in the photoresist in the completely unexposed areas.
  • the gate metal film exposed in the completely exposed region is removed by an etching process, and the photoresist in the completely unexposed region is removed by a lift-off process, and the exposed gate metal film is formed to include the gate 2a as shown in FIG. 4a. ', the graph of the grid line (not shown). At this time, for example, the gate line and the gate are integrally formed.
  • a gate insulating film and an amorphous silicon film are deposited on the substrate 1' on which the gate 2a' is formed.
  • the gate insulating film may be an oxide, a nitride or an oxynitride such as silicon dioxide or silicon nitride.
  • a-si can be used for the crystalline silicon film.
  • the amorphous silicon film is subjected to laser irradiation by a laser irradiation process to convert the amorphous silicon film into a polysilicon film, and the polysilicon film forms a semiconductor layer film required for this step.
  • the semiconductor layer film is deposited by amorphous silicon.
  • the film is formed by a laser irradiation of a polysilicon film, which can be used for forming the active layer 4a' and ion doping the polysilicon film.
  • high temperature polysilicon can be formed by using a high temperature oxidation process of laser annealing to form amorphous silicon.
  • the temperature of this process usually exceeds 1000 ° C.
  • the glass substrate is softened and melted at a high temperature. Therefore, in order to ensure that the substrate can withstand such a high temperature, the substrate is selected from a quartz substrate.
  • a low-temperature irradiation process may be employed, in which an excimer laser is used as a heat source, and after the laser passes through the transmission system, a laser beam having a uniform energy distribution is generated and irradiated on the amorphous silicon film to convert amorphous silicon into Low temperature polysilicon.
  • low-temperature polysilicon has many advantages such as fast electron migration rate, smaller film circuit area, high resolution, simple structure, and stable performance.
  • the latter embodiment low temperature illumination process is used in the embodiments of the present invention.
  • the passivation barrier film may be selected from oxides, nitrides or oxynitrides such as silicon dioxide or silicon nitride.
  • a pattern including the active layer 4' and the passivation mask layer 5' may be formed by a patterning process such that the passivation mask layer is formed in the semiconductor layer 4'.
  • the 5' occluded portion forms a pattern of the active layer 4a', and the other unoccluded portions are identical to the source 4c, the drain 4b', and the data line.
  • the formation of the semiconductor layer 4' including the active layer 4a', the source 4c', the drain 4b', the pattern of the data lines
  • the pattern of the passivation mask layer 5' will be specifically described.
  • a photoresist 9' is coated on the passivation mask layer 5', and exposed using, for example, a two-tone mask, so that the area corresponding to the active layer 4a' on the substrate 1' is completely
  • the unexposed area, the area corresponding to the pattern of the source 4c' and the drain 4b' is a partially exposed area, and the remaining area is a fully exposed area, and the photoresist of the fully exposed area is removed by development, and the completely unexposed area is retained.
  • the passivation shielding film, the semiconductor layer film of the fully exposed region, the partially exposed region (not etched), and the passivation shielding film of the thin film semiconductor layer and the gate insulating layer in the completely unexposed region are removed by an etching process.
  • a thin film which in turn can form a pattern of the semiconductor layer 4' and the gate insulating layer 3', and a pattern of the formed semiconductor layer and a data layer pattern of the active layer 4a', the source 4c', the drain 4b', and the data line the same.
  • the photoresist ⁇ of the partially exposed region is removed by an ashing process to expose the passivation barrier film in the region to form the state shown in Fig. 4e.
  • the passivation shielding film exposed in the partially exposed region is removed by an etching process, and the semiconductor layer in the region is left and exposed, and the exposed semiconductor layer has the same pattern as the source 4c', the drain 4b' and the data line.
  • the pattern of the source 4c', the drain 4b', and the data line is pre-formed so that the exposed semiconductor layer forms a conductor after performing the ion doping process described below.
  • the photoresist 9' in the completely unexposed area is peeled off, and the exposed passivation mask film forms the passivation mask layer 5', and the semiconductor layer remaining in the region and not exposed is the same as the active layer pattern, and The state shown in Fig. 4f is formed.
  • the above-described passivation shielding layer 5' is opposed to the gate electrode 2a' so that the portion of the semiconductor layer film which is blocked by the passivation layer forms the active layer 4a'.
  • the width of the active layer 4a' may be the same as the width of the gate 2a' (such as the width w shown in FIG. 4g), so that there is no direct relationship between the source 4c', the drain 4b' and the gate 2a'.
  • the area can further reduce the coupling capacitance between the source, the drain and the gate, and improve the performance of the thin film transistor.
  • the ion doping process used in step S13 may be doped by chemical deposition, diffusion doping, or ion implantation.
  • doping is performed by ion implantation.
  • ion implantation is performed on a portion of the polysilicon layer (semiconductor layer) that is not blocked by the passivation mask layer 5' by the ion implantation device.
  • the higher the ion concentration of the implant the better the performance of the source 4c, the drain 4b', and the conductor formed by the data line, and the better the ohmic contact with the active layer 4a'.
  • the ion concentration of the implant is not as high as possible, and it is also required to be set according to the actual fabrication method and use of the thin film transistor, which is not specifically limited in the present invention.
  • the source 4c', the drain 4b', and the active layer 4a' are formed on the same semiconductor layer film such that the source 4c' and the drain 4b' are in the same layer as the active layer 4a'.
  • the gate insulating layer 3' exists between the source 4c', the drain 4b' and the gate 2a' without the semiconductor layer.
  • the embodiment of the invention can reduce the dielectric constant between the source, the drain and the gate, and reduce the source and drain.
  • the coupling capacitance between the gates improves the performance of the thin film transistor.
  • the above steps can realize the fabrication of the gate insulating layer, the active layer, the source, the drain, the data line and the passivation occlusion layer pattern by one patterning process, which is beneficial to reduce the patterning process in the manufacturing process. Quantity.
  • the method for fabricating the thin film transistor provided by the embodiment of the present invention can reduce the number of patterning processes and improve the performance of the fabricated thin film transistor.
  • the thin film transistor provided by the embodiment of the present invention can be applied to an array substrate in a display, and can also be applied to an array substrate (or can be referred to as a detection substrate) in an X-ray detector. Accordingly, the embodiment of the present invention
  • the provided method of manufacturing the thin film transistor can be applied not only to the display In the fabrication process of the array substrate, it can also be applied to the fabrication process of the array substrate in the X-ray detector.
  • the structure and fabrication method of the two types of array substrates will be separately described as an example.
  • the embodiment provides an array substrate, the array substrate includes a substrate, a thin film transistor, a passivation layer, and a first pixel electrode, wherein the source and the drain of the thin film transistor are located at two sides of the active layer, and the The source and the drain are in the same layer as the active layer, and the first pixel electrode is electrically connected to the drain.
  • the bottom gate is taken as an example, and the gate is located below the active layer.
  • the embodiment of the present invention may also adopt the structure of the top gate. Regarding the structure of the top gate, the gate is located above the active layer, and the specific structure is This will not be repeated here.
  • the present embodiment provides an array substrate including a substrate 1', a gate 2a', a source 4c', a drain 4b', an active layer 4a', and a gate insulating layer 3', and is passivated.
  • a layer 6', a first pixel electrode 7', the source 4c', the drain 4b' are located on both sides of the active layer 4a', and are in the same layer as the active layer 4a', source
  • the pole 4c' is electrically connected to the first pixel electrode 7'.
  • the pattern of the source 4c, the drain 4b' and the active layer 4a' is formed by one patterning process, which reduces the number of patterning processes and reduces the manufacturing cost.
  • the dielectric constant between the source, the drain, and the gate can be reduced, and the source, the drain, and the gate are reduced, compared to the structure in which the gate insulating layer and the semiconductor layer are present between the source drain and the gate.
  • the coupling capacitance between them improves the performance of the thin film transistor.
  • the source, the drain, and the active are provided.
  • the layer-to-layer setting reduces the area facing the gate compared to the different layer settings, which also reduces the coupling capacitance between the source, drain and gate, and improves the performance of the thin film transistor.
  • the width of the active layer 4a' and the width of the gate 2a' may be made uniform, which may cause the source and the drain to There is no opposing area between the gates, which further reduces the coupling capacitance between the source drain and the gate.
  • Embodiment 4 provides a method for fabricating an array substrate according to the third embodiment, comprising: sequentially forming a semiconductor layer film and a passivation shielding layer film; forming a pattern including a passivation shielding layer by a patterning process to make the semiconductor a portion of the layer film that is blocked by the passivation mask layer forms a pattern of the active layer; a portion of the semiconductor layer film that is not blocked by the passivation mask layer is formed by an ion doping process to form a pattern including a source and a drain, the source a drain and the drain are located on both sides of the active layer; forming a passivation layer film, forming a pattern including the first via hole by a patterning process; forming a pixel electrode film, forming a pattern including the first pixel electrode by a patterning process And electrically connecting the first pixel electrode to the drain through the first via.
  • the bottom gate is taken as an example, and the gate is located below the active layer.
  • the embodiment of the present invention may also adopt the structure of the top gate. Regarding the structure of the top gate, the gate is located above the active layer, and the specific structure is This will not be repeated here.
  • the embodiment provides a method for fabricating the array substrate, which includes the following steps:
  • Step S20 - step S23 can refer to step S10 - step S13 in the second embodiment, corresponding drawings
  • the marking of the photoresist is 16, which will not be repeatedly described in this embodiment.
  • a passivation layer film is formed, and a pattern including the first via hole 10' is formed by a patterning process.
  • a passivation layer film is applied, and a passivation layer 6' shown in Fig. 4h is formed by a patterning process and a first via hole 10' exposing a part of the source is formed on the passivation layer 6'.
  • the passivation layer film may be selected from an organic resin, an oxide, a nitride or an oxynitride such as silicon dioxide or silicon nitride.
  • a pixel electrode film Form a pixel electrode film, and form a pattern including the first pixel electrode by a patterning process, so that the first pixel electrode 7' is electrically connected to the drain electrode 4b' through the first via hole 10'.
  • a pixel electrode film is deposited on the passivation layer, and a pattern including the first pixel electrode shown in FIG. 4i is formed by a patterning process, and the first pixel electrode passes through the first via hole 10' and the drain electrode 4b'. connection.
  • the pixel electrode film may be selected from ruthenium, osmium or other transparent conductive resins, graphene films, carbon nanotube films, and the like.
  • a peripheral passivation layer film is deposited on the substrate 1' on which the first pixel electrode is formed, and a peripheral passivation layer 8' is formed by a patterning process.
  • the peripheral passivation film deposited in this step may be an oxide, a nitride or an oxynitride.
  • an array substrate such as an X-ray detector
  • the bottom gate is taken as an example, and the gate is located below the active layer.
  • the embodiment of the present invention can also use the top gate. Structure, regarding the structure of the top gate, the gate is located above the active layer, and the specific structure will not be described herein.
  • the array substrate is different from the third embodiment in that it further includes a photodiode formed on the source 4c (including an N-type amorphous silicon layer film 6, an intrinsic amorphous silicon layer film 7).
  • the scintillator layer or the phosphor layer of the detector converts the X-ray photons into visible light, and then under the action of the photodiode
  • the visible light is converted into an electrical signal
  • the thin film transistor reads the electrical signal and outputs the electrical signal to obtain a display image.
  • the detection accuracy and sensitivity of the X-ray detector can also be improved.
  • the embodiment further includes a light shielding plate 2b disposed in the same layer as the gate 2a. 2b is located directly below the photodiode, so that the unconverted light signal from the source 4c can be blocked by the light shielding plate 2b and reflected back into the photodiode to ensure that the photodiode can completely convert the optical signal.
  • the bottom gate is taken as an example, and the gate is located below the active layer.
  • the embodiment of the present invention may also adopt the structure of the top gate. Regarding the structure of the top gate, the gate is located above the active layer, and the specific structure is This will not be repeated here.
  • the embodiment provides a method for fabricating an array substrate according to the fifth embodiment, which includes the following steps:
  • a gate metal film is formed on the substrate 1, and a pattern including the gate electrode 2a and the light shielding plate 2b is formed by a patterning process.
  • This step is different from step S10 of the second embodiment or step S20 of the fourth embodiment in that the pattern of the light shielding shutter 2b is also formed together while forming the pattern of the gate electrode 2a and the gate line. 531.
  • a gate insulating layer film, a semiconductor layer film, and a passivation shielding layer film are sequentially formed.
  • a pattern including the semiconductor layer 4 and the passivation shielding layer 5 is formed by a patterning process, and a portion of the semiconductor layer film that is blocked by the passivation shielding layer 5 is formed to be active.
  • the pattern of layer 4a is formed by a patterning process, and a portion of the semiconductor layer film that is blocked by the passivation shielding layer 5 is formed to be active.
  • a portion of the semiconductor layer film that is not blocked by the passivation shielding layer 5 is formed by an ion doping process to form a pattern including the drain electrode 4b and the source electrode 4c.
  • step S31-step S33 may refer to step S11-step S13 in the second embodiment, and the embodiment does not repeat the description.
  • a multilayer film of a photodiode is sequentially formed, and a pattern of the photodiode is formed on the source 4c by a patterning process.
  • a pattern of the photodiode is formed on the source 4c by a patterning process.
  • an N-type amorphous silicon layer film 6, an intrinsic amorphous silicon layer film 7, a P-type amorphous silicon layer film 8, and a transparent conductive layer film 9 are successively deposited.
  • the transparent conductive film 9 may be made of ITO, tantalum or other transparent conductive resin, graphene film, carbon nanotube film or the like.
  • a pattern of the photodiode is formed on the source 4c by a patterning process.
  • the photodiode is located directly above the light shielding plate 2b. This is because the drain is a conductor formed by ion doping by polysilicon, and is not a metal of practical significance, so the source 4c does not well receive light received by the photodiode.
  • the signal is occluded; however, the light shielding plate 2b is formed by a metal film through an etching process, so that it can block and reflect the light signal, thereby preventing the loss of the optical signal, thereby explaining why
  • the pattern of the light shielding plate 2b is also formed at the same time as the pattern of the gate 2a and the gate line.
  • a passivation layer film is coated, and the passivation layer 10 shown in FIG. 5i is formed by a patterning process, and a first via hole 14 exposing a part of the source and a top portion exposing a portion of the photodiode are formed on the passivation layer 10.
  • the passivation layer film may be selected from an organic resin, an oxide, a nitride or an oxynitride such as silicon dioxide or silicon nitride.
  • a pixel electrode film forming a pattern including the first pixel electrode 11 and the second pixel electrode 12 by a patterning process, and electrically connecting the first pixel electrode 11 to the drain electrode 4b through the first via hole 14 and the second pixel electrode 12
  • the photodiode is electrically connected through the second via 15 .
  • a pixel electrode film is deposited on the passivation layer film, and a pattern including the first pixel electrode 11 and the second pixel electrode 12 shown in FIG. 5i is formed by a patterning process, and the first pixel electrode 11 passes through the first via hole 14
  • the drain 4b is electrically connected, and the second pixel electrode 12 is electrically connected to the photodiode through the second via 15.
  • the electrode film may be selected from ruthenium, osmium or other transparent conductive resins, graphene films, carbon nanotube films, and the like.
  • a peripheral passivation layer film is deposited on the substrate on which the first pixel electrode 11 and the second pixel electrode 12 are formed, and the peripheral passivation layer 13 is formed by a patterning process.
  • the peripheral passivation film deposited in this step may be an oxide, a nitride or an oxynitride.
  • an X-ray detector comprising the thin film transistor of any of the first embodiment or the array substrate of any of the fifth embodiments.
  • the thin film transistor or array substrate can be referred to as described above, and will not be described here.
  • a display device comprising the thin film transistor of any of the first embodiment, or the array substrate of any of the third embodiments.
  • the thin film transistor or the array substrate can be referred to the foregoing description, and details are not described herein again.

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Abstract

一种TFT及其制作方法、阵列基板及其制作方法、X射线探测器和显示装置，所述制作方法包括：依次形成栅绝缘层薄膜(3')、半导体层薄膜(4')、钝化遮挡层薄膜(5')；通过一次构图工艺形成包括钝化遮挡层的图形(5')，使所述半导体层薄膜中被所述钝化遮挡层遮挡的部分形成有源层(4a')的图形；以及通过离子掺杂工艺使所述半导体层薄膜中未被所述钝化遮挡层遮挡的部分形成包括源极(4c')和漏极(4b')的图形，所述源极(4c')和所述漏极(4b')位于所述有源层(4a')的两侧，且所述源极(4c')、所述漏极 (4b')和所述有源层(4a')位于同一层。该制作方法可以减少构图工艺的数量，并且可以提高阵列基板中薄膜晶体管的性能。

Description

TFT及其制作方法、 阵列基板及其制作方法、 X射线探测器和显示装置 技术领域
本发明的实施例涉及一种 TFT及其制作方法、 阵列基板及其制作方法、
X射线探测器和显示装置。 背景技术
X射线检测装置在测量医学、 电子工业、 宇航工业及其它领域均有广泛 应用。 X射线检测装置通过将 X射线转化为可见光， 光电二极管接收光并通 过光伏效应将光信号转换为电信号， 电信号通过薄膜晶体管的开关控制输入 到 X射线检测装置的控制电路中， 从而实现检测功能。
例如， 常见的 X射线探测器是一种以非晶硅光电二极管阵列为核心的 X 射线探测器，其包括阵列基板； 该阵列基板包括薄膜晶体管（TFT， Thin Flim Transistor )和光电二极管。 在 X射线的照射下， 探测器的闪烁体层或荧光体 层将 X射线光子转换为可见光， 然后在光电二极管的作用下将可见光转换为 电信号， 薄膜晶体管读取电信号并将电信号输出得到显示图像。 薄膜晶体管 的关闭和导通可以分别控制电信号的储存和读取， 因此薄膜晶体管的性能在 该装置中尤为重要。
一般来说， 薄膜晶体管的结构主要包括基板、 栅极、 源极、 漏极、 半导 体层（有源层）和栅绝缘层， 基板上依次形成有栅极、 栅绝缘层、 半导体层 的图形， 半导体层上形成源极、 漏极。 为了避免定位不准导致源极和漏极与 半导体层的连接不良， 通常釆取源极和漏极与半导体层进行搭接的方式。 发明内容
本发明的实施例提供了一种 TFT及其制作方法、 阵列基板及其制作方 法、 X射线探测器和显示装置， 以减少构图工艺的数量。
第一方面，本发明的至少一个实施例提供了一种薄膜晶体管， 包括栅极、 源极、 漏极、 和有源层， 所述源极和所述漏极位于所述有源层的两侧， 且所 述源极和所述漏极与所述有源层位于同一层。 第二方面，本发明的至少一个实施例提供了一种薄膜晶体管的制作方法， 包括： 依次形成栅绝缘层薄膜、 半导体层薄膜、 钝化遮挡层薄膜； 形成包括 钝化遮挡层的图形， 使所述半导体层薄膜中被所述钝化遮挡层遮挡的部分形 成有源层的图形； 以及通过离子掺杂工艺使所述半导体层薄膜中未被所述钝 化遮挡层遮挡的部分形成包括源极和漏极的图形， 所述源极和漏极位于所述 有源层的两侧。
第三方面，本发明的至少一个实施例还提供了一种阵列基板， 包括基板、 薄膜晶体管、 钝化层、 第一像素电极， 薄膜晶体管中的源极和漏极位于有源 层的两侧，且源极和漏极与有源层位于同一层，第一像素电极与漏极电连接。
第四方面， 本发明的至少一个实施例提供了一种阵列基板的制作方法， 包括:依次形成栅绝缘层薄膜、 半导体层薄膜、 钝化遮挡层薄膜； 形成包括钝 化遮挡层的图形， 使所述半导体层薄膜中被所述钝化遮挡层遮挡的部分形成 有源层的图形； 通过离子掺杂工艺使所述半导体层薄膜中未被所述钝化遮挡 层遮挡的部分形成包括源极和漏极的图形， 所述源极和所述漏极位于所述有 源层的两侧； 形成钝化层薄膜， 形成包括第一过孔的图形； 以及形成像素电 极薄膜， 形成包括第一像素电极的图形， 使所述第一像素电极通过所述第一 过孔与所述漏极电连接。
第五方面， 本发明的至少一个实施例提供了一种 X射线探测器， 包括上 述的薄膜晶体管或阵列基板。
第六方面， 本发明的至少一个实施例提供了一种显示装置， 包括上述薄 膜晶体管或阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例二提供的薄膜晶体管制作方法的流程示意图； 图 2为本发明实施例四提供的一种阵列基板制作方法的流程示意图； 图 3为本发明实施例六提供的另一种阵列基板制作方法的流程示意图； 图 4a-图 4i为本发明实施例四提供的阵列基板制作过程中的结构示意图； 图 5a-图 5i为本发明实施例六提供的阵列基板制作过程中的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有作出创造性劳动的前提 下所获得的所有其他实施例， 都属于本发明保护的范围。
本申请的发明人注意到， 在阵列基板之中薄膜晶体管釆用源极和漏极与 有源层进行搭接的方式时，源极、漏极与有源层需要釆用两次构图工艺制作， 这增加了构图工艺的数量； 并且， 栅极和源极、 漏极之间正对面积比较大， 这导致了栅极和源极、 漏极之间的耦合电容比较大， 从而影响了薄膜晶体管 的性能。
在本发明实施例提供的 TFT及其制作方法、 阵列基板及其制作方法、 X 射线探测器中， 源极、 漏极、 有源层均是在同一半导体层薄膜上形成， 使得 源极、 漏极与有源层位于同一层。 源极、 漏极以及有源层的图案是通过一次 构图工艺形成， 这样可以减少构图工艺的数量； 而且， 由于源极、 漏极与有 源层同层设置， 因此相比三者不同层设置而言， 在源极和漏极的连线方向上 有源层具有同样宽度时， 源极、 漏极与栅极的正对面积减小， 使得源极、 漏 极与栅极之间的耦合电容降低， 从而提高薄膜晶体管的性能。
实施例一
本实施例提供了一种薄膜晶体管， 包括栅极、 源极、 漏极、 有源层和栅 绝缘层， 源极和漏极位于所述有源层的两侧， 且源极和漏极与有源层位于同 一层。
本实施例以底栅为例， 栅极位于有源层的下方； 当然本发明的实施例也 可以釆用顶栅的结构， 即栅极位于有源层的上方， 具体结构在此不再赘述。 参照图 4g， 本实施例提供了一种薄膜晶体管包括： 栅极 2a' 、 源极 4c' 、 漏极 4b' 、 有源层 4a' 和栅绝缘层 3' ， 源极 4c' 、 漏极 4b' 位于有源层 4a' 的两侧且和有源层位于同一层。 源极、 漏极以及有源层的图案是通过一 次构图工艺形成（因此是一体结构的） ， 这样可以减少构图工艺的数量， 而 且源极 4c' 、 漏极 4b' 与栅极 2a' 之间只存在栅绝缘层 3' 而不存在作为有 源层的半导体层， 相比源漏极与栅极之间同时存在栅绝缘层和半导体层的结 构而言， 本发明实施例可以减小源极 4c' 、 漏极 4c与栅极 2a' 之间的介电 常数， 降低源、 漏极与栅极之间的耦合电容， 提高薄膜晶体管的性能。
另外， 在源极和漏极的连线方向上， 在具有相同宽度（即图面所示的左 右方向的距离） 的有源层的情况下， 源极 4c' 、 漏极 4b' 和有源层 4a' 同 层设置相比不同层设置而言， 源极 4c'、 漏极 4b'与栅极 2a' 的正对面积减小， 这样也可以降低源、 漏极与栅极之间的耦合电容， 提高薄膜晶体管的性能。
为了能够进一步提高薄膜晶体管的性能， 例如， 在本发明至少一个实施 例中， 在源极和漏极的连线方向上， 可以使有源层 4a' 的宽度和栅极 2a' 的 宽度一致， 这样可以使得源极 4c' 、 漏极 4b' 与栅极 2a' 之间不存在正对 面积， 进而可以进一步降低源漏极与栅极之间的耦合电容。
需要说明的是， 本发明实施中由于源极、 漏极与栅极之间没有半导体层 从而使得它们之间的距离减小。 通常情况下， 距离的变化也会引起两极之间 的电容发生变化， 但是尽管如此， 本发明的实施例中由于形成半导体层的薄 膜的厚度非常地薄， 因此源极、 漏极与栅极之间的距离变化也非常地微小， 从而对源、 漏极与栅极之间的耦合电容的影响极其小或可以忽略不计。
实施例二
本实施例提供了一种如实施例一所述的薄膜晶体管的制作方法， 包括： 依次形成半导体层薄膜、 钝化遮挡层薄膜； 通过一次构图工艺形成包括钝化 遮挡层的图形， 使半导体层薄膜中被钝化遮挡层遮挡的部分形成有源层的图 形； 再通过例如离子掺杂工艺使半导体层薄膜中未被钝化遮挡层遮挡的部分 形成包括源极和漏极的图形。
本实施例以底栅为例， 栅极位于有源层的下方； 当然本发明实施例也可 以釆用顶栅的结构， 即栅极位于有源层的上方， 具体结构在此不再赘述如图 1 所示， 根据实施例一提供的薄膜晶体管， 本实施例提供了一种制作该薄膜 晶体管结构的方法， 包括如下步骤：
S10、 参照图 4a， 在基板 1' 上形成栅极金属薄膜， 通过构图工艺形成包 括栅极 2a' 的图形。
形成薄膜通常有沉积、 涂敷、 溅射等多种方式， 构图工艺通常包括光刻 胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺。
首先， 可以釆用溅射或热蒸发的方法在基板上沉积一层栅极金属薄膜， 基板可以是透明玻璃基板也可以是石英基板。栅极金属薄膜可以使用 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu等金属及其合金， 当然， 栅极金属薄膜也可以由多层 金属薄膜组成， 本发明在此不做限定。
其次， 在栅极金属薄膜上涂覆光刻胶， 并釆用普通掩模板进行曝光， 在 基板 V 上形成完全曝光区域和完全未曝光区域； 通过显影去除完全曝光区 域内的光刻胶， 使完全曝光区域内的栅极金属薄膜露出， 并保留完全未曝光 区域内的光刻胶。
然后， 通过刻蚀工艺去除完全曝光区域内露出的栅极金属薄膜， 再通过 剥离工艺去除完全未曝光区域内的光刻胶， 露出的栅极金属薄膜形成如图 4a 所示的包括栅极 2a' 、 栅线（图中未示）的图形。 此时， 例如栅线和栅极一 体形成。
Sl l、 依次形成栅绝缘层薄膜、 半导体层薄膜、 钝化遮挡层薄膜。
首先， 在形成栅极 2a' 的基板 1' 上沉积栅绝缘层薄膜、 非晶硅薄膜， 栅绝缘层薄膜可以选用氧化物、 氮化物或者氮氧化合物， 例如二氧化硅或氮 化硅， 非晶硅薄膜例如可以选用 a-si。
接着， 通过激光照射工艺对非晶硅薄膜进行激光照射， 使非晶硅薄膜转 化为多晶硅薄膜， 该多晶硅薄膜形成本步骤所需要的半导体层薄膜。 从上述 内容可以看出， 与通常的由非晶硅薄膜和掺杂非晶硅（如 n+a-si )薄膜形成 的半导体层薄膜不同， 此处的半导体层薄膜是由沉积的非晶硅薄膜通过激光 照射形成的多晶硅薄膜， 这样能够为形成有源层 4a' ， 以及对多晶硅薄膜进 行离子掺杂工艺做铺垫。
对于上述激光照射工艺而言， 可以釆用激光退火的高温氧化工艺， 使非 晶硅形成高温多晶硅。 不过这种处理过程的温度通常会超过 1000 °C， 通常玻 璃基板会在高温下发生软化熔融，因此为了保证基板能够承受如此高的温度， 此时基板选用石英基板。 或者， 可以釆用低温照射工艺， 它以准分子激光作 为热源， 激光经过透射系统后， 会产生能量均勾分布的激光束并被照射在形 成有非晶硅薄膜上， 使非晶硅转化成为低温多晶硅。 此工艺与前者相比， 整 个处理过程可以在 200-400 °C下完成， 因此不但能够使石英基板可以承受， 而且普通的玻璃基板也可承受。 另外， 低温多晶硅具有电子迁移速率快， 薄 膜电路面积更小， 分辨率高以及结构简单、 性能稳定等诸多优点。 因此， 在 一个示例中， 本发明实施例釆用后者（低温照射工艺） 。
然后， 在沉积有多晶硅薄膜（半导体层薄膜） 的基板上沉积钝化遮挡层 薄膜。 钝化遮挡层薄膜可以选用氧化物、 氮化物或者氮氧化合物， 例如二氧 化硅或氮化硅。
S12、 通过一次构图工艺形成包括钝化遮挡层 5' 的图形， 使所述半导体 层薄膜中被所述钝化遮挡层 5' 遮挡的部分形成有源层 4a' 的图形。
参照图 4b和图 4c以及图 4f和图 4g， 可以通过一次构图工艺形成包括 有源层 4' 以及钝化遮挡层 5' 的图形， 使所述半导体层 4' 中被所述钝化遮 挡层 5'遮挡的部分形成有源层 4a'的图形，其它未被遮挡的部分与源极 4c 、 漏极 4b' 和数据线的图形相同。 这里对半导体层 4' (包括有源层 4a' 、 源 极 4c' 、 漏极 4b' 、 数据线的图形）以及钝化遮挡层 5' 的图形的形成方式 进行具体说明。
首先， 如图 4d所示， 在钝化遮挡层 5' 上涂覆光刻胶 9' ， 并使用例如 双色调掩模板进行曝光， 使基板 1' 上与有源层 4a' 对应的区域为完全未曝 光区域， 与源极 4c' 、 漏极 4b' 的图形对应的区域为部分曝光区域， 其余区 域为完全曝光区域， 再通过显影去除完全曝光区域的光刻胶， 并保留完全未 曝光区域的光刻胶、 减薄部分曝光区域的光刻胶的厚度。
然后， 通过刻蚀工艺去除完全曝光区域的钝化遮挡层薄膜、 半导体层薄 膜， 保留 （未被刻蚀）部分曝光区域和完全未曝光区域内的钝化遮挡层薄膜 半导体层薄膜、栅绝缘层薄膜，进而可以形成所述半导体层 4' 、栅绝缘层 3' 的图形， 而形成的半导体层的图形与有源层 4a' 、 源极 4c' 、 漏极 4b' 、 数据线的数据层图形相同。
接下来， 通过灰化工艺去除部分曝光区域的光刻胶 Ψ ， 露出该区域内 的钝化遮挡层薄膜， 形成图 4e所示的状态。
再通过刻蚀工艺去除部分曝光区域露出的钝化遮挡层薄膜， 保留且露出 该区域内的半导体层， 露出的半导体层与源极 4c' 、 漏极 4b' 以及数据线的 图形相同， 这样实现了源极 4c' 、 漏极 4b' 以及数据线的图形的预制作， 以 使露出的半导体层在进行下述的离子掺杂工艺后形成导体。 然后， 剥离完全未曝光区域内的光刻胶 9' ， 露出的钝化遮挡层薄膜形 成所述钝化遮挡层 5' ， 该区域内保留且未露出的半导体层与有源层图形相 同， 并形成图 4f所示的状态。
另外， 可以理解的是， 上述钝化遮挡层 5' 与栅极 2a' 相对， 才使得半 导体层薄膜中被钝化层遮挡的部分形成有源层 4a' 。 有源层 4a' 的宽度可以 与栅极 2a' 的宽度相同 （如图 4g所示的宽度 w )， 这样可以使得源极 4c' 、 漏极 4b' 与栅极 2a' 之间不存在正对面积， 进而可以进一步降低源极、 漏极 与栅极之间的耦合电容， 提高薄膜晶体管的性能。
S13、 通过离子掺杂工艺使半导体层薄膜中未被所述钝化遮挡层遮挡的 部分形成包括源极 4c' 、 漏极 4b' 以及数据线（图中未示） 的图形。
步骤 S13中釆用的离子掺杂工艺可以选用化学沉积过程掺杂、扩散掺杂、 或离子注入掺杂。 例如， 本发明实施例中釆用离子注入掺杂。 例如， 通过离 子注入设备对多晶硅层（半导体层） 中未被钝化遮挡层 5' 遮挡的部分进行 离子注入。 一般而言， 注入的离子浓度越高， 源极 4c 、 漏极 4b' 以及数据 线形成的导体的性能越好， 且与有源层 4a' 的欧姆接触越好。 但是需要强调 的是， 注入的离子浓度也并不是越高越好， 还需要根据实际的薄膜晶体管的 制作方法及使用等情况而设定， 本发明对此不作具体限定。
通过以上步骤可以知道， 源极 4c' 、 漏极 4b' 、 有源层 4a' 均是在同 一半导体层薄膜上形成， 使得源极 4c' 、 漏极 4b' 与有源层 4a' 位于同层， 这样源极 4c' 、 漏极 4b' 与栅极 2a' 之间只存在栅绝缘层 3' 而不存在半导 体层。 相比源极、 漏极与栅极之间同时存在栅绝缘层和半导体层的结构， 本 发明实施例可以减小源极、 漏极与栅极之间的介电常数， 降低源漏极与栅极 之间的耦合电容， 提高薄膜晶体管的性能。
需要强调的是， 以上步骤可以通过一次构图工艺便能够实现栅绝缘层、 有源层、 源极、 漏极、 数据线以及钝化遮挡层图形的制作， 有利于减少制作 过程中的构图工艺的数量。 另外， 本发明实施例提供的薄膜晶体管的制作方 法在能够减少构图工艺数量同时，还能够使制作出的薄膜晶体管的性能提高。
另外， 本发明实施例提供的薄膜晶体管可以应用于显示器中的阵列基板 中， 也可以应用于如 X射线探测器中的阵列基板（或可称之为探测基板） ； 相应地， 本发明实施例提供的薄膜晶体管的制作方法不仅可以适用于显示器 中的阵列基板的制作工艺中，还可以应用于如 X射线探测器中的阵列基板的 制作工艺中， 以下将以这两种类型的阵列基板的结构及制作方法为例进行分 别描述。
实施例三
本实施例提供了一种阵列基板， 该阵列基板包括基板、 薄膜晶体管、 钝 化层、 第一像素电极， 所述薄膜晶体管中的源极和漏极位于有源层的两侧， 且所述源极和所述漏极与所述有源层位于同一层， 所述第一像素电极与所述 漏极电连接。
本实施例以底栅为例， 栅极位于有源层的下方； 当然本发明实施例也可 以釆用顶栅的结构， 关于顶栅的结构是栅极位于有源层的上方， 具体结构在 此不再赘述。 如图 4i所示， 本实施例提供了一种阵列基板， 包括基板 1' 、 栅极 2a' 、 源极 4c' 、 漏极 4b' 、 有源层 4a' 和栅绝缘层 3' 、 钝化层 6' 、 第一像素电极 7' ， 所述源极 4c' 、 所述漏极 4b' 位于所述有源层 4a' 的两 侧、 且和所述有源层 4a' 位于同一层， 源极 4c' 与第一像素电极 7' 电连接。
源极 4c 、 漏极 4b' 与有源层 4a' 的图案是通过一次构图工艺形成， 减少了构图工艺的数量， 降低了制作成本。
由于源极 4c' 、 漏极 4b' 与有源层 4a' 同层设置， 因此源极 4c 、 漏 4c' 极与栅极 4a' 之间只存在栅绝缘层 3' 而不存在半导体层， 相比源漏极 与栅极之间同时存在栅绝缘层和半导体层的结构， 本发明实施例可以减小源 极、 漏极与栅极之间的介电常数， 降低源、 漏极与栅极之间的耦合电容， 提 高薄膜晶体管的性能。
另外需要说明的是， 在源极和漏极的连线方向上， 在具有相同宽度（即 图面所示的左右方向的距离） 的有源层的情况下， 源极、 漏极和有源层同层 设置相比不同层设置而言与栅极的正对面积减小， 这样也可以降低源、 漏极 与栅极之间的耦合电容， 提高薄膜晶体管的性能。
为了能够进一步提高薄膜晶体管的性能， 例如， 在源极和漏极的连线方 向上， 可以使有源层 4a' 的宽度和栅极 2a' 的宽度一致， 这可以使得源极、 漏极与栅极之间不存在正对面积， 进而可以进一步降低源漏极与栅极之间的 耦合电容。
实施例四 本实施例提供了一种如实施例三中所述的阵列基板的制作方法， 包括： 依次形成半导体层薄膜、 钝化遮挡层薄膜； 通过一次构图工艺形成包括 钝化遮挡层的图形， 使半导体层薄膜中被钝化遮挡层遮挡的部分形成有源层 的图形； 通过离子掺杂工艺使半导体层薄膜中未被钝化遮挡层遮挡的部分形 成包括源极和漏极的图形， 所述源极和所述漏极位于所述有源层的两侧； 形 成钝化层薄膜，通过构图工艺形成包括第一过孔的图形；形成像素电极薄膜， 通过构图工艺形成包括第一像素电极的图形， 使第一像素电极通过所述第一 过孔与漏极电连接。
本实施例以底栅为例， 栅极位于有源层的下方； 当然本发明实施例也可 以釆用顶栅的结构， 关于顶栅的结构是栅极位于有源层的上方， 具体结构在 此不再赘述。 如图 2所示， 根据实施例三提供的阵列基板， 本实施例提供了 一种制作该阵列基板的方法， 包括如下步骤：
S20、 在基板: T 上形成栅极金属薄膜， 通过构图工艺形成包括栅极 2a' 的图形。
S21、 依次形成栅绝缘层薄膜、 半导体层薄膜、 钝化遮挡层薄膜。
522、 通过一次构图工艺形成包括钝化遮挡层 5' 的图形， 使所述半导体 层薄膜中被所述钝化遮挡层 5' 遮挡的部分形成有源层 4a' 的图形。
523、通过离子掺杂工艺使半导体层薄膜中未被所述钝化遮挡层 5' 遮挡 的部分形成包括源极 4c' 和漏极 4b' 的图形。
步骤 S20-步骤 S23可参照实施例二中的步骤 S10-步骤 S13 , 对应的附图
5d和 5e中， 光刻胶的标记为 16， 本实施例不再对此进行重复描述。
524、 如图 4h所示， 形成钝化层薄膜， 通过构图工艺形成包括第一过孔 10' 的图形。 例如， 涂覆钝化层薄膜， 并通过构图工艺形成图 4h所示的钝化 层 6' 并在钝化层 6' 上形成露出部分源极的第一过孔 10' 。 该钝化层薄膜 可以选用有机树脂、 氧化物、 氮化物或者氮氧化合物， 例如二氧化硅或氮化 硅。
525、 形成像素电极薄膜， 通过构图工艺形成包括第一像素电极 的图 形，使所述第一像素电极 7' 通过所述第一过孔 10' 与所述漏极 4b' 电连接。 例如， 在上述钝化层上沉积像素电极薄膜， 通过构图工艺形成图 4i所示的包 括第一像素电极 的图形， 第一像素电极 通过第一过孔 10' 与漏极 4b' 连接。 像素电极薄膜可以选用 ΙΤΟ、 ΙΖΟ或其它透明的导电树脂、 石墨烯薄 膜、 碳纳米管薄膜等。
S26、 再次参照图 4i， 在形成有第一像素电极的基板 1' 上沉积外围钝化 层薄膜， 通过构图工艺形成外围钝化层 8' 。 本步骤中沉积的外围钝化层薄 膜可以选用氧化物、 氮化物或者氮氧化合物。
实施例五
本实施例中提供了一种可用于形成如 X射线探测器的阵列基板，本实施 例以底栅为例， 栅极位于有源层的下方； 当然本发明实施例也可以釆用顶栅 的结构，关于顶栅的结构是栅极位于有源层的上方，具体结构在此不再赘述。 如图 5i 所示， 该阵列基板与实施例三的不同之处在于： 还包括形成于源极 4c上的光电二极管 （包括 N型非晶硅层膜 6、 本征非晶型硅层膜 7、 P型非 晶硅层膜 8以及透明导电层 9 ) ， 这样在 X射线的照射下， 探测器的闪烁体 层或荧光体层将 X射线光子转换为可见光， 然后在光电二极管的作用下将可 见光转换为电信号， 薄膜晶体管读取电信号并将电信号输出得到显示图像， 在薄膜晶体管的性能提高的基础上，还能够提高 X射线探测器的检测精确度 和灵敏度。
由于与光电二极管连接的源极 4c为掺杂的多晶硅，可能会有未转化的光 信号透过去， 因此本实施例中还包括与栅极 2a同层设置的光线遮挡板 2b， 该光线遮挡板 2b位于光电二极管的正下方， 这样从透过源极 4c未转化的光 信号可以被光线遮挡板 2b遮挡并反射重新进入光电二极管，保证光电二极管 能够完全转化光信号。
实施例六
本实施例以底栅为例， 栅极位于有源层的下方； 当然本发明实施例也可 以釆用顶栅的结构， 关于顶栅的结构是栅极位于有源层的上方， 具体结构在 此不再赘述。 如图 3所示， 本实施例提供了一种制作如实施例五所述的阵列 基板的制作方法， 包括如下步骤：
S30、 如图 5a所示， 在基板 1上形成栅极金属薄膜， 通过构图工艺形成 包括栅极 2a、 光线遮挡板 2b的图形。 该步骤与实施例二的步骤 S10或实施 例四的步骤 S20的区别在于： 在形成栅极 2a、 栅线的图形的同时还一并形成 光线遮挡板 2b的图形。 531、 依次形成栅绝缘层薄膜、 半导体层薄膜、 钝化遮挡层薄膜。
532、 如图 5b和图 5c所示， 通过一次构图工艺形成包括半导体层 4、 钝 化遮挡层 5的图形， 使所述半导体层薄膜中被所述钝化遮挡层 5遮挡的部分 形成有源层 4a的图形。
S33、 通过离子掺杂工艺使半导体层薄膜中未被所述钝化遮挡层 5遮挡 的部分形成包括漏极 4b和源极 4c的图形。
结合图 5d-图 5g， 步骤 S31-步骤 S33可参照实施例二中的步骤 S11-步骤 S13 , 本实施例也不再对此进行重复描述。
S34、 依次形成光电二极管的多层薄膜， 通过构图工艺在所述源极 4c上 形成光电二极管的图形。 例如， 如图 5h所示， 在本步骤中， 首先， 连续沉积 N型非晶硅层膜 6、 本征非晶型硅层膜 7、 P型非晶硅层膜 8以及透明导电层 薄膜 9， 透明导电薄膜 9可以选用 ITO、 ΙΖΟ或其它透明的导电树脂、 石墨 烯薄膜、碳纳米管薄膜等。 然后， 通过构图工艺在源极 4c上形成光电二极管 的图形。光电二极管位于光线遮挡板 2b的正上方，这是由于漏极是由多晶硅 通过离子掺杂形成的导体， 而并非实际意义的金属， 因此源极 4c不能很好地 对由光电二极管接收到的光信号进行遮挡；但是此处的光线遮挡板 2b是由金 属薄膜通过刻蚀工艺形成， 因此它可以起到遮挡并反射光信号的作用， 达到 了防止光信号损失的目的， 从而也可以解释为什么要在制作栅极 2a、 栅线的 图形的同时还一并形成光线遮挡板 2b的图形。
S35、 形成钝化层薄膜， 通过构图工艺形成包括第一过孔 14和第二过孔
15的图形。 例如， 涂覆钝化层薄膜， 并通过构图工艺形成图 5i所示的钝化 层 10并在钝化层 10上形成露出部分源极的第一过孔 14和露出光电二极管的 部分上端的第二过孔 15。 该钝化层薄膜可以选用有机树脂、 氧化物、 氮化物 或者氮氧化合物， 例如二氧化硅或氮化硅。
S36、 形成像素电极薄膜， 通过构图工艺形成包括第一像素电极 11和第 二像素电极 12的图形， 使第一像素电极 11通过第一过孔 14与漏极 4b电连 接， 第二像素电极 12通过第二过孔 15与光电二极管电连接。 例如， 在上述 钝化层薄膜上沉积像素电极薄膜，通过构图工艺形成图 5i所示的包括第一像 素电极 11和第二像素电极 12的图形， 第一像素电极 11通过第一过孔 14与 漏极 4b电连接，第二像素电极 12通过第二过孔 15与光电二极管电连接。像 素电极薄膜可以选用 ΙΤΟ、 ΙΖΟ或其它透明的导电树脂、 石墨烯薄膜、 碳纳 米管薄膜等。
S37、 再次参照图 5i， 在形成有第一像素电极 11和第二像素电极 12的 基板上沉积外围钝化层薄膜， 通过构图工艺形成外围钝化层 13。 本步骤中沉 积的外围钝化层薄膜可以选用氧化物、 氮化物或者氮氧化合物。
实施例七
本实施例中还提供了一种 X射线探测器， 包括实施例一中任一形式的薄 膜晶体管或实施例五中任一形式的阵列基板。 该薄膜晶体管或阵列基板可参 照前文描述， 在此不再进行赞述。
实施例八
本实施例中还提供了一种显示装置， 包括实施例一中任一形式的薄膜晶 体管， 或实施例三中任一形式的阵列基板。 该薄膜晶体管或阵列基板可参照 前文描述， 在此不再进行赘述。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。
本申请要求于 2013年 9月 16日递交的中国专利申请第 201310420395.6 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种薄膜晶体管， 包括栅极、 源极、 漏极和有源层， 其中， 所述源极 和所述漏极位于所述有源层的两侧， 且所述源极和所述漏极与所述有源层位 于同一层。
2、根据权利要求 1所述的薄膜晶体管， 其中，在所述源极和所述漏极连 线的方向上， 所述有源层与所述栅极的宽度一致。
3、根据权利要求 1或 2所述的薄膜晶体管， 其中， 所述栅极位于所述有 源层的下方； 或者所述栅极位于所述有源层的上方。
4、 一种薄膜晶体管的制作方法， 包括：
依次形成半导体层薄膜、 钝化遮挡层薄膜；
形成包括钝化遮挡层的图形， 使所述半导体层薄膜中被所述钝化遮挡层 遮挡的部分对应于有源层图形； 以及
通过离子掺杂工艺使所述半导体层薄膜中未被所述钝化遮挡层遮挡的部 分形成包括源极和漏极的图形，
其中， 所述源极和漏极位于所述有源层的两侧。
5、根据权利要求 4所述的薄膜晶体管的制作方法， 其中， 形成包括钝化 遮挡层的图形包括：
在所述钝化遮挡层薄膜上涂覆光刻胶；
通过曝光工艺形成包括完全未曝光区域、 部分曝光区域和完全曝光区域 的光刻胶图形；
通过显影工艺去除所述完全曝光区域的所述光刻胶且保留所述完全未曝 光区域和所述部分曝光区域的所述光刻胶；
通过刻蚀工艺去除所述完全曝光区域的所述钝化遮挡层薄膜和所述半导 体层薄膜；
通过灰化工艺去除所述部分曝光区域的所述光刻胶， 露出该区域内的所 述钝化遮挡层薄膜；
通过刻蚀工艺去除所述部分曝光区域露出的所述钝化遮挡层薄膜， 保留 且露出该区域内的所述半导体层薄膜； 以及
通过剥离工艺去除所述完全未曝光区域内的所述光刻胶， 露出的所述钝 化遮挡层薄膜形成所述钝化遮挡层。
6、根据权利要求 4或 5所述的薄膜晶体管的制作方法， 其中， 在依次形 成半导体层薄膜、 钝化遮挡层薄膜之前， 所述制作方法还包括：
在基板上形成栅极金属薄膜，通过构图工艺形成包括栅极的图形，其中， 在所述源极和所述漏极连线的方向上， 所述有源层与所述栅极的宽度一致。
7、 根据权利要求 4-6中任一项所述的薄膜晶体管的制作方法， 其中， 形 成半导体层薄膜包括：
沉积非晶硅薄膜； 以及
通过激光照射工艺对所述非晶硅薄膜进行激光照射， 使所述非晶硅薄膜 转化为多晶硅薄膜， 所述多晶硅薄膜形成所述半导体层薄膜。
8、根据权利要求 7所述的薄膜晶体管的制作方法， 其中， 所述激光照射 工艺包括： 釆用激光退火的高温氧化工艺， 或者釆用准分子激光的低温照射 工艺。
9、 一种阵列基板， 包括： 基板、 薄膜晶体管、 钝化层、 第一像素电极， 其中， 所述薄膜晶体管包括栅极、 源极、 漏极和有源层， 所述源极和所述漏 极位于所述有源层的两侧， 所述源极和所述漏极与所述有源层位于同一层， 所述第一像素电极与所述漏极电连接。
10、 根据权利要求 9所述的阵列基板， 其中， 在所述源极和所述漏极连 线的方向上， 所述有源层与所述栅极的宽度一致。
11、根据权利要求 9或 10所述的阵列基板， 其中， 所述栅极位于所述有 源层的下方； 或所述栅极位于所述有源层的上方。
12、根据权利要求 9-11中任一项所述的阵列基板， 还包括光电二极管和 第二像素电极， 其中， 所述光电管二极管的一端与所述源极电连接， 所述光 电管二极管的另一端与所述第二像素电极电连接。
13、根据权利要求 12所述的阵列基板， 还包括光线遮挡板， 其中， 所述 光线遮挡板与所述栅极位于同一层， 且所述光线遮挡板位于所述光电二极管 的正下方。
14、 一种阵列基板的制作方法， 包括：
依次形成半导体层薄膜、 钝化遮挡层薄膜；
形成包括钝化遮挡层的图形， 使所述半导体层薄膜中被所述钝化遮挡层 遮挡的部分形成有源层图形；
通过离子掺杂工艺使所述半导体层薄膜中未被所述钝化遮挡层遮挡的部 分形成包括源极和漏极的图形，所述源极和所述漏极位于所述有源层的两侧； 形成钝化层薄膜， 形成包括第一过孔的图形； 以及
形成像素电极薄膜， 形成包括第一像素电极的图形， 使所述第一像素电 极通过所述第一过孔与所述漏极电连接。
15、根据权利要求 14所述的阵列基板的制作方法， 其中， 所述形成包括 钝化遮挡层的图形包括：
在所述钝化遮挡层薄膜上涂覆光刻胶；
通过曝光工艺形成包括完全未曝光区域、 部分曝光区域和完全曝光区域 的光刻胶图形； 通过显影工艺去除完全曝光区域的光刻胶且保留完全未曝光 区域和部分曝光区域的光刻胶；
通过刻蚀工艺去除所述完全曝光区域的钝化遮挡层薄膜、半导体层薄膜； 通过灰化工艺去除所述部分曝光区域的光刻胶， 露出该区域内的钝化遮 挡层薄膜；
通过刻蚀工艺去除所述部分曝光区域露出的钝化遮挡层薄膜， 保留且露 出该区域内的半导体层薄膜； 以及
通过剥离工艺去除所述完全未曝光区域内的光刻胶， 露出的钝化遮挡层 薄膜形成所述钝化遮挡层。
16、 根据权利要求 14或 15所述的阵列基板的制作方法， 其中， 在所述 依次形成半导体层薄膜、 钝化遮挡层薄膜之前， 所述制作方法还包括：
在基板上形成栅极金属薄膜，通过构图工艺形成包括栅极的图形，其中， 在所述源极和所述漏极连线的方向上， 所述有源层与所述栅极的宽度一致。
17、 根据权利要求 14-16中任一项所述的阵列基板的制作方法， 其中， 所述形成半导体层薄膜包括：
沉积非晶硅薄膜； 以及
通过激光照射工艺对所述非晶硅薄膜进行激光照射， 使所述非晶硅薄膜 转化为多晶硅薄膜， 所述多晶硅薄膜形成所述半导体层薄膜。
18、根据权利要求 17所述的阵列基板的制作方法， 其中， 所述激光照射 工艺包括： 釆用激光退火的高温氧化工艺， 或者釆用准分子激光的低温照射 工艺。
19、 根据权利要求 14-18中任一项所述的阵列基板的制作方法， 其中， 在所述形成钝化遮挡层薄膜， 通过构图工艺形成包括第一过孔的图形之前还 包括：
依次形成光电二极管的多层薄膜， 通过构图工艺在所述源极上形成光电 二极管的图形。
20、根据权利要求 19所述的阵列基板的制作方法， 其中， 所述包括栅极 的图形中还包括光线遮挡板，所述光线遮挡板位于所述光电二极管的正下方。
21、根据权利要求 19或 20中任一项所述的阵列基板的制作方法，其中， 所述包括第一过孔的图形还包括第二过孔；
所述包括第一像素电极的图形中还包括第二像素电极， 所述第二像素电 极通过所述第二过孔与所述光电二极管的一端电连接， 所述光电二极管的另 一端与所述源极电连接。
22、 一种 X射线探测器， 包括权利要求 1-3任一项所述的薄膜晶体管， 或权利要求 9-11任一项所述的阵列基板。
23、 一种显示装置， 包括权利要求 1-3任一项所述的薄膜晶体管， 或权 利要求 9-11任一项所述的阵列基板。
PCT/CN2014/082411 2013-09-16 2014-07-17 Tft及其制作方法、阵列基板及其制作方法、x射线探测器和显示装置 WO2015035829A1 (zh)

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