WO2018205596A1 - 薄膜晶体管及其制造方法、阵列基板、显示面板及显示装置 - Google Patents

薄膜晶体管及其制造方法、阵列基板、显示面板及显示装置 Download PDF

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WO2018205596A1
WO2018205596A1 PCT/CN2017/115638 CN2017115638W WO2018205596A1 WO 2018205596 A1 WO2018205596 A1 WO 2018205596A1 CN 2017115638 W CN2017115638 W CN 2017115638W WO 2018205596 A1 WO2018205596 A1 WO 2018205596A1
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pattern
insulating layer
gate insulating
target
gate
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PCT/CN2017/115638
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English (en)
French (fr)
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操彬彬
王超
孙林
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/063,743 priority Critical patent/US11417769B2/en
Publication of WO2018205596A1 publication Critical patent/WO2018205596A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/467—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present application relates to the field of display technologies, and in particular, to a thin film transistor and a method of fabricating the same, an array substrate, a display panel, and a display device.
  • the array substrate in the display device includes: a substrate substrate and a plurality of arrayed pixel units disposed on one side of the substrate substrate, each of the pixel units may include a thin film transistor, a pixel electrode, a common electrode, and a liquid crystal.
  • the thin film transistor may include a gate pattern, a gate insulating layer, an active layer pattern, and a source/drain pattern which are sequentially superposed on the base substrate.
  • the source and drain patterns are connected to the active layer pattern
  • the pixel electrode is connected to the drain of the source and drain patterns
  • the material of the gate pattern and the source and drain patterns may be metal
  • the material of the active layer pattern may be oxidized.
  • the material of the source and drain patterns and the gate pattern are metals having a strong surface reflection capability, and the light incident from the substrate substrate can be incident on the active layer under the reflection of the source and drain patterns and the gate pattern. pattern.
  • the volt-ampere characteristic curve of the active layer pattern may shift, affecting the normal operation of the thin film transistor.
  • the present application provides a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which can solve the problem that the volt-ampere characteristic curve of the active layer pattern is shifted and affects the normal operation of the thin film transistor.
  • the technical solution is as follows:
  • a thin film transistor comprising: a gate stacked in sequence a pole pattern, a gate insulating layer, an active layer pattern, a source pattern, and a drain pattern,
  • At least one surface of the surface of the source pattern facing the gate insulating layer, a surface of the drain pattern facing the gate insulating layer, and a surface of the gate pattern facing the gate insulating layer As a target surface, the target surface is capable of diffusely reflecting light incident on the target surface to prevent a portion of the light from entering the active layer pattern.
  • the source pattern includes: a first target pattern disposed on a side of the gate insulating layer away from the gate pattern, and a side of the first target pattern away from the side of the gate pattern a first electrode body pattern;
  • the drain pattern includes: a second target pattern disposed on a side of the gate insulating layer away from the gate pattern, and a second electrode body disposed on a side of the second target pattern away from the gate pattern pattern;
  • a surface of the first target pattern facing the gate insulating layer, and a surface of the second target pattern facing the gate insulating layer are the target surface, the first electrode body pattern and the first The two electrode body patterns are each connected to the active layer pattern.
  • the material of the active layer pattern is an oxide semiconductor
  • the material of the first target pattern and the material of the second target pattern are both oxide semiconductors in a reduced state.
  • the first target pattern and the second target pattern are both disposed around the active layer pattern, that is, the first target pattern and the second target pattern respectively surround both ends of the active layer pattern. And the first target pattern and the second target pattern are both not connected to the active layer pattern.
  • the gate pattern includes: a third electrode body pattern, and a third target pattern disposed on a side of the third electrode body pattern, wherein the gate insulating layer is disposed at the third target pattern away from the One side of the third electrode body pattern, and a surface of the third target pattern that is away from the third electrode body pattern is the target surface.
  • the source pattern includes: a first target pattern disposed on a side of the gate insulating layer away from the gate pattern, and a side of the first target pattern away from the side of the gate pattern a first electrode body pattern;
  • the drain pattern includes: a second target pattern disposed on a side of the gate insulating layer away from the gate pattern, and a second target pattern disposed away from the gate pattern a second electrode body pattern on the side;
  • the gate pattern includes: a third electrode body pattern, and a third target pattern disposed on one side of the third electrode body pattern, the gate insulating layer being disposed in the third a side of the target pattern away from the third electrode body pattern; a surface of the first target pattern facing the gate insulating layer, a surface of the second target pattern facing the gate insulating layer, and the first Three target pattern
  • the surface away from the third electrode body pattern is the target surface, and the first electrode body pattern and the second electrode body pattern are both connected to the active layer pattern.
  • the source pattern includes: a first target pattern disposed on a side of the gate insulating layer away from the gate pattern, and a side of the first target pattern away from the side of the gate pattern a first electrode body pattern;
  • the gate pattern includes: a third electrode body pattern, and a third target pattern disposed on a side of the third electrode body pattern, the gate insulating layer being disposed on the third target pattern a side away from the third electrode body pattern; a surface of the first target pattern facing the gate insulating layer, and a surface of the third target pattern remote from the third electrode body pattern are all a target surface, the first electrode body pattern being connected to the active layer pattern.
  • the drain pattern includes: a second target pattern disposed on a side of the gate insulating layer away from the gate pattern, and a side of the second target pattern away from the side of the gate pattern a second electrode body pattern;
  • the gate pattern includes: a third electrode body pattern, and a third target pattern disposed on one side of the third electrode body pattern, the gate insulating layer being disposed on the third target pattern a side away from the third electrode body pattern;
  • a surface of the second target pattern facing the gate insulating layer, and a surface of the third target pattern remote from the third electrode body pattern are all a target surface, each of the second electrode body patterns being connected to the active layer pattern.
  • the oxide semiconductor is indium gallium zinc oxide.
  • the thin film transistor including: a gate pattern, a gate insulating layer, an active layer pattern, a source drain pattern, and a light absorbing pattern,
  • the gate pattern, the gate insulating layer, the active layer pattern, and the source and drain patterns are sequentially stacked, and the light absorbing pattern is disposed on at least one side of the gate insulating layer, the light The absorption pattern is capable of absorbing light incident into the light absorbing pattern to prevent the light from entering the active layer pattern;
  • An orthographic projection area of the light absorbing pattern on the gate insulating layer is a target area, an orthographic projection area of the source/drain pattern on the gate insulating layer and the active layer pattern are in the gate insulating layer
  • the upper orthographic projection area constitutes a reference area, and the target area has an overlapping area with the reference area.
  • the light absorbing pattern is disposed on a side of the gate insulating layer adjacent to the gate pattern, and the light absorbing pattern covers the gate pattern;
  • the light absorbing pattern is disposed on a side of the gate insulating layer away from the gate pattern, and between the gate insulating layer and the active layer pattern, the target region and the active region
  • the layer pattern is coincident with the orthographic projection regions on the gate insulating layer;
  • the light absorbing pattern is disposed on a side of the gate insulating layer away from the gate pattern, and between the gate insulating layer and the source drain pattern, the target region and the active region
  • the orthographic projection regions of the layer patterns on the gate insulating layer do not overlap, and there is an overlapping region with the orthographic projection regions of the source and drain patterns on the gate insulating layer.
  • the light absorbing pattern comprises: a first partial light absorbing pattern, a second partial light absorbing pattern, and a third partial light absorbing pattern;
  • the first partial light absorbing pattern is disposed on a side of the gate insulating layer adjacent to the gate pattern and covers the gate pattern; the second partial light absorbing pattern is disposed on the gate insulating layer away from the a side of the gate pattern between the gate insulating layer and the active layer pattern, the target region and an orthographic projection area of the active layer pattern on the gate insulating layer; a third portion of the light absorbing pattern is disposed on a side of the gate insulating layer away from the gate pattern, and between the gate insulating layer and the source and drain patterns, the target region and the active layer
  • the orthographic projection regions of the pattern on the gate insulating layer do not overlap, and there is an overlapping region with the orthographic projection region of the source drain pattern on the gate insulating layer.
  • a method of fabricating a thin film transistor comprising:
  • a thin film transistor including a gate pattern, a gate insulating layer, an active layer pattern, a source pattern, and a drain pattern which are sequentially stacked, in a surface of the source pattern facing the gate insulating layer, in the drain pattern
  • a surface facing the gate insulating layer and a surface of the gate pattern facing the gate insulating layer at least one surface is a target surface, and the target surface is capable of diffusely reflecting light incident on the target surface To prevent part of the light from entering the active layer pattern.
  • the manufacturing comprises a gate pattern, a gate insulating layer, an active layer pattern, a source pattern, and a drain pattern of thin film transistors, which are sequentially stacked, including:
  • first electrode body pattern Forming a first electrode body pattern on a side of the first target pattern away from the gate pattern, and forming a second electrode body pattern on a side of the second target pattern away from the gate insulating layer, the first The electrode body pattern and the second electrode body pattern are both connected to the active layer pattern, the source pattern comprising: the first target pattern and the first electrode body pattern, the drain pattern comprising : The second target pattern and the second electrode body pattern.
  • the forming the active layer pattern, the first target pattern, and the second target pattern on a side of the gate insulating layer away from the gate pattern comprises:
  • the photoresist is completely removed, and the photoresist thickness of the first photoresist region is greater than the photoresist thickness of the second photoresist region;
  • the material is a reduced oxide semiconductor
  • the photoresist of the first photoresist region is stripped to obtain the active layer pattern, and the active layer pattern includes an oxide semiconductor of the first oxide semiconductor region.
  • the first target pattern and the second target pattern are both disposed around the active layer pattern, that is, the first target pattern and the second target pattern respectively surround the two ends of the active layer pattern . And the first target pattern and the second target pattern are both not connected to the active layer pattern.
  • the manufacturing comprises a gate pattern, a gate insulating layer, an active layer pattern, a source pattern, and a drain pattern of thin film transistors, which are sequentially stacked, including:
  • a third target pattern on a side of the third electrode body pattern, wherein a surface of the third target pattern that is away from the third electrode body pattern is the target surface, and the gate pattern includes: a three-electrode body pattern and the third target pattern;
  • a method of fabricating another thin film transistor comprising:
  • a thin film transistor including a gate pattern, a gate insulating layer, an active layer pattern, a source drain pattern, and a light absorbing pattern;
  • the gate pattern, the gate insulating layer, the active layer pattern, and the source and drain patterns are sequentially stacked, and the light absorbing pattern is disposed on at least one side of the gate insulating layer, the light The absorption pattern is capable of absorbing light incident into the light absorbing pattern to prevent the light from entering the active layer pattern;
  • An orthographic projection area of the light absorbing pattern on the gate insulating layer is a target area, an orthographic projection area of the source/drain pattern on the gate insulating layer and the active layer pattern are in the gate insulating layer
  • the upper orthographic projection area constitutes a reference area, and the target area has an overlapping area with the reference area.
  • the light absorbing pattern is disposed on a side of the gate insulating layer adjacent to the gate pattern, and the light absorbing pattern covers the gate pattern;
  • the light absorbing pattern is disposed on a side of the gate insulating layer away from the gate pattern, and between the gate insulating layer and the active layer pattern, the target region and the active region
  • the layer pattern is coincident with the orthographic projection regions on the gate insulating layer;
  • the light absorbing pattern is disposed on a side of the gate insulating layer away from the gate pattern, and between the gate insulating layer and the source drain pattern, the target region and the active region
  • the orthographic projection regions of the layer patterns on the gate insulating layer do not overlap, and there is an overlapping region with the orthographic projection regions of the source and drain patterns on the gate insulating layer.
  • an array substrate comprising the thin film transistor of the first aspect or the second aspect.
  • a display device comprising the array substrate of the fifth aspect.
  • a display panel comprising the array substrate of the fifth aspect.
  • a surface of the source-drain pattern facing the gate pattern and a surface of the gate pattern facing the source-drain pattern include a target surface, and the target surface is capable of diffusely reflecting light incident on the target surface to Blocking part of the light from entering the active layer pattern, thereby reducing the amount of light incident on the active layer pattern, reducing the degree of shift of the volt-ampere characteristic curve of the active layer pattern, thereby reducing the light pair The degree of influence of the normal operation of the thin film transistor.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram showing a setting position of a first target pattern, a second target pattern, and an active layer pattern according to an embodiment of the present invention
  • 3-1 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention.
  • 3-2 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention.
  • 3-3 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention.
  • 3-4 is a schematic structural diagram of a thin film transistor according to another embodiment of the present invention.
  • 3-5 is a schematic structural diagram of another thin film transistor according to another embodiment of the present invention.
  • FIG. 3-6 is a schematic structural diagram of still another thin film transistor according to another embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of still another thin film transistor according to another embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a thin film transistor according to another embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of another thin film transistor according to another embodiment of the present invention.
  • FIG. 7 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present invention.
  • FIG. 8 is a flowchart of a method for fabricating another thin film transistor according to an embodiment of the present invention.
  • FIG. 9 is a partial schematic structural diagram of a first thin film transistor according to an embodiment of the present invention.
  • FIG. 10 is a schematic partial structural diagram of a second thin film transistor according to an embodiment of the present invention.
  • FIG. 11 is a partial schematic structural view of a third thin film transistor according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram showing a partial structure of a fourth thin film transistor according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram showing a partial structure of a fifth thin film transistor according to an embodiment of the present invention.
  • FIG. 14 is a schematic partial structural diagram of a sixth thin film transistor according to an embodiment of the present invention.
  • FIG. 15 is a schematic partial structural diagram of a seventh thin film transistor according to an embodiment of the present invention.
  • FIG. 16 is a schematic partial structural diagram of an eighth thin film transistor according to an embodiment of the present invention.
  • FIG. 17 is a schematic diagram showing a partial structure of a ninth thin film transistor according to an embodiment of the present invention.
  • FIG. 18 is a partial schematic structural diagram of a tenth thin film transistor according to an embodiment of the present invention.
  • FIG. 19 is a flowchart of still another method for fabricating a thin film transistor according to an embodiment of the present invention.
  • FIG. 20 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • the thin film transistor may include: a gate pattern 01, a gate insulating layer 02, an active layer pattern 03, and a source pattern 04 which are sequentially stacked. And a drain pattern 05.
  • the target surface X In the surface of the source pattern 04 facing the gate insulating layer 02, the surface of the drain pattern 05 facing the gate insulating layer 02, and the surface of the gate pattern 01 facing the gate insulating layer 02, there is at least one target surface X, the target surface X The light incident on the target surface can be diffusely reflected to prevent part of the light from entering the active layer pattern 03.
  • the target surface is taken as the target surface X in which the surface of the drain pattern 05 facing the gate insulating layer 02 is the target surface X.
  • the surface of the source pattern facing the gate insulating layer, the surface of the drain pattern facing the gate insulating layer, and the surface of the gate pattern facing the gate insulating layer include a target. a surface, and the target surface is capable of diffusely reflecting light incident on the target surface to prevent part of the light from entering the active layer pattern, thereby reducing the amount of light incident on the active layer pattern and reducing the volt of the active layer pattern The degree of deviation of the characteristic curve, thereby reducing the degree of influence of light on the normal operation of the thin film transistor.
  • the target surface may be at least one of the surface of the source pattern 04 facing the gate insulating layer 02, the surface of the drain pattern 05 facing the gate insulating layer 02, and the surface of the gate pattern 01 facing the gate insulating layer 02,
  • the target surface can have a variety of morphologies, which will be explained below.
  • the source pattern 04 may include: a first target pattern 041 disposed on a side of the gate insulating layer 02 away from the gate insulating layer 02, and a first target pattern disposed on the first target pattern 041 is away from the first electrode body pattern 042 on the side of the gate insulating layer 02;
  • the drain pattern 05 may include: a second target pattern 051 disposed on a side of the gate insulating layer 02 away from the gate insulating layer 02, and a second target pattern disposed on the second target pattern 051 is away from the second electrode body pattern 052 on the side of the gate insulating layer 02;
  • the surface of the first target pattern 041 facing the gate insulating layer 02 and the surface of the second target pattern 052 facing the gate insulating layer 02 may be the target surface X.
  • the first body pattern 042 and the second body pattern 052 are both The active layer pattern 03 may be connected, and the pixel electrode may be connected to the thin film transistor by being connected to the second electrode body pattern 052. That is, when the light is incident on the first target pattern 041 and the second target pattern 051, the light can be diffusely reflected on the target surface X on the first target pattern 041 and the second target pattern 051, so that part of the light cannot be made.
  • the gate pattern 01 is incident, and is less reflected by the gate pattern 01 to the active layer pattern 03, thereby preventing part of the light from entering the active layer pattern 03.
  • the material of the active layer pattern 03 may be an oxide semiconductor
  • the material of the first target pattern 041 and the material of the second target pattern 051 may both be oxide semiconductors in a reduced state. Since the surface of the reduced-state oxide semiconductor is relatively rough, both the first target pattern 041 and the second target pattern 051 can achieve diffuse reflection of light.
  • the oxide semiconductor may be indium gallium zinc oxide (English: indium gallium zinc oxide; IGZO for short).
  • an oxide semiconductor has advantages such as high carrier mobility, low preparation temperature, excellent uniformity of large area, and high optical transmittance compared with a conventional amorphous silicon material, and these advantages also determine an oxide film. Transistors are suitable for the preparation of high resolution display devices.
  • the active layer pattern is usually formed by using amorphous indium gallium zinc oxide in the related art.
  • Amorphous indium gallium zinc oxide is a typical transparent metal oxide semiconductor, which has good light transmittance in the visible light band, and light having a wavelength of 420 nm or more illuminates the active layer of the amorphous indium gallium zinc oxide material.
  • the volt-ampere characteristic curve of the thin film transistor is relatively stable.
  • the target surface can diffusely reflect the light incident on the target surface to prevent part of the light from entering the active layer pattern, thereby reducing the amount of light incident on the active layer pattern, and reducing The degree of shift of the volt-ampere characteristic curve of the active layer pattern is small.
  • FIG. 2 is a schematic diagram of a setting position of a first target pattern, a second target pattern, and an active layer pattern according to an embodiment of the present invention.
  • both the first target pattern 041 and the second target pattern 051 may be disposed around the active layer pattern 03, as shown in FIG. 2, the first target pattern 041 and the first The two target patterns 051 are respectively surrounded at both ends of the active layer pattern 03.
  • the first target pattern 041 and the second target pattern 051 may be disposed not to be connected to the active layer pattern 03.
  • FIG. 3-1 is another thin film crystal provided by an embodiment of the present invention.
  • the gate pattern 01 may include a third electrode body pattern 011, and a third target pattern 012 disposed on the side of the third electrode body pattern 011.
  • the gate insulating layer 02 is disposed on a side of the third target pattern 012 away from the third electrode body pattern 011, and a surface of the third target pattern 012 remote from the third electrode body pattern 011 is a target surface X.
  • the material of the third target pattern 012 may be a conductive material or an insulating material, and the surface of the third target pattern 012 away from the gate pattern 01 is uneven, that is, the third target pattern 012 is away from the gate pattern 01.
  • the surface is the target surface X.
  • the material of the third target pattern 012 may be the same as the material of the gate insulating layer 02.
  • FIG. 3-2 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention.
  • the source pattern 04 includes: a first target pattern 041 and The first electrode body pattern 042
  • the drain pattern 05 includes: a second target pattern 051 and a second electrode body pattern 05
  • the gate pattern 01 includes: a third electrode body pattern 011 and a third target pattern 012
  • the first target pattern The surface of the 041 facing the gate insulating layer 02, the surface of the second target pattern 051 facing the gate insulating layer 02, and the surface of the third target pattern 012 remote from the third electrode body pattern 011 are the target surface X.
  • FIG. 3-3 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention.
  • the source pattern 04 includes: a first target pattern 041 and The first electrode body pattern 042
  • the gate pattern 01 includes: a third electrode body pattern 011 and a third target pattern 012
  • the surface of the first target pattern 041 facing the gate insulating layer 02 and the third target pattern 012 are away from the third
  • the surface of the electrode body pattern 011 is the target surface X.
  • FIG. 3-4 is a schematic structural diagram of a thin film transistor according to another embodiment of the present invention.
  • the drain pattern 05 includes: a second target pattern 051.
  • the gate pattern 01 includes: a third electrode body pattern 011 and a third target pattern 012, and the surface of the second target pattern 051 facing the gate insulating layer 02 and the third target pattern 012 are far away from the first
  • the surface of the three-electrode main body pattern 011 is the target surface X.
  • FIG. 3-5 is a schematic structural diagram of another thin film transistor according to another embodiment of the present invention.
  • the source pattern 04 includes: a first target pattern. 041 and the first electrode body pattern 042, and the surface of the first target pattern 041 facing the gate insulating layer 02 is the target surface X.
  • FIG. 3-6 is a schematic structural diagram of still another thin film transistor according to another embodiment of the present invention.
  • the drain pattern 05 includes: a second target pattern. 051 and the second electrode body pattern 052, and the surface of the second target pattern 051 facing the gate insulating layer 02 is the target surface X.
  • the thin film transistor provided by the embodiment of the invention may further include a passivation layer Y, and the pixel electrode Z may be connected to the source/drain pattern 04 through a via hole on the passivation layer Y.
  • the thin film transistor is disposed on the base substrate W as an example, which is not limited in the embodiment of the present invention.
  • the surface of the source pattern facing the gate insulating layer, the surface of the drain pattern facing the gate insulating layer, and the surface of the gate pattern facing the gate insulating layer include a target. a surface, and the target surface is capable of diffusely reflecting light incident on the target surface to prevent part of the light from entering the active layer pattern, thereby reducing the amount of light incident on the active layer pattern and reducing the volt of the active layer pattern The degree of deviation of the characteristic curve, thereby reducing the degree of influence of light on the normal operation of the thin film transistor.
  • the thin film transistor may include: a gate pattern 01, a gate insulating layer 02, an active layer pattern 03, and a source and drain electrode.
  • the pattern (including the source pattern 04 and the drain pattern 05) and the light absorbing pattern 06.
  • the gate pattern 01, the gate insulating layer 02, the active layer pattern 03, and the source and drain patterns are sequentially stacked, and the light absorbing pattern 06 is disposed on at least one side of the gate insulating layer 02, and the light absorbing pattern 06 is capable of absorbing light into the light.
  • the light of the pattern 06 is absorbed to prevent the light (i.e., light absorbed by the light absorbing pattern, such as all or part of the light incident into the thin film transistor) from entering the active layer pattern.
  • the orthographic projection area of the light absorbing pattern 06 on the gate insulating layer 02 is the target area A, and the orthographic projection area of the source/drain pattern on the gate insulating layer 02 and the orthographic projection area of the active layer pattern 03 on the gate insulating layer 02 are composed. With reference to the area B, there is an overlapping area between the target area A and the reference area B.
  • the thin film transistor provided by the embodiment of the present invention includes a light absorbing pattern, and an orthographic projection area of the light absorbing pattern on the gate insulating layer is a target area, and an orthographic projection area of the source and drain patterns on the gate insulating layer and
  • the orthographic projection area of the active layer pattern on the gate insulating layer constitutes a reference area, and the target area and the reference area have an overlapping area, so that light incident between the active layer and the gate pattern can be absorbed by the light absorbing pattern, thereby reducing
  • the amount of light incident on the active layer pattern reduces the degree of volt-ampere characteristic shift of the active layer pattern, thereby reducing the effect of light on the normal operation of the thin film transistor.
  • the light absorbing pattern 06 is disposed on a side of the gate insulating layer 02 close to the gate pattern 01, and the light absorbing pattern 06 covers the gate pattern 01 as an example.
  • FIG. 5 is a schematic structural diagram of a thin film transistor according to another embodiment of the present invention.
  • the light absorbing pattern 06 may also be disposed on a side of the gate insulating layer 02 away from the gate pattern 01.
  • the target region A coincides with the orthographic projection region of the active layer pattern 03 on the gate insulating layer 02.
  • FIG. 6 is a schematic structural diagram of another thin film transistor according to another embodiment of the present invention.
  • the light absorbing pattern 06 may be disposed on a side of the gate insulating layer 02 away from the gate pattern 01, and located at Between the gate insulating layer 02 and the source/drain pattern, the target region A and the active layer pattern 03 do not overlap the orthographic projection area on the gate insulating layer 02, and the orthographic projection area of the source and drain patterns on the gate insulating layer 02 There are overlapping areas.
  • the material of the light absorbing pattern 06 in FIG. 4 and FIG. 6 may be a black conductive material or a black insulating material.
  • the material of the light absorbing pattern 06 in FIGS. 4 and 6 may be carbon.
  • the material of the light absorbing pattern 06 in FIG. 5 may be a black insulating material.
  • the material of the light absorbing pattern 06 in FIG. 5 may be the same as the material of the black matrix (English: Black Matrix; BM for short).
  • the thin film transistor shown in FIG. 6 includes two light absorbing patterns 06, and the two light absorbing patterns 06 are respectively disposed under the source pattern and the drain pattern.
  • the thin film transistor shown in FIG. 6 may further include only one light absorbing pattern 06, and the one light absorbing pattern 06 may be disposed under the source pattern or below the drain pattern.
  • the light absorbing pattern in the thin film transistor may also be simultaneously distributed at positions shown in at least two of FIGS. 4, 5, and 6.
  • a light absorbing pattern is disposed under the source pattern and the drain pattern in the thin film transistor, and light is disposed above the gate.
  • the absorption pattern is also provided with a light absorbing pattern below the active layer.
  • the light absorbing pattern includes: a first partial light absorbing pattern, a second partial light absorbing pattern, and a third partial light absorbing pattern;
  • the first partial light absorbing pattern is disposed on a side of the gate insulating layer adjacent to the gate pattern, and is covered a gate pattern;
  • the second portion of the light absorbing pattern is disposed on a side of the gate insulating layer away from the gate pattern, and between the gate insulating layer and the active layer pattern, and the target region and the active layer pattern are on the gate insulating layer
  • the front projection regions are overlapped;
  • the third portion of the light absorbing pattern is disposed on a side of the gate insulating layer away from the gate pattern, and is located between the gate insulating layer and the source and drain patterns, and the target region and the active layer pattern are on the gate insulating layer
  • the orthographic projection areas do not overlap, and there is an overlapping area with the orthographic projection area of the source and drain patterns on the gate insulating layer.
  • the thin film transistors shown in FIG. 4, FIG. 5 and FIG. 6 may further include a passivation layer Y, and the pixel electrode Z may be connected to the source and drain patterns through via holes on the passivation layer Y.
  • FIG. 5 and FIG. 6 are exemplified by the fact that the thin film transistor is disposed on the base substrate W, which is not limited in the embodiment of the present invention.
  • the thin film transistor provided by the embodiment of the present invention includes a light absorbing pattern, and an orthographic projection area of the light absorbing pattern on the gate insulating layer is a target area, and an orthographic projection area of the source and drain patterns on the gate insulating layer and
  • the orthographic projection area of the active layer pattern on the gate insulating layer constitutes a reference area, and the target area and the reference area have an overlapping area, so that light incident between the active layer and the gate pattern can be absorbed by the light absorbing pattern, thereby reducing
  • the amount of light incident on the active layer pattern reduces the degree of volt-ampere characteristic shift of the active layer pattern, thereby reducing the effect of light on the normal operation of the thin film transistor.
  • FIG. 7 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present invention.
  • the thin film transistor may be FIG. 1, FIG. 3-1, FIG. 3-2, FIG. 3-3, FIG. 3-5 or the thin film transistor shown in FIG. 3-6, as shown in FIG. 7, the manufacturing method of the thin film transistor may include:
  • Step 701 manufacturing a thin film transistor including a gate pattern, a gate insulating layer, an active layer pattern, and a source/drain pattern which are sequentially stacked, a surface of the source and drain patterns facing the gate insulating layer, and a drain pattern facing the gate insulating layer
  • the surface and the surface of the gate pattern facing the gate insulating layer include: at least one target surface capable of diffusely reflecting light incident on the target surface to prevent part of the light from entering the active layer pattern.
  • the surface of the source pattern facing the gate insulating layer, the surface of the drain pattern facing the gate insulating layer, and the gate pattern facing the gate insulating layer includes a target surface, and the target surface is capable of diffusely reflecting light incident on the target surface to prevent part of the light from entering the active layer pattern, thereby reducing the amount of light entering the active layer pattern and reducing the amount of light.
  • the degree of volt-ampere characteristic curve shift of the active layer pattern thereby reducing the degree of influence of light on the normal operation of the thin film transistor.
  • FIG. 8 is a flow chart of a method for fabricating a thin film transistor according to an embodiment of the present invention.
  • the thin film transistor may be the thin film transistor shown in FIG. 1.
  • the method for manufacturing the thin film transistor may include:
  • Step 801 forming a gate pattern.
  • step 801 coating, magnetron sputtering, thermal evaporation, or plasma enhanced chemical vapor deposition may be used first (English: Plasma Enhanced Chemical Vapor) Deposition; abbreviated as: PECVD), a metal material is deposited on the base substrate W to obtain a metal material layer, and then the metal material layer is processed by a patterning process to obtain the gate pattern 01.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • one patterning process includes: photoresist coating, exposure, development, etching, and photoresist stripping.
  • processing the metal layer by using a patterning process includes: coating a layer of photolithography on the metal layer
  • the glue is then exposed to the photoresist by using a mask to form the fully exposed and non-exposed areas of the photoresist, and then processed by a development process to remove the photoresist in the fully exposed area, and the light in the non-exposed area.
  • the engraved glue is retained, and then the corresponding area on the metal material layer is completely etched. After the etching is completed, the photoresist in the non-exposed area is peeled off to obtain the gate pattern 01.
  • Step 802 forming a gate insulating layer on one side of the gate pattern.
  • a gate insulating layer 02 may be coated on the gate pattern 01.
  • Step 803 forming an active layer pattern, a first target pattern, and a second target pattern on a side of the gate insulating layer away from the gate pattern, the surface of the first target pattern facing the gate insulating layer and the second target pattern facing the gate insulating
  • the surface of the layer is the target surface.
  • the oxide semiconductor material layer 07 may be first formed on the side of the gate insulating layer 02 away from the gate pattern 01, and then, as shown in FIG. 12, the oxide semiconductor material layer 06 is away from the gate insulating layer 02.
  • a photoresist layer 08 is formed on one side.
  • the photoresist layer 08 may be subjected to exposure processing and development processing using a gray mask (not shown in FIG. 13) to obtain a photoresist pattern 09, which is patterned 08.
  • the first photoresist region 091, the two second photoresist regions 092, and the photoresist complete removal region 093 may be included, and the photoresist thickness of the first photoresist region 091 is greater than that of the second photoresist region 092. Photoresist thickness.
  • the oxide semiconductor material layer 07 in FIG. 13 can be etched through the photoresist pattern 09 to remove the photoresist completely removed region 093.
  • the oxide semiconductor has a first oxide semiconductor region X1 corresponding to the first photoresist region 091 and two second oxide semiconductor regions X2 corresponding to the two second photoresist regions 092.
  • the photoresist pattern may be subjected to ashing treatment to remove the photoresist of the second photoresist region 092, and to thin the photoresist of the first photoresist region 091;
  • the oxide semiconductors of the two second oxide semiconductor regions X2 may be subjected to a reduction treatment (eg, oxide to the second semiconductor region).
  • the photoresist of the first photoresist region 091 may be peeled off to obtain an active layer pattern 03, and the active layer pattern 03 may include the first oxide.
  • Step 804 forming a first electrode body pattern on a side of the first target pattern away from the gate insulating layer, and forming a second electrode body pattern on a side of the second target pattern away from the gate insulating layer.
  • the first electrode body pattern 042 may be formed on the side of the first target pattern 041 away from the gate insulating layer 02, in the second The second electrode body pattern 052 is formed on a side of the target pattern 051 away from the gate insulating layer 02.
  • the surface of the first target pattern 041 facing the gate insulating layer 02 and the surface of the second target pattern 051 facing the gate insulating layer 02 are the target surface X. That is, when light is incident on the first target pattern 041 and the second target pattern 051, light can be diffusely reflected on the target surface on the first target pattern 041 and the target surface on the second target pattern 051, thereby making Part of the light cannot be incident on the gate pattern 01, and is less reflected by the gate pattern to the active layer pattern 03, thereby preventing part of the light from entering the active layer pattern 03.
  • the first target pattern 041 and the second target pattern 051 are respectively surrounded at both ends of the active layer pattern 03.
  • the first target pattern 041 and the second target pattern 051 may be disposed not to be connected to the active layer pattern 03.
  • a passivation layer Y as shown in FIG. 1 may also be formed on a side of the first electrode body pattern 042 and the second electrode body pattern 052 away from the gate insulating layer 02.
  • the material of the first target pattern is an oxide semiconductor in a reduced state
  • the material of the active layer pattern is an oxide semiconductor. Therefore, the oxide semiconductor layer can be formed first, and then the first oxide semiconductor region and the second oxide semiconductor region are simultaneously formed by one patterning process.
  • the oxide semiconductor of the first oxide semiconductor region is also an active layer pattern. Thereafter, only the oxide semiconductor of the second oxide semiconductor region may be subjected to a reduction treatment to obtain a first target pattern. That is, in the process of forming the first target pattern and the active layer pattern, only one patterning process is employed, so that the entire thin film transistor is manufactured at a faster speed.
  • the surface of the source pattern facing the gate insulating layer, the surface of the drain pattern facing the gate insulating layer, and the gate pattern facing the gate insulating layer includes a target surface, and the target surface can diffusely reflect light incident on the target surface to prevent part of the light from entering the active layer pattern, thereby reducing the light incident on the active layer pattern.
  • the amount reduces the degree of shift of the volt-ampere characteristic curve of the active layer pattern, thereby reducing the influence of light on the normal operation of the thin film transistor.
  • FIG. 19 is a flowchart of still another method for fabricating a thin film transistor according to an embodiment of the present invention.
  • the thin film transistor may be the thin film transistor shown in FIG. 4, FIG. 5 or FIG. 6, as shown in FIG.
  • the manufacturing method can include:
  • Step 1901 manufacturing a thin film transistor including a gate pattern, a gate insulating layer, an active layer pattern, a source drain pattern, and a light absorbing pattern; wherein the gate pattern, the gate insulating layer, the active layer pattern, and the source and drain patterns are sequentially Superimposing, the light absorbing pattern is disposed on at least one side of the gate insulating layer, and the light absorbing pattern is capable of absorbing light entering the light absorbing pattern to prevent light from entering the active layer pattern; and the light absorbing pattern is positive on the gate insulating layer
  • the projection area is a target area, and the orthographic projection area of the source-drain pattern on the gate insulating layer and the orthographic projection area of the active layer pattern on the gate insulating layer constitute a reference area, and the target area and the reference area have an overlapping area.
  • the method of manufacturing the thin film transistor may include: forming a gate pattern on the base substrate; forming a light absorbing layer on the base substrate on which the gate pattern is formed; forming on the base substrate on which the light absorbing layer is formed a gate insulating layer; an active layer pattern is formed on the base substrate on which the gate insulating layer is formed; and a source/drain pattern is formed on the base substrate on which the active layer pattern is formed.
  • the light absorbing pattern 06 may also be disposed on a side of the gate insulating layer 02 away from the gate pattern 01, and Located between the gate insulating layer 02 and the active layer pattern 03, the target region A coincides with the orthographic projection region of the active layer pattern 03 on the gate insulating layer 02.
  • the method of manufacturing the thin film transistor may include: forming a gate pattern on the base substrate; forming a gate insulating layer on the base substrate on which the gate pattern is formed; forming on the base substrate on which the gate insulating layer is formed
  • the light absorbing pattern forms an active layer pattern on the base substrate on which the light absorbing pattern is formed; and the source and drain patterns (including the source pattern and the drain pattern) are formed on the base substrate on which the active layer pattern is formed.
  • the light absorbing pattern 06 may be disposed on a side of the gate insulating layer 02 away from the gate pattern 01, and located at Between the gate insulating layer 02 and the source/drain pattern, the target region A and the active layer pattern 03 do not overlap the orthographic projection area on the gate insulating layer 02, and the source and drain patterns are positive on the gate insulating layer 02.
  • the method of manufacturing the thin film transistor may include: forming a gate pattern on the base substrate; forming a gate insulating layer on the base substrate on which the gate pattern is formed; and forming the substrate on the gate insulating layer A light absorbing pattern is formed on the substrate, an active layer pattern is formed on the base substrate on which the light absorbing pattern is formed, and a source/drain pattern is formed on the base substrate on which the active layer pattern is formed.
  • the thin film transistor manufactured by the method provided by the embodiment of the present invention includes a light absorbing pattern, and the orthographic projection area of the light absorbing pattern on the gate insulating layer is a target area, and the source and drain patterns are on the gate insulating layer.
  • the orthographic projection area and the orthographic projection area of the active layer pattern on the gate insulating layer constitute a reference area, and the target area and the reference area have an overlapping area, so that light incident between the active layer and the gate pattern can be absorbed by the light absorbing pattern.
  • the absorption reduces the amount of light incident on the active layer pattern, reduces the degree of shift of the volt-ampere characteristic curve of the active layer pattern, and thereby reduces the influence of light on the normal operation of the thin film transistor.
  • an embodiment of the present invention provides an array substrate, which may include a substrate substrate W, and a plurality of thin film transistors 0 arranged in an array on the substrate substrate W, the plurality of thin film transistors Each of the thin film transistors may be a thin film transistor as shown in any of FIGS. 1 to 6.
  • the embodiment of the present invention provides a display panel, which may include the array substrate shown in FIG. 20, and the display panel may be a liquid crystal display panel or an organic light emitting diode display panel, which is not limited in the embodiment of the present invention.
  • Embodiments of the present invention provide a display device, which may include the array substrate shown in FIG.
  • the display device may be any product or component having a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the thin film transistor embodiments, the thin film transistor manufacturing method embodiments, the array substrate embodiments, the display panel embodiments, and the display device embodiments of the embodiments of the present invention may be referred to each other. Make a limit.

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Abstract

一种薄膜晶体管及其制造方法、阵列基板、显示面板及显示装置，其中，薄膜晶体管包括：依次叠加的栅极图案（01）、栅绝缘层（02）、有源层图案（03）、源极图案（04）以及漏极图案（05），源极图案（04）中朝向栅绝缘层（02）的表面、漏极图案（05）中朝向栅绝缘层（02）的表面以及栅极图案（01）中朝向栅绝缘层（02）的表面中，存在至少一个表面为目标表面（X），目标表面（X）能够对射入目标表面（X）的光线进行漫反射，以阻止部分光线射入有源层图案（03）。该显示装置解决了有源层图案（03）的伏安特性曲线会发生偏移，影响薄膜晶体管的正常工作的问题，减弱了光线对薄膜晶体管正常工作的影响程度。

Description

薄膜晶体管及其制造方法、阵列基板、显示面板及显示装置
本申请要求于2017年5月11日提交中国国家知识产权局、申请号为201710329780.8、发明名称为“薄膜晶体管及其制造方法、阵列基板、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本申请涉及显示技术领域，特别涉及薄膜晶体管及其制造方法、阵列基板、显示面板及显示装置。
背景技术
显示装置中的阵列基板包括：衬底基板以及设置在衬底基板一侧的多个阵列排布的像素单元，每个像素单元可以包括薄膜晶体管、像素电极、公共电极和液晶。
相关技术中，通常通过薄膜晶体管向像素电极输入不同的电压，从而改变液晶的偏转程度，调整像素单元的透光率，进而实现显示装置显示图像的功能。示例的，薄膜晶体管可以包括：依次叠加在衬底基板上的栅极图案、栅绝缘层、有源层图案和源漏极图案。源漏极图案与有源层图案相连接，像素电极与源漏极图案中的漏极相连接，栅极图案和源漏极图案的材质均可以为金属，有源层图案的材质可以为氧化物半导体。
相关技术中，源漏极图案与栅极图案的材质均为表面反光能力较强的金属，从衬底基板入射的光线能够在源漏极图案和栅极图案的反光作用下射入有源层图案。当射入有源层图案的光线的能量达到有源层图案的禁带宽度时，有源层图案的伏安特性曲线会发生偏移，影响薄膜晶体管的正常工作。
发明内容
本申请提供了薄膜晶体管及其制造方法、阵列基板、显示装置，可以解决有源层图案的伏安特性曲线发生偏移，影响薄膜晶体管的正常工作的问题。所述技术方案如下：
第一方面，提供了一种薄膜晶体管，所述薄膜晶体管包括：依次叠加的栅 极图案、栅绝缘层、有源层图案、源极图案以及漏极图案，
所述源极图案中朝向所述栅绝缘层的表面、所述漏极图案中朝向所述栅绝缘层的表面以及所述栅极图案中朝向所述栅绝缘层的表面中，存在至少一个表面为目标表面，所述目标表面能够对射入所述目标表面的光线进行漫反射，以阻止部分光线射入所述有源层图案。
可选的，所述源极图案包括：设置在所述栅绝缘层远离所述栅极图案一侧的第一目标图案，以及设置在所述第一目标图案远离所述栅极图案一侧的第一电极主体图案；
所述漏极图案包括：设置在所述栅绝缘层远离所述栅极图案一侧的第二目标图案，以及设置在所述第二目标图案远离所述栅极图案一侧的第二电极主体图案；
所述第一目标图案中朝向所述栅绝缘层的表面，以及所述第二目标图案中朝向所述栅绝缘层的表面均为所述目标表面，所述第一电极主体图案和所述第二电极主体图案均与所述有源层图案相连接。
可选的，所述有源层图案的材质为氧化物半导体，所述第一目标图案的材质和所述第二目标图案的材质均为还原态的氧化物半导体，
所述第一目标图案和所述第二目标图案均围绕所述有源层图案设置，也即第一目标图案和第二目标图案分别围绕在有源层图案的两端。且第一目标图案和第二目标图案均与所述有源层图案不连接。
可选的，所述栅极图案包括：第三电极主体图案，以及设置在所述第三电极主体图案一侧的第三目标图案，所述栅绝缘层设置在所述第三目标图案远离所述第三电极主体图案的一侧，所述第三目标图案中远离所述第三电极主体图案的表面为所述目标表面。
可选的，所述源极图案包括：设置在所述栅绝缘层远离所述栅极图案一侧的第一目标图案，以及设置在所述第一目标图案远离所述栅极图案一侧的第一电极主体图案；所述漏极图案包括：设置在所述栅绝缘层远离所述栅极图案一侧的第二目标图案，以及设置在所述第二目标图案远离所述栅极图案一侧的第二电极主体图案；所述栅极图案包括：第三电极主体图案，以及设置在所述第三电极主体图案一侧的第三目标图案，所述栅绝缘层设置在所述第三目标图案远离所述第三电极主体图案的一侧；所述第一目标图案中朝向所述栅绝缘层的表面，所述第二目标图案中朝向所述栅绝缘层的表面，以及所述第三目标图案 中远离所述第三电极主体图案的表面均为所述目标表面，所述第一电极主体图案和所述第二电极主体图案均与所述有源层图案相连接。
可选的，所述源极图案包括：设置在所述栅绝缘层远离所述栅极图案一侧的第一目标图案，以及设置在所述第一目标图案远离所述栅极图案一侧的第一电极主体图案；所述栅极图案包括：第三电极主体图案，以及设置在所述第三电极主体图案一侧的第三目标图案，所述栅绝缘层设置在所述第三目标图案远离所述第三电极主体图案的一侧；所述第一目标图案中朝向所述栅绝缘层的表面，以及所述第三目标图案中远离所述第三电极主体图案的表面均为所述目标表面，所述第一电极主体图案与所述有源层图案相连接。
可选的，所述漏极图案包括：设置在所述栅绝缘层远离所述栅极图案一侧的第二目标图案，以及设置在所述第二目标图案远离所述栅极图案一侧的第二电极主体图案；所述栅极图案包括：第三电极主体图案，以及设置在所述第三电极主体图案一侧的第三目标图案，所述栅绝缘层设置在所述第三目标图案远离所述第三电极主体图案的一侧；所述第二目标图案中朝向所述栅绝缘层的表面，以及所述第三目标图案中远离所述第三电极主体图案的表面均为所述目标表面，所述第二电极主体图案均与所述有源层图案相连接。
可选的，氧化物半导体为铟镓锌氧化物。
第二方面，提供了另一种薄膜晶体管，所述薄膜晶体管包括：栅极图案、栅绝缘层、有源层图案、源漏极图案以及光吸收图案，
其中，所述栅极图案、所述栅绝缘层、所述有源层图案以及所述源漏极图案依次叠加，所述光吸收图案设置在所述栅绝缘层的至少一侧，所述光吸收图案能够对射入所述光吸收图案的光线进行吸收，以阻止所述光线射入所述有源层图案；
所述光吸收图案在所述栅绝缘层上的正投影区域为目标区域，所述源漏极图案在所述栅绝缘层上的正投影区域与所述有源层图案在所述栅绝缘层上的正投影区域组成参考区域，所述目标区域与所述参考区域存在重叠区域。
可选的，所述光吸收图案设置在所述栅绝缘层靠近所述栅极图案的一侧，且所述光吸收图案覆盖所述栅极图案；
或者，所述光吸收图案设置在所述栅绝缘层远离所述栅极图案的一侧，且位于所述栅绝缘层与所述有源层图案之间，所述目标区域与所述有源层图案在所述栅绝缘层上的正投影区域重合；
或者，所述光吸收图案设置在所述栅绝缘层远离所述栅极图案的一侧，且位于所述栅绝缘层与所述源漏极图案之间，所述目标区域与所述有源层图案在所述栅绝缘层上的正投影区域不重叠，且与所述源漏极图案在所述栅绝缘层上的正投影区域存在重叠区域。
可选的，所述光吸收图案包括：第一部分光吸收图案、第二部分光吸收图案以及第三部分光吸收图案；
所述第一部分光吸收图案设置在所述栅绝缘层靠近所述栅极图案的一侧，且覆盖所述栅极图案；所述第二部分光吸收图案设置在所述栅绝缘层远离所述栅极图案的一侧，且位于所述栅绝缘层与所述有源层图案之间，所述目标区域与所述有源层图案在所述栅绝缘层上的正投影区域重合；所述第三部分光吸收图案设置在所述栅绝缘层远离所述栅极图案的一侧，且位于所述栅绝缘层与所述源漏极图案之间，所述目标区域与所述有源层图案在所述栅绝缘层上的正投影区域不重叠，且与所述源漏极图案在所述栅绝缘层上的正投影区域存在重叠区域。
第三方面，提供了一种薄膜晶体管的制造方法，所述方法包括：
制造包括依次叠加的栅极图案、栅绝缘层、有源层图案、源极图案以及漏极图案的薄膜晶体管，所述源极图案中朝向所述栅绝缘层的表面、所述漏极图案中朝向所述栅绝缘层的表面以及所述栅极图案中朝向所述栅绝缘层的表面中，存在至少一个表面为目标表面，所述目标表面能够对射入所述目标表面的光线进行漫反射，以阻止部分光线射入所述有源层图案。
可选的，所述制造包括依次叠加的栅极图案、栅绝缘层、有源层图案、源极图案以及漏极图案的薄膜晶体管，包括：
形成栅极图案；
在所述栅极图案的一侧形成所述栅绝缘层；
在所述栅绝缘层远离所述栅极图案的一侧形成所述有源层图案、第一目标图案和第二目标图案，所述第一目标图案中朝向所述栅绝缘层的表面，以及所述第二目标图案中朝向所述栅绝缘层的表面均为所述目标表面；
在所述第一目标图案远离所述栅极图案一侧形成第一电极主体图案，以及在所述第二目标图案远离所述栅绝缘层的一侧形成第二电极主体图案，所述第一电极主体图案和所述第二电极主体图案均与所述有源层图案相连接，所述源极图案包括：所述第一目标图案和所述第一电极主体图案，所述漏极图案包括： 所述第二目标图案和所述第二电极主体图案。
可选的，所述在所述栅绝缘层远离所述栅极图案的一侧形成所述有源层图案、第一目标图案和第二目标图案，包括：
在所述栅绝缘层远离所述栅极图案的一侧形成氧化物半导体材质层；
在所述氧化物半导体材质层远离所述栅极图案的一侧形成光刻胶层；
采用灰度掩膜板对所述光刻胶层进行曝光处理和显影处理，得到光刻胶图案，所述光刻胶图案包括第一光刻胶区、两个第二光刻胶区和光刻胶完全去除区，且所述第一光刻胶区的光刻胶厚度大于所述第二光刻胶区的光刻胶厚度；
透过所述光刻胶图案对所述氧化物半导体材质层进行刻蚀处理，以去除与所述光刻胶完全去除区对应的氧化物半导体，得到与所述第一光刻胶区对应的第一氧化物半导体区，以及与所述两个第二光刻胶区对应的两个第二氧化物半导体区；
对所述光刻胶图案进行灰化处理，以去除所述两个第二光刻胶区的光刻胶，以及减薄所述第一光刻胶区的光刻胶；
对所述两个第二氧化物半导体区的氧化物半导体进行还原处理，得到所述第一目标图案和所述第二目标图案，所述第一目标图案的材质和所述第二目标图案的材质均为还原态的氧化物半导体；
剥离所述第一光刻胶区的光刻胶，得到所述有源层图案，所述有源层图案包括所述第一氧化物半导体区的氧化物半导体。
可选的，所述第一目标图案和所述第二目标图案均围绕所述有源层图案设置，也即第一目标图案和第二目标图案分别围绕在所述有源层图案的两端。且第一目标图案和第二目标图案均与所述有源层图案不连接。
可选的，所述制造包括依次叠加的栅极图案、栅绝缘层、有源层图案、源极图案以及漏极图案的薄膜晶体管，包括：
形成第三电极主体图案；
在所述第三电极主体图案的一侧形成第三目标图案，所述第三目标图案中远离所述第三电极主体图案的表面为所述目标表面，所述栅极图案包括：所述第三电极主体图案和所述第三目标图案；
在所述第三目标图案远离所述第三电极主体的一侧形成所述栅绝缘层；
在所述栅绝缘层远离所述第三电极主体图案的一侧形成所述有源层图案；
在所述有源层图案远离所述栅极图案一侧形成所述源极图案和所述漏极 图案。
第四方面，提供了另一种薄膜晶体管的制造方法，所述方法包括：
制造包括栅极图案、栅绝缘层、有源层图案、源漏极图案以及光吸收图案的薄膜晶体管；
其中，所述栅极图案、所述栅绝缘层、所述有源层图案以及所述源漏极图案依次叠加，所述光吸收图案设置在所述栅绝缘层的至少一侧，所述光吸收图案能够对射入所述光吸收图案的光线进行吸收，以阻止所述光线射入所述有源层图案；
所述光吸收图案在所述栅绝缘层上的正投影区域为目标区域，所述源漏极图案在所述栅绝缘层上的正投影区域与所述有源层图案在所述栅绝缘层上的正投影区域组成参考区域，所述目标区域与所述参考区域存在重叠区域。
可选的，所述光吸收图案设置在所述栅绝缘层靠近所述栅极图案的一侧，且所述光吸收图案覆盖所述栅极图案；
或者，所述光吸收图案设置在所述栅绝缘层远离所述栅极图案的一侧，且位于所述栅绝缘层与所述有源层图案之间，所述目标区域与所述有源层图案在所述栅绝缘层上的正投影区域重合；
或者，所述光吸收图案设置在所述栅绝缘层远离所述栅极图案的一侧，且位于所述栅绝缘层与所述源漏极图案之间，所述目标区域与所述有源层图案在所述栅绝缘层上的正投影区域不重叠，且与所述源漏极图案在所述栅绝缘层上的正投影区域存在重叠区域。
第五方面，提供了一种阵列基板，所述阵列基板包括第一方面或第二方面所述的薄膜晶体管。
第六方面，提供了一种显示装置，所述显示装置包括第五方面所述的阵列基板。
第七方面，提供了一种显示面板，所述显示面板包括第五方面所述的阵列基板。
本申请提供的技术方案带来的有益效果是：
由于薄膜晶体管中，源漏极图案中朝向所述栅极图案的表面以及栅极图案中朝向源漏极图案的表面包括目标表面，且目标表面能够对射入目标表面的光线进行漫反射，以阻止部分光线射入有源层图案，从而减少了射入有源层图案的光线量，减小了有源层图案的伏安特性曲线偏移的程度，从而减弱了光线对 薄膜晶体管正常工作的影响程度。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种薄膜晶体管的结构示意图；
图2为本发明实施例提供的一种第一目标图案、第二目标图案与有源层图案的设置位置示意图；
图3-1为本发明实施例提供的另一种薄膜晶体管的结构示意图；
图3-2为本发明实施例提供的又一种薄膜晶体管的结构示意图；
图3-3为本发明实施例提供的再一种薄膜晶体管的结构示意图；
图3-4为本发明另一实施例提供的一种薄膜晶体管的结构示意图；
图3-5为本发明另一实施例提供的另一种薄膜晶体管的结构示意图；
图3-6为本发明另一实施例提供的又一种薄膜晶体管的结构示意图；
图4为本发明另一实施例提供的再一种薄膜晶体管的结构示意图；
图5为本发明又一实施例提供的一种薄膜晶体管的结构示意图；
图6为本发明又一实施例提供的另一种薄膜晶体管的结构示意图；
图7为本发明实施例提供的一种薄膜晶体管的制造方法的方法流程图；
图8为本发明实施例提供的另一种薄膜晶体管的制造方法的方法流程图；
图9为本发明实施例提供的第一种薄膜晶体管的局部结构示意图；
图10为本发明实施例提供的第二种薄膜晶体管的局部结构示意图；
图11为本发明实施例提供的第三种薄膜晶体管的局部结构示意图；
图12为本发明实施例提供的第四种薄膜晶体管的局部结构示意图；
图13为本发明实施例提供的第五种薄膜晶体管的局部结构示意图；
图14为本发明实施例提供的第六种薄膜晶体管的局部结构示意图；
图15为本发明实施例提供的第七种薄膜晶体管的局部结构示意图；
图16为本发明实施例提供的第八种薄膜晶体管的局部结构示意图；
图17为本发明实施例提供的第九种薄膜晶体管的局部结构示意图；
图18为本发明实施例提供的第十种薄膜晶体管的局部结构示意图；
图19为本发明实施例提供的又一种薄膜晶体管的制造方法的方法流程图；
图20为本发明实施例提供的一种阵列基板的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
图1为本发明实施例提供的一种薄膜晶体管的结构示意图，如图1所示，薄膜晶体管可以包括：依次叠加的栅极图案01、栅绝缘层02、有源层图案03源极图案04以及漏极图案05。
源极图案04中朝向栅绝缘层02的表面、漏极图案05中朝向栅绝缘层02的表面以及栅极图案01中朝向栅绝缘层02的表面中，存在至少一个目标表面X，目标表面X能够对射入目标表面的光线进行漫反射，以阻止部分光线射入有源层图案03。图1中以目标表面为漏极图案05中朝向栅绝缘层02的表面为目标表面X为例。
综上所述，由于本发明实施例提供的薄膜晶体管中，源极图案中朝向栅绝缘层的表面、漏极图案中朝向栅绝缘层的表面以及栅极图案中朝向栅绝缘层的表面包括目标表面，且目标表面能够对射入目标表面的光线进行漫反射，以阻止部分光线射入有源层图案，从而减少了射入有源层图案的光线量，减小了有源层图案的伏安特性曲线偏移的程度，从而减弱了光线对薄膜晶体管正常工作的影响程度。
由于目标表面可以为源极图案04中朝向栅绝缘层02的表面、漏极图案05中朝向栅绝缘层02的表面以及栅极图案01中朝向栅绝缘层02的表面中的至少一个表面，因此，目标表面可以具有多种形态，以下将对这多种形态进行解释说明。
在目标表面的第一种形态中，请继续参考图1，源极图案04可以包括：设置在栅绝缘层02远离栅绝缘层02一侧的第一目标图案041，以及设置在第一目标图案041远离栅绝缘层02一侧的第一电极主体图案042；漏极图案05可以包括：设置在栅绝缘层02远离栅绝缘层02一侧的第二目标图案051，以及设置在第二目标图案051远离栅绝缘层02一侧的第二电极主体图案052；第一目标图案041中朝向栅绝缘层02的表面以及第二目标图案052中朝向栅绝缘层02的表面均可以为目标表面X。第一主体图案042和第二主体图案052均 可以与有源层图案03连接，像素电极可以通过与第二电极主体图案052连接，实现与薄膜晶体管的连接。也即是，当光线射入第一目标图案041和第二目标图案051时，光线能够在第一目标图案041和第二目标图案051上的目标表面X上进行漫反射，从而使得部分光线无法射入栅极图案01，更无法被栅极图案01反射至有源层图案03，进而阻止部分光线射入有源层图案03。
可选的，有源层图案03的材质可以为氧化物半导体，第一目标图案041的材质和第二目标图案051的材质均可以为还原态的氧化物半导体。由于还原态的氧化物半导体的表面比较粗糙，因此第一目标图案041和第二目标图案051均可以实现对光线的漫反射。示例的，氧化物半导体可以为铟镓锌氧化物(英文：indium gallium zinc oxide；简称：IGZO)。氧化物半导体作为有源层材料，相比传统的非晶硅材料具有载流子迁移率高、制备温度低、大面积均匀性优良和光学透过率高等优势，这些优势也决定了氧化物薄膜晶体管适用于制备高分辨率的显示器件。
需要说明的是，相关技术中通常采用非晶铟镓锌氧化物制造有源层图案。非晶铟镓锌氧化物是一种典型的透明金属氧化物半导体，在可见光波段具有较好的透光性，在420纳米以上的波长的光照射非晶铟镓锌氧化物材料的有源层图案时，薄膜晶体管的伏安特性曲线较稳定。但是对于波长低于450纳米的紫外光照射时，由于紫外光的能量已经高于非晶铟镓锌氧化物材料的有源层图案的禁带宽度(3.2电子伏特～3.6电子伏特)，因此薄膜晶体管的伏安特性曲线会大幅度漂移，很不稳定。而本发明实施例提供的薄膜晶体管中，目标表面能够对射入目标表面的光线进行漫反射，以阻止部分光线射入有源层图案，从而减少了射入有源层图案的光线量，减小了有源层图案的伏安特性曲线偏移的程度。
图2为本发明实施例提供的一种第一目标图案、第二目标图案与有源层图案的设置位置示意图。为了尽可能的阻止更多的光线进入有源层图案03，第一目标图案041和第二目标图案051均可以围绕有源层图案03设置，如图2所示，第一目标图案041和第二目标图案051分别围绕在有源层图案03的两端。且为了保证有源层图案03的特性不受到第一目标图案041和第二目标图案051的影响，可以设置第一目标图案041和第二目标图案051均与有源层图案03不连接。
在目标表面的第二种形态中，图3-1为本发明实施例提供的另一种薄膜晶 体管的结构示意图，如图3-1所示，栅极图案01可以包括：第三电极主体图案011，以及设置在第三电极主体图案011一侧的第三目标图案012。栅绝缘层02设置在第三目标图案012远离第三电极主体图案011的一侧，第三目标图案012中远离第三电极主体图案011的表面为目标表面X。也即是，当光线射入第三目标图案012时，光线能够在第三目标图案012上的目标表面X上进行漫反射，从而使得部分光线无法射入源层图案03，从而阻止部分光线射入有源层图案03。可选的，第三目标图案012的材质可以为导电材质或绝缘材质，且第三目标图案012远离栅极图案01的表面是凹凸不平的，也即第三目标图案012远离栅极图案01的表面为目标表面X。可选的，第三目标图案012的材质可以与栅绝缘层02的材质相同。
在目标表面的第三种形态中，图3-2为本发明实施例提供的又一种薄膜晶体管的结构示意图，如图3-2所示，源极图案04包括：第一目标图案041和第一电极主体图案042，漏极图案05包括：第二目标图案051和第二电极主体图案052，栅极图案01包括：第三电极主体图案011以及第三目标图案012，且第一目标图案041中朝向栅绝缘层02的表面、第二目标图案051中朝向栅绝缘层02的表面以及第三目标图案012中远离第三电极主体图案011的表面均为目标表面X。
在目标表面的第四种形态中，图3-3为本发明实施例提供的再一种薄膜晶体管的结构示意图，如图3-3所示，源极图案04包括：第一目标图案041和第一电极主体图案042，栅极图案01包括：第三电极主体图案011以及第三目标图案012，且第一目标图案041中朝向栅绝缘层02的表面以及第三目标图案012中远离第三电极主体图案011的表面均为目标表面X。
在目标表面的第五种形态中，图3-4为本发明另一实施例提供的一种薄膜晶体管的结构示意图，如图3-4所示，漏极图案05包括：第二目标图案051和第二电极主体图案052，栅极图案01包括：第三电极主体图案011以及第三目标图案012，且第二目标图案051中朝向栅绝缘层02的表面以及第三目标图案012中远离第三电极主体图案011的表面均为目标表面X。
在目标表面的第六种形态中，图3-5为本发明另一实施例提供的另一种薄膜晶体管的结构示意图，如图3-5所示，源极图案04包括：第一目标图案041和第一电极主体图案042，且第一目标图案041中朝向栅绝缘层02的表面为目标表面X。
在目标表面的第七种形态中，图3-6为本发明另一实施例提供的又一种薄膜晶体管的结构示意图，如图3-6所示，漏极图案05包括：第二目标图案051和第二电极主体图案052，且第二目标图案051中朝向栅绝缘层02的表面为目标表面X。
可选的，本发明实施例提供的薄膜晶体管(如图1、图3-1、图3-2、图3-3、图3-4、图3-5和图3-6所示的薄膜晶体管)均还可以包括钝化层Y，且像素电极Z可以通过钝化层Y上的过孔与源漏极图案04相连接。本发明实施例中以薄膜晶体管设置在衬底基板W上为例，本发明实施例对此不做限定。
综上所述，由于本发明实施例提供的薄膜晶体管中，源极图案中朝向栅绝缘层的表面、漏极图案中朝向栅绝缘层的表面以及栅极图案中朝向栅绝缘层的表面包括目标表面，且目标表面能够对射入目标表面的光线进行漫反射，以阻止部分光线射入有源层图案，从而减少了射入有源层图案的光线量，减小了有源层图案的伏安特性曲线偏移的程度，从而减弱了光线对薄膜晶体管正常工作的影响程度。
图4为本发明另一实施例提供的再一种薄膜晶体管的结构示意图，如图4所示，薄膜晶体管可以包括：栅极图案01、栅绝缘层02、有源层图案03、源漏极图案(包括源极图案04和漏极图案05)以及光吸收图案06。
其中，栅极图案01、栅绝缘层02、有源层图案03以及源漏极图案依次叠加，光吸收图案06设置在栅绝缘层02的至少一侧，光吸收图案06能够对射入光吸收图案06的光线进行吸收，以阻止该光线(即被光吸收图案吸收的光线，如射入薄膜晶体管的全部光线或部分光线)射入有源层图案。
光吸收图案06在栅绝缘层02上的正投影区域为目标区域A，源漏极图案在栅绝缘层02上的正投影区域与有源层图案03在栅绝缘层02上的正投影区域组成参考区域B，目标区域A与参考区域B存在重叠区域。
综上所述，由于本发明实施例提供的薄膜晶体管包括光吸收图案，且光吸收图案在栅绝缘层上的正投影区域为目标区域，源漏极图案在栅绝缘层上的正投影区域和有源层图案在栅绝缘层上的正投影区域组成参考区域，目标区域与参考区域存在重叠区域，从而使得射入有源层与栅极图案之间的光线能够被光吸收图案吸收，减少了射入有源层图案的光线量，减小了有源层图案的伏安特性曲线偏移的程度，从而减弱了光线对薄膜晶体管正常工作的影响程度。
可选的，图4中以光吸收图案06设置在栅绝缘层02靠近栅极图案01的一侧，且光吸收图案06覆盖栅极图案01为例。
实际应用中，图5为本发明又一实施例提供的一种薄膜晶体管的结构示意图，如图5所示，光吸收图案06还可以设置在栅绝缘层02远离栅极图案01的一侧，且位于栅绝缘层02与有源层图案03之间，目标区域A与有源层图案03在栅绝缘层02上的正投影区域重合。
或者，图6为本发明又一实施例提供的另一种薄膜晶体管的结构示意图，如图6所示，光吸收图案06可以设置在栅绝缘层02远离栅极图案01的一侧，且位于栅绝缘层02与源漏极图案之间，目标区域A与有源层图案03在栅绝缘层02上的正投影区域不重叠，且与源漏极图案在栅绝缘层02上的正投影区域存在重叠区域。
示例的，图4和图6中光吸收图案06的材质均可以为黑色导电材质或黑色绝缘材质，如：图4和图6中光吸收图案06的材质可以为炭。图5中光吸收图案06的材质可以为黑色绝缘材质，如：图5中光吸收图案06的材质可以与黑矩阵(英文：Black Matrix；简称：BM)的材质相同。
可选的，图6所示的薄膜晶体管包括两个光吸收图案06，且该两个光吸收图案06分别设置在源极图案和漏极图案的下方。实际应用中，图6所示的薄膜晶体管还可以仅仅包括一个光吸收图案06，该一个光吸收图案06可以设置在源极图案的下方或漏极图案的下方。
进一步的，薄膜晶体管中的光吸收图案还可以同时分布在如图4、图5和图6中至少两个图所示的位置。当光吸收图案还可以同时分布在如图4、图5和图6所示的位置时，薄膜晶体管中源极图案和漏极图案的下方均设置有光吸收图案，栅极的上方设置有光吸收图案，有源层的下方也设置有光吸收图案。此时，该光吸收图案包括：第一部分光吸收图案、第二部分光吸收图案以及第三部分光吸收图案；该第一部分光吸收图案设置在栅绝缘层靠近栅极图案的一侧，且覆盖栅极图案；该第二部分光吸收图案设置在栅绝缘层远离栅极图案的一侧，且位于栅绝缘层与有源层图案之间，目标区域与有源层图案在栅绝缘层上的正投影区域重合；该第三部分光吸收图案设置在栅绝缘层远离栅极图案的一侧，且位于栅绝缘层与源漏极图案之间，目标区域与有源层图案在栅绝缘层上的正投影区域不重叠，且与源漏极图案在栅绝缘层上的正投影区域存在重叠区域。
可选的，图4、图5和图6所示的薄膜晶体管均还可以包括钝化层Y，且像素电极Z可以通过钝化层Y上的过孔与源漏极图案相连接。图4、图5和图6中以薄膜晶体管设置在衬底基板W上为例，本发明实施例对此不做限定。
综上所述，由于本发明实施例提供的薄膜晶体管包括光吸收图案，且光吸收图案在栅绝缘层上的正投影区域为目标区域，源漏极图案在栅绝缘层上的正投影区域和有源层图案在栅绝缘层上的正投影区域组成参考区域，目标区域与参考区域存在重叠区域，从而使得射入有源层与栅极图案之间的光线能够被光吸收图案吸收，减少了射入有源层图案的光线量，减小了有源层图案的伏安特性曲线偏移的程度，从而减弱了光线对薄膜晶体管正常工作的影响程度。
图7为本发明实施例提供的一种薄膜晶体管的制造方法的方法流程图，该薄膜晶体管可以为图1、图3-1、图3-2、图3-3、图3-4、图3-5或图3-6所示的薄膜晶体管，如图7所示，该薄膜晶体管的制造方法可以包括：
步骤701、制造包括依次叠加的栅极图案、栅绝缘层、有源层图案以及源漏极图案的薄膜晶体管，源漏极图案中朝向栅绝缘层的表面、漏极图案中朝向栅绝缘层的表面以及栅极图案中朝向栅绝缘层的表面包括：至少一个目标表面，目标表面能够对射入目标表面的光线进行漫反射，以阻止部分光线射入有源层图案。
综上所述，由于本发明实施例提供的方法所制造的薄膜晶体管中，源极图案中朝向栅绝缘层的表面、漏极图案中朝向栅绝缘层的表面以及栅极图案中朝向栅绝缘层的表面包括目标表面，且目标表面能够对射入目标表面的光线进行漫反射，以阻止部分光线射入有源层图案，从而减少了射入有源层图案的光线的光线量，减小了有源层图案的伏安特性曲线偏移的程度，从而减弱了光线对薄膜晶体管正常工作的影响程度。
图8为本发明实施例提供的另一种薄膜晶体管的制造方法的方法流程图，该薄膜晶体管可以为图1所示的薄膜晶体管，如图8所示，该薄膜晶体管的制造方法可以包括：
步骤801、形成栅极图案。
如图9所示，在步骤801中可以首先采用涂覆、磁控溅射、热蒸发或者等离子体增强化学气相沉积法(英文：Plasma Enhanced Chemical Vapor  Deposition；简称：PECVD)等方法在衬底基板W上沉积一层金属材料，得到金属材质层，然后采用一次构图工艺对该金属材质层进行处理就可以得到栅极图案01。其中，一次构图工艺包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离，因此，采用一次构图工艺对金属材质层进行处理包括：在金属材质层上涂覆一层光刻胶，然后采用掩膜版对光刻胶进行曝光，使光刻胶形成完全曝光区和非曝光区，之后采用显影工艺进行处理，使完全曝光区的光刻胶被去除，非曝光区的光刻胶保留，之后对完全曝光区在金属材质层上的对应区域进行刻蚀，刻蚀完毕后剥离非曝光区的光刻胶即可得到栅极图案01。
步骤802、在栅极图案的一侧形成栅绝缘层。
如图10所示，可以在栅极图案01上涂覆一层栅绝缘层02。
步骤803、在栅绝缘层远离栅极图案的一侧形成有源层图案、第一目标图案和第二目标图案，第一目标图案中朝向栅绝缘层的表面以及第二目标图案中朝向栅绝缘层的表面均为目标表面。
如图11所示，可以首先在栅绝缘层02远离栅极图案01的一侧形成氧化物半导体材质层07，然后，如图12所示，在氧化物半导体材质层06远离栅绝缘层02的一侧形成光刻胶层08。
之后，如图13所示，就可以采用灰度掩膜板(图13中未示出)对光刻胶层08进行曝光处理和显影处理，得到光刻胶图案09，该光刻胶图案08可以包括第一光刻胶区091、两个第二光刻胶区092和光刻胶完全去除区093，且第一光刻胶区091的光刻胶厚度大于第二光刻胶区092的光刻胶厚度。
在得到光刻胶图案09后，如图14所示，可以透过光刻胶图案09对图13中的氧化物半导体材质层07进行刻蚀处理，以去除与光刻胶完全去除区093对应的氧化物半导体，得到与第一光刻胶区091对应的第一氧化物半导体区X1，以及与两个第二光刻胶区092对应的两个第二氧化物半导体区X2。
然后，如图15所示，可以对光刻胶图案进行灰化处理，以去除第二光刻胶区092的光刻胶，以及减薄第一光刻胶区091的光刻胶；
如图16所示，在减薄第一光刻胶区091的光刻胶后，可以对两个第二氧化物半导体区X2的氧化物半导体进行还原处理(如向第二半导体区的氧化物半导体输入还原气体：氢气或氨气)，得到第一目标图案041和第二目标图案051，第一目标图案041的材质和第二目标图案051的材质均可以为还原态的氧化物半导体；
如图17所示，在得到第一目标图案和第二目标图案后，可以剥离第一光刻胶区091的光刻胶，得到有源层图案03，有源层图案03可以包括第一氧化物半导体区091的氧化物半导体。
步骤804、在第一目标图案远离栅绝缘层一侧形成第一电极主体图案，以及在第二目标图案远离栅绝缘层的一侧形成第二电极主体图案。
如图18所示，在得到第一目标图案、第二目标图案和有源层图案后，可以在第一目标图案041远离栅绝缘层02的一侧形成第一电极主体图案042，在第二目标图案051远离栅绝缘层02的一侧形成第二电极主体图案052。
可选的，第一目标图案041中朝向栅绝缘层02的表面以及第二目标图案051中朝向栅绝缘层02的表面均为目标表面X。也即是，当光线射入第一目标图案041和第二目标图案051时，光线能够在第一目标图案041上的目标表面和第二目标图案051上的目标表面上进行漫反射，从而使得部分光线无法射入栅极图案01，更无法被栅极图案反射至有源层图案03，从而阻止部分光线射入有源层图案03。
如图2所示，为了尽可能的阻止更多的光线进入有源层图案03，第一目标图案041和第二目标图案051分别围绕在有源层图案03的两端。且为了保证有源层图案03的特性不受到第一目标图案041和第二目标图案051的影响，可以设置第一目标图案041和第二目标图案051均与有源层图案03不连接。
进一步的，在步骤804之后，还可以在第一电极主体图案042和第二电极主体图案052远离栅绝缘层02的一侧形成如图1所示的钝化层Y。
由于本发明实施例中，第一目标图案的材质为还原态的氧化物半导体，有源层图案的材质为氧化物半导体。因此，可以首先形成氧化物半导体层，然后采用一次构图工艺同时形成第一氧化物半导体区和第二氧化物半导体区。其中的第一氧化物半导体区的氧化物半导体也即是有源层图案。之后，可以仅仅对第二氧化物半导体区的氧化物半导体进行还原处理，得到第一目标图案。也即是，在形成第一目标图案和有源层图案的过程中，仅仅采用了一次构图工艺，因此制造整个薄膜晶体管的速度较快。
综上所述，由于本发明实施例提供的方法所制造的薄膜晶体管中，源极图案中朝向栅绝缘层的表面、漏极图案中朝向栅绝缘层的表面以及栅极图案中朝向栅绝缘层的表面包括目标表面，且目标表面能够对射入目标表面的光线进行漫反射，以阻止部分光线射入有源层图案，从而减少了射入有源层图案的光线 量，减小了有源层图案的伏安特性曲线偏移的程度，从而减弱了光线对薄膜晶体管正常工作的影响程度。
图19为本发明实施例提供的又一种薄膜晶体管的制造方法的方法流程图，该薄膜晶体管可以为图4、图5或图6所示的薄膜晶体管，如图19所示，该薄膜晶体管的制造方法可以包括：
步骤1901、制造包括栅极图案、栅绝缘层、有源层图案、源漏极图案以及光吸收图案的薄膜晶体管；其中，栅极图案、栅绝缘层、有源层图案以及源漏极图案依次叠加，光吸收图案设置在栅绝缘层的至少一侧，光吸收图案能够对射入光吸收图案的光线进行吸收，以阻止光线射入有源层图案；光吸收图案在栅绝缘层上的正投影区域为目标区域，源漏极图案在栅绝缘层上的正投影区域与有源层图案在栅绝缘层上的正投影区域组成参考区域，目标区域与参考区域存在重叠区域。
可选的，当本发明实施例提供的薄膜晶体管的制造方法所制造的薄膜晶体管如图4所示时，光吸收图案06设置在栅绝缘层02靠近栅极图案01的一侧，且光吸收图案06覆盖栅极图案01。此时，该薄膜晶体管的制造方法可以包括：在衬底基板上形成栅极图案；在形成有栅极图案的衬底基板上形成光吸收层；在形成有光吸收层的衬底基板上形成栅绝缘层；在形成有栅绝缘层的衬底基板上形成有源层图案；在形成有有源层图案的衬底基板上形成源漏极图案。
可选的，当本发明实施例提供的薄膜晶体管的制造方法所制造的薄膜晶体管如图5所示时，光吸收图案06还可以设置在栅绝缘层02远离栅极图案01的一侧，且位于栅绝缘层02与有源层图案03之间，目标区域A与有源层图案03在栅绝缘层02上的正投影区域重合。此时，该薄膜晶体管的制造方法可以包括：在衬底基板上形成栅极图案；在形成有栅极图案的衬底基板上形成栅绝缘层；在形成有栅绝缘层的衬底基板上形成光吸收图案，在形成有光吸收图案的衬底基板上形成有源层图案；在形成有有源层图案的衬底基板上形成源漏极图案(包括源极图案和漏极图案)。
可选的，当本发明实施例提供的薄膜晶体管的制造方法所制造的薄膜晶体管如图6所示时，光吸收图案06可以设置在栅绝缘层02远离栅极图案01的一侧，且位于栅绝缘层02与源漏极图案之间，目标区域A与有源层图案03在栅绝缘层02上的正投影区域不重叠，且与源漏极图案在栅绝缘层02上的正 投影区域存在重叠区域，该薄膜晶体管的制造方法可以包括：在衬底基板上形成栅极图案；在形成有栅极图案的衬底基板上形成栅绝缘层；在形成有栅绝缘层的衬底基板上形成光吸收图案，在形成有光吸收图案的衬底基板上形成有源层图案；在形成有有源层图案的衬底基板上形成源漏极图案。
需要说明的是，无论制造的薄膜晶体管如图4、图5还是图6所示，均需要保证目标区域与参考区域存在重叠区域，从而能够保证光吸收图案能够吸收即将要射入有源层图案的光线。
综上所述，由于本发明实施例提供的方法所制造的薄膜晶体管包括光吸收图案，且光吸收图案在栅绝缘层上的正投影区域为目标区域，源漏极图案在栅绝缘层上的正投影区域和有源层图案在栅绝缘层上的正投影区域组成参考区域，目标区域与参考区域存在重叠区域，从而使得射入有源层与栅极图案之间的光线能够被光吸收图案吸收，减少了射入有源层图案的光线量，减小了有源层图案的伏安特性曲线偏移的程度，从而减弱了光线对薄膜晶体管正常工作的影响程度。
如图20所示，本发明实施例提供了一种阵列基板，该阵列基板可以包括衬底基板W，以及形成在衬底基板W上阵列排布的多个薄膜晶体管0，该多个薄膜晶体管中的每个薄膜晶体管均可以为图1至图6任一所示的薄膜晶体管。
本发明实施例提供了一种显示面板，该显示面板可以包括图20所示的阵列基板，该显示面板可以为液晶显示面板或有机发光二极管显示面板，本发明实施例对此不作限定。
本发明实施例提供了一种显示装置，该显示装置可以包括图20所示的阵列基板。示例的，该显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要说明的是，本发明实施例提供的薄膜晶体管实施例、薄膜晶体管的制造方法实施例、阵列基板实施例、显示面板实施例以及显示装置实施例均可以互相参考，本发明实施例对此不做限定。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其 他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (16)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管包括：依次叠加的栅极图案、栅绝缘层、有源层图案、源极图案以及漏极图案，
    所述源极图案中朝向所述栅绝缘层的表面、所述漏极图案中朝向所述栅绝缘层的表面以及所述栅极图案中朝向所述栅绝缘层的表面中存在至少一个表面为目标表面，所述目标表面能够对射入所述目标表面的光线进行漫反射，以阻止部分光线射入所述有源层图案。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述源极图案包括：设置在所述栅绝缘层远离所述栅极图案一侧的第一目标图案，以及设置在所述第一目标图案远离所述栅极图案一侧的第一电极主体图案；
    所述漏极图案包括：设置在所述栅绝缘层远离所述栅极图案一侧的第二目标图案，以及设置在所述第二目标图案远离所述栅极图案一侧的第二电极主体图案；
    所述第一目标图案中朝向所述栅绝缘层的表面，以及所述第二目标图案中朝向所述栅绝缘层的表面均为所述目标表面，所述第一电极主体图案和所述第二电极主体图案均与所述有源层图案相连接。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述有源层图案的材质为氧化物半导体，所述第一目标图案的材质和所述第二目标图案的材质均为还原态的氧化物半导体，
    所述第一目标图案和所述第二目标图案分别围绕在所述有源层图案的两端，且与所述有源层图案不连接。
  4. 根据权利要求1至3任一所述的薄膜晶体管，其中，所述栅极图案包括：第三电极主体图案，以及设置在所述第三电极主体图案一侧的第三目标图案，所述栅绝缘层设置在所述第三目标图案远离所述第三电极主体图案的一侧，所述第三目标图案中远离所述第三电极主体图案的表面为所述目标表面。
  5. 一种薄膜晶体管，其中，所述薄膜晶体管包括：栅极图案、栅绝缘层、 有源层图案、源漏极图案以及光吸收图案，
    其中，所述栅极图案、所述栅绝缘层、所述有源层图案以及所述源漏极图案依次叠加，所述光吸收图案设置在所述栅绝缘层的至少一侧，所述光吸收图案能够对射入所述光吸收图案的光线进行吸收，以阻止所述光线射入所述有源层图案；
    所述光吸收图案在所述栅绝缘层上的正投影区域为目标区域，所述源漏极图案在所述栅绝缘层上的正投影区域与所述有源层图案在所述栅绝缘层上的正投影区域组成参考区域，所述目标区域与所述参考区域存在重叠区域。
  6. 根据权利要求5所述的薄膜晶体管，其中，所述光吸收图案设置在所述栅绝缘层靠近所述栅极图案的一侧，且所述光吸收图案覆盖所述栅极图案；
    或者，所述光吸收图案设置在所述栅绝缘层远离所述栅极图案的一侧，且位于所述栅绝缘层与所述有源层图案之间，所述目标区域与所述有源层图案在所述栅绝缘层上的正投影区域重合；
    或者，所述光吸收图案设置在所述栅绝缘层远离所述栅极图案的一侧，且位于所述栅绝缘层与所述源漏极图案之间，所述目标区域与所述有源层图案在所述栅绝缘层上的正投影区域不重叠，且与所述源漏极图案在所述栅绝缘层上的正投影区域存在重叠区域。
  7. 一种薄膜晶体管的制造方法，其中，所述方法包括：
    制造包括依次叠加的栅极图案、栅绝缘层、有源层图案、源极图案以及漏极图案的薄膜晶体管，所述源极图案中朝向所述栅绝缘层的表面、所述漏极图案中朝向所述栅绝缘层的表面以及所述栅极图案中朝向所述栅绝缘层的表面中，存在至少一个表面为目标表面，所述目标表面能够对射入所述目标表面的光线进行漫反射，以阻止部分光线射入所述有源层图案。
  8. 根据权利要求7所述的方法，其中，所述制造包括依次叠加的栅极图案、栅绝缘层、有源层图案、源极图案以及漏极图案的薄膜晶体管，包括：
    形成栅极图案；
    在所述栅极图案的一侧形成所述栅绝缘层；
    在所述栅绝缘层远离所述栅极图案的一侧形成所述有源层图案、第一目标 图案和第二目标图案，所述第一目标图案中朝向所述栅绝缘层的表面，以及所述第二目标图案中朝向所述栅绝缘层的表面均为所述目标表面；
    在所述第一目标图案远离所述栅极图案一侧形成第一电极主体图案，以及在所述第二目标图案远离所述栅绝缘层的一侧形成第二电极主体图案，所述第一电极主体图案和所述第二电极主体图案均与所述有源层图案相连接，所述源极图案包括：所述第一目标图案和所述第一电极主体图案，所述漏极图案包括：所述第二目标图案和所述第二电极主体图案。
  9. 根据权利要求8所述的方法，其中，所述在所述栅绝缘层远离所述栅极图案的一侧形成所述有源层图案、第一目标图案和第二目标图案，包括：
    在所述栅绝缘层远离所述栅极图案的一侧形成氧化物半导体材质层；
    在所述氧化物半导体材质层远离所述栅极图案的一侧形成光刻胶层；
    采用灰度掩膜板对所述光刻胶层进行曝光处理和显影处理，得到光刻胶图案，所述光刻胶图案包括第一光刻胶区、两个第二光刻胶区和光刻胶完全去除区，且所述第一光刻胶区的光刻胶厚度大于所述第二光刻胶区的光刻胶厚度；
    透过所述光刻胶图案对所述氧化物半导体材质层进行刻蚀处理，以去除与所述光刻胶完全去除区对应的氧化物半导体，得到与所述第一光刻胶区对应的第一氧化物半导体区，以及与所述两个第二光刻胶区对应的两个第二氧化物半导体区；
    对所述光刻胶图案进行灰化处理，以去除所述两个第二光刻胶区的光刻胶，以及减薄所述第一光刻胶区的光刻胶；
    对所述两个第二氧化物半导体区的氧化物半导体进行还原处理，得到所述第一目标图案和所述第二目标图案，所述第一目标图案的材质和所述第二目标图案的材质均为还原态的氧化物半导体；
    剥离所述第一光刻胶区的光刻胶，得到所述有源层图案，所述有源层图案包括所述第一氧化物半导体区的氧化物半导体。
  10. 根据权利要求9所述的方法，其中，所述第一目标图案和所述第二目标图案分别围绕在所述有源层图案的两端，且与所述有源层图案不连接。
  11. 根据权利要求7至10任一所述的方法，其中，所述制造包括依次叠加 的栅极图案、栅绝缘层、有源层图案、源极图案以及漏极图案的薄膜晶体管，包括：
    形成第三电极主体图案；
    在第三电极主体图案的一侧形成第三目标图案，所述第三目标图案中远离所述第三电极主体图案的表面为所述目标表面，所述栅极图案包括：所述第三电极主体图案和所述第三目标图案；
    在所述第三目标图案远离所述第三电极主体的一侧形成所述栅绝缘层；
    在所述栅绝缘层远离所述第三电极主体图案的一侧形成所述有源层图案；
    在所述有源层图案远离所述栅极图案一侧形成所述源极图案和所述漏极图案。
  12. 一种薄膜晶体管的制造方法，其中，所述方法包括：
    制造包括栅极图案、栅绝缘层、有源层图案、源漏极图案以及光吸收图案的薄膜晶体管；
    其中，所述栅极图案、所述栅绝缘层、所述有源层图案以及所述源漏极图案依次叠加，所述光吸收图案设置在所述栅绝缘层的至少一侧，所述光吸收图案能够对射入所述光吸收图案的光线进行吸收，以阻止所述光线射入所述有源层图案；
    所述光吸收图案在所述栅绝缘层上的正投影区域为目标区域，所述源漏极图案在所述栅绝缘层上的正投影区域与所述有源层图案在所述栅绝缘层上的正投影区域组成参考区域，所述目标区域与所述参考区域存在重叠区域。
  13. 根据权利要求12所述的方法，其中，所述光吸收图案设置在所述栅绝缘层靠近所述栅极图案的一侧，且所述光吸收图案覆盖所述栅极图案；
    或者，所述光吸收图案设置在所述栅绝缘层远离所述栅极图案的一侧，且位于所述栅绝缘层与所述有源层图案之间，所述目标区域与所述有源层图案在所述栅绝缘层上的正投影区域重合；
    或者，所述光吸收图案设置在所述栅绝缘层远离所述栅极图案的一侧，且位于所述栅绝缘层与所述源漏极图案之间，所述目标区域与所述有源层图案在所述栅绝缘层上的正投影区域不重叠，且与所述源漏极图案在所述栅绝缘层上的正投影区域存在重叠区域。
  14. 一种阵列基板，其中，所述阵列基板包括权利要求1至6任一所述的薄膜晶体管。
  15. 一种显示装置，其中，所述显示装置包括权利要求14所述的阵列基板。
  16. 一种显示面板，其中，所述显示面板包括权利要求14所述的阵列基板。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113097227A (zh) * 2021-03-22 2021-07-09 北海惠科光电技术有限公司 薄膜晶体管、显示装置以及薄膜晶体管制备方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107123687B (zh) * 2017-05-11 2020-03-13 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、阵列基板、显示装置
CN110364566B (zh) * 2019-07-19 2023-07-25 京东方科技集团股份有限公司 晶体管及其制作方法、晶体管器件、显示基板及装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002303883A (ja) * 2001-04-06 2002-10-18 Matsushita Electric Ind Co Ltd 半透過型アクティブ素子アレイ基板及びその製造方法
US20100038648A1 (en) * 2008-08-12 2010-02-18 Samsung Electronics Co., Ltd. Thin film transistor array panel and method of manufacturing the same
CN104716197A (zh) * 2015-03-25 2015-06-17 京东方科技集团股份有限公司 一种氧化物薄膜晶体管及制作方法和阵列基板、显示装置
CN106057909A (zh) * 2016-07-22 2016-10-26 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置
CN106328714A (zh) * 2016-08-12 2017-01-11 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置
CN106653776A (zh) * 2017-01-20 2017-05-10 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN107123687A (zh) * 2017-05-11 2017-09-01 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、阵列基板、显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5784479B2 (ja) * 2010-12-28 2015-09-24 株式会社半導体エネルギー研究所 半導体装置
KR101851565B1 (ko) * 2011-08-17 2018-04-25 삼성전자주식회사 트랜지스터와 그 제조방법 및 트랜지스터를 포함하는 전자소자
CN106229344B (zh) 2016-08-19 2019-10-15 京东方科技集团股份有限公司 薄膜晶体管、其制备方法及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002303883A (ja) * 2001-04-06 2002-10-18 Matsushita Electric Ind Co Ltd 半透過型アクティブ素子アレイ基板及びその製造方法
US20100038648A1 (en) * 2008-08-12 2010-02-18 Samsung Electronics Co., Ltd. Thin film transistor array panel and method of manufacturing the same
CN104716197A (zh) * 2015-03-25 2015-06-17 京东方科技集团股份有限公司 一种氧化物薄膜晶体管及制作方法和阵列基板、显示装置
CN106057909A (zh) * 2016-07-22 2016-10-26 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置
CN106328714A (zh) * 2016-08-12 2017-01-11 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置
CN106653776A (zh) * 2017-01-20 2017-05-10 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN107123687A (zh) * 2017-05-11 2017-09-01 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、阵列基板、显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113097227A (zh) * 2021-03-22 2021-07-09 北海惠科光电技术有限公司 薄膜晶体管、显示装置以及薄膜晶体管制备方法

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