WO2015035615A1 - 一种薄膜晶体管开关及其制造方法 - Google Patents

一种薄膜晶体管开关及其制造方法 Download PDF

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WO2015035615A1
WO2015035615A1 PCT/CN2013/083484 CN2013083484W WO2015035615A1 WO 2015035615 A1 WO2015035615 A1 WO 2015035615A1 CN 2013083484 W CN2013083484 W CN 2013083484W WO 2015035615 A1 WO2015035615 A1 WO 2015035615A1
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Prior art keywords
gate
electrode
switch
semiconductor layer
drain
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English (en)
French (fr)
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杜鹏
陈政鸿
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to KR1020167009187A priority Critical patent/KR101894163B1/ko
Priority to JP2016539383A priority patent/JP6279086B2/ja
Priority to GB1603048.8A priority patent/GB2533717B/en
Priority to RU2016113118A priority patent/RU2634088C2/ru
Priority to US14/119,189 priority patent/US9680025B2/en
Publication of WO2015035615A1 publication Critical patent/WO2015035615A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a thin film transistor switch and a method of fabricating the same.
  • the conventional switching TFT for detecting a line has only three electrodes: G (gate), D (drain), and S (source).
  • G gate
  • D drain
  • S source
  • FIG 1 is a leakage circuit diagram of the switching TFT, as shown in Figure 1, if a shorting bar is used (shorting Bar)
  • shorting Bar When designing, the connection between the drains 11 and 14 of the two TFTs is shorting Bar, the sources 12, 15 of the two TFTs are connected to different scan lines (GL) or data lines (DL).
  • the two gates 13, 16 are connected to a low voltage to turn off the two TFTs. If leakage occurs at this time, the leakage current can pass through the two TFTs and the shorting bar, thereby causing short circuits between different scanning lines or data lines, that is, different signals. A short circuit between them has an adverse effect on the display.
  • the technical problem to be solved by the present invention is to provide a thin film transistor switch and a method of manufacturing the same, which can reduce leakage current in a channel when the switch is in a closed state, and improve the characteristics of the switch.
  • an embodiment of the present invention provides a thin film transistor switch including a gate, a drain, a source, a semiconductor layer, and a fourth electrode.
  • the drain is connected to the first signal
  • the gate is connected to the control signal to control the switch. Turning on or off, the source outputs a first signal when the switch is turned on, the fourth electrode and the gate are respectively disposed on both sides of the source and the drain, and the fourth electrode is a conductive material, which connects different potentials as needed .
  • the gate and the fourth electrode are connected to a high potential.
  • the potential of the fourth electrode is the same as the potential of the gate.
  • the potential of the fourth electrode is different from the potential of the gate.
  • the switch further includes a gate insulating layer disposed on the gate, a semiconductor layer disposed on the gate insulating layer, a drain and a source disposed on the semiconductor layer, and a passivation layer disposed thereon, fourth The electrode is disposed on the passivation layer.
  • the gate is connected to a low potential
  • the fourth electrode is connected to a high potential to conduct electrons accumulated in the semiconductor layer and away from the gate side, and then the fourth electrode is connected to a low potential.
  • the fourth electrode when the fourth electrode is connected to a low potential, its potential is the same as the potential of the gate.
  • the fourth electrode when the fourth electrode is connected to a low potential, the potential thereof is different from the potential of the gate.
  • the switch further includes a gate insulating layer disposed on the gate, a drain and a source disposed on the gate insulating layer, a semiconductor layer disposed thereon, and a fourth electrode disposed on the semiconductor layer
  • the passivation layer is disposed on the periphery of the fourth electrode.
  • the first signal is a test signal, and the source is connected to a scan line or a data line to be tested.
  • an embodiment of the present invention provides a method for fabricating a thin film transistor switch, comprising: sequentially forming a gate and a gate insulating layer on a substrate, and the gate is used for connecting a control signal to control the conduction of the switch or Turning off; forming a semiconductor layer on the gate insulating layer; forming a drain and a source on the semiconductor layer and covering a passivation layer, a drain for connecting the first signal; and a fourth electrode on the passivation layer, The four electrodes are used to connect different potentials as needed.
  • an embodiment of the present invention provides a method for fabricating a thin film transistor switch, comprising: sequentially forming a gate and a gate insulating layer on a substrate, and the gate is used for connecting a control signal to control the conduction of the switch or Off; a drain and a source are respectively formed on the gate insulating layer, a drain is used to connect the first signal; a semiconductor layer is formed on the drain and the source and is in contact with the gate insulating layer; and a fourth electrode is formed on the semiconductor layer, A passivation layer is covered around the fourth electrode, and the fourth electrode is used to connect different potentials as needed.
  • the beneficial effects of the present invention are: a thin film transistor switch by adding a fourth electrode on the basis of a conventional gate, drain, and source, and the drain is connected to the first signal, and the gate is connected to the control signal to control
  • the source outputs a first signal when the switch is turned on
  • the fourth electrode and the gate are respectively disposed on two sides of the semiconductor layer, and the fourth electrode is a conductive material, and can connect different potentials as needed
  • the leakage current in the channel is reduced when the switch is in the off state, improving the characteristics of the switch.
  • 1 is a leakage circuit diagram of a thin film transistor switch in the prior art
  • FIG. 2 is a schematic view showing the symbol of a thin film transistor switch according to a first embodiment of the present invention
  • FIG. 3 is a schematic structural view of a thin film transistor switch according to a first embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a thin film transistor switch according to a second embodiment of the present invention.
  • FIG. 5 is a schematic view showing a manufacturing method of a thin film transistor switch according to a first embodiment of the present invention
  • Fig. 6 is a view showing a method of manufacturing a switch of a thin film transistor of a second embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a symbol of a thin film transistor switch according to a first embodiment of the present invention.
  • the thin film transistor switch 20 of the embodiment of the present invention includes a gate G, a drain D, a source S, a semiconductor layer 23 disposed between the gate G, the drain D, and the source S, and a fourth Electrode B.
  • the drain D is connected to the first signal
  • the gate G is connected to the control signal to control the on or off of the switch 20.
  • the switch 20 is turned on, the source S outputs the first signal
  • the fourth electrode B and the gate G are respectively disposed on the semiconductor layer. Both sides of 23, and the fourth electrode B is connected to different potentials as needed.
  • the gate G, the drain D, the source S, and the fourth electrode B are conductive materials.
  • the thin film transistor switch 20 can be applied to different circuits, such as a pixel electrode region or a test line or a peripheral wiring of a TFT of an active matrix liquid crystal display, preferably applied to a test line.
  • the first signal connected to the drain D is a test signal
  • the source S is connected to the line to be tested, wherein the test line may be the data line DL or the scan line GL.
  • the following is an example of a thin film transistor switch applied to a test line.
  • the gate D and the fourth electrode B are connected to a high potential.
  • the potential of the fourth electrode B and the potential of the gate D may be the same or different. It is worth noting that when the potentials of the two are not the same, the potential difference between the two should not be too large.
  • the switch 20 starts to be turned off, the gate D is connected to a low potential, and the fourth electrode B is connected to different potentials according to the test to guide the leakage current away from the gate D side of the semiconductor layer 23, and then the fourth electrode B is also connected to the low potential.
  • the potential of the fourth electrode B and the potential of the gate D may be the same or different. It is worth noting that when the potentials of the two are not the same, the potential difference between the two should not be too large.
  • FIG. 3 is a schematic structural view of a thin film transistor switch of a first embodiment of the present invention.
  • the switch 20 is provided with a gate G on the substrate 21, the gate insulating layer 22 is disposed on the gate G, the semiconductor layer 23 is disposed on the gate insulating layer 22, and the drain D and the source S are both disposed.
  • a PAV layer is used in the middle (Passivating Layer, passivation layer 24 is spaced apart, while PAV layer 24 also covers the entire plane, and fourth electrode B is disposed on the PAV layer, specifically, directly above the interval between drain D and source S, and extends at both ends Up to the drain D and the source S.
  • An n+ layer 25 having a higher electron concentration is disposed between the drain D and the source S and the semiconductor layer 22, which respectively belong to a portion of the drain D or the source S, and the n+ layer 25 can greatly reduce the turn-on of the switch 20. Channel resistance.
  • the gate G and the drain D and the source S are respectively located on both sides of the semiconductor layer 23.
  • the switch 20 When the switch 20 is turned off, the gate G is connected to a low potential, and the fourth electrode B is connected to a high potential to conduct electrons accumulated in the semiconductor layer 23 and away from the gate G side, thereby reducing leakage current.
  • the fourth electrode B is then connected to a low potential.
  • the connected low potential of the fourth electrode B and the potential of the gate D may be the same or different. It is worth noting that when the potentials of the two are not the same, the potential difference between the two should not be too large.
  • the fourth electrode B is changed from a high potential to a low potential, and the voltage of the gate G is changed from a high potential to a low potential when the switch 20 is turned off. Therefore, the semiconductor 23 is concentrated in the electron and semiconductor layer 23 away from the gate G side. Electrons near the gate G side are discharged.
  • FIG. 4 is a schematic structural view of a thin film transistor switch of a second embodiment of the present invention.
  • the switch 30 is provided with a gate G on the substrate 31, the gate insulating layer 32 is disposed on the gate G, and the drain D and the source S are both disposed on the gate insulating layer 32, the drain D and the source.
  • the pole S is interposed with the semiconductor layer 33 while the semiconductor layer 33 also covers the entire drain D and source S.
  • the fourth electrode B is disposed on the semiconductor layer 33, specifically, directly above the interval between the drain D and the source S, and both ends extend above the drain D and the source S, but not all cover the entire drain Pole D and source S.
  • the PAV layer 34 is covered elsewhere in the plane, that is, the PAV layer 34 is disposed on the periphery of the fourth electrode B, and the PAV layer 34 is spaced apart from the fourth electrode B by a certain interval.
  • An n+ layer 35 having a higher electron concentration is disposed between the drain D and the source S and the semiconductor layer 32, respectively belonging to a portion of the drain D or the source S, and the n+ layer 35 can greatly reduce the conduction of the switch 30.
  • the gate G, the drain D, the source S, and the fourth electrode B are conductive materials.
  • the gate G and the drain D and the source S are respectively located on the same side of the semiconductor layer 33, and the fourth electrode B and the gate G are respectively disposed on both sides of the semiconductor layer 33.
  • the switch 30 When the switch 30 is turned off, the gate G is connected to a low potential, and the fourth electrode B is connected to conduct electrons accumulated in the semiconductor 33 layer and away from the gate G side, thereby reducing leakage current.
  • the fourth electrode B When the fourth electrode B is connected to the low potential, since it is in direct contact with the semiconductor layer 33, electrons in the semiconductor layer 33 away from the gate G side, that is, electrons close to the fourth electrode B are directly guided through the fourth electrode B.
  • the potential connected to the fourth electrode B and the potential of the gate D may be the same or different. It is worth noting that when the potentials of the two are not the same, the potential difference between the two should not be too large.
  • FIG. 5 is a schematic diagram of a method of manufacturing a thin film transistor switch according to a first embodiment of the present invention. As shown in FIG. 5, the manufacturing method of the thin film transistor switch includes the following steps:
  • Step S101 sequentially forming a gate and a gate insulating layer on the substrate, and the gate is used to connect a control signal to control the on or off of the switch.
  • Step S102 fabricating a semiconductor layer on the gate insulating layer.
  • Step S103 respectively forming a drain and a source on the semiconductor layer and covering a passivation layer, and the drain is used to connect the first signal.
  • the first signal is a test signal
  • the source is used to connect the circuit to be tested.
  • the test line can be a data line or a scan line.
  • Step S104 forming a fourth electrode on the passivation layer, and the fourth electrode is used to connect different potentials as needed.
  • the gate and drain and the source are located on both sides of the semiconductor layer.
  • the fourth electrode and the gate are connected to a high voltage, and the voltages of the two electrodes may be the same or different.
  • the switch is turned off, the gate is connected to a low voltage, and the fourth electrode is connected to a high voltage to conduct electrons away from the gate side of the semiconductor layer to reduce leakage current.
  • the fourth electrode is also connected to a low voltage, and the voltage thereof may be the same as or different from the voltage connected to the gate. It is worth noting that when the potentials of the two are not the same, the potential difference between the two should not be too large.
  • FIG. 6 is a schematic diagram of a method of manufacturing a thin film transistor switch according to a second embodiment of the present invention. As shown in FIG. 6, the manufacturing method of the thin film transistor switch includes the following steps:
  • Step S201 sequentially forming a gate and a gate insulating layer on the substrate, and the gate is used to connect a control signal to control the on or off of the switch.
  • Step S202 respectively forming a drain and a source on the gate insulating layer, and a drain for connecting the first signal.
  • the first signal is a test signal
  • the source is used to connect the circuit to be tested
  • the test circuit may be a data line or a scan line.
  • Step S203 The semiconductor layer is formed on the drain and the source and in contact with the gate insulating layer.
  • Step S204 The fourth electrode is formed on the semiconductor layer, and a passivation layer is covered around the fourth electrode, and the fourth electrode is used to connect different potentials as needed.
  • the gate and drain and the source are on the same side of the semiconductor layer.
  • the fourth electrode and the gate are connected to a high voltage, and the voltages of the two electrodes may be the same or different.
  • the switch is turned off, the gate is connected to a low voltage, and the fourth electrode is grounded to conduct electrons away from the gate side of the semiconductor layer to reduce leakage current.
  • the potential connected to the fourth electrode and the potential of the gate may be the same or different. It is worth noting that when the potentials of the two are not the same, the potential difference between the two should not be too large.
  • the present invention has a thin film transistor switch including a gate, a drain, a source, and a fourth electrode, the drain is connected to the first signal, and the gate is connected to the control signal to control the on or off of the switch.
  • the source When the current is turned on, the source outputs a first signal, the fourth electrode and the gate are respectively disposed on both sides of the source and the drain, and the fourth electrode is a conductive material, and the different potentials are connected according to the need, and the switch can be turned off.
  • the leakage current in the channel is reduced, the characteristics of the switch are improved.

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  • Thin Film Transistor (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Automation & Control Theory (AREA)
  • Liquid Crystal (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

一种薄膜晶体管（20）开关及其制作方法，开关包括栅极G、漏极D、源极S、半导体层（23）以及第四电极B，漏极D连接第一信号，栅极G连接控制信号以控制开关的导通或关闭，开关导通时源极S输出所述第一信号，第四电极B和栅极G分别设置于半导体层（23）的两侧，且第四电极B为导电材料，其根据需要连接不同的电位。通过上述方式，能够在开关处于关闭状态时降低沟道中的漏电流，改善开关的特性。

Description

一种薄膜晶体管开关及其制造方法
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种薄膜晶体管开关及其制造方法。
【背景技术】
在液晶显示面板的检测中，检测线路常用的设计方法有两种，一种是检测线路和面板内显示区的扫描线或数据线直接相连，采用这种方式的设计在检测完毕后需要进行激光切割（Laser cut）把测试线路和显示区内的线路切断。第二种方式是测试线路和显示区的信号线通过一个TFT (Thin Film Transistor，薄膜场效应晶体管)的开关连接，检测时TFT的栅极侧加高电压，此时开关处于导通状态，信号能够进入显示区。当面板正常工作时，TFT的栅极侧加低电压，此时开关关闭，测试线路和扫描线或数据线的连接断开，省去了laser cut这道制程。
传统的用于检测线路的开关TFT只有3个电极：G（栅极）、D（漏极）、S（源极）。TFT在面板正常工作时长期处于栅电极为负偏压的状态，可能导致TFT中半导体层的电学特性发生变化，漏电流增大。图1是开关TFT的漏电线路图，如图1所示，如果采用短路棒（shorting bar）设计的时候，两个TFT的漏极11、14之间连接shorting bar，两个TFT的源极12、15连接不同的扫描线（GL）或者数据线（DL）。两个栅极13、16接低电压以使两个TFT关闭，如果此时发生漏电，漏电流能通过两个TFT以及短路棒，进而造成不同扫描线或者数据线之间的短路，即不同信号之间的短路，对显示产生不良影响。
【发明内容】
本发明解决的技术问题是提供一种薄膜晶体管开关及其制造方法，能够在开关处于关闭状态时降低沟道中的漏电流，改善开关的特性。
为解决上述技术问题，本发明实施例提供了一种薄膜晶体管开关，包括栅极、漏极、源极、半导体层以及第四电极，漏极连接第一信号，栅极连接控制信号以控制开关的导通或关闭，开关导通时源极输出第一信号，第四电极和栅极分别设置于源极和漏极的两侧，且第四电极为导电材料，其根据需要连接不同的电位。
其中，开关导通时，栅极和第四电极接高电位。
其中，第四电极的电位与栅极的电位相同。
其中，第四电极的电位与栅极的电位不相同。
其中，开关还包括栅绝缘层以及钝化层，栅绝缘层设置在栅极上，半导体层设置在栅绝缘层上，漏极和源极设置在半导体层上，上面设置钝化层，第四电极设置在钝化层上，开关关闭时，栅极接低电位，第四电极连接高电位以导走积累在半导体层中且远离栅极侧的电子，之后第四电极接低电位。
其中，第四电极接低电位时，其电位与栅极的电位相同。
其中，第四电极接低电位时，其电位与栅极的电位不相同。
其中，开关还包括栅绝缘层以及钝化层，栅绝缘层设置在栅极上，漏极和源极设置在所述栅绝缘层上，上面设置半导体层，第四电极设置在半导体层上，钝化层设置在第四电极的外围，开关关闭时，栅极接低电位，第四电极接地以导走积累在半导体层中且远离栅极侧的电子。
其中，第一信号为测试信号，源极连接待测试的扫描线或数据线。
为解决上述技术问题，本发明实施例提供了另一种薄膜晶体管开关的制造方法，包括：依次在基底上制作栅极和栅绝缘层，栅极用于连接控制信号以控制开关的导通或关闭；在栅绝缘层上制作一半导体层；在半导体层上分别制作漏极和源极并覆盖一钝化层，漏极用于连接第一信号；在钝化层上制作第四电极，第四电极用于根据需要连接不同的电位。
为解决上述技术问题，本发明实施例提供了又一种薄膜晶体管开关的制造方法，包括：依次在基底上制作栅极和栅绝缘层，栅极用于连接控制信号以控制开关的导通或关闭；在栅绝缘层上分别制作漏极和源极，漏极用于连接第一信号；半导体层制作在漏极和源极上并与栅绝缘层接触；第四电极制作在半导体层上，并在第四电极的周围覆盖钝化层，第四电极用于根据需要连接不同的电位。
通过上述方案，本发明的有益效果是：一种薄膜晶体管开关通过在传统的栅极、漏极、源极基础上增加第四电极，并且漏极连接第一信号，栅极连接控制信号以控制开关的导通或关闭，开关导通时源极输出第一信号，第四电极和栅极分别设置于半导体层的两侧，且第四电极为导电材料，并根据需要连接不同的电位，能够在开关处于关闭状态时降低沟道中的漏电流，改善开关的特性。
【附图说明】
图1是现有技术中薄膜晶体管开关的漏电线路图；
图2是本发明第一实施例的薄膜晶体管开关的符号示意图；
图3是本发明第一实施例的薄膜晶体管开关的结构示意图；
图4是本发明第二实施例的薄膜晶体管开关的结构示意图；
图5是本发明第一实施例的薄膜晶体管开关的制造方法示意图；
图6是本发明第二实施例的薄膜晶体管的开关的制造方法示意图。
【具体实施方式】
请参阅图2，图2是本发明第一实施例的薄膜晶体管开关的符号示意图。如图2所示，本发明实施例的薄膜晶体管开关20包括栅极G、漏极D、源极S、设置在栅极G、漏极D、源极S之间的半导体层23以及第四电极B。漏极D连接第一信号，栅极G连接控制信号以控制开关20的导通或关闭，开关20导通时源极S输出第一信号，第四电极B和栅极G分别设置于半导体层23的两侧，且第四电极B根据需要连接不同的电位。其中，栅极G、漏极D、源极S以及第四电极B为导电材料。
在本实施例中，薄膜晶体管开关20可以应用到不同的电路中，如像素电极区域或者测试线路或者主动式矩阵液晶显示器的TFT的周边布线中，优选为应用于测试线路。此时，漏极D连接的第一信号为测试信号，源极S连接待测试线路，其中，测试线路可以是数据线DL或者扫描线GL。以下以应用于测试线路的薄膜晶体管开关为例进行说明。
在本实施例中，开关20导通时，栅极D和第四电极B接高电位，此时第四电极B的电位与栅极D的电位可以相同，也可以不相同。值得注意的是，当两者电位不相同时，两者的电位相差不应太大。在开关20开始关闭时，栅极D接低电位，第四电极B根据测试需要连接不同的电位以导走半导体层23中远离栅极D侧的漏电流，之后第四电极B也接低电位，第四电极B的电位与栅极D的电位也可以相同，或者不相同。值得注意的是，当两者电位不相同时，两者的电位相差不应太大。
图3是本发明第一实施例的薄膜晶体管开关的结构示意图。如图3所示，开关20在衬底21上设置栅极G，栅绝缘层22设置在栅极G上，半导体层23设置在栅绝缘层22上，漏极D和源极S都设置在半导体层23上，中间用PAV层（Passivating Layer，钝化层）24间隔开，同时PAV层24还覆盖整个平面，第四电极B设置在PAV层上，具体地，在漏极D和源极S间隔处的正上方，并且两端延伸至漏极D和源极S的上方。漏极D和源极S与半导体层22之间各设置一电子浓度较高的n+层25，其分别属于漏极D或源极S的一部分，该n+层25可以大大降低开关20导通时的沟道电阻。
在本实施例中，栅极G与漏极D以及源极S分别位于半导体层23的两侧。开关20关闭时，栅极G接低电位，第四电极B连接高电位以导走积累在半导体层23中且远离栅极G侧的电子，减少漏电流。之后第四电极B接低电位。第四电极B的所接的低电位与栅极D的电位可以相同，或者不相同。值得注意的是，当两者电位不相同时，两者的电位相差不应太大。第四电极B由高电位变到低电位，与开关20关闭时栅极G的电压由高电位变换到低电位类似，因此，半导体23中聚集在远离栅极G侧的电子与半导体层23中靠近栅极G侧的电子一样会被排出。
图4是本发明第二实施例的薄膜晶体管开关的结构示意图。如图4所示，开关30在衬底31上设置栅极G，栅绝缘层32设置在栅极G上，漏极D和源极S都设置在栅绝缘层32上，漏极D和源极S中间用半导体层33间隔开，同时半导体层33还覆盖整个漏极D和源极S。第四电极B设置在半导体层33上，具体地，在漏极D和源极S间隔处的正上方，并且两端延伸至漏极D和源极S的上方，但并不全部覆盖整个漏极D和源极S。在平面的其它地方都覆盖PAV层34，即PAV层34设置在第四电极B的外围，PAV层34与第四电极B保持一定的间隔。在漏极D和源极S与半导体层32之间各设置一电子浓度较高的n+层35，其分别属于漏极D或源极S的一部分，该n+层35可以大大降低开关30导通时的沟道电阻。其中，栅极G、漏极D、源极S以及第四电极B为导电材料。
在本实施例中，栅极G与漏极D以及源极S分别位于半导体层33的同侧，第四电极B和栅极G分别设置于半导体层33的两侧。开关30关闭时，栅极G接低电位，第四电极B连接地以导走积累在半导体33层中且远离栅极G侧的电子，减少漏电流。第四电极B接低电位时，因其直接与半导体层33接触，半导体层33中远离栅极G侧的电子，也即靠近第四电极B的电子直接通过第四电极B导走。开关30关闭后，第四电极B的所接的电位与栅极D的电位可以相同，或者不相同。值得注意的是，当两者电位不相同时，两者的电位相差不应太大。
请参阅图5，图5是本发明第一实施例的薄膜晶体管开关的制造方法示意图。如图5所示，薄膜晶体管开关的制造方法包括以下步骤：
步骤S101：依次在基底上制作栅极和栅绝缘层，栅极用于连接控制信号以控制开关的导通或关闭。
步骤S102：在栅绝缘层上制作一半导体层。
步骤S103：在半导体层上分别制作漏极和源极并覆盖一钝化层，漏极用于连接第一信号。其中，薄膜晶体管开关用于测试线路时，第一信号为测试信号，而源极用于连接待测试线路。测试线路可以是数据线或者扫描线。
步骤S104：在钝化层上制作第四电极，第四电极用于根据需要连接不同的电位。
在本实施例中，栅极和漏极以及源极位于半导体层的两侧。开关导通时，第四电极和栅极都接高电压，两者电压可以相同，也可以不相同。开关关闭时，栅极接低电压，第四电极先接高电压以导走半导体层中远离栅极侧的电子，减少漏电流。之后第四电极也接低电压，其电压与栅极所接电压可相同，亦可不相同。值得注意的是，当两者电位不相同时，两者的电位相差不应太大。
请参阅图6，图6是本发明第二实施例的薄膜晶体管开关的制造方法示意图。如图6所示，薄膜晶体管开关的制造方法包括以下步骤：
步骤S201：依次在基底上制作栅极和栅绝缘层，栅极用于连接控制信号以控制开关的导通或关闭。
步骤S202：在栅绝缘层上分别制作漏极和源极，漏极用于连接第一信号。其中，薄膜晶体管开关用于测试线路时，第一信号为测试信号，而源极用于连接待测试线路，测试线路可以是数据线或者扫描线。
步骤S203：半导体层制作在漏极和源极上并与栅绝缘层接触。
步骤S204：第四电极制作在半导体层上，并在第四电极的周围覆盖钝化层，第四电极用于根据需要连接不同的电位。
在本实施例中，栅极和漏极以及源极位于半导体层的同侧。开关导通时，第四电极和栅极都接高电压，两者电压可以相同，也可以不相同。开关关闭时，栅极接低电压，第四电极接地以导走半导体层中远离栅极侧的电子，减少漏电流。开关关闭后，第四电极的所接的电位与栅极的电位可以相同，或者不相同。值得注意的是，当两者电位不相同时，两者的电位相差不应太大。
综上所述，本发明通过一种薄膜晶体管开关，包括栅极、漏极、源极以及第四电极，漏极连接第一信号，栅极连接控制信号以控制开关的导通或关闭，开关导通时源极输出第一信号，第四电极和栅极分别设置于源极和漏极的两侧，且第四电极为导电材料，其根据需要连接不同的电位，能够在开关处于关闭状态时降低沟道中的漏电流，改善开关的特性。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (11)

  1. 一种薄膜晶体管开关，其中，所述开关包括栅极、漏极、源极、半导体层以及第四电极，所述漏极连接第一信号，所述栅极连接控制信号以控制所述开关的导通或关闭，所述开关导通时所述源极输出所述第一信号，所述第四电极和所述栅极分别设置于所述半导体层的两侧，且所述第四电极为导电材料，其根据需要连接不同的电位。
  2. 根据权利要求1所述的开关，其中，所述开关导通时，所述栅极和所述第四电极接高电位。
  3. 根据权利要求2所述的开关，其中，所述第四电极的电位与所述栅极的电位相同。
  4. 根据权利要求2所述的开关，其中，所述第四电极的电位与所述栅极的电位不相同。
  5. 根据权利要求1所述的开关，其中，所述开关还包括栅绝缘层以及钝化层，所述栅绝缘层设置在所述栅极上，所述半导体层设置在所述栅绝缘层上，所述漏极和所述源极设置在所述半导体层上，上面设置所述钝化层，所述第四电极设置在所述钝化层上；所述开关关闭时，所述栅极接低电位，所述第四电极连接高电位以导走积累在所述半导体层中且远离所述栅极侧的电子，之后所述第四电极接低电位。
  6. 根据权利要求5所述的开关，其中，所述第四电极接低电位时，其电位与所述栅极的电位相同。
  7. 根据权利要求5所述的开关，其中，所述第四电极接低电位时，其电位与所述栅极的电位不相同。
  8. 根据权利要求1所述的开关，其中，所述开关还包括栅绝缘层以及钝化层，所述栅绝缘层设置在所述栅极上，所述漏极和所述源极设置在所述栅绝缘层上，上面设置所述半导体层，所述第四电极设置在所述半导体层上，所述钝化层设置在所述第四电极的外围；所述开关关闭时，所述栅极接低电位，所述第四电极接地以导走积累在所述半导体层中且远离所述栅极侧的电子。
  9. 根据权利要求1所述的开关，其中，所述第一信号为测试信号，所述源极连接待测试的扫描线或数据线。
  10. 一种薄膜晶体管开关的制造方法，其中，所述方法包括：
    依次在基底上制作栅极和栅绝缘层，所述栅极用于连接控制信号以控制所述开关的导通或关闭；
    在所述栅绝缘层上制作一半导体层；
    在所述半导体层上分别制作漏极和源极并覆盖一钝化层，所述漏极用于连接第一信号；
    在所述钝化层上制作第四电极，所述第四电极用于根据需要连接不同的电位。
  11. 一种薄膜晶体管开关的制造方法，其中，所述方法包括：
    依次在基底上制作栅极和栅绝缘层，所述栅极用于连接控制信号以控制所述开关的导通或关闭；
    在所述栅绝缘层上分别制作漏极和源极，所述漏极用于连接第一信号；
    半导体层制作在漏极和源极上并与所述栅绝缘层接触；
    第四电极制作在所述半导体层上，并在所述第四电极的周围覆盖钝化层，所述第四电极用于根据需要连接不同的电位。
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