JP6279086B2 - 薄膜トランジスタスイッチ及びその製造方法 - Google Patents
薄膜トランジスタスイッチ及びその製造方法 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims description 43
- 238000004519 manufacturing process Methods 0.000 title description 11
- 239000004065 semiconductor Substances 0.000 claims description 47
- 238000007689 inspection Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 17
- 238000002161 passivation Methods 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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Description
図2を参照する。図2は、本発明の実施例1における薄膜トランジスタスイッチの記号概略図である。本発明の実施例において、薄膜トランジスタスイッチ20は、ゲートGと、ドレインDと、ソースSと、ゲートG・ドレインD・ソースSの間に設けられた半導体層23と、第四電極Bとからなる。ドレインDは、第一信号と接続される。ゲートGは、制御信号と接続されることでスイッチ20の導通或はオフを制御する。スイッチ20導通時、ソースSは第一信号を出力する。第四電極BとゲートGは、それぞれ半導体層23の両側に設けられるとともに、第四電極Bは需要に応じて異なる電位と接続される。このうち、ゲートG・ドレインD・ソースS・第四電極Bは、導電素材からなる。
図4は、本発明の実施例2における薄膜トランジスタスイッチの構造概略図である。スイッチ30は、基板31上にゲートGが設けられ、ゲート絶縁層32がゲートG上に設けられ、ドレインDとソースSがいずれもゲート絶縁層32上に設けられ、ドレインDとソースSの中間を隔てるように半導体層33が設けられ、更に同時に半導体層33がドレインDとソースS全体を被覆するように設けられる。第四電極Bは、半導体層33上に設けられ、具体的には、ドレインDとソースSが隔てられた部分の真上の位置、且つ両端がドレインDとソースSの上方まで延伸して設けられる。ただし、ドレインDとソースS全体を全て覆ってしまうわけではなく、平面のその他部分には、いずれもPAV層34が被覆される。即ち、PAV層34は第四電極Bの周囲に設けられ、PAV層34と第四電極Bは一定の間隔を保つ。ドレインDとソースSは、半導体層32との間に、それぞれ電子濃度が比較的高いn+層35が設けられる。n+層35は、それぞれドレインD或はソースSの一部分に属するとともに、n+層35は、スイッチ30導通時のチャネル抵抗を大幅に低減させることが出来る。このうち、ゲートG・ドレインD・ソースS・第四電極Bは、導電素材からなる。
図5を参照する。図5は、本発明の実施例1の薄膜トランジスタスイッチの製造方法を示したフロー図である。薄膜トランジスタスイッチの製造方法は、以下の工程を含む。
図6を参照する。図6は、本発明の実施例2における薄膜トランジスタスイッチの製造方法を示したフロー図である。薄膜トランジスタスイッチの製造方法は、以下の工程を含む。
11 ドレイン
12 ソース
13 ゲート
14 ドレイン
15 ソース
16 ゲート
GL 走査線
DL データ線
(本発明)
20 スイッチ
21 基板
22 ゲート絶縁層
23 半導体層
24 PAV層(不動態化層)
25 n+層
30 スイッチ
31 基板
32 ゲート絶縁層
33 半導体層
34 PAV層
35 n+層
B 第四電極
D ドレイン
G ゲート
S ソース
GL 走査線
DL データ線
Claims (5)
- 薄膜トランジスタスイッチの制御方法であって、
前記薄膜トランジスタスイッチは、
ゲートと、ドレインと、ソースと、半導体層と、第四電極とからなり、
前記ドレインは、第一信号と接続され、
前記ゲートは、制御信号と接続されることで当該薄膜トランジスタスイッチの導通或はオフを制御し、
前記スイッチ導通時、前記ソースは、前記第一信号を出力し、
前記第四電極と前記ゲートは、それぞれ前記半導体層の両側に設けられ、
前記第四電極は、導電素材からなり、
当該薄膜トランジスタスイッチの制御方法は、
当該薄膜トランジスタスイッチの導通時、前記ゲートと前記第四電極とは、高電位を受け取り、
また更に、
当該薄膜トランジスタスイッチのスイッチオフ時、
前記ゲートは、低電位を受け取り、
前記第四電極は、高電位と接続されることで、前記半導体層中に蓄積され且つ前記ゲートから離れた側の電子を誘導した後、
前記第四電極は、低電位を受け取る
ことを特徴とする薄膜トランジスタスイッチの制御方法。 - 請求項1に記載の薄膜トランジスタスイッチの制御方法において、
更に、前記薄膜トランジスタスイッチには、ゲート絶縁層及び不動態化層が設けられ、
前記ゲート絶縁層は、前記ゲート上に設けられ、
前記半導体層は、前記ゲート絶縁層上に設けられ、
前記ドレインと前記ソースは、前記半導体層上に設けられるとともに、上面には前記不動態化層が設けられ、
前記第四電極は、前記不動態化層上に設けられている
ことを特徴とする薄膜トランジスタスイッチの制御方法。 - 請求項1または請求項2に記載の薄膜トランジスタスイッチの制御方法において、
更に、前記第四電極が低電位を受け取った時、前記第四電極の電位は、前記ゲートの電位と等しい
ことを特徴とする薄膜トランジスタスイッチの制御方法。 - 請求項1または請求項2に記載の薄膜トランジスタスイッチの制御方法において、
更に、前記第四電極が低電位を受け取った時、前記第四電極の電位は、前記ゲートの電位と異なる
ことを特徴とする薄膜トランジスタスイッチの制御方法。 - 請求項1に記載の薄膜トランジスタスイッチの制御方法において、
更に、前記第一信号は、検査信号であり、
前記ソースは、検査待機中の走査線或はデータ線と接続される
ことを特徴とする薄膜トランジスタスイッチの制御方法。
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CN201310411135.2 | 2013-09-10 | ||
CN201310411135.2A CN103474473B (zh) | 2013-09-10 | 2013-09-10 | 一种薄膜晶体管开关及其制造方法 |
PCT/CN2013/083484 WO2015035615A1 (zh) | 2013-09-10 | 2013-09-13 | 一种薄膜晶体管开关及其制造方法 |
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JP6279086B2 true JP6279086B2 (ja) | 2018-02-14 |
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US (4) | US9680025B2 (ja) |
JP (1) | JP6279086B2 (ja) |
KR (1) | KR101894163B1 (ja) |
CN (1) | CN103474473B (ja) |
GB (1) | GB2533717B (ja) |
RU (1) | RU2634088C2 (ja) |
WO (1) | WO2015035615A1 (ja) |
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JP3409542B2 (ja) * | 1995-11-21 | 2003-05-26 | ソニー株式会社 | 半導体装置の製造方法 |
JPH11214698A (ja) * | 1998-01-27 | 1999-08-06 | Matsushita Electric Ind Co Ltd | 液晶表示装置における薄膜トランジスタ |
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JP2016534570A (ja) | 2016-11-04 |
US9680025B2 (en) | 2017-06-13 |
GB2533717B (en) | 2017-02-15 |
US20170194508A1 (en) | 2017-07-06 |
US20170222060A1 (en) | 2017-08-03 |
US20150069398A1 (en) | 2015-03-12 |
US9761729B2 (en) | 2017-09-12 |
WO2015035615A1 (zh) | 2015-03-19 |
CN103474473B (zh) | 2016-02-03 |
KR20160052713A (ko) | 2016-05-12 |
GB201603048D0 (en) | 2016-04-06 |
KR101894163B1 (ko) | 2018-08-31 |
CN103474473A (zh) | 2013-12-25 |
RU2016113118A (ru) | 2017-10-11 |
US9735073B1 (en) | 2017-08-15 |
GB2533717A (en) | 2016-06-29 |
US20170221784A1 (en) | 2017-08-03 |
US9887141B2 (en) | 2018-02-06 |
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