WO2015033463A1 - 半導体装置およびその製造方法、電力変換装置、3相モータシステム、自動車、ならびに鉄道車両 - Google Patents
半導体装置およびその製造方法、電力変換装置、3相モータシステム、自動車、ならびに鉄道車両 Download PDFInfo
- Publication number
- WO2015033463A1 WO2015033463A1 PCT/JP2013/074222 JP2013074222W WO2015033463A1 WO 2015033463 A1 WO2015033463 A1 WO 2015033463A1 JP 2013074222 W JP2013074222 W JP 2013074222W WO 2015033463 A1 WO2015033463 A1 WO 2015033463A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- region
- semiconductor device
- semiconductor
- type
- concentration
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 120
- 238000000034 method Methods 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 238000006243 chemical reaction Methods 0.000 title claims description 12
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 53
- 239000012535 impurity Substances 0.000 claims description 45
- 239000000758 substrate Substances 0.000 claims description 23
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 22
- 229910052782 aluminium Inorganic materials 0.000 claims description 22
- 230000015556 catabolic process Effects 0.000 description 27
- 238000010586 diagram Methods 0.000 description 14
- 230000002093 peripheral effect Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 230000008569 process Effects 0.000 description 10
- 238000002513 implantation Methods 0.000 description 7
- 230000005684 electric field Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 208000025174 PANDAS Diseases 0.000 description 1
- 208000021155 Paediatric autoimmune neuropsychiatric disorders associated with streptococcal infection Diseases 0.000 description 1
- 240000000220 Panda oleosa Species 0.000 description 1
- 235000016496 Panda oleosa Nutrition 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60L—PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
- B60L50/00—Electric propulsion with power supplied within the vehicle
- B60L50/50—Electric propulsion with power supplied within the vehicle using propulsion power supplied by batteries or fuel cells
- B60L50/51—Electric propulsion with power supplied within the vehicle using propulsion power supplied by batteries or fuel cells characterised by AC-motors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
- Y02T10/00—Road transport of goods or passengers
- Y02T10/60—Other road transportation technologies with climate change mitigation effect
- Y02T10/70—Energy storage systems for electromobility, e.g. batteries
Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof, a power conversion device, a three-phase motor system, an automobile, and a railway vehicle.
- Patent Document 1 Japanese Patent No. 5122810
- This publication describes an edge termination structure for a silicon carbide device, the edge termination structure being a plurality of concentric circles in a silicon carbide layer spaced from a silicon carbide based semiconductor junction. Has a floating guard ring.
- Non-Patent Document 1 includes two-zone JTE (Junction Termination Extension: junction termination, junction termination extension, etch termination) and spatial modulation JTE. A JTE structure combining the above is described.
- the amount of positive charges existing at the interface between silicon carbide and the insulating film is about 1 ⁇ 10 12 to 1 ⁇ 10 13 cm ⁇ 2. Even so, it is possible to suppress fluctuations in the breakdown voltage of the semiconductor device.
- the JTE structure described in Non-Patent Document 1 requires a JTE with a width of 250 ⁇ m or more. For this reason, the semiconductor device adopting the JTE structure described in Non-Patent Document 1 described above cannot take the area of the active region for the chip size, or if the area of the active region is taken, the chip size increases and the cost increases. become. As a result, it becomes disadvantageous for miniaturization of the power converter using the semiconductor device and the three-phase motor system using the power converter, or it is difficult to reduce the cost. Furthermore, it is disadvantageous for reducing the weight of automobiles and railway vehicles using the three-phase motor system, or it is difficult to reduce the cost.
- the present invention provides a technique capable of suppressing a fluctuation in breakdown voltage and realizing a reduction in area of a termination structure in a semiconductor device having a silicon carbide device.
- a semiconductor device having a silicon carbide device in order to solve the above problems, in the present invention, a p-type first region and a p-type second provided at the outer peripheral side of the first region at the junction termination portion. A first concentration gradient is provided in the first region, and a second concentration gradient greater than the first concentration gradient is provided in the second region.
- the present invention in a semiconductor device having a silicon carbide device, it is possible to suppress withstand voltage fluctuations and reduce the area of the termination structure.
- FIG. 2 is a schematic diagram showing a concentration distribution of a p-type impurity (aluminum (Al)) in a cross section taken along line AA of FIG. It is a graph which shows the relationship between the withstand pressure
- a p-type impurity aluminum (Al)
- FIG. 1 is a plan view of a principal part showing an example of a configuration of a semiconductor device in Example 1.
- FIG. FIG. 6 is a cross-sectional view of main parts showing an example of the configuration of the semiconductor device in Example 1 (cross-sectional view of main parts along the line BB in FIG. 5).
- FIG. 7 is a schematic diagram showing a concentration distribution of a p-type impurity (aluminum (Al)) in a cross section taken along the line CC of FIG. 6. 7 is a cross-sectional view of the principal part showing the production process of the semiconductor device in Example 1.
- FIG. FIG. 9 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 8; FIG.
- FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 9;
- FIG. 11 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 10;
- 12 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 11;
- FIG. FIG. 13 is a main part cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 12;
- FIG. 6 is a process diagram illustrating a method for manufacturing a semiconductor device according to Example 1.
- FIG. 10 is a main part sectional view showing an example of a configuration of a semiconductor device in Example 2; It is a circuit diagram which shows an example of the power converter device (inverter) in Example 3.
- FIG. 10 is a main part sectional view showing an example of a configuration of a semiconductor device in Example 2; It is a circuit diagram which shows an example of the power converter device (inverter) in Example 3.
- FIG. 10 is a main part
- FIG. 10 is a circuit diagram illustrating an example of a converter and an inverter provided in a railway vehicle according to a fifth embodiment.
- the constituent elements are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.
- a semiconductor device using silicon carbide as a semiconductor can reduce the loss of the power conversion device as compared with a semiconductor device using silicon as a semiconductor. Therefore, the loss of a three-phase motor system can be reduced by using a power converter using a semiconductor device having a silicon carbide device for a three-phase motor system. Moreover, since the cooling system for radiating the heat generated due to the loss of the three-phase motor system can be simplified, it is possible to reduce the weight of automobiles and railway vehicles including the three-phase motor system.
- Patent Document 1 in a semiconductor device having a silicon carbide device, 1 ⁇ 10 12 to 2 at the interface between silicon carbide and an insulating film formed to protect the surface thereof. There is a positive charge of about ⁇ 10 12 cm ⁇ 2 , and this positive charge may cause fluctuation in the breakdown voltage of the semiconductor device due to application of a high electric field.
- a JTE composed of a low concentration region and a high concentration region is formed around a silicon carbide PIN (P-Intrinsic-N) diode, and the width and interval of the high concentration region are formed.
- a technique has been proposed in which the ratio is reduced in order as it approaches the end of the chip.
- the purpose of JTE is to reduce the electric field concentration at the edge of the silicon carbide device, and to suppress the non-uniform expansion of the depletion region, thereby reducing the breakdown voltage fluctuation of the semiconductor device.
- the present inventors examined a JTE having a constant concentration gradient, which is composed of a low concentration region and a high concentration region, in a semiconductor device having a silicon carbide pn diode.
- FIG. 1 is a cross-sectional view of a principal part showing a semiconductor device in which a JTE having a constant concentration gradient is provided around a silicon carbide pn diode.
- FIG. 2 is a schematic diagram showing the concentration distribution of the p-type impurity (aluminum (Al)) in the cross section along the line AA in FIG.
- FIG. 3 is a graph showing the relationship between the breakdown voltage of a semiconductor device in which a JTE having a constant concentration gradient is provided around a silicon carbide pn diode and the amount of p-type impurity implanted into a high concentration region of JTE.
- the semiconductor device is composed of a silicon carbide pn diode and JTE formed around the silicon carbide pn diode, and is formed in one semiconductor chip.
- an n-type drift layer 22 is formed on the surface of a substrate 21 made of n-type silicon carbide.
- a p-type region 23 is formed in the central region on the upper surface of the drift layer 22, and a JTE 26 is formed on the upper surface of the drift layer 22 so as to surround the p-type region 23.
- an anode electrode 25 is electrically connected to the p-type region 23, and a cathode electrode 24 is electrically connected to the back surface of the substrate 21 to constitute a silicon carbide pn diode.
- the JTE 26 is in contact with the p-type region 23, a p-type region 30 formed around the p-type region 23, a plurality of p-type high-concentration regions 27 having different widths and intervals, and adjacent high-concentration regions 27. And a plurality of p-type low concentration regions 28 having different widths and intervals from each other.
- the p-type region 30, the high-concentration region 27, and the low-concentration region 28 are formed by introducing a p-type impurity such as aluminum into the drift layer 22 by an ion implantation method.
- the ratio between the width and the interval of the high concentration region 27 decreases in order as it approaches the outside of the JTE 26 (chip end), and the JTE 26 has a constant concentration gradient S.
- the implantation amount of p-type impurities implanted into the high concentration region 27 is 8 ⁇ 10 12 cm. Even if the variation is about ⁇ 2 cm, the breakdown voltage variation of the semiconductor device can be suppressed.
- the width L of the JTE 26 excluding the p-type region 30 needs to be 250 ⁇ m or more. It has been made clear by the present inventors that the area of the region increases the chip size and the cost.
- FIG. 4 is an explanatory diagram showing the definition of the JTE concentration gradient.
- the respective concentrations of the high concentration region 27 and the low concentration region 28 constituting the JTE 26 are NH and NL, and the sum of the widths of both regions is a constant pitch P.
- the width of the i-th (i is a positive integer) high-concentration region 27 is a i
- the horizontal concentration gradient is obtained after obtaining the average concentration at regular intervals (for example, 10 ⁇ m). S can be obtained.
- the approximate value of the concentration gradient S can be obtained using the width L of the JTE 26.
- the concentration NH of the high concentration region 27 is 6 ⁇ 10 17 cm ⁇ 3 and the concentration N L of the low concentration region 28 is 2 ⁇ 10 17 cm ⁇ 3 will be described.
- the width L of the JTE 26 excluding the p-type region 30 is 600 ⁇ m, the concentration gradient S is 0.7 ⁇ 10 15 cm ⁇ 3 / ⁇ m.
- the width of the p-type region 30 was fixed at 20 ⁇ m, JTE 26 having widths L of 600 ⁇ m, 250 ⁇ m, 200 ⁇ m, and 130 ⁇ m was produced, and the breakdown voltage of the semiconductor device was evaluated under various conditions.
- the breakdown voltage of the semiconductor device was evaluated under various conditions.
- no light emission due to avalanche breakdown was observed in the semiconductor device having JTE 26 having a width L of 600 ⁇ m and 250 ⁇ m.
- the semiconductor device having the JTE 26 having a width L of 200 ⁇ m light emission due to avalanche breakdown was observed near the outermost periphery or the innermost periphery of the JTE 26.
- the semiconductor device having the JTE 26 with the width L of 130 ⁇ m light emission accompanying avalanche breakdown was observed at various locations in the JTE 26.
- the concentration gradient S needs to be 1.6 ⁇ 10 15 cm ⁇ 3 / ⁇ m or less, and for that purpose, the width L of the JTE 26 needs to be 250 ⁇ m or more. I understand that there is. Therefore, in order to avoid the avalanche breakdown, even if the JTE 26 having a constant concentration gradient S of 1.6 ⁇ 10 15 cm ⁇ 3 / ⁇ m or less is provided around the silicon carbide pn diode, the width L of the JTE 26 is 250 ⁇ m. Since the above is required, the area of the active region cannot be obtained for the chip size, or if the area of the active region is taken, the chip size increases and the cost increases.
- the size of the semiconductor chip be 2 to 3 mm square or less. Therefore, the inability to reduce the JTE area is a problem directly related to a decrease in the effective area of the semiconductor chip (the area obtained by subtracting the JTE area from the area of the semiconductor chip).
- FIG. 5 is a main part plan view showing an example of the configuration of the semiconductor device according to the first embodiment.
- FIG. 6 is a main part sectional view showing an example of the configuration of the semiconductor device in Example 1 (main part sectional view taken along line BB in FIG. 5).
- an epitaxial layer 10 made of n-type silicon carbide is formed on the surface of a substrate 11 made of n-type silicon carbide.
- the epitaxial layer 10 is formed of an n-type drift layer 12.
- Can be used as A p-type region 13 is formed in a central region that is an active region on the upper surface of the epitaxial layer 10, and JTE 16 is formed on the upper surface of the epitaxial layer 10 so as to surround the p-type region 13.
- An anode electrode 15 is electrically connected to the p-type region 13, and a cathode electrode 14 is electrically connected to the back surface of the substrate 11 to constitute a silicon carbide pn diode.
- the length of one side of the semiconductor device is, for example, a square shape of about 3 mm ⁇ 3 mm.
- the JTE 16 is in contact with the p-type region 13, a p-type region 20 formed around the p-type region 13, a plurality of p-type high concentration regions 17, a plurality of p-type medium concentration regions 19, and a plurality of P-type low concentration region 18. Then, the high concentration region 17 and the medium concentration region 19 are alternately formed in the region on the inner peripheral side of the JTE 16 following the p-type region 20, and the low concentration region 18 is formed in the region on the outer peripheral side of the JTE 16, High concentration regions 17 and low concentration regions 18 are alternately formed in an intermediate region between the inner peripheral region and the outer peripheral region of the JTE 16.
- the p-type region 20, the high concentration region 17, the medium concentration region 19, and the low concentration region 18 are formed by introducing a p-type impurity such as aluminum into the epitaxial layer 10 by an ion implantation method.
- the p-type region 20 has a width of, for example, 20 ⁇ m, a depth from the upper surface of the epitaxial layer 10 of, for example, 0.8 ⁇ m, and an aluminum concentration of, for example, 6 ⁇ 10 17 cm ⁇ 3 .
- the epitaxial layer 10 in the high concentration region 17 has a depth from the upper surface of, for example, 0.8 ⁇ m, and an aluminum concentration of, for example, 6 ⁇ 10 17 cm ⁇ 3 .
- the epitaxial layer 10 in the medium concentration region 19 has a depth from the upper surface of, for example, 0.8 ⁇ m, and an aluminum concentration of, for example, 4 ⁇ 10 17 cm ⁇ 3 .
- the epitaxial layer 10 in the low concentration region 18 has a depth from the upper surface of, for example, 0.8 ⁇ m, and an aluminum concentration of, for example, 2 ⁇ 10 17 cm ⁇ 3 .
- an insulating film IF is formed to protect the upper surface of the epitaxial layer 10, and an opening for exposing the anode electrode 15 is provided in the insulating film IF.
- FIG. 7 is a schematic diagram showing the concentration distribution of the p-type impurity (aluminum (Al)) in the cross section taken along the line CC of FIG.
- a plurality of regions in which the concentration gradually decreases from the end of the p-type region 20 opposite to the p-type region 13 toward the outer periphery (chip end) of the JTE 16 are formed.
- a first area AR 1 composed of a high concentration area 17 and a medium concentration area 19
- a second area AR 2 composed of a high concentration area 17 and a low concentration area 18
- a third area AR3 composed of the low concentration area 18 is provided.
- the first concentration gradient S1 of the first region AR1 located on the inner peripheral side of the JTE16 and the third concentration gradient of the third region AR3 located on the outer peripheral side of the JTE16 in which avalanche breakdown is likely to occur due to the change in breakdown voltage.
- S3 is set to 1.6 ⁇ 10 15 cm ⁇ 3 / ⁇ m or less. That is, the first concentration gradient S1 of the first region AR1 is 1.6 ⁇ 10 15 cm ⁇ 3 / ⁇ m or less, and the second concentration gradient S2 of the second region AR2 is 1.6 ⁇ 10 15 cm ⁇ 3.
- the third concentration gradient S3 of the third region AR3 is set to 1.6 ⁇ 10 15 cm ⁇ 3 / ⁇ m or less and larger than 6.3 ⁇ 10 15 cm ⁇ 3 / ⁇ m.
- the amount of positive charges existing at the interface between the epitaxial layer 10 and the insulating film IF is 1 ⁇ .
- Avalanche breakdown can be avoided on the inner peripheral side of the JTE 16 where the electric field intensity reaches a peak at about 10 13 cm ⁇ 2 .
- the third concentration gradient S3 of the third region AR3 can be 1.6 ⁇ 10 15 cm ⁇ 3 / ⁇ m or less.
- An avalanche breakdown can be avoided on the outer peripheral side of the JTE 16 where the electric field strength reaches a peak in the case of about 0 to 1 ⁇ 10 12 cm ⁇ 2 . If the amount of positive charges existing at the interface between the epitaxial layer 10 and the insulating film IF does not become less than 2 ⁇ 10 12 cm ⁇ 12 , an avalanche breakdown on the outer peripheral side of the JTE 16 is unlikely to occur. S3 becomes unnecessary.
- the second concentration gradient S2 of the second region AR2 can be larger than 1.6 ⁇ 10 15 cm ⁇ 3 / ⁇ m and not larger than 6.3 ⁇ 10 15 cm ⁇ 3 / ⁇ m, the avalanche breakdown in JTE16 can be reduced. While avoiding, the width L of the JTE 16 excluding the p-type region 20 can be shortened. This is because the width L1 of the first area AR1, the width L2 of the second area AR2, and the width L3 of the third area AR3 can be set independently.
- a width L1 necessary for obtaining a first concentration gradient S1 (1.6 ⁇ 10 15 cm ⁇ 3 / ⁇ m or less) that can avoid avalanche breakdown is set.
- a width L3 necessary for obtaining a third concentration gradient S3 (1.6 ⁇ 10 15 cm ⁇ 3 / ⁇ m or less) that can avoid avalanche breakdown is set.
- the second concentration gradient S2 is larger than 1.6 ⁇ 10 15 cm ⁇ 3 / ⁇ m.
- 6.3 ⁇ 10 15 cm ⁇ 3 / ⁇ m or less) can be made larger than the first concentration gradient S1 and the third concentration gradient S3.
- the widths of the high concentration region 17 and the medium concentration region 19 are adjusted to obtain a width of 125 ⁇ m.
- L1 can be set.
- the second concentration gradient S2 of 6.3 ⁇ 10 15 cm ⁇ 3 / ⁇ m in the second region AR2 the respective widths of the high concentration region 17 and the low concentration region 18 are adjusted to 32 ⁇ m.
- Width L2 can be set.
- the width L3 of, for example, 20 ⁇ m can be set by adjusting the width of the low concentration region 18.
- the width L of the JTE 16 excluding the p-type region 20 can be set to 177 ⁇ m.
- the concentration gradient of the inner peripheral region (first region AR1) of the JTE 16 where the avalanche breakdown is likely to occur and the outer peripheral region (third region AR3) as necessary is 1.6 ⁇ 10 15 cm. -3 / ⁇ m or less.
- the concentration gradient in the intermediate region (second region AR2) of JTE16 in which avalanche breakdown is unlikely to occur is set to be larger than 1.6 ⁇ 10 15 cm ⁇ 3 / ⁇ m and smaller than 6.3 ⁇ 10 15 cm ⁇ 3 / ⁇ m, Reduce the width of the region.
- the withstand voltage fluctuation due to the positive charges existing at the interface between the epitaxial layer 10 and the insulating film IF is suppressed, and avalanche breakdown can be avoided. Furthermore, since the area of the JTE 16 can be reduced, the area of the active region can be increased for the chip size, or the cost can be reduced by reducing the chip size.
- JTE16 for example high density region 17 having a 6 ⁇ 10 17 cm -3
- the concentration region 19 in having, for example, 4 ⁇ 10 17 cm -3, and for example, a 2 ⁇ 10 17 cm -3 It has a low-concentration region 18.
- the medium concentration region 19 is sandwiched between the high concentration regions 17, and in the second region AR, the low concentration region 18 is sandwiched between the high concentration regions 17.
- the high concentration region 17, the medium concentration region 19, and the low concentration region 18 are ion-implanted twice instead of three times. Therefore, the cost of the semiconductor device can be reduced.
- FIGS. 8 to 13 are cross-sectional views of main parts of the semiconductor device according to the first embodiment.
- FIG. 14 is a process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment.
- an n-type substrate 11 mainly containing silicon carbide is prepared.
- an epitaxial layer 10 made of silicon carbide is formed on the surface of the substrate 11 by an epitaxial growth method.
- the epitaxial layer 10 can be used as the drift layer 12.
- the substrate 11 and the epitaxial layer 10 contain n-type impurities (for example, nitrogen), and the impurity concentration of the substrate 11 is higher than the impurity concentration of the epitaxial layer 10.
- the impurity concentration of the substrate 11 is, for example, about 1 ⁇ 10 18 to 1 ⁇ 10 19 cm ⁇ 3 .
- the surface of the substrate 11 can be a (0001) plane, a (000-1) plane, a (11-2) plane, or the like, any of which may be selected.
- the specifications of the epitaxial layer 10 differ depending on the breakdown voltage set in the silicon carbide pn diode formed through the subsequent process, but the impurity contained in the epitaxial layer 10 has the same conductivity type as that of the substrate 11, and the impurity concentration is For example, about 1 ⁇ 10 15 to 4 ⁇ 10 16 cm ⁇ 3 and the thickness is about 3 to 80 ⁇ m, for example.
- a mask material layer RP1 is formed on the upper surface of the epitaxial layer 10, and p-type impurities (for example, aluminum) are ion-implanted into the upper surface of the epitaxial layer 10 exposed from the mask material layer RP1.
- p-type impurities for example, aluminum
- a p-type low concentration region 18 is formed on the upper surface of the epitaxial layer 10.
- the concentration of the p-type impurity (for example, aluminum) in the low concentration region 18 is 2 ⁇ 10 17 cm ⁇ 3 , for example, and the implantation depth is 0.8 ⁇ m, for example.
- a mask material layer RP2 is formed on the upper surface of the epitaxial layer 10, and a p-type impurity (on the upper surface of the epitaxial layer 10 exposed from the mask material layer RP2).
- a p-type impurity on the upper surface of the epitaxial layer 10 exposed from the mask material layer RP2.
- aluminum is ion-implanted to form the p-type region 20, the high concentration region 17, and the medium concentration region 19 on the upper surface of the epitaxial layer 10.
- the concentration of the p-type impurity is 4 ⁇ 10 17 cm ⁇ 3 , the implantation depth, for example. Is performed under the condition of, for example, 0.8 ⁇ m.
- the p-type region 20 and the high-concentration region 17 are formed by ion-implanting p-type impurities into the region where the low-concentration region 18 is formed.
- the p-type region 20 and the high-concentration region 17 have a p-type overlap with the p-type impurity (for example, aluminum) concentration of 2 ⁇ 10 17 cm ⁇ 3 and the implantation depth of 0.8 ⁇ m that have already been formed.
- the concentration of the impurity (for example, aluminum) is, for example, 6 ⁇ 10 17 cm ⁇ 3
- the implantation depth is, for example, 0.8 ⁇ m.
- the intermediate concentration region 19 is formed by ion-implanting p-type impurities into a region where the low concentration region 18 is not formed. That is, the concentration of the p-type impurity (for example, aluminum) in the medium concentration region 19 is, for example, 4 ⁇ 10 17 cm ⁇ 3 , and the implantation depth is, for example, 0.8 ⁇ m.
- the concentration of the p-type impurity (for example, aluminum) in the medium concentration region 19 is, for example, 4 ⁇ 10 17 cm ⁇ 3
- the implantation depth is, for example, 0.8 ⁇ m.
- a mask material layer RP3 is formed on the upper surface of the epitaxial layer 10, and a p-type impurity (on the upper surface of the epitaxial layer 10 exposed from the mask material layer RP3).
- a p-type impurity on the upper surface of the epitaxial layer 10 exposed from the mask material layer RP3.
- aluminum is ion-implanted to form the p-type region 13 in the central region of the upper surface of the epitaxial layer 10.
- the concentration of the p-type impurity (for example, aluminum) in the p-type region 13 is 2 ⁇ 10 19 cm ⁇ 3 , for example, and the implantation depth is 0.8 ⁇ m, for example.
- ⁇ Process P5> Next, after removing the mask material layer RP3, annealing is performed to activate the implanted impurities. Thus, a silicon carbide pn diode composed of p-type region 13 and drift layer 12 is formed in the central region of the upper surface of epitaxial layer 10, and high concentration region 17, medium concentration region 19, and low concentration region are formed around it. A JTE 16 composed of 18 is formed.
- an anode electrode 15 is formed on the upper surface of the p-type region 13 by, for example, sputtering. Subsequently, an insulating film (not shown) is formed on the upper surface of the epitaxial layer 10 so as to expose the upper surface of the anode electrode 15.
- the cathode electrode 14 is formed on the back surface of the substrate 11 by, for example, sputtering.
- the semiconductor device having the silicon carbide pn diode in Example 1 can be manufactured.
- Example 1 even when a positive charge is present at the interface between silicon carbide and the insulating film, it is possible to suppress fluctuations in breakdown voltage in a semiconductor device having a silicon carbide pn diode. Furthermore, since the area of the JTE 16 can be reduced, the area of the active region can be increased for the chip size, or the cost can be reduced by reducing the chip size.
- the high concentration region 17, the medium concentration region 19 and the low concentration region 18 constituting the JTE 16 can be formed by ion implantation twice instead of three times, the cost of the semiconductor device can be reduced. .
- FIG. 15 is a cross-sectional view of main parts showing an example of the configuration of the semiconductor device according to the second embodiment.
- the silicon carbide JBS diode is formed by discretely forming p-type regions 13 in the silicon carbide pn diode described in the first embodiment.
- the p-type region 13 is not formed, and a thermionic emission current at the time of forward bias flows through the region of the drift layer 12 in direct Schottky contact with the anode electrode 15. Since this thermoelectron emission current flows at a lower voltage than the diffusion current of the silicon carbide pn diode, the silicon carbide JBS diode can have a lower forward voltage than the silicon carbide pn diode. Further, at the time of reverse bias, the depletion layer expands from the p-type region 13 and the electric field strength applied to the interface between the anode electrode 15 and the drift layer 12 is relaxed. As a result, the silicon carbide JBS diode can reduce the reverse leakage current as compared with the Schottky barrier diode without the p-type region 13.
- the manufacturing process of the semiconductor device in Example 2 is different from the manufacturing process of the semiconductor device in Example 1 described above only in the manufacturing process of the p-type region 13.
- the mask material layer PR3 shown in FIG. 11 may be a discrete pattern.
- the same effect as that of the first embodiment can be obtained even in the semiconductor device having the silicon carbide JBS diode.
- FIG. 16 is a circuit diagram illustrating an example of a power converter (inverter) according to the third embodiment.
- the inverter 2 includes a switching element (for example, an IGBT (Insulated Gate Bipolar Transistor)) 4 and a diode 5.
- the switching element 4 and the diode 5 are connected in antiparallel between the power supply potential (Vcc) and the input potential of the load (for example, motor) 1, and the input potential of the load 1 and the ground potential (GND) ),
- the switching element 4 and the diode 5 are connected in antiparallel. That is, in the load 1, two switching elements 4 and two diodes 5 are provided for each single phase, and six switching elements 4 and six diodes 5 are provided for three phases.
- a control circuit 3 is connected to the gate electrode of each switching element 4, and the switching element 4 is controlled by the control circuit 3. Therefore, the load 1 can be driven by controlling the current flowing through the switching element 4 constituting the inverter 2 by the control circuit 3.
- the switching element 4 and the diode 5 are connected in antiparallel.
- the function of the diode 5 at this time will be described below.
- the diode 5 is not necessary when the load 1 is a pure resistance that does not include an inductance because there is no energy to return.
- a circuit including an inductance such as a motor
- the switching element 4 alone does not have a function of allowing the load current flowing in the reverse direction to flow, and therefore it is necessary to connect the diode 5 to the switching element 4 in antiparallel.
- the inverter 1 when the load 1 includes an inductance like a motor, for example, when the switching element 4 is turned off, the energy stored in the inductance must be released.
- the switching element 4 alone cannot flow a reverse current for releasing the energy stored in the inductance. Therefore, the diode 5 is connected to the switching element 4 in the reverse direction in order to recirculate the electric energy stored in the inductance. That is, the diode 5 has a function of flowing a reverse current in order to release the electric energy stored in the inductance.
- the semiconductor device described in the first embodiment or the second embodiment as the diode 5 for example, by increasing the area of the active region, the number of elements of the diode can be increased.
- the power conversion device such as an inverter can be reduced in size.
- the power conversion device can be used for a three-phase motor system.
- the load 1 shown in FIG. 16 is a three-phase motor
- the inverter 2 is a three-phase motor by using the power conversion device including the semiconductor device described in the first embodiment or the second embodiment.
- the system can be miniaturized.
- FIG. 17A is a schematic diagram illustrating an example of the configuration of the electric vehicle according to the fourth embodiment
- FIG. 17B is a circuit diagram illustrating an example of the boost converter according to the fourth embodiment.
- the electric vehicle drives a three-phase motor 103 that enables power to be input / output to / from a drive shaft 102 to which the drive wheels 101a and 101b are connected, and the three-phase motor 103.
- Inverter 104 and battery 105 are provided. Further, it includes a boost converter 108, a relay 109, and an electronic control unit 110.
- the boost converter 108 is connected to a power line 106 to which an inverter 104 is connected and a power line 107 to which a battery 105 is connected. Yes.
- the three-phase motor 103 is a synchronous generator motor including a rotor embedded with permanent magnets and a stator wound with a three-phase coil.
- the inverter 104 the inverter 2 described in the third embodiment can be used.
- the boost converter 108 has a configuration in which a reactor 111 and a smoothing capacitor 112 are connected to an inverter 113.
- the inverter 113 is the same as the inverter 2 described in the third embodiment, and the configuration of the switching element 114 and the diode 115 in the inverter 2 is the same as that of the switching element 4 and the diode 5 described in the third embodiment. The same.
- the electronic control unit 110 includes a microprocessor, a storage device, and an input / output port, and receives a signal from a sensor that detects the rotor position of the three-phase motor 103, a charge / discharge value of the battery 105, and the like. . Then, a signal for controlling inverter 104, boost converter 108, and relay 109 is output.
- the power conversion device described in the above-described third embodiment can be used for the inverter 104 and the boost converter 108 which are power conversion devices.
- the three-phase motor system described in the third embodiment can be used for a three-phase motor system including the three-phase motor 103 and the inverter 104. As a result, the volume of the drive system in the electric vehicle can be reduced, and the electric vehicle can be reduced in size, weight, and space.
- Example 4 demonstrated the electric vehicle, a three-phase motor system is applicable similarly to the hybrid vehicle which also uses an engine.
- FIG. 18 is a circuit diagram illustrating an example of a converter and an inverter provided in the railway vehicle according to the fifth embodiment.
- electric power is supplied to the railway vehicle from the overhead line OW (for example, 25 kV) via the panda graph PG.
- the voltage is stepped down to 1.5 kV through the transformer 9 and converted from AC to DC by the converter 7. Furthermore, it is converted from direct current to alternating current by the inverter 2 through the capacitor 8 to drive the three-phase motor as the load 1.
- the configuration of switching element 4 and diode 5 in converter 7 and the configuration of switching element 4 and diode 5 in inverter 2 are the same as the configuration of switching element 4 and diode 5 described in the third embodiment.
- the control circuit 3 described in the third embodiment is omitted.
- symbol RT indicates a track
- symbol WH indicates a wheel.
- the power conversion device described in the third embodiment can be used for the converter 7.
- the three-phase motor system described in the third embodiment can be used for the three-phase motor system including the load 1, the inverter 2, and the control circuit. Thereby, size reduction and weight reduction of a railway vehicle can be achieved.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Sustainable Energy (AREA)
- Transportation (AREA)
- Mechanical Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Inverter Devices (AREA)
Abstract
Description
Ni=[NHai+NL(P-ai)]/P
で表される。
Ni+1=[NHai+1+NL(P-ai+1)]/P
で表される。
S=(Ni-Ni+1)/P
=(ai-ai+1)(NH-NL)/P2
と求められる。
まず、図8に示すように、炭化ケイ素を主に含むn型の基板11を準備する。続いて、基板11の表面に炭化ケイ素からなるエピタキシャル層10をエピタキシャル成長法により形成する。エピタキシャル層10はドリフト層12として利用することができる。基板11およびエピタキシャル層10はn型不純物(例えば窒素)を含んでおり、基板11の不純物濃度はエピタキシャル層10の不純物濃度よりも高い。
次に、図9に示すように、エピタキシャル層10の上面にマスク材料層RP1を形成し、マスク材料層RP1から露出するエピタキシャル層10の上面にp型不純物(例えばアルミニウム)をイオン注入することにより、エピタキシャル層10の上面にp型の低濃度領域18を形成する。低濃度領域18のp型不純物(例えばアルミニウム)の濃度は、例えば2×1017cm-3、注入深さは、例えば0.8μmである。
次に、図10に示すように、マスク材料層RP1を除去した後、エピタキシャル層10の上面にマスク材料層RP2を形成し、マスク材料層RP2から露出するエピタキシャル層10の上面にp型不純物(例えばアルミニウム)をイオン注入することにより、エピタキシャル層10の上面にp型領域20、高濃度領域17、および中濃度領域19を形成する。この際、p型不純物(例えばアルミニウム)のイオン注入は、仮にイオン注入を行っていない領域に行ったとしたら、p型不純物(例えばアルミニウム)の濃度が、例えば4×1017cm-3、注入深さが、例えば0.8μmとなる条件で行う。
次に、図11に示すように、マスク材料層RP2を除去した後、エピタキシャル層10の上面にマスク材料層RP3を形成し、マスク材料層RP3から露出するエピタキシャル層10の上面にp型不純物(例えばアルミニウム)をイオン注入することにより、エピタキシャル層10の上面の中央領域にp型領域13を形成する。p型領域13のp型不純物(例えばアルミニウム)の濃度は、例えば2×1019cm-3、注入深さは、例えば0.8μmである。
次に、マスク材料層RP3を除去した後、アニールを行い、イオン注入した不純物の活性化を行う。これにより、エピタキシャル層10の上面の中央領域にp型領域13とドリフト層12とから構成される炭化ケイ素pnダイオードが形成され、その周囲に高濃度領域17、中濃度領域19、および低濃度領域18から構成されるJTE16が形成される。
次に、図12に示すように、p型領域13の上面にアノード電極15を、例えばスパッタリング法などにより形成する。続いて、アノード電極15の上面を露出するようにエピタキシャル層10の上面に絶縁膜(図示は省略)を形成する。
次に、図13に示すように、基板11の裏面にカソード電極14を、例えばスパッタリング法などにより形成する。
2 インバータ
3 制御回路
4 スイッチング素子
5 ダイオード
7 コンバータ
8 キャパシタ
9 トランス
10 エピタキシャル層
11 基板
12 ドリフト層
13 p型領域
14 カソード電極
15 アノード電極
16 JTE
17 高濃度領域
18 低濃度領域
19 中濃度領域
20 p型領域
21 基板
22 ドリフト層
23 p型領域
24 カソード電極
25 アノード電極
26 JTE
27 高濃度領域
28 低濃度領域
30 p型領域
101a,101b 駆動輪
102 駆動軸
103 3相モータ
104 インバータ
105 バッテリ
106,107 電力ライン
108 昇圧コンバータ
109 リレー
110 電子制御ユニット
111 リアクトル
112 平滑用コンデンサ
113 インバータ
114 スイッチング素子
115 ダイオード
AR1 第1の領域
AR2 第2の領域
AR3 第3の領域
IF 絶縁膜
L1,L2,L3 幅
OW 架線
PG パンダグラフ
RP1,RP2,RP3 マスク材料層
RT 線路
S 濃度勾配
S1 第1の濃度勾配
S2 第2の濃度勾配
S3 第3の濃度勾配
WH 車輪
Claims (15)
- 半導体基板と、
前記半導体基板の表面に形成されたn型の半導体層と、
前記半導体層の上面側に形成された接合終端部と、
を備える半導体装置であって、
前記接合終端部は、
p型の第1領域と、
前記第1領域よりも前記半導体基板の端部側に設けられたp型の第2領域と、
を備え、
前記第1領域は、第1濃度勾配を有し、
前記第2領域は、前記第1濃度勾配よりも大きい第2濃度勾配を有する、半導体装置。 - 請求項1記載の半導体装置において、
前記第1濃度勾配が、1.6×1015cm-3/μm以下であり、
前記第2濃度勾配が、1.6×1015cm-3/μmよりも大きく、6.3×1015cm-3/μm以下である、半導体装置。 - 請求項1記載の半導体装置において、
前記半導体層は、炭化ケイ素である、半導体装置。 - 請求項1記載の半導体装置において、
前記第1領域および前記第2領域は、アルミニウムを含有する、半導体装置。 - 請求項1記載の半導体装置において、
前記接合終端部は、
前記第2領域よりも前記半導体基板の端部側に設けられたp型の第3領域、を備え、
前記第3領域は、前記第2濃度勾配よりも小さい第3濃度勾配を有する、半導体装置。 - 請求項5記載の半導体装置において、
前記第1濃度勾配および前記第3濃度勾配が、1.6×1015cm-3/μm以下であり、
前記第2濃度勾配が、1.6×1015cm-3/μmよりも大きく、6.3×1015cm-3/μm以下である、半導体装置。 - 半導体基板と、
前記半導体基板の表面に形成されたn型の半導体層と、
前記半導体層の上面側に形成された接合終端部と、
を備える半導体装置であって、
前記接合終端部は、
第1不純物濃度を有するp型の第1半導体領域と、
前記第1不純物濃度よりも低い第2不純物濃度を有するp型の第2半導体領域と、
前記第2不純物濃度よりも低い第3不純物濃度を有するp型の第3半導体領域と、
を備え、
第1領域において、前記第2半導体領域が前記第1半導体領域に挟まれ、
前記第1領域よりも前記半導体基板の端部側に設けられた第2領域において、前記第3半導体領域が前記第1半導体領域に挟まれている、半導体装置。 - 請求項7記載の半導体装置において、
前記半導体層は、炭化ケイ素である、半導体装置。 - 請求項7記載の半導体装置において、
前記第1半導体領域、前記第2半導体領域、および前記第3半導体領域は、アルミニウムを含有する、半導体装置。 - (a)半導体基板の表面にn型の半導体層を形成する工程と、
(b)前記半導体層の上面側に、第1濃度勾配を有するp型の第1領域と、第2濃度勾配を有するp型の第2領域とが、前記半導体基板の端部に向かって順に配置される接合終端部を形成する工程と、
を含む半導体装置の製造方法において、
前記(b)工程は、
(b1)前記第1領域の一部、および前記第2領域に、p型の第1不純物をイオン注入する工程と、
(b2)前記第1領域、および前記第2領域の一部に、p型の第2不純物をイオン注入する工程と、
を含み、
前記第1領域には、前記第1不純物と前記第2不純物とが重畳してイオン注入された第1不純物領域、および前記第2不純物のみがイオン注入された第2不純物領域が形成され、
前記第2領域には、前記第1不純物と前記第2不純物とが重畳してイオン注入された第3不純物領域、および前記第1不純物のみがイオン注入された第4不純物領域が形成される、半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記第1濃度勾配が、1.6×1015cm-3/μm以下であり、
前記第2濃度勾配が、1.6×1015cm-3/μmよりも大きく、6.3×1015cm-3/μm以下である、半導体装置の製造方法。 - 請求項1記載の半導体装置を備える、電力変換装置。
- 請求項12記載の電力変換装置を備える、3相モータシステム。
- 請求項13記載の3相モータシステムを備える、自動車。
- 請求項13記載の3相モータシステムを備える、鉄道車両。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015535257A JP6236456B2 (ja) | 2013-09-09 | 2013-09-09 | 半導体装置およびその製造方法 |
EP13892962.5A EP3046149B1 (en) | 2013-09-09 | 2013-09-09 | Semiconductor device, method for manufacturing same, power conversion apparatus, three-phase motor system, automobile, and rail vehicle |
CN201380079101.6A CN105493293B (zh) | 2013-09-09 | 2013-09-09 | 半导体装置及其制造方法 |
PCT/JP2013/074222 WO2015033463A1 (ja) | 2013-09-09 | 2013-09-09 | 半導体装置およびその製造方法、電力変換装置、3相モータシステム、自動車、ならびに鉄道車両 |
US14/916,801 US9711600B2 (en) | 2013-09-09 | 2013-09-09 | Semiconductor device and method of manufacturing the same, power conversion device, three-phase motor system, automobile, and railway vehicle |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2013/074222 WO2015033463A1 (ja) | 2013-09-09 | 2013-09-09 | 半導体装置およびその製造方法、電力変換装置、3相モータシステム、自動車、ならびに鉄道車両 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015033463A1 true WO2015033463A1 (ja) | 2015-03-12 |
Family
ID=52627968
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2013/074222 WO2015033463A1 (ja) | 2013-09-09 | 2013-09-09 | 半導体装置およびその製造方法、電力変換装置、3相モータシステム、自動車、ならびに鉄道車両 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9711600B2 (ja) |
EP (1) | EP3046149B1 (ja) |
JP (1) | JP6236456B2 (ja) |
CN (1) | CN105493293B (ja) |
WO (1) | WO2015033463A1 (ja) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016103814A1 (ja) * | 2014-12-25 | 2016-06-30 | 富士電機株式会社 | 半導体装置 |
JP2017055026A (ja) * | 2015-09-11 | 2017-03-16 | 株式会社東芝 | 半導体装置 |
JP2017208490A (ja) * | 2016-05-19 | 2017-11-24 | ローム株式会社 | 高速ダイオード及びその製造方法 |
WO2018012159A1 (ja) * | 2016-07-15 | 2018-01-18 | 富士電機株式会社 | 炭化珪素半導体装置 |
CN108630681A (zh) * | 2017-03-17 | 2018-10-09 | 富士电机株式会社 | 半导体集成电路装置 |
JPWO2019159237A1 (ja) * | 2018-02-13 | 2021-01-07 | 新電元工業株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2022508206A (ja) * | 2018-11-21 | 2022-01-19 | 比亜迪半導体股▲ふん▼有限公司 | ファストリカバリーダイオード及びその製造方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019054170A (ja) | 2017-09-15 | 2019-04-04 | 株式会社東芝 | 半導体装置 |
CN107910379A (zh) * | 2017-11-22 | 2018-04-13 | 北京燕东微电子有限公司 | 一种SiC结势垒肖特基二极管及其制作方法 |
US10937869B2 (en) * | 2018-09-28 | 2021-03-02 | General Electric Company | Systems and methods of masking during high-energy implantation when fabricating wide band gap semiconductor devices |
EP4029139A4 (en) | 2019-09-13 | 2023-09-27 | Milwaukee Electric Tool Corporation | CURRENT TRANSFORMER WITH WIDE BANDGAP SEMICONDUCTORS |
US20220157951A1 (en) * | 2020-11-17 | 2022-05-19 | Hamza Yilmaz | High voltage edge termination structure for power semicondcutor devices and manufacturing method thereof |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010267783A (ja) * | 2009-05-14 | 2010-11-25 | Mitsubishi Electric Corp | 炭化珪素半導体装置の製造方法 |
JP2011165856A (ja) * | 2010-02-09 | 2011-08-25 | Mitsubishi Electric Corp | 炭化珪素半導体装置の製造方法 |
WO2012049872A1 (ja) * | 2010-10-15 | 2012-04-19 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP2012094683A (ja) * | 2010-10-27 | 2012-05-17 | National Institute Of Advanced Industrial & Technology | ワイドバンドギャップ半導体装置 |
JP5122810B2 (ja) | 2003-01-15 | 2013-01-16 | クリー インコーポレイテッド | 炭化ケイ素半導体デバイスのためのエッジ終端構造及びその製造方法 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6393153A (ja) * | 1986-10-07 | 1988-04-23 | Toshiba Corp | 半導体装置の製造方法 |
JP3171888B2 (ja) | 1991-10-25 | 2001-06-04 | 松下電工株式会社 | シャフト盤 |
US6002159A (en) * | 1996-07-16 | 1999-12-14 | Abb Research Ltd. | SiC semiconductor device comprising a pn junction with a voltage absorbing edge |
JP4562835B2 (ja) * | 1999-11-05 | 2010-10-13 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP5088993B2 (ja) * | 2001-02-16 | 2012-12-05 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US7589032B2 (en) * | 2001-09-10 | 2009-09-15 | Semiconductor Energy Laboratory Co., Ltd. | Laser apparatus, laser irradiation method, semiconductor manufacturing method, semiconductor device, and electronic equipment |
JP2005079339A (ja) * | 2003-08-29 | 2005-03-24 | National Institute Of Advanced Industrial & Technology | 半導体装置、およびその半導体装置を用いた電力変換器、駆動用インバータ、汎用インバータ、大電力高周波通信機器 |
JP4186919B2 (ja) * | 2004-12-07 | 2008-11-26 | 三菱電機株式会社 | 半導体装置 |
US20060194400A1 (en) * | 2005-01-21 | 2006-08-31 | Cooper James A | Method for fabricating a semiconductor device |
US7498633B2 (en) * | 2005-01-21 | 2009-03-03 | Purdue Research Foundation | High-voltage power semiconductor device |
JP2008103529A (ja) | 2006-10-19 | 2008-05-01 | Toyota Central R&D Labs Inc | 半導体装置 |
JP4286877B2 (ja) * | 2007-03-13 | 2009-07-01 | Okiセミコンダクタ株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP5452062B2 (ja) * | 2009-04-08 | 2014-03-26 | 三菱電機株式会社 | 炭化珪素半導体装置の製造方法 |
US8637386B2 (en) | 2009-05-12 | 2014-01-28 | Cree, Inc. | Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same |
KR102434906B1 (ko) * | 2010-04-23 | 2022-08-23 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치의 제작 방법 |
JP2012195519A (ja) | 2011-03-18 | 2012-10-11 | Kyoto Univ | 半導体素子及び半導体素子の製造方法 |
DE112012001565T5 (de) * | 2011-04-04 | 2014-01-16 | Mitsubishi Electric Corp. | Halbleitervorrichtung und Verfahren zur Herstellung derselben |
JP5721902B2 (ja) | 2012-03-16 | 2015-05-20 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
KR101916223B1 (ko) * | 2012-04-13 | 2018-11-07 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
JP6029397B2 (ja) * | 2012-09-14 | 2016-11-24 | 三菱電機株式会社 | 炭化珪素半導体装置 |
WO2014045480A1 (ja) | 2012-09-21 | 2014-03-27 | 三菱電機株式会社 | 半導体装置及び半導体装置の製造方法 |
CN105027288B (zh) * | 2013-03-25 | 2018-09-18 | 新电元工业株式会社 | 半导体元件 |
-
2013
- 2013-09-09 EP EP13892962.5A patent/EP3046149B1/en active Active
- 2013-09-09 US US14/916,801 patent/US9711600B2/en active Active
- 2013-09-09 JP JP2015535257A patent/JP6236456B2/ja active Active
- 2013-09-09 WO PCT/JP2013/074222 patent/WO2015033463A1/ja active Application Filing
- 2013-09-09 CN CN201380079101.6A patent/CN105493293B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5122810B2 (ja) | 2003-01-15 | 2013-01-16 | クリー インコーポレイテッド | 炭化ケイ素半導体デバイスのためのエッジ終端構造及びその製造方法 |
JP2010267783A (ja) * | 2009-05-14 | 2010-11-25 | Mitsubishi Electric Corp | 炭化珪素半導体装置の製造方法 |
JP2011165856A (ja) * | 2010-02-09 | 2011-08-25 | Mitsubishi Electric Corp | 炭化珪素半導体装置の製造方法 |
WO2012049872A1 (ja) * | 2010-10-15 | 2012-04-19 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP2012094683A (ja) * | 2010-10-27 | 2012-05-17 | National Institute Of Advanced Industrial & Technology | ワイドバンドギャップ半導体装置 |
Non-Patent Citations (2)
Title |
---|
EXTENDED ABSTRACT OF THE 73RD ACADEMIC LECTURE PRESENTATION OF THE JAPAN SOCIETY OF APPLIED PHYSICS, pages 15 - 282 |
See also references of EP3046149A4 |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016103814A1 (ja) * | 2014-12-25 | 2016-06-30 | 富士電機株式会社 | 半導体装置 |
JPWO2016103814A1 (ja) * | 2014-12-25 | 2017-05-25 | 富士電機株式会社 | 半導体装置 |
US10727304B2 (en) | 2014-12-25 | 2020-07-28 | Fuji Electric Co., Ltd. | Semiconductor device |
US10374043B2 (en) | 2014-12-25 | 2019-08-06 | Fuji Electric Co., Ltd. | Semiconductor device |
JP2017055026A (ja) * | 2015-09-11 | 2017-03-16 | 株式会社東芝 | 半導体装置 |
CN106531801A (zh) * | 2015-09-11 | 2017-03-22 | 株式会社东芝 | 半导体装置 |
JP2017208490A (ja) * | 2016-05-19 | 2017-11-24 | ローム株式会社 | 高速ダイオード及びその製造方法 |
US10355090B2 (en) | 2016-07-15 | 2019-07-16 | Fuji Electric Co., Ltd. | Silicon carbide semiconductor device |
JPWO2018012159A1 (ja) * | 2016-07-15 | 2018-10-25 | 富士電機株式会社 | 炭化珪素半導体装置 |
WO2018012159A1 (ja) * | 2016-07-15 | 2018-01-18 | 富士電機株式会社 | 炭化珪素半導体装置 |
CN108630681A (zh) * | 2017-03-17 | 2018-10-09 | 富士电机株式会社 | 半导体集成电路装置 |
CN108630681B (zh) * | 2017-03-17 | 2023-09-08 | 富士电机株式会社 | 半导体集成电路装置 |
JPWO2019159237A1 (ja) * | 2018-02-13 | 2021-01-07 | 新電元工業株式会社 | 半導体装置及び半導体装置の製造方法 |
US11195907B2 (en) | 2018-02-13 | 2021-12-07 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
JP2022508206A (ja) * | 2018-11-21 | 2022-01-19 | 比亜迪半導体股▲ふん▼有限公司 | ファストリカバリーダイオード及びその製造方法 |
JP7518829B2 (ja) | 2018-11-21 | 2024-07-18 | 比亜迪半導体股▲ふん▼有限公司 | ファストリカバリーダイオード及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP3046149A4 (en) | 2017-04-12 |
EP3046149B1 (en) | 2019-08-21 |
US9711600B2 (en) | 2017-07-18 |
JP6236456B2 (ja) | 2017-11-22 |
US20160218187A1 (en) | 2016-07-28 |
EP3046149A1 (en) | 2016-07-20 |
CN105493293B (zh) | 2018-08-24 |
CN105493293A (zh) | 2016-04-13 |
JPWO2015033463A1 (ja) | 2017-03-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6236456B2 (ja) | 半導体装置およびその製造方法 | |
CN107342329B (zh) | 二极管以及使用了二极管的电力变换装置 | |
JP6309656B2 (ja) | 半導体装置及びその製造方法、電力変換装置、3相モータシステム、自動車並びに鉄道車両 | |
US9960259B2 (en) | Semiconductor device, method for manufacturing same, power conversion device, three-phase motor system, automobile, and railway carriage | |
JP6336055B2 (ja) | 半導体装置、半導体装置の製造方法、電力変換装置、3相モータシステム、自動車、および鉄道車両 | |
US10367090B2 (en) | Silicon carbide semiconductor device, power module, and power conversion device | |
US10236370B2 (en) | Semiconductor device and method of manufacturing the same, power converter, three-phase motor system, automobile and railway vehicle | |
JP6255111B2 (ja) | 半導体装置、インバータモジュール、インバータ、鉄道車両、および半導体装置の製造方法 | |
WO2016002057A1 (ja) | 半導体装置、パワーモジュール、電力変換装置、3相モータシステム、自動車、並びに鉄道車両 | |
JP6283122B2 (ja) | 半導体スイッチング素子および炭化珪素半導体装置の製造方法 | |
JP2017174969A (ja) | 半導体装置およびその製造方法並びに電力変換装置 | |
WO2015040675A1 (ja) | 半導体装置、電力変換装置、鉄道車両、および半導体装置の製造方法 | |
JP2018037621A (ja) | 半導体装置およびその製造方法、電力変換装置 | |
WO2016002058A1 (ja) | 半導体装置およびその製造方法、パワーモジュール、並びに電力変換装置 | |
JP6556892B2 (ja) | 半導体装置、半導体装置の製造方法、電力変換装置、3相モータシステム、自動車、および鉄道車両 | |
JP6592119B2 (ja) | 半導体スイッチング素子および炭化珪素半導体装置の製造方法 | |
JP7075876B2 (ja) | 炭化ケイ素半導体装置、電力変換装置、3相モータシステム、自動車および鉄道車両 | |
JP6473073B2 (ja) | 半導体装置、パワーモジュール、電力変換装置、自動車および鉄道車両 | |
JP2020038944A (ja) | 半導体装置およびその製造方法、電力変換装置、3相モータシステム、自動車並びに鉄道車両 | |
JP2019207906A (ja) | 半導体装置及びその製造方法、電力変換装置、3相モータシステム、自動車、並びに鉄道車両 | |
WO2015193965A1 (ja) | 半導体装置、パワーモジュール、電力変換装置、鉄道車両、および半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201380079101.6 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 13892962 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2015535257 Country of ref document: JP Kind code of ref document: A |
|
REEP | Request for entry into the european phase |
Ref document number: 2013892962 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2013892962 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14916801 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |