WO2015006993A1 - 一种阵列基板及显示面板 - Google Patents

一种阵列基板及显示面板 Download PDF

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Publication number
WO2015006993A1
WO2015006993A1 PCT/CN2013/080019 CN2013080019W WO2015006993A1 WO 2015006993 A1 WO2015006993 A1 WO 2015006993A1 CN 2013080019 W CN2013080019 W CN 2013080019W WO 2015006993 A1 WO2015006993 A1 WO 2015006993A1
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WO
WIPO (PCT)
Prior art keywords
metal layer
disposed
ito film
opening
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2013/080019
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English (en)
French (fr)
Inventor
姜佳丽
施明宏
杜鹏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to RU2016105305A priority Critical patent/RU2627938C1/ru
Priority to US14/006,100 priority patent/US9184182B2/en
Priority to JP2016526396A priority patent/JP6273357B2/ja
Priority to KR1020167004365A priority patent/KR101894161B1/ko
Priority to GB1522577.4A priority patent/GB2529980B/en
Publication of WO2015006993A1 publication Critical patent/WO2015006993A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a display panel.
  • a conventional display panel includes an array substrate, a color filter substrate, and a liquid crystal layer therebetween.
  • the color film substrate comprises an ITO film
  • the array substrate comprises a pixel unit for providing image display
  • the pixel unit comprises an ITO film
  • the ITO film of the pixel unit is electrically connected to the corresponding metal layer through the opening.
  • the ITO film on the color filter substrate and the ITO film of the pixel unit generate an electric field. Due to the provision of the via hole, a curved electric field is formed at the edge, and the curved electric field overlaps the liquid crystal on the edge side toward the liquid crystal in the middle vertical electric field. Thus forming a disclination line (Disclination) Line).
  • the wrong line will reduce the transmittance of the display panel, thereby increasing the cost.
  • the area of the disclination line is large, even a variety of display unevenness (Mura) may occur in the display panel, thereby affecting the display quality.
  • the technical problem to be solved by the present invention is to provide an array substrate and a display panel, which can reduce the probability of occurrence of a disclination line and improve the display quality of the display panel.
  • a technical solution adopted by the present invention is to provide an array substrate including a data line, a scan line, and a pixel structure surrounded by a data line and a scan line.
  • the pixel structure includes an ITO film and is disposed on At least one metal layer under the ITO film, wherein the ITO film is electrically connected to the metal layer through the opening, the ITO film is provided with a slit, and the slit is disposed at the joint of the ITO film and the opening to reduce the occurrence of the disclination line.
  • the pixel structure further includes a thin film transistor disposed near the intersection of the data line and the scan line, and a passivation layer disposed between the ITO film and the metal layer, the metal layer including a source and a drain metal layer of the thin film transistor, the opening penetrates the passivation layer and exposes the source or drain metal layer of the thin film transistor, and the ITO film is disposed through the opening in the source or drain metal layer of the thin film transistor Above.
  • the slit is disposed at an edge of the source or drain metal layer of the thin film transistor and extends away from the hole.
  • an array substrate including a data line, a scan line, and a pixel structure surrounded by a data line and a scan line.
  • the pixel structure includes an ITO film and a setting. At least one metal layer under the ITO film, wherein the ITO film is electrically connected to the metal layer through the opening, the ITO film is provided with a slit, and the slit is disposed at the joint of the ITO film and the opening to reduce the occurrence of the disclination line The probability.
  • the length and width of the slit are respectively greater than 2.5 microns.
  • the pixel structure further includes a thin film transistor disposed near the intersection of the data line and the scan line, and a passivation layer disposed between the ITO film and the metal layer, the metal layer including the source and drain metal layers of the thin film transistor, and the opening The passivation layer is penetrated and the source or drain metal layer of the thin film transistor is exposed, and the ITO film is disposed through the opening above the source or drain metal layer of the thin film transistor.
  • the slit is disposed at an edge of the source or drain metal layer of the thin film transistor and extends away from the hole.
  • the pixel structure further comprises a passivation layer and an insulating layer disposed between the ITO film and the metal layer, the metal layer comprises a common electrode metal layer, the opening penetrates the passivation layer and the insulating layer simultaneously and exposes the common electrode metal layer, The ITO film is disposed above the common electrode metal layer through the opening.
  • the slit is disposed at an edge of the common electrode metal layer and extends away from the hole.
  • a display panel including a color film substrate and an array substrate disposed opposite to each other, the array substrate including data lines, scan lines, and data lines and scanning a pixel structure surrounded by a line, the pixel structure comprising an ITO film and at least one metal layer disposed under the ITO film, wherein the ITO film is electrically connected to the metal layer through the opening, the ITO film is provided with a slit, and the slit is disposed on the ITO The junction of the film and the opening to reduce the probability of occurrence of the disclination line.
  • the length and width of the slit are respectively greater than 2.5 microns.
  • the pixel structure further includes a thin film transistor disposed near the intersection of the data line and the scan line, and a passivation layer disposed between the ITO film and the metal layer, the metal layer including the source and drain metal layers of the thin film transistor, and the opening The passivation layer is penetrated and the source or drain metal layer of the thin film transistor is exposed, and the ITO film is disposed through the opening above the source or drain metal layer of the thin film transistor.
  • the slit is disposed at an edge of the source or drain metal layer of the thin film transistor and extends away from the hole.
  • the pixel structure further comprises a passivation layer and an insulating layer disposed between the ITO film and the metal layer, the metal layer comprises a common electrode metal layer, the opening penetrates the passivation layer and the insulating layer simultaneously and exposes the common electrode metal layer, The ITO film is disposed above the common electrode metal layer through the opening.
  • the slit is disposed at an edge of the common electrode metal layer and extends away from the hole.
  • the beneficial effects of the present invention are: different from the prior art, the ITO film of the pixel structure on the array substrate of the present invention is electrically connected to the underlying metal layer through the opening, and the slit is provided on the ITO film, the slit It is placed at the junction of the ITO film and the opening.
  • the corresponding bending electric field is respectively generated on both sides of the slit, thereby reducing the bending electric field generated by the opening, thereby reducing the probability of occurrence of the disclination line and improving the display of the display panel. quality.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present invention
  • Figure 2 is a cross-sectional view of the array substrate shown in Figure 1 taken along line A-A';
  • FIG. 3 is a schematic structural view of another embodiment of the array substrate of the present invention.
  • Figure 4 is a cross-sectional view of the array substrate shown in Figure 3 taken along line BB';
  • Fig. 5 is a schematic structural view of an embodiment of a display panel of the present invention.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • 2 is a cross-sectional view of the array substrate shown in FIG. 1 taken along line AA'.
  • the array substrate 10 includes a data line 11, a scan line 12, and a pixel structure 13 surrounded by the data line 11 and the scan line 12.
  • the pixel structure 13 includes an ITO film 14 and at least one metal layer M disposed under the ITO film 14.
  • the ITO film 14 is electrically connected to the metal layer M through the opening 151.
  • the ITO film 14 is provided with a slit 16 and narrow. A slit 16 is provided at the junction of the ITO film 14 and the opening 151 to reduce the probability of occurrence of the disclination line.
  • the pixel structure 13 further includes a thin film transistor T and a common electrode 111 disposed near the intersection of the data line 11 and the scan line 12.
  • the thin film transistor T includes a gate G, a source S, and a drain D.
  • the gate G is electrically connected to the scan line 12
  • the source S is electrically connected to the data line 11
  • the drain D is electrically connected to the ITO film 14 through the opening 151.
  • the common electrode 111 is disposed in parallel with the scanning line 12, and the common electrode 111 is electrically connected to the ITO film 14 through the opening 152.
  • the metal layer M includes a gate metal layer M11, a source metal layer M21, and a drain metal layer M22.
  • the gate G is formed on the glass substrate 17 of the array substrate 10 by the gate metal layer M11.
  • a gate insulating layer 18 is formed on the gate G for insulating between the gate G and the source S and the drain D.
  • a semiconductor layer 19 and a doped semiconductor layer 20 are formed on the gate insulating layer 18.
  • a hole 21 is formed in the semiconductor layer 19 and the doped semiconductor layer 20, and the hole 21 penetrates the doped semiconductor layer 20 and passes through a portion of the semiconductor layer 19.
  • the source S is formed of the source metal layer M21
  • the drain D is formed of the drain metal layer M22
  • the source metal layer M21 and the drain metal layer M22 are respectively disposed on both sides of the hole 21, and are disposed on the doped semiconductor On layer 20.
  • the semiconductor layer 19 and the doped semiconductor layer 20 function as switches. Specifically, when the gate G receives the turn-on signal of the scan line 12 to turn on the thin film transistor T, the semiconductor layer 19 and the doped semiconductor layer 20 turn on the source S and the drain D, thereby causing the signal transmitted by the data line 11.
  • a passivation layer 22 is covered on the source metal layer M21 and the drain metal layer M22, and an opening 151 is disposed at a position corresponding to the drain metal layer M22 of the passivation layer 22, and the opening 151 penetrates the passivation layer 22 and The drain metal layer M22 of the thin film transistor T is exposed.
  • the ITO film 14 is disposed on the passivation layer 22 and electrically connected to the drain metal layer M22 through the opening 151.
  • the slit 16 is disposed at the edge of the drain metal layer M22 of the thin film transistor T and extends away from the hole 151.
  • the length and width of the slit 16 are preferably greater than 2.5 microns, respectively.
  • the slit 16 may also be disposed at the position P1 or P2 in FIG. 1 or the slit 16 is annular, and the opening 151 is surrounded.
  • the position and shape of the slit 16 are not limited herein. It is to be noted that although the slit 16 is provided at the junction of the ITO film 14 and the opening 151, the ITO film 14 and the opening 151 still have a connecting portion.
  • the source metal layer M21 and the drain metal layer M22 are the same metal material.
  • the opening 151 may also be disposed at a position corresponding to the source metal layer M21 of the passivation layer 22, that is, the ITO film 14 is electrically connected to the source metal layer M21 through the opening 151.
  • the slit 16 is provided at the edge of the source metal layer M21 of the thin film transistor T, and extends in a direction away from the hole 151.
  • the present invention provides a slit 16 on the ITO film 14, and the slit 16 is disposed at the junction of the ITO film 14 and the opening 151, so that a corresponding bending electric field is generated on both sides of the slit 16 when displayed.
  • the bending electric field generated by the provision of the opening 151 is reduced, and therefore, the probability of occurrence of the disclination line is reduced.
  • FIG. 3 is a structural diagram of another embodiment of the array substrate of the present invention.
  • the array substrate 30 shown in FIG. 3 is different from the array substrate 10 shown in FIG. 1 in that a slit 36 is provided at a junction of the ITO film 34 and the opening 352.
  • FIG. 4 is a cross-sectional view of the array substrate 30 shown in FIG. 3 taken along line BB′.
  • the metal layer further includes a common electrode metal layer M12.
  • the common electrode 311 is formed of a common electrode metal layer M12, and the common electrode metal layer M12 and the gate metal layer M11 are made of the same metal material, and both are disposed in the same layer.
  • the opening 352 penetrates the insulating layer 38 and the passivation layer 42 at the same time and exposes the common electrode metal layer M12.
  • the ITO film 34 passes through the opening 352 and the common electrode.
  • the metal layer M12 is electrically connected.
  • the slit 36 is disposed at an edge of the common electrode layer M12 and extends away from the hole 352.
  • the slit 36 can also be disposed at other positions, such as the W1 or W2 position in the figure, or the slit 36 is annular, and the opening 352 is surrounded.
  • the position and shape of the slit 36 are not limited herein. It should be noted that although the slit 36 is disposed at the junction of the ITO film 34 and the opening 352, the ITO film 34 and the opening 352 still have a connecting portion.
  • the arrangement of the slit 36 of the present embodiment can also produce a corresponding bending electric field on both sides of the display, thereby reducing the bending electric field generated by the provision of the opening 352, thereby reducing the disclination line. The probability of occurrence.
  • FIG. 5 is a schematic structural diagram of an embodiment of a display panel according to the present invention.
  • the display panel 50 of the present invention includes a color film substrate 51, an array substrate 52, and a color arrangement disposed opposite to each other.
  • the array substrate 52 is an array substrate as described above, and details are not described herein again.
  • the ITO film of the pixel structure on the array substrate of the present invention is electrically connected to the underlying metal layer through the opening, and a slit is disposed on the ITO film, and the slit is disposed at the junction of the ITO film and the opening. .
  • the corresponding bending electric field is respectively generated on both sides of the slit, thereby reducing the bending electric field generated by the opening, thereby reducing the probability of occurrence of the disclination line and improving the display panel. Display quality.

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  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
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Abstract

一种阵列基板（10）及显示面板（50）。该阵列基板（10）包括数据线（11）、扫描线（12）以及数据线（11）和扫描线（12）围成的像素结构（13）。像素结构（13）包括ITO薄膜（14）以及设置在ITO薄膜（14）下方的至少一金属层（M）。ITO薄膜（14）通过开孔（151）与金属层（M）电连接，并且ITO薄膜（14）上设置有狭缝（16）,其中狭缝（16）设置在ITO薄膜（14）与开孔（151）的连接处的外侧。通过上述方式，能够降低向错线出现的概率，从而改善显示面板（50）的显示品质。

Description

一种阵列基板及显示面板
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板及显示面板。
【背景技术】
现有的显示面板包括相对设置的阵列基板、彩膜基板以及两者之间的液晶层。其中，彩膜基板包括ITO薄膜，阵列基板包括提供图像显示的像素单元，像素单元包括ITO薄膜，像素单元的ITO薄膜通过开孔与相应的金属层电连接。
彩膜基板上的ITO薄膜与像素单元的ITO薄膜会产生电场，由于设置了过孔，在边缘处会形成弯曲的电场，弯曲的电场使边缘侧的液晶向中间垂直电场的液晶重叠在一起，从而形成向错线（Disclination line）。
向错线会使显示面板的穿透率降低，进而提升成本。当向错线面积较大时，甚至会造成显示面板出现各种显示不均(Mura)的现象，进而影响显示品质。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及显示面板，能够降低向错线出现的概率，改善显示面板的显示品质。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，该阵列基板包括数据线、扫描线以及数据线和扫描线围成的像素结构，像素结构包括ITO薄膜以及设置在ITO薄膜下方的至少一金属层，其中，ITO薄膜通过开孔与金属层电连接，ITO薄膜上设置有狭缝，狭缝设置在ITO薄膜与开孔的连接处，以降低向错线出现的概率；其中，狭缝的长和宽分别大于2.5微米；像素结构还包括设置在数据线和扫描线相交处附近的薄膜晶体管以及设置在ITO薄膜和金属层之间的钝化层，金属层包括薄膜晶体管的源极和漏极金属层，开孔穿透钝化层并暴露出薄膜晶体管的源极或漏极金属层，ITO薄膜通过开孔设置在薄膜晶体管的源极或漏极金属层的上方。
其中，狭缝对应薄膜晶体管的源极或漏极金属层的边缘处设置，并朝远离开孔的方向延伸。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，该阵列基板包括数据线、扫描线以及数据线和扫描线围成的像素结构，像素结构包括ITO薄膜以及设置在ITO薄膜下方的至少一金属层，其中，ITO薄膜通过开孔与金属层电连接，ITO薄膜上设置有狭缝，狭缝设置在ITO薄膜与开孔的连接处，以降低向错线出现的概率。
其中，狭缝的长和宽分别大于2.5微米。
其中，像素结构还包括设置在数据线和扫描线相交处附近的薄膜晶体管以及设置在ITO薄膜和金属层之间的钝化层，金属层包括薄膜晶体管的源极和漏极金属层，开孔穿透钝化层并暴露出薄膜晶体管的源极或漏极金属层，ITO薄膜通过开孔设置在薄膜晶体管的源极或漏极金属层的上方。
其中，狭缝对应薄膜晶体管的源极或漏极金属层的边缘处设置，并朝远离开孔的方向延伸。
其中，像素结构还包括设置在ITO薄膜和金属层之间的钝化层和绝缘层，金属层包括公共电极金属层，开孔同时穿透钝化层和绝缘层并暴露出公共电极金属层，ITO薄膜通过开孔设置在公共电极金属层的上方。
其中，狭缝对应公共电极金属层的边缘处设置，并朝远离开孔的方向延伸。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种显示面板，该显示面板包括相对设置的彩膜基板和阵列基板，该阵列基板包括数据线、扫描线以及数据线和扫描线围成的像素结构，像素结构包括ITO薄膜以及设置在ITO薄膜下方的至少一金属层，其中，ITO薄膜通过开孔与金属层电连接，ITO薄膜上设置有狭缝，狭缝设置在ITO薄膜与开孔的连接处，以降低向错线出现的概率。
其中，狭缝的长和宽分别大于2.5微米。
其中，像素结构还包括设置在数据线和扫描线相交处附近的薄膜晶体管以及设置在ITO薄膜和金属层之间的钝化层，金属层包括薄膜晶体管的源极和漏极金属层，开孔穿透钝化层并暴露出薄膜晶体管的源极或漏极金属层，ITO薄膜通过开孔设置在薄膜晶体管的源极或漏极金属层的上方。
其中，狭缝对应薄膜晶体管的源极或漏极金属层的边缘处设置，并朝远离开孔的方向延伸。
其中，像素结构还包括设置在ITO薄膜和金属层之间的钝化层和绝缘层，金属层包括公共电极金属层，开孔同时穿透钝化层和绝缘层并暴露出公共电极金属层，ITO薄膜通过开孔设置在公共电极金属层的上方。
其中，狭缝对应公共电极金属层的边缘处设置，并朝远离开孔的方向延伸。
本发明的有益效果是：区别于现有技术的情况，本发明阵列基板上的像素结构的ITO薄膜通过开孔与其下方的金属层电连接，并在ITO薄膜上设置有狭缝，该狭缝设置在ITO薄膜与开孔的连接处。通过上述方式，本发明在显示时，狭缝两侧分别产生相对应的弯曲电场，从而减少了因设置开孔产生的弯曲电场，因此减小了向错线出现的概率，改善显示面板的显示品质。
【附图说明】
图1是本发明阵列基板的一实施例的结构示意图；
图2是图1所示的阵列基板沿A-A＇线的剖面图；
图3是本发明阵列基板的另一实施例的结构示意图；
图4是图3所示的阵列基板沿B-B＇线的剖面图；
图5是本发明显示面板的一实施例的结构示意图。
【具体实施方式】
下面结合附图和实施例对本发明进行详细的说明。
请一并参阅图1和图2，图1是本发明阵列基板的一实施例的结构示意图。图2是图1所示的阵列基板沿A-A＇线的剖面图。如图1和2所示，阵列基板10包括数据线11、扫描线12以及数据线11和扫描线12围成的像素结构13。其中，像素结构13包括ITO薄膜14以及设置在ITO薄膜14下方的至少一金属层M，其中，ITO薄膜14通过开孔151与金属层M电连接，ITO薄膜14上设置有狭缝16，狭缝16设置在ITO薄膜14与开孔151的连接处，以降低向错线出现的概率。
具体地，像素结构13还包括设置在数据线11和扫描线12相交处附近的薄膜晶体管T以及公共电极111。薄膜晶体管T包括栅极G、源极S以及漏极D。其中，栅极G与扫描线12电连接，源极S与数据线11电连接，漏极D通过开孔151与ITO薄膜14电连接。公共电极111与扫描线12平行设置，公共电极111通过开孔152与ITO薄膜14电连接。
本实施例中，金属层M包括栅极金属层M11、源极金属层M21和漏极金属层M22。栅极G由栅极金属层M11形成在阵列基板10的玻璃基板17上。栅极G上形成栅极绝缘层18，用于在栅极G和源极S以及漏极D之间起到绝缘作用。栅极绝缘层18上形成半导体层19和掺杂半导体层20。在半导体层19和掺杂半导体层20上设置孔槽21，孔槽21穿透掺杂半导体层20并穿过一部分的半导体层19。源极S由源极金属层M21形成，漏极D由漏极金属层M22形成，并且源极金属层M21和漏极金属层M22分别设置在孔槽21的两侧，并设置在掺杂半导体层20上。半导体层19和掺杂半导体层20起到开关的作用。具体的，当栅极G接收到扫描线12的开启信号而打开薄膜晶体管T时，半导体层19和掺杂半导体层20使源极S和漏极D导通，从而使数据线11传输的信号经过源极S传输到漏极D；当栅极G未接收到扫描线12的信号，或者接收到扫描线12的关闭信号而关闭薄膜晶体管T时，半导体层19和掺杂半导体层20使源极S和漏极D断开。在源极金属层M21和漏极金属层M22上覆盖着一钝化层22，在钝化层22对应漏极金属层M22的位置设置开孔151，并且开孔151穿透钝化层22并暴露出薄膜晶体管T的漏极金属层M22。ITO薄膜14设置在钝化层22上，并通过开孔151与漏极金属层M22电连接。
本实施例中，狭缝16对应薄膜晶体管T的漏极金属层M22的边缘处设置，并朝远离开孔151的方向延伸。其中，狭缝16的长和宽分别优选大于2.5微米。其中，狭缝16还可以设置在如图1中的P1或者P2位置，或者狭缝16为环状，将开孔151包围，具体狭缝16的位置和形状在此不再限制。值得注意的是，虽然狭缝16设置在ITO薄膜14与开孔151的连接处，但ITO薄膜14与开孔151仍保有相连部分。
本实施例中，源极金属层M21和漏极金属层M22是同一金属材料。
在其他优选实施例中，开孔151也可以设置在钝化层22对应源极金属层M21的位置，即ITO薄膜14通过开孔151与源极金属层M21电连接。此时，狭缝16对应薄膜晶体管T的源极金属层M21的边缘处设置，并朝远离开孔151的方向延伸。
因此，本发明通过在ITO薄膜14上设置狭缝16，并且狭缝16设置在ITO薄膜14与开孔151的连接处，使得在显示时，狭缝16两侧分别产生相对应的弯曲电场，从而减少了因设置开孔151产生的弯曲电场，因此，减小了向错线出现的概率。
请参阅图3，图3是本发明阵列基板的另一实施例的结构图。图3所示的阵列基板30与图1所示的阵列基板10的不同之处在于：狭缝36设置在ITO薄膜34与开孔352的连接处。请一并参阅图4，图4是图3所示的阵列基板30沿B-B＇的剖面图。本实施例中，金属层还包括公共电极金属层M12。公共电极311由公共电极金属层M12形成，公共电极金属层M12与栅极金属层M11是由同一金属材料，并且两者设置在同一层。公共电极金属层M12上依次设置绝缘层38和钝化层42，开孔352同时穿透绝缘层38和钝化层42并暴露出公共电极金属层M12，ITO薄膜34通过开孔352与公共电极金属层M12电连接。狭缝36对应公共电极层M12的边缘处设置，并朝远离开孔352的方向延伸。当然，狭缝36还可以设置在其他位置，如图中的W1或W2位置，或者狭缝36为环状，将开孔352包围，具体狭缝36的位置和形状在此不再限制。值得注意的是，虽然狭缝36设置在ITO薄膜34与开孔352的连接处，但ITO薄膜34与开孔352仍保有相连部分。
同理，本实施例的狭缝36的设置同样可以在显示时，其两侧分别产生相对应的弯曲电场，从而减少了因设置开孔352产生的弯曲电场，因此，减小了向错线出现的概率。
请参阅图5，图5是本发明一种显示面板的一实施例的结构示意图，如图5所示，本发明的显示面板50包括相对设置的彩膜基板51、阵列基板52以及设置在彩膜基板51和阵列基板52之间的液晶层53。其中阵列基板52如前文所述的阵列基板，在此不再赘述。
综上所述，本发明阵列基板上的像素结构的ITO薄膜通过开孔与其下方的金属层电连接，并在ITO薄膜上设置有狭缝，该狭缝设置在ITO薄膜与开孔的连接处。通过上述方式，本发明在显示时，狭缝两侧分别产生相对应的弯曲电场，从而减少了因设置开孔产生的弯曲电场，因此，减小了向错线出现的概率，改善显示面板的显示品质。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (14)

  1. 一种阵列基板，其中，所述阵列基板包括数据线、扫描线以及所述数据线和所述扫描线围成的像素结构，所述像素结构包括ITO薄膜以及设置在所述ITO薄膜下方的至少一金属层，所述ITO薄膜通过开孔与所述金属层电连接，所述ITO薄膜上设置有狭缝，所述狭缝设置在所述ITO薄膜与所述开孔的连接处，以降低向错线出现的概率；
    其中，所述狭缝的长和宽分别大于2.5微米；
    所述像素结构还包括设置在所述数据线和所述扫描线相交处附近的薄膜晶体管以及设置在所述ITO薄膜和所述金属层之间的钝化层，所述金属层包括所述薄膜晶体管的源极和漏极金属层，所述开孔穿透所述钝化层并暴露出所述薄膜晶体管的所述源极或漏极金属层，所述ITO薄膜通过所述开孔设置在所述薄膜晶体管的所述源极或漏极金属层的上方。
  2. 根据权利要求1所示的阵列基板，其中，所述狭缝对应所述薄膜晶体管的源极或漏极金属层的边缘处设置，并朝远离所述开孔的方向延伸。
  3. 一种阵列基板，其中，所述阵列基板包括数据线、扫描线以及所述数据线和所述扫描线围成的像素结构，所述像素结构包括ITO薄膜以及设置在所述ITO薄膜下方的至少一金属层，其中，所述ITO薄膜通过开孔与所述金属层电连接，所述ITO薄膜上设置有狭缝，所述狭缝设置在所述ITO薄膜与所述开孔的连接处，以降低向错线出现的概率。
  4. 根据权利要求3所述的阵列基板，其中，所述狭缝的长和宽分别大于2.5微米。
  5. 根据权利要求3所述的阵列基板，其中，所述像素结构还包括设置在所述数据线和所述扫描线相交处附近的薄膜晶体管以及设置在所述ITO薄膜和所述金属层之间的钝化层，所述金属层包括所述薄膜晶体管的源极和漏极金属层，所述开孔穿透所述钝化层并暴露出所述薄膜晶体管的所述源极或漏极金属层，所述ITO薄膜通过所述开孔设置在所述薄膜晶体管的所述源极或漏极金属层的上方。
  6. 根据权利要求5所示的阵列基板，其中，所述狭缝对应所述薄膜晶体管的源极或漏极金属层的边缘处设置，并朝远离所述开孔的方向延伸。
  7. 根据权利要求3所示的阵列基板，其中，所述像素结构还包括设置在所述ITO薄膜和所述金属层之间的钝化层和绝缘层，所述金属层包括公共电极金属层，所述开孔同时穿透所述钝化层和所述绝缘层并暴露出所述公共电极金属层，所述ITO薄膜通过所述开孔设置在所述公共电极金属层的上方。
  8. 根据权利要求7所述的阵列基板，其中，所述狭缝对应所述公共电极金属层的边缘处设置，并朝远离所述开孔的方向延伸。
  9. 一种显示面板，所述显示面板包括相对设置的彩膜基板和阵列基板，其中，所述阵列基板包括数据线、扫描线以及所述数据线和所述扫描线围成的像素结构，所述像素结构包括ITO薄膜以及设置在所述ITO薄膜下方的至少一金属层，其中，所述ITO薄膜通过开孔与所述金属层电连接，所述ITO薄膜上设置有狭缝，所述狭缝设置在所述ITO薄膜与所述开孔的连接处，以降低向错线出现的概率。
  10. 根据权利要求9所述的显示面板，其中，所述狭缝的长和宽分别大于2.5微米。
  11. 根据权利要求9所述的显示面板，其中，所述像素结构还包括设置在所述数据线和所述扫描线相交处附近的薄膜晶体管以及设置在所述ITO薄膜和所述金属层之间的钝化层，所述金属层包括所述薄膜晶体管的源极和漏极金属层，所述开孔穿透所述钝化层并暴露出所述薄膜晶体管的所述源极或漏极金属层，所述ITO薄膜通过所述开孔设置在所述薄膜晶体管的所述源极或漏极金属层的上方。
  12. 根据权利要求11所示的显示面板，其中，所述狭缝对应所述薄膜晶体管的源极或漏极金属层的边缘处设置，并朝远离所述开孔的方向延伸。
  13. 根据权利要求9所示的显示面板，其中，所述像素结构还包括设置在所述ITO薄膜和所述金属层之间的钝化层和绝缘层，所述金属层包括公共电极金属层，所述开孔同时穿透所述钝化层和所述绝缘层并暴露出所述公共电极金属层，所述ITO薄膜通过所述开孔设置在所述公共电极金属层的上方。
  14. 根据权利要求13所述的显示面板，其中，所述狭缝对应所述公共电极金属层的边缘处设置，并朝远离所述开孔的方向延伸。
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