WO2014206021A1 - 一种薄膜晶体管、其制备方法及包含该薄膜晶体管的装置 - Google Patents

一种薄膜晶体管、其制备方法及包含该薄膜晶体管的装置 Download PDF

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WO2014206021A1
WO2014206021A1 PCT/CN2013/089030 CN2013089030W WO2014206021A1 WO 2014206021 A1 WO2014206021 A1 WO 2014206021A1 CN 2013089030 W CN2013089030 W CN 2013089030W WO 2014206021 A1 WO2014206021 A1 WO 2014206021A1
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Prior art keywords
thin film
film transistor
active layer
layer
semiconductor material
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PCT/CN2013/089030
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English (en)
French (fr)
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李延钊
王刚
方金钢
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京东方科技集团股份有限公司
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Priority to US14/377,946 priority Critical patent/US9461070B2/en
Publication of WO2014206021A1 publication Critical patent/WO2014206021A1/zh

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Definitions

  • Embodiments of the present invention relate to the field of display technologies, and in particular, to a thin film transistor, a method of fabricating the same, and an apparatus including the same. Background technique
  • the existing Thin Film Transistor is usually an amorphous silicon thin film transistor, and the active layer of the amorphous silicon thin film transistor, that is, the thin film transistor is an amorphous silicon material, and the carrier of the amorphous silicon thin film transistor
  • the mobility is low, and its electron mobility is 0.1-1 cn ⁇ 1 , which cannot meet the needs of technological development. Therefore, low temperature polysilicon (LTPS) thin film transistors and oxide (Oxide) thin film transistors have been developed.
  • the LTPS thin film transistor is a thin film transistor whose active layer is a low temperature polysilicon material.
  • the low temperature polysilicon is obtained by converting amorphous silicon into polycrystalline silicon at a lower temperature.
  • the carrier mobility of the LTPS thin film transistor is about 100-500. Cn ⁇ V- 1 , but its uniformity is poor, so it is difficult to overcome when applied to large-size panels.
  • An oxide thin film transistor that is, a thin film transistor whose active layer is an oxide semiconductor material, which is sacrificed in order to ensure good uniformity of large size, and is currently oxidized while ensuring good uniformity.
  • the carrier mobility of the thin film transistor can reach 10 cm 1 ⁇ but the mobility of the carrier of the oxide thin film transistor cannot meet the development of the flat panel display technology. Therefore, current thin film transistors need to further improve carrier mobility with good uniformity. Summary of the invention
  • embodiments of the present invention provide a thin film transistor having a high carrier mobility. Embodiments of the present invention also provide a method of fabricating the thin film transistor and related apparatus including the thin film transistor.
  • Embodiments of the present invention provide a thin film transistor including: a substrate substrate, and a a gate, an active layer, a source and a drain on the substrate of the substrate; wherein the material of the active layer is an amorphous phosphide semiconductor material.
  • Embodiments of the present invention provide an array substrate including a thin film transistor provided by an embodiment of the present invention.
  • the embodiment of the invention provides a display panel comprising the array substrate provided by the embodiment of the invention.
  • Embodiments of the present invention provide a method for preparing the above thin film transistor.
  • the active layer of the thin film transistor is prepared by magnetron sputtering, pulsed laser deposition, chemical vapor deposition or solution deposition.
  • the active layer in the thin film transistor provided by the embodiment of the present invention is prepared using an amorphous phosphide semiconductor material. Since the mobility of carriers of the phosphide semiconductor material is relatively high, the active layer of the existing thin film transistor is prepared using amorphous silicon, polycrystalline silicon, microcrystalline silicon or an oxide semiconductor material, and amorphous phosphorus is used.
  • the semiconductor material is used to prepare an active layer of a thin film transistor, and a thin film transistor having a high carrier mobility can be obtained.
  • the array substrate and the display panel using such a thin film transistor can improve carrier mobility while ensuring good uniformity.
  • FIG. 1 is a schematic structural view of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of an array substrate according to an embodiment of the invention.
  • FIG. 3a is a schematic diagram showing a transfer characteristic curve of a thin film transistor according to an embodiment of the present invention
  • FIG. 3b is a schematic diagram showing an output characteristic curve of a thin film transistor according to an embodiment of the present invention
  • FIG. 4 is an output characteristic of an amorphous silicon thin film transistor according to a conventional technique. Schematic diagram of the curve. detailed description
  • an embodiment of the present invention provides a thin film transistor including: a substrate
  • the material of the active layer 3 is an amorphous phosphide semiconductor material.
  • the active layer is made of an amorphous phosphide semiconductor material. Since the mobility of carriers of the phosphide semiconductor material is relatively high, the thin film transistor made of amorphous silicon, polycrystalline silicon, microcrystalline silicon or oxide semiconductor material is used as compared with the conventional active layer material thereof. A thin film transistor whose source layer is made of an amorphous phosphide semiconductor material has a high carrier mobility.
  • the thickness of the active layer is usually controlled at
  • It is preferably between 5 nm and 200 nm.
  • the active layer may be an amorphous binary phosphide semiconductor material, such as: InP, Zn 3 P 2 , Ga 3 P 2 , or an amorphous multi-phosphorus compound.
  • the semiconductor material for example: InGaZnP or InGaZnOP, is not limited herein.
  • An amorphous binary phosphide semiconductor material refers to an amorphous binary compound semiconductor material composed of a metal element or a non-metal element and phosphorus
  • an amorphous multi-component phosphide refers to a metal element and/or a non-metal element.
  • the active layer of the above thin film transistor according to an embodiment of the present invention may also be made of an amorphous compound doped phosphor semiconductor material.
  • doping may be performed in an amorphous compound semiconductor material by adjusting the ratio.
  • the proportion of phosphorus element is used to achieve high carrier mobility, which will not be described in detail herein.
  • a thin film transistor having a bottom gate structure is taken as an example for description.
  • the above-mentioned thin film transistor TFT device provided by the embodiment of the present invention can be applied to various types of structures, that is, the TFT device can be a bottom gate type structure, a top gate type structure, an overlap type structure, an anti-overlap type structure, and a coplanar type. Structure or anti-coplanar structure, this article does not limit this.
  • the base substrate may be made of a transparent material such as glass or quartz, and the base substrate may also be made of other opaque materials, such as ceramic or metal, which is not described herein. limited.
  • the gate may be, for example,
  • the metal material of Mo, Ah or Cr may also be made of an alloy material, or may also be made of a composite metal layer such as Mo/Al, which is not limited herein.
  • the thickness of the gate is typically controlled between 1 nm and 500 nm.
  • the thin film transistor according to an embodiment of the present invention may further include: a gate insulating layer 6 formed between the gate electrode 2 and the active layer 3.
  • the gate insulating layer 6 may be an insulating material such as silicon oxide or silicon nitride, and the thickness of the gate insulating layer 6 is usually controlled between 1 nm and 300 nm.
  • the thin film transistor according to an embodiment of the present invention may further include: an etch barrier layer 7 formed between the active layer 3 and the drain 4 and the source 5.
  • the etch barrier layer 7 may be made of silicon oxide, silicon nitride or an organic insulating material, and the thickness of the etch barrier layer 7 is usually in the range of 5 nm to 500 nm.
  • the source and the drain may be respectively made of a metal material such as Mo, Al or Cr, or an alloy material, or may also be a composite metal layer such as Mo/Al. production. This article does not limit this.
  • the thickness of the source and drain are typically controlled between 1 nm and 500 nm, respectively.
  • an embodiment of the present invention further provides an array substrate including the above thin film transistor according to an embodiment of the present invention.
  • Those skilled in the art can implement the array substrate after reading the above embodiments of the thin film transistor, which will not be described herein.
  • the array substrate according to an embodiment of the present invention may include: a pixel electrode 8 formed on a thin film transistor, and the pixel electrode 8 is connected to the source 5.
  • the array substrate according to an embodiment of the present invention may further include: a passivation layer 9 formed between the source 5 and the pixel electrode 8, and the pixel electrode 8 passes through a via hole in the passivation layer 9. Connected to source 5.
  • the passivation layer 9 may be made of an insulating material such as silicon oxide, silicon nitride or an organic material, and the thickness of the passivation layer 9 is usually controlled to be between 5 nm and 500 nm.
  • the array substrate according to the embodiment of the present invention may further include a buffer layer between the substrate substrate and the gate, a planarization layer on the pixel electrode, a pixel defining layer, etc., which is not described herein. limited.
  • the above array substrate provided by the implementation of the present invention can be applied to liquid crystal display (Liquid Crystal)
  • the display panel can also be applied to an Organic Light Emitting Diode (OLED) display panel, which is not limited herein.
  • OLED Organic Light Emitting Diode
  • an embodiment of the present invention further provides a display panel, which includes the above-mentioned array substrate provided by the embodiment of the present invention.
  • the display panel may be a liquid crystal display panel or an OLED display panel.
  • the indispensable components are understood by those of ordinary skill in the art, and are not described herein, nor should they be construed as limiting the invention.
  • For the implementation of the display panel refer to the embodiment of the above array substrate, and the repeated description is omitted.
  • the OLED display panel may further include: an anode, a hole transport layer, an organic light-emitting layer, an electron transport layer, and a cathode formed on the array substrate in sequence, and may also be Other film layers need to be set, which is not limited herein.
  • an embodiment of the present invention also provides a method of fabricating the above thin film transistor.
  • the active layer is made of an amorphous phosphide semiconductor material, specifically by magnetron sputtering, pulsed laser deposition, chemical vapor deposition (CVD) or solution deposition. To prepare the active layer.
  • the pattern of the active layer can be prepared by magnetron sputtering.
  • the method comprises: depositing an InGaZnP film by magnetron sputtering under an oxygen atmosphere with a pressure of 1 Pa-10 Pa; the thickness of the InGaZnP film is usually controlled at about 50 nm; and the air atmosphere at a temperature of 100 ° C to 600 ° C
  • the InGaZnP film was annealed for 1 hour; and the InGaZnP film was patterned to form a pattern of the active layer. Further, the InGaZnP film was annealed at an air atmosphere temperature of 100 ° C to 400 ° C for 1 hour.
  • a pattern of the active layer can be prepared by pulsed laser deposition.
  • the method comprises: depositing an InP film by pulsed laser deposition under an oxygen atmosphere at a pressure of 1 Pa to 10 Pa; the thickness of the InP film is usually controlled at about 50 nm; and the air atmosphere is at a temperature of 100 ° C to 600 ° C. Annealing the InP film for 10 minutes; and patterning the InP film to form a pattern of the active layer. Further, the InP film was annealed for 10 minutes in an air atmosphere at a temperature of 100 ° C to 400 ° C.
  • the working performance curves of the amorphous InP thin film transistor prepared by the above method are shown in Fig. 3a and Fig.
  • FIG. 4 is a schematic diagram of the output characteristic curve of the conventional amorphous silicon thin film transistor.
  • the thin film transistor prepared by the above preparation method can be applied to an LCD panel, and can of course also be applied to an OLED display panel, which is not limited herein. The steps of the fabrication process of the thin film transistor are described in detail below by two examples. In both cases, a thin film transistor of a bottom gate type structure is taken as an example.
  • the thin film transistor is applied to an active matrix organic light emitting diode (AMOLED) display panel, and the preparation method thereof comprises the following steps:
  • Step S01 forming a pattern of the gate on the base substrate.
  • the gate is typically prepared by magnetron sputtering to form a pattern of gates by a patterning process.
  • the material of the gate may be Mo.
  • the thickness of the gate electrode can be controlled to be about 200 nm.
  • the preparation method may further include the step of forming a buffer layer on the base substrate, as needed.
  • the base substrate can be cleaned using standard methods, and then a buffer layer is deposited on the base substrate by CVD.
  • the buffer layer can be made of Si0 2 . Further, the thickness of the buffer layer is usually controlled to be about 200 nm.
  • Step S02 forming a gate insulating layer on the gate.
  • the gate insulating layer is usually prepared by a CVD method. Specifically, the gate insulating layer may be made of SiO 2 . Further, the thickness of the gate insulating layer can be controlled to be about 150 nm.
  • Step S03 forming a pattern of the active layer on the gate insulating layer.
  • the active layer can be made of InGaZnP, and the pattern of the active layer can be prepared by magnetron sputtering: First, the InGaZnP film is deposited by magnetron sputtering under an oxygen atmosphere of pressure 1Pa ⁇ 10Pa; the thickness of the InGaZnP film The InGaZnP film may be annealed at about 50 nm; the InGaZnP film is annealed for 1 hour in an air atmosphere at a temperature of 100 ° C to 600 ° C; and a pattern of the active layer is formed by a patterning process.
  • the InGaZnP film was annealed in an air atmosphere at a temperature of 100 ° C to 400 ° C for 1 hour.
  • Step S04 forming a pattern of an etch barrier layer on the active layer.
  • the etch barrier layer is mostly prepared by a CVD method, and a pattern of an etch barrier layer is formed by a patterning process.
  • the etch stop layer can be made of SiO 2 . Further, the thickness of the etch barrier layer is usually controlled to be about 50 nm. Step S05, forming a pattern of source and drain on the etch barrier layer.
  • the source and drain are typically formed by sputtering and the source and drain patterns are formed by a patterning process.
  • the source and drain electrodes may be made of a composite metal layer Mo/Al. Further, the thicknesses of the source and drain are typically controlled to be about 200 nm, respectively.
  • the structure of the AMOLED needs to be formed by the following steps.
  • Step S06 forming a pattern of a passivation layer on the source and the drain.
  • the ruthenium layer is usually prepared by CVD.
  • the material of the passivation layer may be made of SiO 2 and is typically dry etched to form vias in the passivation layer to connect the pixel electrodes and sources to be formed. Further, the thickness of the passivation layer is usually controlled in the range of 100 nm to 500 nm.
  • Step S07 forming a pattern of the pixel electrode on the passivation layer, and the pixel electrode is connected to the source through the via hole in the passivation layer.
  • a pixel electrode layer is usually prepared by sputtering, and a pattern of pixel electrodes is formed by a patterning process.
  • the pixel electrode can be made of indium tin oxide (ITO).
  • Step S08 depositing a pixel defining layer of an acrylic material on the pixel electrode, and then forming a pattern of the pixel defining layer by a patterning process.
  • the thickness of the pixel defining layer can be controlled to be about 1.5 ⁇ m.
  • step S08 the following steps may also be included:
  • Step S09 forming a hole transport layer.
  • a hole transport layer was prepared by thermal evaporation evaporation in an OLED or EL organometallic thin film deposition high vacuum system of ⁇ 5 Pa and about 170 °C.
  • the hole transport layer may be made of NPB (N, N, -diphenyl-NN, bis(1-caiyl)-1, 1, diphenyl-4,4,-diamine).
  • the thickness of the hole transport layer is usually controlled at about 50 nm.
  • Step S10 forming a pattern of the organic light-emitting layer on the hole transport layer.
  • the organic light-emitting layer was prepared by thermal evaporation evaporation in an OLED or EL (Electroluminescence) organic metal thin film deposition high vacuum system of lxlO -5 Pa.
  • the green sub-pixel region, the blue sub-pixel region, and the red sub-pixel region may be sequentially formed by a sub-pixel region mask evaporation process.
  • the materials of the green, blue and red pixel regions of the organic light-emitting layer may be made of a host material CBP doped with a phosphorescent material: (ppy) 2 Ir(acac), CBP: FIrpic and CBP: Btp2Ir (acac), respectively.
  • the thickness of the organic light-emitting layer is usually controlled to be about 25 nm.
  • Step S l l forming an electron transport layer on the organic light-emitting layer.
  • the electron transport layer was prepared by thermal evaporation evaporation.
  • the electron transport layer can be made of Bphen.
  • the thickness of the electron transport layer is usually controlled to be about 25 nm.
  • Step S12 forming a cathode on the electron transport layer.
  • the cathode was prepared by thermal evaporation evaporation in an OLED or EL organometallic film deposition high vacuum system of ⁇ 5 Pa and about 900 °C.
  • the material of the cathode may be a composite metal layer Sm/Al.
  • the thickness of the cathode is typically controlled to be about 200 nm.
  • the thin film transistor is applied to an LCD display panel, and the preparation method thereof comprises the following steps: Step S01, forming a pattern of a gate on the substrate;
  • the gate is mostly prepared by magnetron sputtering, and the pattern of the gate is formed by a patterning process.
  • the material of the gate may be Mo.
  • the thickness of the gate can be controlled to be about 200 nm.
  • the method further includes: forming a buffer layer on the substrate substrate;
  • the substrate may be first cleaned by standard methods, and then a buffer layer is deposited on the substrate by CVD.
  • the material of the buffer layer may be Si0 2 .
  • the thickness of the buffer layer is usually controlled to be 200 nm.
  • Step S02 forming a gate insulating layer on the gate
  • the gate insulating layer is mostly prepared by CVD.
  • the material of the gate insulating layer may be Si0 2 .
  • the thickness of the gate insulating layer can be controlled at about 150 nm.
  • Step S03 forming a pattern of an active layer on the gate insulating layer
  • the material of the active layer may specifically be ⁇ , and the pattern of the active layer may be prepared by pulse laser deposition: the substrate may be fed into a vacuum chamber having a degree of vacuum of (1 ⁇ 10)*10" 4 Pa, and then passed into the vacuum chamber. ⁇ 30 sccm of oxygen (0 2 ), such as 5sccm, 10sccm, 20sccm or 30sccm, the pressure of the vacuum chamber is controlled to 0.5 ⁇ 1.5Pa, such as 0.5 Pa, 1 Pa or 1.5 Pa; pulse frequency is l ⁇ 10Hz, pulse A pulsed laser with an energy of 200 to 500 mJ, for example, a pulse laser having a frequency of 5 Hz and a pulse energy of 350 mJ, depositing an InP film for 1 to 5 minutes, and the deposition time may be, for example, 1 minute, 2 minutes, 3 minutes, or 5 minutes; The thickness can be controlled at about 30 to 80 nm, for example, 30 nm, 50 nm or 80 nm; then at an air atmosphere
  • the temperature can be 100 ° C, 300 ° C, 500 ° C or 600 ° C
  • the InP film is annealed for 5 to 20 minutes
  • the annealing time can be 5 minutes, 10 minutes, 15 minutes or 20 minutes
  • the pattern of the active layer is formed by a patterning process.
  • Step S04 forming a pattern of an etch barrier layer on the active layer
  • the etch barrier layer is mostly prepared by a CVD method, and a pattern of an etch barrier layer is formed by a patterning process.
  • the material of the etch barrier layer may be Si0 2 .
  • the thickness of the etch barrier layer is usually controlled to be 50 nm.
  • Step S05 forming a pattern of a source and a drain on the etch barrier layer
  • the source and the drain are mostly prepared by sputtering, and the pattern of the source and the drain are formed by one patterning process.
  • the material of the source and the drain may be a composite metal layer ⁇ / ⁇ 1.
  • the source and drain thicknesses are typically controlled to be 200 nm, respectively.
  • the pixel structure of the LCD needs to be formed by the following steps, including the following steps:
  • Step S06 forming a pattern of a passivation layer on the source and the drain;
  • the passivation layer is mostly prepared by CVD.
  • the material of the passivation layer may be SiO 2 and is typically dry etched to form vias in the passivation layer that connect the pixel electrode and source to be formed.
  • the thickness of the passivation layer is usually controlled to be between 100 nm and 500 nm.
  • Step S07 forming a pattern of a pixel electrode on the passivation layer, and the pixel electrode is connected to the source through a via hole in the passivation layer;
  • the pixel electrode is usually prepared by sputtering, and the pattern of the pixel electrode is formed by a patterning process.
  • the pixel electrode may be made of indium tin oxide (ITO).
  • the PI coating, the embossing orientation, the Spacer preparation, and the preparation of the color filter substrate disposed opposite to the TFT array substrate are also required, and the color filter substrate and the TFT array substrate are processed in a box, and the liquid crystal molecules are poured. , coating the sealant and other steps.
  • a thin film transistor, a method for fabricating the same, and a related device are provided in an embodiment of the present invention.
  • the active layer in the thin film transistor is prepared by using an amorphous phosphide semiconductor material. Since the mobility of carriers of the phosphide semiconductor material is relatively high, the active layer of the existing thin film transistor is prepared using amorphous silicon, polycrystalline silicon, microcrystalline silicon or an oxide semiconductor material, and amorphous phosphorus is used.
  • the semiconductor material is used to prepare an active layer of a thin film transistor, and a thin film transistor having a high carrier mobility can be obtained.

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Abstract

提供一种薄膜晶体管，薄膜晶体管中的有源层（3）采用非晶态磷化物半导体材料制备。由于磷化物半导体材料的载流子的迁移率比较高，采用非晶态磷化物半导体材料制备薄膜晶体管的有源层，可以得到载流子迁移率较高的薄膜晶体管。还提供了制备这种薄膜晶体管的方法及包括该薄膜晶体管的阵列基板和显示面板。

Description

一种薄膜晶体管、 其制备方法及包含该薄膜晶体管的装置 技术领域
本发明的实施例涉及显示技术领域， 尤其涉及一种薄膜晶体管、 其制备 方法及包含该薄膜晶体管的装置。 背景技术
随着平板显示行业的发展， 对显示面板的要求越来越高， 其中对面板中 薄膜晶体管的迁移率也提出了更高的要求。 目前， 现有的薄膜晶体管 （Thin Film Transistor, TFT )通常为非晶硅薄膜晶体管， 非晶硅薄膜晶体管即薄膜 晶体管的有源层为非晶硅材料， 非晶硅薄膜晶体管的载流子的迁移率较低， 其电子迁移率为 0.1-1 cn^ 1, 无法满足技术发展的需要。 因此开发了低温 多晶硅（ LTPS, Low Temperature Poly Silicon )薄膜晶体管和氧化物（ Oxide ) 薄膜晶体管。
LTPS 薄膜晶体管即有源层为低温多晶硅材料的薄膜晶体管， 低温多晶 硅通过在较低温度下将非晶硅转变为多晶硅而获得， LTPS 薄膜晶体管的载 流子迁移率 4艮高约为 100-500 cn^V- 1, 但是其均匀性较差， 因而在应用于 大尺寸面板时， 面临难以克服的障碍。 氧化物薄膜晶体管即有源层为氧化物 半导体材料的薄膜晶体管， 氧化物薄膜晶体管为了保证较好的大尺寸均匀性 而牺牲了部分迁移率， 目前， 在保证较好均匀性的前提下， 氧化物薄膜晶体 管的载流子迁移率可以达到 lO cm 1^^但氧化物薄膜晶体管的载流子的迁 移率已不能满足平板显示技术的发展。 因此， 目前的薄膜晶体管需要在良好 均匀性的前提下进一步提高载流子迁移率。 发明内容
为解决上述问题， 本发明实施例提供了一种薄膜晶体管， 其具有较高的 载流子迁移率。 本发明的实施例还提供了一种制备该薄膜晶体管的方法及包 含该薄膜晶体管的相关装置。
本发明实施例提供了一种薄膜晶体管， 其包括： 衬底基板， 以及形成于 所述村底基板上的栅极、 有源层、 源极和漏极； 其中， 所述有源层的材料为 非晶态磷化物半导体材料。
本发明实施例提供了一种阵列基板， 其包括本发明实施例提供的薄膜晶 体管。
本发明实施例提供了一种显示面板， 其包括本发明实施例提供的阵列基 板。
本发明实施例提供了一种用于制备上述薄膜晶体管的方法， 所述薄膜晶 体管的有源层采用磁控溅射方式、 脉沖激光沉积方式、 化学气相沉积方式或 溶液沉积方式制备。
本发明实施例提供的薄膜晶体管中的有源层采用非晶态磷化物半导体材 料制备。 由于磷化物半导体材料的载流子的迁移率比较高， 因此， 相对于现 有的薄膜晶体管的有源层采用非晶硅、 多晶硅、 微晶硅或氧化物半导体材料 制备， 采用非晶态磷化物半导体材料制备薄膜晶体管的有源层， 可以得到载 流子迁移率较高的薄膜晶体管。 采用这种薄膜晶体管的阵列基板和显示面板 可以在保证良好均匀性的前提下提高载流子迁移率。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为根据本发明实施例的薄膜晶体管的结构示意图；
图 2为根据本发明实施例的阵列基板的结构示意图；
图 3a为根据本发明实施例的薄膜晶体管的转移特性曲线示意图； 图 3b为根据本发明实施例的薄膜晶体管的输出特性曲线示意图； 以及 图 4为根据惯常技术的非晶硅薄膜晶体管的输出特性曲线示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
附图中各层薄膜厚度和形状不反映薄膜晶体管的真实比例， 目的只是示 意说明本发明实施例的内容。
如图 1所示， 本发明实施例提供了一种薄膜晶体管， 其包括： 衬底基板
1 , 以及形成于衬底基板 1上的栅极 2、 有源层 3、 漏极 4和源极 5; 其中， 有源层 3的材料为非晶态磷化物半导体材料。
根据本发明实施例的上述薄膜晶体管中， 有源层由非晶态磷化物半导体 材料制成。 由于磷化物半导体材料的载流子的迁移率比较高， 因此， 相对于 惯常技术中的其有源层材料由非晶硅、 多晶硅、 微晶硅或氧化物半导体材料 制成的薄膜晶体管， 有源层由非晶态磷化物半导体材料制成的薄膜晶体管的 载流子迁移率较高。
根据本发明实施例的上述薄膜晶体管中， 有源层的厚度通常控制在
5nm-200nm之间为佳。
在本发明实施例提供的上述薄膜晶体管中， 有源层可以为非晶态二元磷 化物半导体材料， 例如： InP、 Zn3P2、 Ga3P2, 也可以为非晶体态多元磷化物 半导体材料， 例如： InGaZnP或 InGaZnOP, 在此不做限定。 非晶态二元磷 化物半导体材料指的是金属元素或非金属元素与磷组成的非晶态二元化合物 半导体材料，而非晶态多元磷化物指的是金属元素和 /或非金属元素中的多种 与磷组成的非晶态多元化合物半导体材料。
进一步地， 根据本发明实施例的上述薄膜晶体管的有源层还可以由非晶 态化合物掺杂磷半导体材料制成， 在实践中， 可以通过配比调整在非晶态化 合物半导体材料中掺杂磷元素的比例来实现高载流子迁移率，在此不做详述。
在图 1中是以底栅型结构的薄膜晶体管为例进行说明的。 但， 本发明实 施例提供的上述薄膜晶体管 TFT器件可以适用于各种类型结构， 即 TFT器 件可以为底栅型结构、 顶栅型结构、 交叠型结构、 反交叠型结构、 共面型结 构或反共面型结构， 本文对此不做限定。
在根据本发明实施例的薄膜晶体管中， 衬底基板可以由透明材料制成， 例如： 玻璃或石英， 衬底基板也可以由其它不透明材料制成， 例如： 陶瓷或 金属， 本文对此不做限定。 进一步地， 在根据本发明实施例的上述薄膜晶体管中， 栅极可以由例如
Mo、 Ah 或 Cr的金属材料， 也可以由合金材料， 或者还可以由例如 Mo/Al 的复合金属层制成， 本文对此不做限定。 在实施时， 栅极的厚度通常控制在 lnm-500nm之间。
进一步地， 如图 1所示，根据本发明实施例的薄膜晶体管，还可以包括： 形成于栅极 2与有源层 3之间的栅极绝缘层 6。 例如， 栅极绝缘层 6可以为 氧化硅、 氮化硅等绝缘材料，栅极绝缘层 6的厚度通常控制在 lnm-300nm之 间。
进一步地， 如图 1所示，根据本发明实施例的薄膜晶体管，还可以包括： 形成于有源层 3与漏极 4和源极 5之间的刻蚀阻挡层 7。例如，刻蚀阻挡层 7 可以由氧化硅、 氮化硅或者有机绝缘材料制成， 刻蚀阻挡层 7的厚度通常在 5nm-500nm范围内。
例如， 在根据本发明实施例的上述薄膜晶体管中， 源极和漏极可以分别 由例如 Mo、 A1或 Cr的金属材料， 也可以由合金材料， 或者还可以由例如 Mo/Al的复合金属层制成。 本文对此不做限定。 源极和漏极的厚度通常分别 控制在 lnm-500nm之间。
基于同一发明构思， 本发明实施例还提供了一种阵列基板， 包括根据本 发明实施例的上述薄膜晶体管。 本领域技术人员阅读了上述薄膜晶体管的实 施例之后可以实施该阵列基板， 本文不再赘述。
图 2是根据本发明实施例的阵列基板的结构示意图。 如图 2所示， 根据 本发明实施例的阵列基板可以包括： 形成于薄膜晶体管上的像素电极 8, 该 像素电极 8与源极 5相连。
进一步地， 如图 2所示， 根据本发明实施例的阵列基板还可以包括： 形 成于源极 5和像素电极 8之间的钝化层 9, 像素电极 8通过钝化层 9中的过 孔与源极 5相连。 钝化层 9可以由氧化硅、 氮化硅或有机材料等绝缘材料制 成， 钝化层 9的厚度通常控制在 5nm-500nm之间。
更进一步地， 根据需要， 根据本发明实施例的阵列基板还可以包括位于 衬底基板与栅极之间的緩沖层，位于像素电极上的平坦化层、像素界定层等， 本文对此不做限定。
本发明实施提供的上述阵列基板可以应用于液晶显示 （Liquid Crystal Display, LCD ) 面板， 当然也可以应用于有机发光二极管 （Organic Light Emitting Diode, OLED )显示面板， 本文对此不做限定。
基于同一发明构思， 本发明实施例还提供了一种显示面板， 包括本发明 实施例提供的上述阵列基板， 该显示面板可以是液晶显示面板， 也可以是 OLED显示面板， 对于显示面板的其它必不可少的组成部分均为本领域的普 通技术人员应该理解具有的， 在此不做赘述， 也不应作为对本发明的限制。 该显示面板的实施可以参见上述阵列基板的实施例， 重复之处不再赘述。
根据本发明实施例的显示面板为 OIED显示面板时， 该 OLED显示面板 还可以包括： 依次形成于阵列基板上的阳极、 空穴传输层、 有机发光层、 电 子传输层以及阴极， 当然也可以根据需要设置其他的膜层， 本文对此不做限 定。
基于同一发明构思，本发明实施例还提供了制备上述薄膜晶体管的方法。 在制备上述薄膜晶体管时， 有源层由非晶态磷化物半导体材料制成， 具体可 以通过磁控溅射方式、 脉沖激光沉积方式、 化学气相沉积 （Chemical vapor deposition, CVD )方式或溶液沉积方式来制备有源层。
当有源层由 InGaZnP制成时，可以采用磁控溅射方式制备有源层的图形。 该方法包括： 在压力为 lPa-10Pa的氧气氛围条件下， 采用磁控溅射方式沉积 InGaZnP薄膜； InGaZnP薄膜的厚度通常控制在约 50nm;在温度为 100°C-600 °C的空气氛围条件下对 InGaZnP薄膜退火 1小时； 以及， 对 InGaZnP薄膜进 行构图， 形成有源层的图形。 更进一步地， 在温度为 100°C-400°C的空气氛 围条件下对 InGaZnP薄膜退火 1小时。
当有源层由 ΙΉΡ制成时，可以采用脉沖激光沉积方式制备有源层的图形。 该方法包括： 在压力为 lPa-10Pa的氧气氛围条件下， 采用脉沖激光沉积方式 沉积 InP薄膜； InP薄膜的厚度通常控制在约 50nm; 在温度为 100°C-600°C 的空气氛围条件下， 对 InP薄膜退火 10分钟； 以及， 对 InP薄膜进行构图， 形成有源层的图形。 更进一步地， 在温度为 100°C-400°C的空气氛围条件下， 对 InP薄膜退火 10分钟。采用上述方式制备出的非晶态 InP薄膜晶体管的工 作性能曲线如图 3a和图 3b所示， 可以看出薄膜晶体管的载流子的迁移率较 高。 该器件还未经过优化， 其载流子的迁移率已达到非晶硅薄膜晶体管的水 平， 图 4为惯常的非晶硅薄膜晶体管的输出特性曲线示意图。 进一步地， 上述制备方法制备出的薄膜晶体管可以应用于 LCD 面板， 当然也可以应用于 OLED显示面板， 本文对此不^ ^限定。 下文通过两个实例 对薄膜晶体管的制备工艺的各步骤进行详细的说明。 在两个实例中都是以底 栅型结构的薄膜晶体管为例进行说明的。
实例一：
薄膜晶体管应用于有源有机发光二极管 （Active Matrix Organic Light Emitting Diode, AMOLED )显示面板， 其制备方法具体包括以下步骤：
步骤 S01、 在衬底基板上形成栅极的图形。
栅极通常采用磁控溅射的方式来制备， 通过构图工艺形成栅极的图形。 栅极的材料可以为 Mo。 进一步地， 可以将栅极的厚度控制在约 200nm。
在步骤 S01制备栅极的图形之前， 根据需要， 该制备方法还可以包括在 衬底基板上形成緩沖层的步骤。
可以采用标准方法对衬底基板进行清洗， 之后通过 CVD方式在衬底基 板上沉积緩沖层。 緩沖层可以由 Si02制成。 进一步地， 通常将緩沖层的厚度 控制在约 200nm。
步骤 S02、 在栅极上形成栅极绝缘层。
通常通过 CVD方式来制备栅极绝缘层。具体地，栅极绝缘层可以由 Si02 制成。 进一步地， 可以将栅极绝缘层的厚度控制在约 150nm。
步骤 S03、 在栅极绝缘层上形成有源层的图形。
有源层可以由 InGaZnP制成，可以采用磁控溅射方式制备有源层的图形： 首先在压力为 lPa~10Pa的氧气氛围条件下，采用磁控溅射方式沉积 InGaZnP 薄膜； InGaZnP薄膜的厚度可以控制在约 50nm; 在温度为 100°C~600°C的空 气氛围条件下对 InGaZnP薄膜退火 1小时； 以及， 通过构图工艺形成有源层 的图形。
更进一步地， 在温度为 100 °C~400°C的空气氛围条件下对 InGaZnP薄膜 退火 1小时。
步骤 S04、 在有源层上形成刻蚀阻挡层的图形。
刻蚀阻挡层多采用 CVD方式来制备， 并通过构图工艺形成刻蚀阻挡层 的图形。 刻蚀阻挡层可以由 Si02制成。 进一步地， 刻蚀阻挡层的厚度通常控 制在约 50nm。 步骤 S05、 在刻蚀阻挡层上形成源极和漏极的图形。
通常采用溅射方式来制备源极和漏极， 并通过一次构图工艺形成源极和 漏极的图形。 源极和漏极可以由复合金属层 Mo/Al制成。 进一步地， 源极和 漏极的厚度通常分别控制在约 200nm。
形成薄膜晶体管之后， 需要通过以下步骤形成 AMOLED的结构。
步骤 S06、 在源极和漏极上形成钝化层的图形。
通常采用 CVD方式来制备 4屯化层。 钝化层的材料可以由 Si02制成， 并 通常采用干法刻蚀的方式来在钝化层中形成过孔， 以连接将要形成的像素电 极和源极。 进一步地， 钝化层的厚度通常控制在 100nm-500nm范围内。
步骤 S07、 在钝化层上形成像素电极的图形， 像素电极通过钝化层中的 过孔与源极相连。
通常采用溅射方式来制备像素电极层， 并通过构图工艺形成像素电极的 图形。 像素电极可以由铟锡氧化物 （ITO )制成。
步骤 S08、 在像素电极上旋涂沉积丙烯酸材料的像素界定层， 然后通过 构图工艺形成像素界定层的图形。 像素界定层的厚度可以控制在约 1.5μηι。
在步骤 S08之后， 还可以包括以下步骤：
步骤 S09、 形成空穴传输层。
在 ΙχΙΟ·5 Pa且约 170摄氏度的 OLED或 EL有机金属薄膜沉积高真空系 统中热蒸发蒸镀制备空穴传输层。空穴传输层可以由 NPB(N, N，-二苯基 -N-N， 二 (1-蔡基) -1 , 1，二苯基 -4, 4，-二胺)制成。 空穴传输层的厚度通常控制在约 50nm„
步骤 S 10、 在空穴传输层上形成有机发光层的图形。
在 lxlO-5 Pa的 OLED或电致发光（EL, Electrolumiescent )有机金属薄 膜沉积高真空系统中热蒸发蒸镀制备有机发光层。 还可以采用分像素区掩模 蒸镀工艺形成依次排列的绿光亚像素区、 蓝光亚像素区、 红光亚像素区。 有 机发光层的绿光、 蓝光和红光像素区的材料可以分别采用掺杂磷光材料的主 体材料 CBP: (ppy)2Ir(acac)、 CBP: FIrpic和 CBP: Btp2Ir(acac)。 有机发光层的 厚度通常控制在约 25nm。
步骤 S l l、 在有机发光层上形成电子传输层。
在 ΙχΙΟ·5 Pa且约 190摄氏度的 OLED或 EL有机金属薄膜沉积高真空系 统中热蒸发蒸镀制备电子传输层。 电子传输层可以由 Bphen制成。 电子传输 层的厚度通常控制在约 25nm。
步骤 S12、 在电子传输层上形成阴极。
在 ΙχΙΟ·5 Pa且约 900摄氏度的 OLED或 EL有机金属薄膜沉积高真空系 统中热蒸发蒸镀制备阴极。 阴极的材料可以为复合金属层 Sm/Al。 阴极的厚 度通常控制在约 200nm。
实例二：
薄膜晶体管应用于 LCD显示面板， 其制备方法包括以下步骤： 步骤 S01、 在衬底基板上形成栅极的图形；
栅极多采用磁控溅射的方式来制备， 通过构图工艺形成栅极的图形。 具 体地， 栅极的材料可以为 Mo。 栅极的厚度可以控制在约 200nm。
在步骤 S01制备栅极的图形之前， 根据需要还可以包括： 在衬底基板上 形成緩沖层的步骤；
可以先将衬底基板采用标准方法清洗， 之后采用 CVD方式在衬底基板 上沉积緩沖层。 緩沖层的材料可以为 Si02。 緩沖层的厚度通常控制在 200nm 为佳。
步骤 S02、 在栅极上形成栅极绝缘层；
栅极绝缘层多采用 CVD方式来制备。 栅极绝缘层的材料可以为 Si02。 栅极绝缘层的厚度可以控制在约 150nm。
步骤 S03、 在栅极绝缘层上形成有源层的图形；
有源层的材料具体可以为 ΙΉΡ, 可以采用脉沖激光沉积方式制备有源层 的图形： 可以将基板送入真空度为 （1~10 ) *10"4 Pa的真空腔内， 然后通入 5~30 sccm的氧气 ( 02 ) , 例如 5sccm、 10sccm、 20sccm或 30sccm, 将真空 腔的压力控制到 0.5~1.5Pa, 例如 0.5 Pa、 1 Pa或 1.5Pa; 采用脉沖频率为 l~10Hz、 脉沖能量为 200~500mJ的脉沖激光， 例如脉沖激光的频率为 5Hz、 脉沖能量为 350mJ, 沉积 InP薄膜 1~5分钟， 沉积时间例如可以为 1分钟、 2 分钟、 3分钟或 5分钟； InP薄膜的厚度可以控制在约 30~80nm, 例如可以 为 30nm、 50nm或 80nm; 然后在温度为 100°C -600°C的空气氛围条件下， 更 进一步地， 在温度为 100°C-400°C的空气氛围条件下， 例如温度可以为 100°C、 300 °C、 500 °C或 600 °C ,对 InP薄膜退火 5~20分钟，退火的时间可以为 5分钟、 10分钟、 15分钟或 20分钟； 最后通过构图工艺形成有源层的图形。
步骤 S04、 在有源层上形成刻蚀阻挡层的图形；
刻蚀阻挡层多采用 CVD方式来制备， 并通过构图工艺形成刻蚀阻挡层 的图形。刻蚀阻挡层的材料可以为 Si02。刻蚀阻挡层的厚度通常控制在 50nm 为佳。
步骤 S05、 在刻蚀阻挡层上形成源极和漏极的图形；
在具体实施时， 源极和漏极多采用溅射方式来制备， 并通过一次构图工 艺形成源极和漏极的图形。 源极和漏极的材料可以为复合金属层 Μο/Α1。 源 极和漏极厚度通常分别控制在 200nm为佳。
形成薄膜晶体管之后， 需要通过以下步骤形成 LCD 的像素结构， 具体 包括以下步骤：
步骤 S06、 在源极和漏极上形成钝化层的图形；
钝化层多采用 CVD方式来制备。 钝化层的材料可以为 Si02, 并通常采 用干法刻蚀的方式来形成钝化层中连接将要形成的像素电极和源极的过孔。 钝化层的厚度通常控制在 100nm-500nm之间为佳。
步骤 S07、 在钝化层上形成像素电极的图形， 像素电极通过钝化层中的 过孔与源极相连；
通常通过溅射方式来制备像素电极， 并通过构图工艺形成像素电极的图 形。 像素电极可以由铟锡氧化物（ITO )制成。
在完成步骤 S07之后， 还需要进行 PI涂布、 压印取向以及 Spacer制备、 以及与 TFT阵列基板相对设置的彩膜基板的制备， 并将彩膜基板和 TFT阵 列基板对盒处理， 灌注液晶分子， 涂覆封框胶等步骤。 这些工艺都属于惯常 技术， 其详细的工艺内容在此不再赘述。
本发明实施例提供的一种薄膜晶体管、 其制备方法及相关装置， 在薄膜 晶体管中的有源层采用非晶态磷化物半导体材料制备。 由于磷化物半导体材 料的载流子的迁移率比较高， 因此， 相对于现有的薄膜晶体管的有源层采用 非晶硅、 多晶硅、 微晶硅或氧化物半导体材料制备， 采用非晶态磷化物半导 体材料制备薄膜晶体管的有源层,可以得到载流子迁移率较高的薄膜晶体管。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1. 一种薄膜晶体管， 包括： 衬底基板， 以及形成于所述衬底基板上的栅 极、 有源层、 源极和漏极， 其中，
所述有源层的材料为非晶态磷化物半导体材料。
2. 如权利要求 1所述的薄膜晶体管， 其中， 所述非晶态磷化物半导体材 料为非晶态二元磷化物半导体材料或非晶态多元磷化物半导体材料。
3. 如权利要求 2所述的薄膜晶体管， 其中， 所述非晶态二元磷化物半导 体材料为 ΙΉΡ、 Ζη3Ρ2或 Ga3P2。
4. 如权利要求 2所述的薄膜晶体管， 其中， 所述非晶态多元磷化物半导 体材料为 InGaZnP或 InGaZnOP。
5. 如权利要求 1-4中任一项所述的薄膜晶体管， 其中， 所述有源层的厚 度为 5nm-200nm„
6. 如权利要求 1-4中任一项所述的薄膜晶体管， 其中， 所述薄膜晶体管 为底栅型结构、 顶栅型结构、 交叠型结构、 反交叠型结构、 共面型结构或反 共面型结构。
7. 一种阵列基板， 包括如权利要求 1-6任一项所述的薄膜晶体管。
8. 一种显示面板， 包括如权利要求 7所述的阵列基板。
9. 一种制备如权利要求 1-6任一项所述的薄膜晶体管的方法， 其中， 所 述薄膜晶体管的有源层采用磁控溅射方式、 脉沖激光沉积方式、 化学气相沉 积方式或溶液沉积方式制备。
10. 如权利要求 9所述的方法， 其中， 当所述有源层的材料为 InGaZnP 时， 采用磁控溅射方式制备所述有源层的图形， 所述方法包括：
在压力为 1 Pa~ 1 OPa的氧气氛围条件下， 沉积 InGaZnP薄膜；
在 100°C~600°C的空气氛围条件下， 对所述 InGaZnP薄膜退火 1小时； 以及
对所述 InGaZnP薄膜进行构图， 形成所述有源层的图形。
11. 如权利要求 10所述的方法， 其中， 在 100°C~400°C的空气氛围条件 下， 对所述 InGaZnP薄膜退火 1小时。
12. 如权利要求 9所述的方法， 其中， 当所述有源层的材料为 InP时， 采用脉沖激光沉积方式制备所述有源层的图形， 所述方法包括： 在压力为 lPa~10Pa的氧气氛围条件下， 沉积 InP薄膜；
在 100°C~600°C的空气氛围条件下， 对所述 InP薄膜退火 10分钟； 以及 对所述 InP薄膜进行构图， 形成所述有源层的图形。
13. 如权利要求 12所述的方法， 其中， 在 100°C~400°C的空气氛围条件 下， 对所述 InP薄膜退火 10分钟。
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Publication number Priority date Publication date Assignee Title
CN104393002A (zh) * 2014-10-29 2015-03-04 合肥京东方光电科技有限公司 一种显示基板及其制作方法、显示装置
US9666658B2 (en) * 2015-01-05 2017-05-30 Samsung Display Co., Ltd. Organic light emitting diode display and manufacturing method thereof
US10424670B2 (en) * 2016-12-30 2019-09-24 Intel Corporation Display panel with reduced power consumption
CN107275339B (zh) * 2017-04-20 2020-06-12 惠科股份有限公司 主动开关阵列基板及制造方法与应用的显示面板
CN109801875B (zh) * 2018-12-26 2021-06-04 惠科股份有限公司 阵列基板的制作方法、阵列基板和显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4065781A (en) * 1974-06-21 1977-12-27 Westinghouse Electric Corporation Insulated-gate thin film transistor with low leakage current
JPS60251666A (ja) * 1984-05-28 1985-12-12 Seiko Epson Corp 薄膜トランジスタ
US5536953A (en) * 1994-03-08 1996-07-16 Kobe Steel Usa Wide bandgap semiconductor device including lightly doped active region
CN101136312A (zh) * 2006-08-31 2008-03-05 株式会社半导体能源研究所 半导体器件的制造方法及显示器件的制造方法
CN101960605A (zh) * 2008-03-26 2011-01-26 国立大学法人东京大学 半导体基板、半导体装置、及半导体装置的制造方法
CN101996989A (zh) * 2009-08-07 2011-03-30 株式会社半导体能源研究所 发光装置以及该发光装置的制造方法
CN102074480A (zh) * 2009-11-20 2011-05-25 E.I.内穆尔杜邦公司 薄膜晶体管组成及其相关方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5700617B2 (ja) * 2008-07-08 2015-04-15 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP6234100B2 (ja) * 2012-07-31 2017-11-22 株式会社半導体エネルギー研究所 発光素子、複素環化合物、ディスプレイモジュール、照明モジュール、発光装置、表示装置、照明装置及び電子機器

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4065781A (en) * 1974-06-21 1977-12-27 Westinghouse Electric Corporation Insulated-gate thin film transistor with low leakage current
JPS60251666A (ja) * 1984-05-28 1985-12-12 Seiko Epson Corp 薄膜トランジスタ
US5536953A (en) * 1994-03-08 1996-07-16 Kobe Steel Usa Wide bandgap semiconductor device including lightly doped active region
CN101136312A (zh) * 2006-08-31 2008-03-05 株式会社半导体能源研究所 半导体器件的制造方法及显示器件的制造方法
CN101960605A (zh) * 2008-03-26 2011-01-26 国立大学法人东京大学 半导体基板、半导体装置、及半导体装置的制造方法
CN101996989A (zh) * 2009-08-07 2011-03-30 株式会社半导体能源研究所 发光装置以及该发光装置的制造方法
CN102074480A (zh) * 2009-11-20 2011-05-25 E.I.内穆尔杜邦公司 薄膜晶体管组成及其相关方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
M. KUNZE ET AL.: "First demonstration of low temperature grown InP-channel HFET transferred onto GaAs substrate.", SOLID-STATE ELECTRONICS, vol. 43, 1999, pages 1535 - 1540 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112038216A (zh) * 2020-09-08 2020-12-04 重庆邮电大学 一种p型非晶态半导体薄膜及其薄膜晶体管制备方法

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