WO2019019614A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2019019614A1
WO2019019614A1 PCT/CN2018/076371 CN2018076371W WO2019019614A1 WO 2019019614 A1 WO2019019614 A1 WO 2019019614A1 CN 2018076371 W CN2018076371 W CN 2018076371W WO 2019019614 A1 WO2019019614 A1 WO 2019019614A1
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Prior art keywords
layer
forming
pixel circuit
electrode
display panel
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PCT/CN2018/076371
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English (en)
French (fr)
Inventor
刘帅
邱云
赵合彬
曲连杰
齐永莲
仝维维
石广东
晏斌
刘韬
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/082,049 priority Critical patent/US11152436B2/en
Priority to EP18758528.6A priority patent/EP3660904B1/en
Publication of WO2019019614A1 publication Critical patent/WO2019019614A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
    • H10K50/115—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers comprising active inorganic nanostructures, e.g. luminescent quantum dots
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/14—Carrier transporting layers
    • H10K50/15—Hole transporting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/814—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/828—Transparent cathodes, e.g. comprising thin metal layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
    • H10K71/135—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing using ink-jet printing

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display panel, a method for fabricating the same, and a display device.
  • the above transparent display panel can be generally applied to glass of a building or a car, a display window of a shopping mall, and the like.
  • An embodiment of the present disclosure provides a display panel including a substrate substrate and a plurality of pixels disposed on the base substrate; wherein each pixel includes a pixel circuit disposed on the base substrate, the display panel a pixel defining layer covering the pixel circuit; a plurality of grooves disposed on a surface of the pixel defining layer facing away from the pixel circuit; the plurality of grooves and the plurality of pixels Corresponding to each; wherein each of the grooves is provided with a light emitting diode electrically connected to the pixel circuit.
  • an orthographic projection of each groove on the substrate substrate overlaps with a light emitting region in a corresponding pixel.
  • the pixel defining layer is composed of a passivation layer covering the pixel circuit; the depth of the groove is smaller than the thickness of the passivation layer.
  • the pixel defining layer is composed of a passivation layer covering the pixel circuit and a photoresist layer disposed on a surface of the passivation layer facing away from the pixel circuit; the depth of the groove is less than or equal to The thickness of the photoresist layer.
  • the pixel circuit comprises a thin film transistor electrically connected to a drain of the thin film transistor.
  • a bottom portion of the recess is disposed at a position corresponding to a drain of the thin film transistor, and a first via hole of the first electrode of the light emitting diode passes through the drain of the thin film transistor Extremely electrical connection.
  • a plurality of retaining walls spanning the recess are disposed in the groove; the retaining wall is of the same material as the pixel defining layer.
  • any two of the retaining walls extend in the same direction, and the distance between the two directly adjacent retaining walls is fixed.
  • the plurality of retaining walls include a first sub-retaining wall and a second sub-retaining wall that are horizontally and vertically intersected; the first sub-retaining wall and the second sub-retaining wall are intersected to define a plurality of matrixes.
  • the enclosed area; the two adjacent areas directly adjacent are equal in area.
  • the light emitting diode comprises: a hole transport layer, an illuminating layer, an electron transport layer and a second electrode which are sequentially located on a side of the first electrode facing away from the pixel circuit; wherein the first electrode is transparent
  • the conductive material is composed of a metal material; or the first electrode is made of a metal material, and the second electrode is made of a transparent conductive material.
  • the light emitting diode is a quantum dot light emitting diode
  • the material of the light emitting layer includes at least any one of CdSe, CdS, CdTe, ZnSe, ZnTe, ZnS, HgTe, InAs, InP, and GaAs.
  • the material constituting the active layer of the thin film transistor includes at least one of an oxide semiconductor material and a low temperature polysilicon.
  • a display device including the display panel according to any of the above embodiments is provided.
  • a method of fabricating a display panel includes: forming a plurality of pixels on a substrate by a patterning process, each pixel including a pixel circuit disposed on the substrate; forming a pixel defining layer covering the pixel circuit; a surface of the pixel defining layer facing away from the pixel circuit is provided with a plurality of grooves, the plurality of grooves are in one-to-one correspondence with the plurality of pixels; A light emitting diode electrically connected to the pixel circuit is formed in the recess.
  • the step of forming the pixel defining layer comprises: sequentially forming a passivation layer and a photoresist layer on the substrate substrate on which the pixel circuit is formed; using a halftone mask, by a patterning process
  • the groove is formed on the passivation layer; a first via hole is formed at the bottom of the groove.
  • the step of forming the light emitting diode includes forming a first electrode in the recess, and the first electrode is electrically connected to the pixel circuit through the first via.
  • the step of forming the pixel defining layer comprises: sequentially forming a passivation layer and a photoresist layer on the substrate substrate on which the pixel circuit is formed; using a halftone mask, by a patterning process
  • the groove is formed on the photoresist layer; a first via hole penetrating the photoresist layer and the passivation layer is formed at a bottom of the groove.
  • the step of forming the light emitting diode includes forming a first electrode in the recess, and the first electrode is electrically connected to the pixel circuit through the first via.
  • the step of forming the pixel defining layer comprises: forming a passivation layer on the substrate substrate on which the pixel circuit is formed, and forming a first via hole on the passivation layer by a patterning process; Forming a transparent conductive layer on the base substrate, and forming the first electrode by a patterning process; the first electrode is electrically connected to the pixel circuit through the first via hole; forming an insulation on the base substrate a layer of material and forming the recess on the layer of insulating material by a patterning process.
  • the step of forming the light emitting diode further comprises: forming a hole transport layer at a position corresponding to the groove by a patterning process on a side of the first electrode facing away from the base substrate; On the base substrate having the hole transport layer, a light-emitting layer is formed at a position corresponding to the groove by an inkjet printing process or an evaporation process; on the base substrate on which the light-emitting layer is formed, by patterning a process of forming an electron transport layer at a position corresponding to the groove; and forming a second electrode of the light emitting diode on the base substrate on which the electron transport layer is formed.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 2 is a schematic top plan view of the display panel of FIG. 1;
  • FIG. 3a is a schematic structural view of the light emitting diode of FIG. 1;
  • 3b is a schematic diagram of energy levels of the LED of FIG. 1;
  • 3c is a color gamut diagram of the light emitting diode of FIG. 1;
  • FIG. 4 is a schematic structural diagram of a pixel defining layer in a display panel according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of another structure of a pixel defining layer in a display panel according to an embodiment of the present disclosure
  • FIG. 6 is still another schematic structural diagram of a pixel defining layer in a display panel according to an embodiment of the present disclosure.
  • Figure 7a is a schematic structural view of a retaining wall disposed in the recess of Figure 1;
  • Figure 7b is another structural schematic view of the retaining wall disposed in the recess of Figure 1;
  • 8a, 8b, 8c, 8d, and 8e are schematic views showing a process of forming a thin film transistor on a substrate
  • FIG. 9 is a flowchart of a method for fabricating a display panel according to an embodiment of the present disclosure.
  • 10a, 10b, 10c, 10d, and 10e are schematic diagrams of an implementation manner of step S101 in FIG. 9;
  • FIG. 11a and 11b are schematic diagrams showing another implementation manner of step S101 in FIG. 9;
  • 12a, 12b, and 12c are schematic views showing an implementation of fabricating a quantum dot light-emitting layer
  • FIG. 13a, 13b, and 13c are schematic diagrams showing still another implementation manner of step S101 in FIG.
  • An embodiment of the present disclosure provides a display panel including a substrate substrate 01 and a plurality of pixels 101 disposed on the substrate substrate 01, wherein each pixel 101 is disposed at a pixel circuit 102 on the base substrate 01, the display panel further includes a pixel defining layer 20 covering the pixel circuit 102; the pixel defining layer 20 faces away from the surface of the pixel circuit 102 A plurality of grooves 201 are disposed; the plurality of grooves 201 are in one-to-one correspondence with the plurality of pixels 101; wherein each of the grooves 201 is provided with a light emitting diode 30 electrically connected to the pixel circuit 102.
  • the light emitting diode may be a Quantum Dot Light-emitting Diode (QLED).
  • a pixel circuit corresponding to the pixel circuit is formed.
  • the orthographic projection of the groove 201 on the above-described base substrate 01 may overlap with the light-emitting area A in the corresponding pixel 101.
  • the light-emitting area A is an area other than the pixel circuit 102 provided in the pixel 101.
  • the light emitting diode 30 may include a structure as shown in FIG. 3a.
  • the light emitting diode 30 may include a first electrode 301, a hole transport layer 302 (HTL), a light emitting layer 303, an electron transport layer 304, and a second electrode 305 which are sequentially located on a side of the thin film transistor facing away from the base substrate 01.
  • the light emitting diode 30 may further include a hole injection layer between the first electrode 301 and the hole transport layer 302, and an electron input layer between the electron transport layer 304 and the second electrode 305.
  • the first electrode 301 can be the anode of the LED 30, and the second electrode 305 is the cathode of the LED 30.
  • the light-emitting diode 30 may be a top-emitting type or a bottom-emitting type.
  • the material constituting the second electrode 305 may be a transparent conductive material, for example, Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO);
  • the material of an electrode 301 may be a metal material.
  • the light emitting diode 30 can be a quantum dot light emitting diode.
  • the light-emitting layer 303 may include a II-VI pair or a III-V paired nano-semiconductor compound including at least one of CdSe, CdS, CdTe, ZnSe, ZnTe, ZnS, HgTe, InAs, InP, and GaAs. , thereby forming a quantum dot luminescent layer.
  • the light-emitting layer 303 may be a single-layer film layer or a multilayer film layer.
  • the material constituting each film layer may include at least any one of the above-mentioned CdSe, CdS, CdTe, ZnSe, ZnTe, ZnS, HgTe, InAs, InP, and GaAs.
  • the pairing method of the above nano semiconductor compound includes an organic fusion method or an aqueous phase synthesis method.
  • the organic fusion method is: injecting the organometallic precursor solution into the high temperature ligand solution, the precursor is rapidly pyrolyzed and nucleated under high temperature (200-600 ° C) conditions, and then the crystal nucleus is slowly grown into nanocrystals.
  • the method is relatively expensive to manufacture, and the metal compound precursor used has relatively large toxicity and self-ignitability, requires high pressure storage, and explosively releases a large amount of gas and heat upon injection.
  • the aqueous phase synthesis method is: using various sulfhydryl compounds, such as a small molecule such as a base acid, a mercapto alcohol, a sulfhydryl amine and a sulfhydryl amino acid as a stabilizer, and crystallizing and growing the fluorescent nanometer in an aqueous solution at 100 ° C. Particles.
  • aqueous phase synthesis has the advantages of simple operation, low cost and toxic small lamp.
  • the pairing method of the above nano-semiconductor compound may further include a high-temperature hydrothermal method, a microwave irradiation method, and the like, which will not be repeated herein.
  • the material constituting the first electrode of the light-emitting diode 30 is molybdenum trioxide (MoO 3 ), and the material constituting the second electrode is zinc oxide (ZnO).
  • MoO 3 molybdenum trioxide
  • ZnO zinc oxide
  • the light-emitting process of the light-emitting diode 30 will be described. Specifically, as shown in FIG. 3b, electrons (e - ) and holes (h + ) are respectively injected by the second electrode and the first electrode, driven by an external voltage. The injected electrons and holes migrate from the electron transport layer (ETL) and the hole transport layer (HTL) to the light emitting layer (R, G, B), respectively.
  • ETL electron transport layer
  • HTL hole transport layer
  • Electrons and holes are directly injected into the conduction band and the valence band of the light-emitting layer to form excitons, which are then combined to emit photons.
  • the band gap energy of the light-emitting layer varies with the R, G, and B colors, and the difference of the band gap energy becomes smaller in the order of R, G, and B.
  • holes are injected from the hole injection layer to the light-emitting layer, there is a hole energy barrier from about 0.7 eV to 2 eV despite having a difference between colors.
  • the pixel circuit 102 is used to drive the LED 30 to emit light.
  • the pixel circuit 102 can include at least two thin film transistors and one capacitor.
  • the at least two thin film transistors include a driving transistor having a driving function, and some switching transistors that implement a switching function. Part of the switching transistor can write the data voltage Vdata on the data line to the driving transistor.
  • the pixel circuit 102 further includes a threshold voltage compensation function, a part of the switching transistors can compensate the threshold voltage Vth of the driving transistor to reduce the luminance difference between the respective pixels 101.
  • a part of the switching transistor can perform voltage reset on the gate of the driving transistor and the LED 30.
  • the present disclosure does not limit the structure of the pixel circuit 102 described above.
  • at least one of the thin film transistors in the pixel circuit 102 is electrically connected to the light emitting diode 30.
  • the thin film transistor may be the above-described driving transistor.
  • the material constituting the active layer of the thin film transistor may be Low Temperature Poly-Silicon (LTPS).
  • the material constituting the active layer of the thin film transistor may include an oxide semiconductor material such as IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ITWO (Indium Tungsten Zinc Oxide), ZnO (Zinc Oxide). At least one of CdO (cadmium oxide) or Al2O3 (aluminum oxide).
  • the active layer of the thin film transistor is taken as an example of ITZO or ITWO, and the influence of the preparation process of the active layer on the carrier mobility of the thin film transistor is explained.
  • the solution is treated by an annealing process and a UV light process.
  • the annealing process at 250 ° C ⁇ 500 ° C as an example, the relationship between the temperature of the annealing process and the UV light process temperature range and the carrier mobility of the thin film transistor is shown in Table 1.
  • the base substrate 01 may be made of a transparent resin material, and the resin material may be a flexible material or a hard material; or the base substrate 01 may be a glass substrate.
  • the display panel provided by the embodiment of the present disclosure includes a light emitting diode, which may be a quantum dot light emitting diode.
  • Quantum dot materials in quantum dot light-emitting diodes In the process of photoluminescence, the half-width of the emitted light is about 30 nm. Therefore, the quantum dot light emitting diode has a near-Gaussian symmetrical narrow-band emission characteristic, so the purity of the excited color is higher, so that the display panel obtains a higher color gamut, as shown in FIG. 3c, which can reach 100% NTSC or more, thereby making The color displayed on the display panel is more realistic.
  • the pixel circuit 102 includes a thin film transistor, and the first electrode 301 of the light emitting diode 30 can be connected to the drain of the thin film transistor to electrically connect the light emitting diode 30 to the pixel circuit 102.
  • the bottom of the recess 201 is provided with a first via 401 at a position corresponding to the drain of the thin film transistor, and the first electrode 301 of the LED passes the A via 401 is electrically connected to the drain of the thin film transistor.
  • the manner in which the pixel defining layer 20 is disposed may be:
  • the pixel defining layer 20 is composed of a passivation layer 130 covering the pixel circuit 102; the depth of the groove 201 is smaller than the thickness of the passivation layer 130.
  • the bank 202 is formed of a passivation layer 130.
  • the pixel defining layer 20 is composed of a passivation layer 130 covering the pixel circuit 102 and a photoresist disposed on a surface of the passivation layer 130 facing away from the pixel circuit 102.
  • the layer 131 is formed; the depth of the groove 201 is smaller than the thickness of the photoresist layer 131.
  • the bank 202 is formed of a photoresist layer 131.
  • the passivation layer 130 in FIG. 4 functions as the pixel defining layer 20.
  • the passivation layer 130 and the photoresist layer 131 are used as the pixel defining layer 20, so that the step of separately forming the pixel defining layer 20 can be omitted, so as to simplify the manufacturing process of the display panel.
  • the pixel defining layer 20 is composed of a passivation layer 130 covering the pixel circuit 102 and a photoresist layer 131 disposed on a surface of the passivation layer 130 facing away from the pixel circuit 102.
  • the depth of the groove 201 is equal to the thickness of the photoresist layer 131.
  • the bank 202 is formed of a photoresist layer 131.
  • the bottom of the groove 201 may be provided with a pixel electrode 50. That is, the pixel electrode 50 functions as the first electrode 301 of the light emitting diode 30.
  • the groove 201 is spaced apart from the retaining wall 203 across the groove 201.
  • the area in which the groove 201 is located can be subdivided into a plurality of closed areas B surrounded by the retaining wall 203 by the above-mentioned retaining wall 203 and the above-mentioned dam 202.
  • the film-forming material in the closed region B can be further diffused by the above-mentioned retaining wall 203.
  • the trend is limited to reduce the problem that the light-emitting layer 303 is uneven due to the above-described diffusion region.
  • the above-mentioned retaining wall 203 can be arranged in the same manner as shown in Fig. 7a, and the extending directions of any two retaining walls 203 are the same, and the distance between the directly adjacent two retaining walls 203 is fixed. Thereby, the uniformity of the film layers located in any two adjacent closed regions B can be made equal or approximately equal.
  • the plurality of retaining walls 203 include a first sub-retaining wall 2031 and a second sub-retaining wall 2032 that intersect horizontally and vertically.
  • the first sub-retaining wall 2031 and the second sub-retaining wall 2032 intersect to define a plurality of closed areas B arranged in a matrix form.
  • the areas of the two adjacent areas B that are directly adjacent are equal. Thereby, the uniformity of the film layers located in any two adjacent closed regions B can be made equal or approximately equal.
  • the optional retaining wall 203 and the pixel defining layer 20 are of the same material.
  • the above-mentioned retaining wall 203 may be integrated with the pixel defining layer 20.
  • An embodiment of the present disclosure provides a display device including the display panel according to any of the above embodiments.
  • the display device has the same advantageous effects as the display panel provided in the foregoing embodiment, and details are not described herein again.
  • the display device may be any product or component having a display function such as a display, a television, a digital photo frame, a mobile phone or a tablet computer.
  • Embodiments of the present disclosure provide a method of fabricating a display panel, including: forming a plurality of pixels on a substrate by a patterning process, each pixel including a pixel circuit disposed on the substrate; forming a pixel circuit covering the substrate a pixel defining layer; a surface of the pixel defining layer facing away from the pixel circuit is provided with a plurality of grooves, the plurality of grooves are in one-to-one correspondence with the plurality of pixels; and formed in the groove a light emitting diode electrically connected to the pixel circuit.
  • forming a pixel circuit including, for example, a thin film transistor may include the following steps.
  • a metal layer is formed on the base substrate 01 by a magnetron sputtering process, for example, the metal layer is made of metallic copper.
  • the gate 110 and the gate lines (G1, G2, ...) as shown in FIG. 8a are formed by an exposure, development, and etching process.
  • a gate insulating layer 111 is formed by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process.
  • the material constituting the gate insulating layer 111 is silicon nitride (SiN).
  • an organic solution is applied to the surface of the above-mentioned gate insulating layer 111 to form an organic thin film 1120.
  • the solute of the above organic solution may include ITZO (indium tin zinc oxide) or ITWO (indium tungsten zinc oxide); the viscosity of the organic solution is 2 to 4 cp.
  • the organic thin film 1120 is in a semi-cured state, as shown in FIG. 8c, the organic thin film 1120 is pressed by a mold 120.
  • the organic film 1120 is pre-baked for 1 to 2 hours by an annealing process and a UV light process at 200 to 300 °C. Then, the organic thin film 1120 was subjected to Hard-bake for 1 h at 350 ° C to form an active layer 112 as shown in FIG. 8d, and the thickness of the active layer 112 was about 5 nm. In this way, drying at 200 to 400 ° C can completely decompose the thermal decomposition of the organic solution, so that the organic contaminants in the organic film 1120 can be completely removed to improve the purity of the active layer 112. Specifically, the relationship between the temperature range of the annealing process and the UV illumination process and the carrier mobility of the thin film transistor is shown in Table 1, and details are not described herein again.
  • a metal layer is formed by a magnetron sputtering process, and then a source 113 of the thin film transistor as shown in FIG. 8e is formed by an exposure, development, and etching process. Drain 114.
  • the method for manufacturing the display panel further includes:
  • a pixel defining layer 20 covering the pixel circuit 102 is formed.
  • the surface of the pixel defining layer 20 facing away from the pixel circuit 102 is provided with a plurality of grooves 201.
  • a dam 202 is disposed around each of the grooves 201.
  • the plurality of grooves 201 are in one-to-one correspondence with the plurality of pixels 101.
  • a light emitting diode 30 electrically connected to the pixel circuit 102 is formed.
  • the manufacturing method of the above display panel has the same technical effects as the display panel provided in the foregoing embodiment, and details are not described herein again.
  • the passivation layer 130 and the photoresist layer 131 as shown in FIG. 10a are sequentially formed.
  • the material constituting the passivation layer 130 is PMMA (polymethyl methacrylate), and the dielectric constant ⁇ of the PMMA is 3.2 to 3.5.
  • Sub-step 2 mask exposure is performed on the photoresist layer 131 by using a half-tone mask 132 as shown in FIG. 10b.
  • the halftone mask 132 includes a completely transparent region, a completely light-shielding region, and a semi-transmissive region.
  • the photoresist layer 131 through which the light passes through the completely transparent region can be completely dissolved in the developer; the light passes through the light in the semi-transmissive region.
  • the engraved layer 131 can be partially dissolved in the developer; the photoresist layer 131 through which the light passes through the completely light-shielding region is not dissolved in the developer.
  • Sub-step three the photoresist layer 131 is developed to form a structure as shown in Fig. 10d.
  • Sub-step 4 in the position where the photoresist is completely developed, the material constituting the passivation layer 130 is completely removed by an etching process to form a first via hole 401 as shown in FIG. 10e. Then, the photoresist corresponding to the semi-transmissive region is removed by an ashing process, and the recess 201 is formed by an etching process.
  • the first via 401 is located at the bottom of the recess 201, and the first via 401 corresponds to the drain 114 of the thin film transistor for driving the QLED in the pixel circuit.
  • the recess 201 and the first via 401 at the bottom of the recess 201 are formed on the passivation layer 130, so that the passivation layer 130 can be shared as the pixel defining layer 20, so that the pixel defining layer 20 need not be separately fabricated. Thus, the cost of the manufacturing process can be reduced.
  • the method of forming the above-described light emitting diode 30 includes: forming a first electrode 301 as shown in FIG. 4 in the recess 201, the first electrode 301 being electrically connected to the drain 301 of the thin film transistor through the first via 401 connection.
  • an ITO or IZO thin film can be formed in the above-mentioned groove by a magnetron sputtering process as the first electrode 301.
  • the manufacturing method of the light emitting diode 30 further includes forming a hole transport layer 302 at a position corresponding to the groove 201 by a patterning process on a side of the first electrode 301 facing away from the base substrate 01.
  • a metal layer is formed on the surface of the first electrode 301 by a magnetron sputtering process, and the metal layer may be composed of a material such as MoO3, NiO, CBP, TCTA or the like. Then, the above metal layer is patterned by an exposure, development, and etching process to form a hole transport layer 302.
  • the light-emitting layer 303 is formed at a position corresponding to the groove 201 by an inkjet printing process or an evaporation process.
  • the materials constituting the light-emitting layer 303 are the same as those described above, and are not described herein again.
  • the manufacturing process of the above-described light-emitting layer 303 will be described by taking an inkjet printing process as an example. Specifically, as shown in FIG. 12a, a quantum dot solution 501 composed of a nano quantum dot compound is dropped onto the surface of the hole transport layer 302 in the recess 201 by inkjet printing. Next, as shown in Fig. 12b, the above quantum dot solution 501 is prebaked. Finally, as shown in FIG. 12c, the above quantum dot solution 501 is subjected to UV illumination treatment to form the above-described light-emitting layer 303. Wherein, after the above pre-baking and UV illumination treatment, the organic contaminants in the quantum dot solution 501 can be removed, and the luminous efficiency of the luminescent layer 303 can be improved.
  • the electron transport layer 304 is formed at a position corresponding to the groove 201 by a patterning process.
  • the material constituting the electron transport layer 304 includes ZnO, TiO 2 , WO 3 , SnO 2 , and the like.
  • the preparation process of the electron transport layer 304 is the same as that of the hole transport layer 302, and will not be described herein.
  • the second electrode 305 of the light emitting diode 30 is formed on the base substrate 01 on which the electron transport layer 304 is formed.
  • the light-emitting diode 30 is used as the bottom light-emitting type, and the material constituting the second electrode 305 may be metal aluminum.
  • the second electrodes 305 of all the light emitting diodes 30 may be connected to each other.
  • the substrate of the electron transport layer 304 may be formed by a magnetron sputtering process. 01, the formation of the second electrode 305 can be completed by forming a metal layer.
  • a metal layer may be formed on the base substrate 01 on which the electron transport layer 304 is formed by a magnetron sputtering process; The metal layer is patterned by a mask, an exposure, and a development process to form the second electrode 305 described above.
  • forming the pixel defining layer 20 described above may include the following sub-steps.
  • Sub-step 1 on the base substrate 01 on which the thin film transistor is formed, as shown in FIG. 10a, the passivation layer 130 and the photoresist layer 131 are sequentially formed.
  • a half-tone mask 132 is used to form a groove 201 as shown in FIG. 11a on the photoresist layer 131 by a patterning process, and at the bottom of the groove 201, and corresponding to the light-emitting A via 401' is formed at a location where the diode-connected thin film transistor drain 114 is located.
  • Sub-step three as shown in FIG. 11b, a first via hole 401 penetrating the photoresist layer 131 and the passivation layer 130 is formed at the bottom of the recess 201 by a patterning process.
  • the patterning process may include a photolithography process, or include a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, etc.;
  • the engraving process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, and development.
  • the corresponding patterning process can be selected according to the structure formed in the present disclosure.
  • the one-time patterning process in the embodiment of the present disclosure may be to form different exposure regions by one mask exposure process, and then perform multiple etching, ashing, etc. removal processes on different exposure regions to finally obtain a desired pattern.
  • the method for forming the first electrode of the light-emitting diode 30 includes: forming a first electrode 301 in the recess 201, the first electrode 301 passing through the first via 401 and the thin film transistor The drain is electrically connected.
  • forming the pixel defining layer 20 described above may include the following sub-steps.
  • Sub-step 1 as shown in FIG. 13a, a passivation layer 130 is formed on the base substrate 01 on which the pixel circuit is formed, and a first via hole 401 is formed on the passivation layer 130 by a patterning process.
  • Sub-step 2 as shown in FIG. 13b, on the base substrate 01 on which the above structure is formed, a transparent conductive layer is formed, and the first electrode 301 is formed by a patterning process.
  • the first electrode 301 is electrically connected to the drain of the thin film transistor through the first via 401.
  • Sub-step 3 as shown in FIG. 13c, on the base substrate 01 on which the above structure is formed, an insulating material layer (for example, a photoresist layer 131) is formed, and formed on the insulating material layer by a patterning process as shown in FIG. The groove 202 is shown.
  • an insulating material layer for example, a photoresist layer 131
  • the display panel provided by the embodiment of the present disclosure includes a light emitting diode, which may be a quantum dot light emitting diode.
  • Quantum dot materials in quantum dot light-emitting diodes In the process of photoluminescence, the half-width of the emitted light is about 30 nm. Therefore, the quantum dot light emitting diode has a near-Gaussian symmetrical narrow-band emission characteristic, so that the purity of the excited color is higher, so that the display panel obtains a higher color gamut, and can reach 100% NTSC or more, thereby causing the display panel to display a picture. The color is more realistic.

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Abstract

一种显示面板及其制作方法、显示装置。显示面板包括衬底基板（01）和布置在衬底基板上的多个像素（101）；其中，每个像素包括布置在衬底基板上的像素电路（102），显示面板还包括覆盖像素电路的像素界定层（20）；像素界定层背离像素电路的表面上设置有多个凹槽（201）；多个凹槽与多个像素一一对应；其中，每个凹槽内设置有与像素电路电连接的发光二极管（30）。

Description

显示面板及其制作方法、显示装置
相关申请
本申请要求保护在2017年7月25日提交的申请号为201710617292.7的中国专利申请的优先权，该申请的全部内容以引用的方式结合到本文中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制作方法、显示装置。
背景技术
随着显示技术的日益发展，根据用户的需求一些新型的显示面板，例如透明显示面板应运而生。用户在通过透明显示面板看到显示画面的同时，还可以透过显示面板看到该显示面板后面的景象。上述透明显示面板通常可以应用于建筑物或汽车的玻璃，以及商场的展示窗等。
公开内容
本公开实施例提供一种显示面板，包括衬底基板和布置在所述衬底基板上的多个像素；其中，每个像素包括布置在所述衬底基板上的像素电路，所述显示面板还包括覆盖所述像素电路的像素界定层(pixel defining layer)；所述像素界定层背离所述像素电路的表面上设置有多个凹槽；所述多个凹槽与所述多个像素一一对应；其中，每个凹槽内设置有与所述像素电路电连接的发光二极管。
可选地，每个凹槽在所述衬底基板上的正投影与对应像素中的发光区重叠。
可选地，所述像素界定层由覆盖所述像素电路的钝化层构成；所述凹槽的深度小于所述钝化层的厚度。
可选地，所述像素界定层由覆盖所述像素电路的钝化层和布置在所述钝化层背离所述像素电路的表面的光刻胶层构成；所述凹槽的深度小于或等于所述光刻胶层的厚度。
可选地，所述像素电路包括薄膜晶体管，所述发光二极管与所述薄膜晶体管的漏极电连接。
可选地，所述凹槽的底部在对应所述薄膜晶体管的漏极的位置设置有第一过孔，所述发光二极管的第一电极通过所述第一过孔与所述 薄膜晶体管的漏极电连接。
可选地，所述凹槽内间隔设置有多个横跨所述凹槽的挡墙；所述挡墙与所述像素界定层同层同材料。
可选地，任意两个所述挡墙的延伸方向相同，且直接相邻的两个所述挡墙之间的距离是固定的。
可选地，多个所述挡墙包括横纵交叉的第一子挡墙和第二子挡墙；所述第一子挡墙和所述第二子挡墙交叉界定多个呈矩阵形式排列的封闭区；直接相邻的两个封闭区的面积相等。
可选地，所述发光二极管包括：依次位于所述第一电极背离所述像素电路一侧的空穴传输层、发光层、电子传输层以及第二电极；其中，所述第一电极由透明导电材料构成，所述第二电极由金属材料构成；或者，所述第一电极由金属材料构成，所述第二电极由透明导电材料构成。
可选地，所述发光二极管是量子点发光二极管，所述发光层的材料至少包括CdSe、CdS、CdTe、ZnSe、ZnTe、ZnS、HgTe、InAs、InP和GaAs中的任意一种。
可选地，构成所述薄膜晶体管有源层的材料包括氧化物半导体材料和低温多晶硅中至少一种。
本公开实施例的另一方面，提供一种显示装置，包括如以上任一实施例所述的显示面板。
本公开实施例的又一方面，提供一种显示面板的制作方法，包括：通过构图工艺在衬底基板上形成多个像素，每个像素包括布置在所述衬底基板上的像素电路；形成覆盖所述像素电路的像素界定层；所述像素界定层背离所述像素电路的表面上设置有多个凹槽，所述多个凹槽与所述多个像素一一对应；以及在所述凹槽内，形成与所述像素电路电连接的发光二极管。
可选地，形成所述像素界定层的步骤包括：在形成有所述像素电路的衬底基板上，依次形成钝化层和光刻胶层；采用半色调掩模板，通过构图工艺在所述钝化层上形成所述凹槽；在所述凹槽的底部形成第一过孔。形成所述发光二极管的步骤包括：在所述凹槽内形成第一电极，所述第一电极通过所述第一过孔与所述像素电路电连接。
可选地，形成所述像素界定层的步骤包括：在形成有所述像素电 路的衬底基板上，依次形成钝化层和光刻胶层；采用半色调掩模板，通过构图工艺在所述光刻胶层上形成所述凹槽；在所述凹槽的底部形成贯穿所述光刻胶层和所述钝化层的第一过孔。形成所述发光二极管的步骤包括：在所述凹槽内形成第一电极，所述第一电极通过所述第一过孔与所述像素电路电连接。
可选地，形成所述像素界定层的步骤包括：在形成有所述像素电路的衬底基板上形成钝化层，并通过构图工艺在所述钝化层上形成第一过孔；在所述衬底基板上形成透明导电层，并通过构图工艺形成所述第一电极；所述第一电极通过所述第一过孔与所述像素电路电连接；在所述衬底基板上形成绝缘材料层，并通过构图工艺在所述绝缘材料层上形成所述凹槽。
可选地，形成所述发光二极管的步骤进一步包括：在所述第一电极背离所述衬底基板的一侧，通过构图工艺，在对应所述凹槽的位置形成空穴传输层；在形成有所述空穴传输层的衬底基板上，通过喷墨打印工艺或蒸镀工艺，在对应所述凹槽的位置形成发光层；在形成有所述发光层的衬底基板上，通过构图工艺，在对应所述凹槽的位置形成电子传输层；以及在形成有所述电子传输层的衬底基板上，形成所述发光二极管的第二电极。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种显示面板的结构示意图；
图2为图1中显示面板的俯视结构示意图；
图3a为图1中发光二极管的结构示意图；
图3b为图1中发光二极管的能级示意图；
图3c为图1中发光二极管的色域示意图；
图4为本公开实施例提供的显示面板中像素界定层的一种结构示意图；
图5为本公开实施例提供的显示面板中像素界定层的另一种结构 示意图；
图6为本公开实施例提供的显示面板中像素界定层的又一种结构示意图；
图7a为设置于图1所述的凹槽内的挡墙的一种结构示意图；
图7b为设置于图1所述的凹槽内的挡墙的另一种结构示意图；
图8a、图8b、图8c、图8d、图8e为在衬底基板上形成薄膜晶体管的过程示意图；
图9为本公开实施例提供的一种显示面板的制作方法流程图；
图10a、图10b、图10c、图10d、图10e为图9中步骤S101的一种实现方式示意图；
图11a、图11b为图9中步骤S101的另一种实现方式示意图；
图12a、图12b、图12c为制作量子点发光层的一种实现方式示意图；以及
图13a、图13b、图13c为图9中步骤S101的又一种实现方式示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供一种显示面板，如图2所示，所述显示面板包括衬底基板01和布置在所述衬底基板01上的多个像素101；其中，每个像素101包括布置在所述衬底基板01上的像素电路102，所述显示面板还包括覆盖所述像素电路102的像素界定层(pixel defining layer)20；所述像素界定层20背离所述像素电路102的表面上设置有多个凹槽201；所述多个凹槽201与所述多个像素101一一对应；其中，每个凹槽201内设置有与所述像素电路102电连接的发光二极管30。所述发光二极管可以是量子点发光二极管(Quantum Dot Light-emitting Diode，QLED)。
在此基础上，如图1和图2所示，由于多个凹槽201与所述多个像素101一一对应，并且所述多个像素101是相互连接的，因此形成 了对应于像素电路102的围堰(cofferdam)202。该凹槽201在上述衬底基板01上的正投影可以与对应像素101中的发光区A重叠。该发光区A为上述像素101中除了设置有上述像素电路102以外的区域。
具体的，该发光二极管30可以包括如图3a所示的结构。该发光二极管30可以包括依次位于上述薄膜晶体管背离衬底基板01一侧的第一电极301、空穴传输层302(HTL)、发光层303、电子传输层304以及第二电极305。可选地，该发光二极管30还可以包括位于第一电极301与空穴传输层302之间的空穴注入层，以及位于电子传输层304与第二电极305之间的电子输入层。其中，通常上述第一电极301可以为该发光二极管30的阳极，而第二电极305为该发光二极管30的阴极。
在此基础上，上述发光二极管30可以为顶发光式也可以为底发光式。当该发光二极管30为顶发光式时，构成第二电极305的材料可以为透明导电材料，例如，氧化铟锡(Indium Tin Oxide，ITO)或氧化铟锌(Indium Zinc Oxide，IZO)；构成第一电极301的材料可以为金属材料。当该发光二极管30为底发光式时，构成第一电极301的材料可以为上述透明导电材料；构成第二电极305的材料可以为金属材料。
此外，所述发光二极管30可以是量子点发光二极管。发光层303可以包括II-VI族配对或III-V族配对的纳米半导体化合物，该纳米半导体化合物至少包括CdSe、CdS、CdTe、ZnSe、ZnTe、ZnS、HgTe、InAs、InP和GaAs中的任意一种，从而形成量子点发光层。
基于此，上述发光层303可以为单层薄膜层或者多层薄膜层。当该发光层303为多层薄膜层时，构成每一层薄膜层的材料可以至少包括上述CdSe、CdS、CdTe、ZnSe、ZnTe、ZnS、HgTe、InAs、InP和GaAs中的任意一种。
其中，上述纳米半导体化合物的配对方法包括有机融合法或水相合成法。
具体的，有机融合法为：将有机金属前驱体溶液注射进高温配体溶液中，前驱体在高温(200～600℃)条件下迅速热解并成核，接着晶核缓慢生长为纳米晶。该方法造价相对较高，且使用的金属化合物前驱体具有相对大的毒性与自燃性，需要高压存储，反应时在注入时会爆炸性地释放出大量气体和热。
水相合成法为：采用各种疏基化合物，如疏基酸、疏基醇、疏基胺及疏基氨基酸等小分子作为稳定剂，在水溶液中，100℃的条件下晶化生长荧光纳米颗粒。与有机合成相比，水相合成具有操作简单、成本低、毒性小灯优势。
此外，上述纳米半导体化合物的配对方法还可以包括高温水热法与微波辐射法等，在此不再一一赘述。
基于此，以构成发光二极管30第一电极的材料为三氧化钼(MoO 3)，构成第二电极的材料为氧化锌(ZnO)为例，对上述发光二极管30的发光过程进行说明。具体的，如图3b所示，在外界电压的驱动下，电子(e -)和空穴(h +)由第二电极和第一电极分别注入。注入的电子和空穴分别从电子传输层(ETL)和空穴传输层(HTL)向发光层(R、G、B)迁移。电子和空穴直接注入到发光层的导带和价带，形成激子，随后复合发射出光子。其中，发光层的带隙能量随R、G、B颜色而变化，并且带隙能量的差值按照R、G、B的顺序变小。此外，在空穴从空穴注入层注入到发光层时，尽管在颜色之间具有差值，但存在从大约0.7eV到2eV的空穴能量势垒。
在此基础上，上述像素电路102用于驱动发光二极管30发光。其中，该像素电路102可以包括至少两个薄膜晶体管和一个电容。其中，上述至少两个薄膜晶体管中包括具有驱动功能的驱动晶体管，以及一些实现开关功能的开关晶体管。部分开关晶体管可以将数据线上的数据电压Vdata写入至驱动晶体管。此外，当上述像素电路102还具备阈值电压补偿功能时，还有部分开关晶体管可以对驱动晶体管的阈值电压Vth进行补偿，以减小各个像素101之间的亮度差异。或者，当上述像素电路102还具有重置功能时，还有部分开关晶体管可以对驱动晶体管的栅极、发光二极管30进行电压重置。本公开对上述像素电路102的结构不做限定。在此情况下，上述像素电路102中至少有一个薄膜晶体管与该发光二极管30电连接。例如，该薄膜晶体管可以为上述驱动晶体管。
基于此，为了提高上述薄膜晶体管的迁移率以及导通性能，可选的，构成上述薄膜晶体管有源层的材料可以为低温多晶硅(Low Temperature Poly-Silicon，LTPS)。或者，构成上述薄膜晶体管有源层的材料可以包括氧化物半导体材料，例如，IGZO(铟镓锌氧化物)、 ITZO(氧化铟锡锌)、ITWO(氧化铟钨锌)、ZnO(氧化锌)、CdO(氧化镉)或者Al2O3(三氧化二铝)中的至少一种。
其中，以上述薄膜晶体管有源层采用ITZO或ITWO为例，对有源层的制备工艺对薄膜晶体管载流子迁移率的影响进行说明。具体的，当进行ITZO或ITWO溶液制程制备后，采用退火工艺和UV光照工艺对上述溶液进行处理。以退火工艺在250℃～500℃为例，该退火工艺和UV光照工艺温度范围温度与薄膜晶体管载流子迁移率的关系如表1所示。
表1
Figure PCTCN2018076371-appb-000001
由表1可知，退火工艺温度越高，薄膜晶体管的载流子迁移率(Mobility)越高。在此基础上，经过UV光照后，上述载流子迁移率能够明显升高。此外，经过UV光照后，薄膜晶体管的阈值电压(Vth)也有所降低。而退火工艺和UV光照工艺对薄膜晶体管的阈值电压摆幅(SS)的影响，暂未发现相应的规律。
进一步的，为了实现透明显示，可选的，上述衬底基板01可以由透明树脂材料构成，且该树脂材料可以为柔性材料或者材质较硬的材料；或者衬底基板01还可以为玻璃基板。
综上所述，本公开实施例提供的显示面板包括发光二极管，该发光二极管可以是量子点发光二极管。量子点发光二极管中的量子点材料在光致发光的过程中，发射光线的半峰宽在30nm左右。因此量子点发光二极管具有近乎高斯对称的窄带发射特性，所以激发出的颜色的纯度更高，使得该显示面板获得较高的色域，如图3c所示，可以达到100％NTSC以上，进而使得该显示面板显示的画面色彩更加逼真。
基于上述发光二极管30的结构，以下对上述显示面板的具体结构进行详细说明。
例如，所述像素电路102包括薄膜晶体管，并且所述发光二极管 30的第一电极301可以与上述薄膜晶体管的漏极相连接，以实现发光二极管30与所述像素电路102电连接。
具体的，如图4-6所示，所述凹槽201的底部在对应所述薄膜晶体管的漏极的位置设置有第一过孔401，所述发光二极管的第一电极301通过所述第一过孔401与所述薄膜晶体管的漏极电连接。
在此情况下，上述像素界定层20的设置方式可以为：
例如，如图4所示，所述像素界定层20由覆盖所述像素电路102的钝化层130构成；所述凹槽201的深度小于所述钝化层130的厚度。在该实施例中，围堰202由钝化层130形成。
或者，又例如，如图5所示，所述像素界定层20由覆盖所述像素电路102的钝化层130和布置在所述钝化层130背离所述像素电路102的表面的光刻胶层131构成；所述凹槽201的深度小于所述光刻胶层131的厚度。在该实施例中，围堰202由光刻胶层131形成。
由上述可知，图4中钝化层130用作像素界定层20。而图5中钝化层130和光刻胶层131用作像素界定层20，从而可以省略单独制作像素界定层20的步骤，达到简化显示面板的制作工艺的目的。
具体的，如图6所示，所述像素界定层20由覆盖所述像素电路102的钝化层130和布置在所述钝化层130背离所述像素电路102的表面的光刻胶层131构成；所述凹槽201的深度等于所述光刻胶层131的厚度。在该实施例中，围堰202由光刻胶层131形成。
此外，该凹槽201的底部可以设置有像素电极50。也就是说，该像素电极50用作发光二极管30的第一电极301。
在此基础上，为了使得凹槽201内的薄膜层分布均匀，可选的，如图7a或7b所示，上述凹槽201内间隔设置有多个横跨所述凹槽201的挡墙203。通过上述挡墙203以及上述围堰202可以将该凹槽201所在的区域细分为多个由挡墙203围挡而成的封闭区B。在此情况下，当采用蒸镀或者喷墨打印等工艺等制作工艺，在上述凹槽201内形成发光层303时，可以通过上述挡墙203对该封闭区B内的成膜材料的进一步扩散趋势进行限制，减小由于上述扩散区域导致发光层303不均的问题。
基于此，上述挡墙203的排布方式，可以如图7a所示，任意两个挡墙203的延伸方向相同，且直接相邻的两个挡墙203之间的距离是 固定的。从而可以使得位于任意相邻两个封闭区B的薄膜层的均匀度相等或近似相等。
或者，如图7b所示，多个挡墙203包括横纵交叉的第一子挡墙2031和第二子挡墙2032。其中，第一子挡墙2031和第二子挡墙2032交叉界定多个呈矩阵形式排列的封闭区B。直接相邻的两个封闭区B的面积相等。从而可以使得位于任意相邻两个封闭区B的薄膜层的均匀度相等或近似相等。
此外，为了简化制作工艺，可选的上述挡墙203与像素界定层20同层同材料。在此情况下，上述挡墙203可以与像素界定层20为一体结构。
本公开实施例提供一种显示装置，包括如以上任意实施例所述的显示面板。该显示装置具有与前述实施例提供的显示面板相同的有益效果，此处不再赘述。
需要说明的是，该显示装置可以为显示器、电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
本公开实施例提供一种显示面板的制作方法，包括：通过构图工艺在衬底基板上形成多个像素，每个像素包括布置在所述衬底基板上的像素电路；形成覆盖所述像素电路的像素界定层；所述像素界定层背离所述像素电路的表面上设置有多个凹槽，所述多个凹槽与所述多个像素一一对应；以及在所述凹槽内，形成与所述像素电路电连接的发光二极管。
具体的，形成例如包括薄膜晶体管的像素电路可以包括以下步骤。
首先，在衬底基板01上，采用磁控溅射(Sputter)工艺制备形成一层金属层，例如该金属层由金属铜构成。然后采用曝光、显影、刻蚀工艺形成如图8a所示的栅极110以及栅线(G1、G2……)。
接下来，在形成有栅极110的衬底基板01上，采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)工艺形成栅极绝缘层111。其中，构成栅极绝缘层111的材料为氮化硅(SiN)。
接下来，以采用半导体透明导电材料构成有源层为例，对薄膜晶体管的有源层的制作方法进行说明。
具体的，如图8b所示，在上述栅极绝缘层111的表面涂覆有机溶 液，以形成有机薄膜1120。上述有机溶液的溶质可以包括ITZO(氧化铟锡锌)或ITWO(氧化铟钨锌)；该有机溶液的粘度为2～4cp。
然后，当上述有机薄膜1120在半固化状态下，如图8c所示，采用模具120对上述有机薄膜1120进行压合。
接下来，采用退火工艺和UV光照工艺在200～300℃的条件下，对有机薄膜1120的进行前烘(Pre-bake)1～2h。然后，在采用350℃，对有机薄膜1120的进行后烘(Hard-bake)1h，从而形成如图8d所示的有源层112，该有源层112的厚度为5nm左右。这样一来，在200～400℃进行烘干，可以使得有机溶液的热分解最完全，从而使得该有机薄膜1120中的有机污染物可完全经去除，以提高有源层112的纯度。具体的，上述退火工艺和UV光照工艺温度范围温度与薄膜晶体管载流子迁移率的关系如表1所示，此处不再赘述。
接下来，在形成有有源层112的衬底基板01上，通过磁控溅射工艺形成金属层，然后采用曝光、显影、刻蚀工艺形成如图8e所示的薄膜晶体管的源极113和漏极114。
此外，如图9所示，在制作完上述包括薄膜晶体管的像素电路以后，该显示面板的制作方法还包括：
S101、如图1所示，形成覆盖所述像素电路102的像素界定层20。
其中，该像素界定层20背离所述像素电路102的表面上设置有多个凹槽201。每个凹槽201四周布置有围堰202。所述多个凹槽201与所述多个像素101一一对应。
S102、在上述凹槽201内，形成与所述像素电路102电连接的发光二极管30。
上述显示面板的制作方法具有与前述实施例提供的显示面板相同的技术效果，此处不再赘述。
以下，对形成覆盖上述像素电路102的像素界定层20的步骤进行详细的举例说明。
例如，子步骤一，在形成有像素电路102的衬底基板01上，依次形成如图10a所示的钝化层130和光刻胶层131。其中，构成上述钝化层130的材料为PMMA(聚甲基丙烯酸甲酯)，该PMMA的介电常数ε＝3.2～3.5。
子步骤二，采用如图10b所示的半色调掩模板132(Gray-tone  Mask)，通过对光刻胶层131进行掩模曝光。其中，上述半色调掩模板132包括完全透光区域、完全遮光区域以及半透光区域。其中，以构成上述光刻胶层131为正胶为例，如图10c所示，光线透过完全透光区域的光刻胶层131能够完全溶解于显影液；光线透过半透光区域的光刻胶层131能够部分溶解于显影液；光线透过完全遮光区域的光刻胶层131不溶解于显影液。
子步骤三，对光刻胶层131进行显影，形成如图10d所示的结构。
子步骤四，在光刻胶完全显影的位置，采用刻蚀工艺完全去除构成钝化层130的材料，形成如图10e所示的第一过孔401。然后采用灰化工艺去除对应上述半透光区域的光刻胶，再采用刻蚀工艺形成凹槽201。其中，上述第一过孔401位于该凹槽201的底部，且上述第一过孔401与像素电路中用于驱动QLED的薄膜晶体管的漏极114相对应。
由上述可知，在钝化层130上形成凹槽201和位于该凹槽201底部的第一过孔401，因此该钝化层130可以共用为像素界定层20，从而无需单独制作像素界定层20，从而可以降低制作工艺的成本。
在此情况下，形成上述发光二极管30的方法包括：在凹槽201内形成如图4所示的第一电极301，该第一电极301通过第一过孔401与薄膜晶体管的漏极301电连接。
具体的，以发光二极管30为底发光式为例，可以通过磁控溅射工艺在上述凹槽内形成ITO或IZO薄膜，作为上述第一电极301。
上述发光二极管30的制造方法还包括：在第一电极301背离衬底基板01的一侧，通过构图工艺，在对应凹槽201的位置形成空穴传输层302。
具体的，在第一电极301的表面通过磁控溅射工艺形成金属层，该金属层可以由MoO3、NiO、CBP、TCTA等材料构成。然后，通过曝光、显影、刻蚀工艺对上述金属层进行构图，以形成空穴传输层302。
然后，在形成有上述空穴传输层302的衬底基板01上，通过喷墨打印工艺或蒸镀工艺，在对应凹槽201的位置形成发光层303。其中，构成上述发光层303的材料同上所述，此处不再赘述。
以喷墨打印工艺为例，对上述发光层303的制作过程进行说明。具体的，如图12a所示，将由纳米量子点化合物构成的量子点溶液501通过喷墨打印的方式，滴入凹槽201中的空穴传输层302表面。接下 来，如图12b所示，对上述量子点溶液501进行前烘。最后，如图12c所示，对上述量子点溶液501进行UV光照处理，从而形成上述发光层303。其中，经过上述前烘以及UV光照处理，可以去除上述量子点溶液501中的有机污染物，提高该发光层303的发光效率。
接下来，在形成有发光层303的衬底基板01上，通过构图工艺，在对应凹槽201的位置形成电子传输层304。其中，构成该电子传输层304的材料包括ZnO、TiO2、WO3和SnO2等。该电子传输层304的制备过程与空穴传输层302的制备工艺相同，此处不再赘述。
最后，在形成有电子传输层304的衬底基板01上，形成发光二极管30的第二电极305。其中，以发光二极管30为底发光式为例，构成该第二电极305的材料可以为金属铝。
需要说明的是，所有发光二极管30的第二电极305可以相互连接，在此情况下，在制作上述第二电极305时，可以采用磁控溅射工艺在形成有电子传输层304的衬底基板01上，形成一层金属层即可完成上述第二电极305的制备。
或者，当上述第二电极305如图4所示，位于该凹槽201内时，可以采用磁控溅射工艺在形成有电子传输层304的衬底基板01上，形成一层金属层；然后，通过掩模、曝光以及显影工艺对该金属层进行构图，从而形成上述第二电极305。
或者，又例如，形成上述像素界定层20可以包括以下子步骤。
子步骤一，在形成有薄膜晶体管的衬底基板01上，如图10a所示，依次形成钝化层130和光刻胶层131。
子步骤二、如图10b所示，采用半色调掩模板132，通过构图工艺在光刻胶层131上形成如图11a所示的凹槽201，并在凹槽201的底部，且对应与发光二极管电连接的薄膜晶体管漏极114所在的位置形成过孔401′。
子步骤三，如图11b所示，通过构图工艺，在所述凹槽201的底部形成贯穿所述光刻胶层131和所述钝化层130的第一过孔401。
需要说明的是，在本公开中，构图工艺，可指包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本公 开中所形成的结构选择相应的构图工艺。
其中，本公开实施例中的一次构图工艺，可以是通过一次掩模曝光工艺形成不同的曝光区域，然后对不同的曝光区域进行多次刻蚀、灰化等去除工艺最终得到预期图案。
在此基础上，形成上述发光二极管30第一电极的方法包括：如图5所示，在凹槽201内形成第一电极301，该第一电极301通过第一过孔401与上述薄膜晶体管的漏极电连接。
此外，制备上述发光二极管30中其他薄膜层的方法同上所述，此处不再赘述。
或者，再例如，形成上述像素界定层20可以包括以下子步骤。
子步骤一，如图13a所示，在形成有所述像素电路的衬底基板01上形成钝化层130，并通过构图工艺在钝化层130上形成第一过孔401。
子步骤二、如图13b所示，在形成有上述结构的衬底基板01上，形成透明导电层，并通过构图工艺形成第一电极301。该第一电极301通过第一过孔401与薄膜晶体管的漏极电连接。
子步骤三，如图13c所示，在形成有上述结构的衬底基板01上，形成绝缘材料层(例如，光刻胶层131)，并通过构图工艺在绝缘材料层上形成如图6所示的凹槽202。
综上所述，本公开实施例提供的显示面板包括发光二极管，该发光二极管可以是量子点发光二极管。量子点发光二极管中的量子点材料在光致发光的过程中，发射光线的半峰宽在30nm左右。因此量子点发光二极管具有近乎高斯对称的窄带发射特性，所以激发出的颜色的纯度更高，使得该显示面板获得较高的色域，可以达到100％NTSC以上，进而使得该显示面板显示的画面色彩更加逼真。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种显示面板，包括衬底基板和布置在所述衬底基板上的多个像素；
    其中，每个像素包括布置在所述衬底基板上的像素电路，所述显示面板还包括覆盖所述像素电路的像素界定层；所述像素界定层背离所述像素电路的表面上设置有多个凹槽；所述多个凹槽与所述多个像素一一对应；
    其中，每个凹槽内设置有与所述像素电路电连接的发光二极管。
  2. 根据权利要求1所述的显示面板，其中，每个凹槽在所述衬底基板上的正投影与对应像素中的发光区重叠。
  3. 根据权利要求1所述的显示面板，其中，所述像素界定层由覆盖所述像素电路的钝化层构成；所述凹槽的深度小于所述钝化层的厚度。
  4. 根据权利要求1所述的显示面板，其中，所述像素界定层由覆盖所述像素电路的钝化层和布置在所述钝化层背离所述像素电路的表面的光刻胶层构成；所述凹槽的深度小于或等于所述光刻胶层的厚度。
  5. 根据权利要求1-4任一项所述的显示面板，其中，所述像素电路包括薄膜晶体管，所述发光二极管与所述薄膜晶体管的漏极电连接。
  6. 根据权利要求5所述的显示面板，其中，所述凹槽的底部在对应所述薄膜晶体管的漏极的位置设置有第一过孔，所述发光二极管的第一电极通过所述第一过孔与所述薄膜晶体管的漏极电连接。
  7. 根据权利要求1-4任一项所述的显示面板，其中，所述凹槽内间隔设置有多个横跨所述凹槽的挡墙；所述挡墙与所述像素界定层同层同材料。
  8. 根据权利要求7所述的显示面板，其中，任意两个所述挡墙的延伸方向相同，且直接相邻的两个所述挡墙之间的距离是固定的。
  9. 根据权利要求7所述的显示面板，其中，多个所述挡墙包括横纵交叉的第一子挡墙和第二子挡墙；所述第一子挡墙和所述第二子挡墙交叉界定多个呈矩阵形式排列的封闭区；直接相邻的两个封闭区的面积相等。
  10. 根据权利要求1-4任一项所述的显示面板，其中，所述发光二 极管包括：依次位于所述第一电极背离所述像素电路一侧的空穴传输层、发光层、电子传输层以及第二电极；
    其中，所述第一电极由透明导电材料构成，所述第二电极由金属材料构成；或者，所述第一电极由金属材料构成，所述第二电极由透明导电材料构成。
  11. 根据权利要求10所述的显示面板，其中，所述发光二极管是量子点发光二极管，所述发光层的材料至少包括CdSe、CdS、CdTe、ZnSe、ZnTe、ZnS、HgTe、InAs、InP和GaAs中的任意一种。
  12. 根据权利要求5所述的显示面板，其中，构成所述薄膜晶体管有源层的材料包括氧化物半导体材料和低温多晶硅中至少一种。
  13. 一种显示装置，包括如权利要求1-12任一项所述的显示面板。
  14. 一种显示面板的制作方法，包括：
    通过构图工艺在衬底基板上形成多个像素，每个像素包括布置在所述衬底基板上的像素电路；
    形成覆盖所述像素电路的像素界定层；所述像素界定层背离所述像素电路的表面上设置有多个凹槽，所述多个凹槽与所述多个像素一一对应；以及
    在所述凹槽内，形成与所述像素电路电连接的发光二极管。
  15. 根据权利要求14所述的制作方法，其中，形成所述像素界定层的步骤包括：
    在形成有所述像素电路的衬底基板上，依次形成钝化层和光刻胶层；采用半色调掩模板，通过构图工艺在所述钝化层上形成所述凹槽；在所述凹槽的底部形成第一过孔；
    其中，形成所述发光二极管的步骤包括：
    在所述凹槽内形成第一电极，所述第一电极通过所述第一过孔与所述像素电路电连接。
  16. 根据权利要求14所述的制作方法，其中，形成所述像素界定层的步骤包括：
    在形成有所述像素电路的衬底基板上，依次形成钝化层和光刻胶层；采用半色调掩模板，通过构图工艺在所述光刻胶层上形成所述凹槽；在所述凹槽的底部形成贯穿所述光刻胶层和所述钝化层的第一过孔；
    其中，形成所述发光二极管的步骤包括：
    在所述凹槽内形成第一电极，所述第一电极通过所述第一过孔与所述像素电路电连接。
  17. 根据权利要求14所述的制作方法，其中，形成所述像素界定层的步骤包括：
    在形成有所述像素电路的衬底基板上形成钝化层，并通过构图工艺在所述钝化层上形成第一过孔；
    在所述衬底基板上形成透明导电层，并通过构图工艺形成所述第一电极；所述第一电极通过所述第一过孔与所述像素电路电连接；
    在所述衬底基板上形成绝缘材料层，并通过构图工艺在所述绝缘材料层上形成所述凹槽。
  18. 根据权利要求15-17任一项所述的制作方法，其中，形成所述发光二极管的步骤进一步包括：
    在所述第一电极背离所述衬底基板的一侧，通过构图工艺，在对应所述凹槽的位置形成空穴传输层；
    在形成有所述空穴传输层的衬底基板上，通过喷墨打印工艺或蒸镀工艺，在对应所述凹槽的位置形成发光层；
    在形成有所述发光层的衬底基板上，通过构图工艺，在对应所述凹槽的位置形成电子传输层；以及
    在形成有所述电子传输层的衬底基板上，形成所述发光二极管的第二电极。
PCT/CN2018/076371 2017-07-25 2018-02-12 显示面板及其制作方法、显示装置 WO2019019614A1 (zh)

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