WO2019028955A1 - 有机电致发光显示面板及其制作方法 - Google Patents

有机电致发光显示面板及其制作方法 Download PDF

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WO2019028955A1
WO2019028955A1 PCT/CN2017/100205 CN2017100205W WO2019028955A1 WO 2019028955 A1 WO2019028955 A1 WO 2019028955A1 CN 2017100205 W CN2017100205 W CN 2017100205W WO 2019028955 A1 WO2019028955 A1 WO 2019028955A1
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layer
disposed
bottom electrode
forming
display panel
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PCT/CN2017/100205
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French (fr)
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李松杉
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武汉华星光电半导体显示技术有限公司
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Priority to US15/578,117 priority Critical patent/US10546903B2/en
Publication of WO2019028955A1 publication Critical patent/WO2019028955A1/zh

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    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing

Definitions

  • the invention belongs to the technical field of organic electroluminescence display, and in particular to an organic electroluminescence display panel and a manufacturing method thereof.
  • OLED display panels have become very popular emerging flat display panel products at home and abroad, because OLED display panels have self-luminous, wide viewing angle, short reaction time, high luminous efficiency, Wide color gamut, thin thickness, large size and flexible display panel, and simple process, it also has the potential for low cost.
  • the pixel defining layer (PDL layer) obtained by the steps of coating, exposing, developing, baking, etc. of the organic photoresist may have a hydrophobic top surface and a hydrophilic side surface, so that When the subsequent organic electroluminescent device is fabricated, after the ink formed by each functional layer material is printed into the pixel defining layer, the intermediate thin edges of each functional layer appear thick, and finally the current flows through the edges of the functional layers. When the brightness of the light is not uniform.
  • an object of the present invention to provide an organic electroluminescence display panel capable of eliminating edge luminance unevenness of an organic electroluminescence device and a method of fabricating the same.
  • an organic electroluminescent display panel includes: a substrate; a thin film transistor disposed on the substrate; a bottom electrode disposed on a drain of the thin film transistor; a light shielding layer, Provided on the bottom electrode, the light shielding layer has a first via hole, the first via hole exposing the bottom electrode; a pixel defining layer disposed on the thin film transistor, the bottom electrode, and the light shielding layer a layer, the pixel defining layer has a second via, a diameter of the second via is larger than an aperture of the first via, and the second via completely exposes the first via; A light-emitting device is disposed on the bottom electrode; and a top electrode is disposed on the organic electroluminescent device.
  • a central axis of the second via hole coincides with a central axis of the first via hole.
  • the light shielding layer is made of an opaque and insulating silicon-rich oxide or silicon-rich nitride.
  • the pixel defining layer is made of polymethyl methacrylate or polyimide.
  • the thin film transistor includes: a polysilicon layer disposed on the substrate, the polysilicon layer including an undoped layer, a heavily doped layer respectively disposed on both sides of the undoped layer, and disposed on the a lightly doped layer between the heavily doped layer and the undoped layer; a gate insulating layer disposed on the polysilicon layer and the substrate; a gate disposed on the gate insulating layer and located The polysilicon layer; an interlayer insulating layer disposed on the gate and the gate insulating layer; a third via and a fourth via extending through the interlayer insulating layer and the gate respectively a layer; a source and a drain disposed on the interlayer insulating layer, wherein the source and the drain respectively pass through the first via and the second via and the corresponding heavily doped a layer contact; a planarization layer disposed on the interlayer insulating layer, the source and the drain; and a fifth via extending through the planarization layer to expose the drain.
  • the thin film transistor further includes a buffer layer disposed between the substrate and the polysilicon layer and the gate insulating layer.
  • the organic electroluminescent device sequentially includes a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, and an electron injection layer from the bottom electrode to the top electrode.
  • one of the bottom electrode and the top electrode is transparent or translucent, and the other is opaque and reflects light.
  • a method for fabricating an organic electroluminescence display panel includes the steps of: providing a substrate; forming a thin film transistor on the substrate; and forming a drain of the thin film transistor Forming a bottom electrode; forming a light shielding layer on the bottom electrode; forming a first via hole exposing the bottom electrode in the light shielding layer; and the thin film transistor, the bottom electrode, and the light shielding layer Forming a pixel defining layer; forming a second via hole in the pixel defining layer that completely exposes the first via hole, wherein a diameter of the second via hole is larger than an aperture of the first via hole; An organic electroluminescent device is formed on the bottom electrode; a top electrode is formed on the organic electroluminescent device.
  • the step of implementing the step of “forming a thin film transistor on the substrate” comprises: forming a buffer layer on the substrate; forming a polysilicon layer on the buffer layer; and the polysilicon layer includes an undoped layer a heavily doped layer disposed on both sides of the undoped layer and a lightly doped layer disposed between the heavily doped layer and the undoped layer; in the polysilicon layer and the buffer Forming a gate insulating layer on the layer; forming a gate on the polysilicon layer on the gate insulating layer; forming an interlayer insulating layer on the gate and the gate insulating layer; Forming a third via hole and a fourth via hole penetrating the interlayer insulating layer and the gate insulating layer in the interlayer insulating layer; forming a filling of the third via on the interlayer insulating layer a source having a hole in contact with the corresponding heavily doped layer and a drain filling the fourth via in contact with the corresponding heavily doped layer; in the
  • the invention has the beneficial effects that the invention blocks the edge of the organic electroluminescent device by using the light shielding layer, thereby improving the phenomenon that the brightness of the edge of the organic electroluminescent device is uneven.
  • FIG. 1 is a schematic structural view of an organic electroluminescence display panel according to an embodiment of the present invention.
  • FIGS. 2A through 2Q are process diagrams of an organic electroluminescent display panel in accordance with an embodiment of the present invention.
  • FIG. 1 is a schematic structural view of an organic electroluminescence display panel according to an embodiment of the present invention.
  • an organic electroluminescent display panel includes a substrate 100, a thin film transistor 200, a bottom electrode 300, a light shielding layer 400, a pixel defining layer 500, an organic electroluminescent device 600, and a top electrode 700.
  • the thin film transistor 200 includes a buffer layer 210, a polysilicon layer 220, a gate insulating layer 230, a gate 240, an interlayer insulating layer 250, a source 260, a drain 270, and a flat layer 280.
  • the structure of the thin film transistor of the present invention is not limited thereto, and it may be another type of thin film transistor such as an amorphous silicon thin film transistor or a metal oxide thin film transistor.
  • the substrate 100 may be, for example, a transparent glass substrate or a resin substrate, but the present invention is not limited thereto.
  • the buffer layer 210 is disposed on the substrate 100.
  • the buffer layer 210 may be, for example, a SiN x /SiO x structure, but the present invention is not limited thereto.
  • the buffer layer 210 may also be a single-layer SiN x structure or a SiO x structure.
  • the buffer layer 210 may not be present.
  • the polysilicon layer 220 is disposed on the buffer layer 200. Further, when the buffer layer 210 is not present, the polysilicon layer 220 is directly disposed on the substrate 100.
  • the polysilicon layer 220 includes an undoped layer 221, a heavily doped layer 223 disposed on both sides of the undoped layer 221, and a lightly doped layer 222 disposed between the heavily doped layer 223 and the undoped layer 221.
  • the lightly doped layer 222 is an N-type lightly doped layer
  • the heavily doped layer 223 is an N-type heavily doped layer.
  • the invention is not limited thereto, for example, the lightly doped layer 222 may also be a P-type lightly doped layer.
  • the hetero-layer, heavily doped layer 223 may also be a P-type heavily doped layer.
  • the gate insulating layer 230 is disposed on the polysilicon layer 220 and the buffer layer 210.
  • the gate insulating layer 230 may be, for example, a SiN x /SiO x structure, but the present invention is not limited thereto.
  • the gate insulating layer 230 may also be a single-layer SiN x structure or a SiO x structure.
  • the buffer layer 210 is not present, the gate insulating layer 230 is disposed on the polysilicon layer 220 and the substrate 100.
  • the gate 240 is disposed on the gate insulating layer 230, and the gate 240 is disposed on the polysilicon layer 220.
  • the gate 240 may be a MoAlMo structure or a TiAlTi structure, or may be A single layer of molybdenum structure or a single layer of aluminum structure, but the invention is not limited thereto.
  • the interlayer insulating layer 250 is disposed on the gate electrode 240 and the gate insulating layer 230.
  • the interlayer insulating layer 250 may be, for example, a SiN x /SiO x structure, but the present invention is not limited thereto.
  • the interlayer insulating layer 250 may also be a single-layer SiN x structure or a SiO x structure.
  • the third via 251 and the fourth via 252 are disposed in the interlayer insulating layer 250.
  • the third via 251 penetrates the gate insulating layer 230, and the fourth via 252 also penetrates the gate insulating layer 230 to respectively The heavily doped layer 223 is exposed.
  • the source 260 and the drain 270 are disposed on the interlayer insulating layer 250.
  • the source 260 fills the third via 251 to contact the corresponding heavily doped layer 223; the drain 270 fills the fourth via 252 to contact the corresponding heavily doped layer 223.
  • the source 260 and the drain 270 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • the flat layer 280 is disposed on the interlayer insulating layer 250, the source 260, and the drain 270.
  • the flat layer 280 has a fifth via 281 that exposes the drain 270.
  • the bottom electrode 300 is disposed on the flat layer 280, and the bottom electrode 300 fills the fifth via 281 to be in contact with the exposed drain 270.
  • the bottom electrode 300 is typically provided as an anode.
  • the bottom electrode 300 may be made of a reflective metal and should be thin enough to have a partial light transmittance at a wavelength of emitted light, which is said to be translucent, or the bottom electrode 300 may be made of a transparent metal oxide. Such as indium tin oxide or zinc tin oxide.
  • the patterned light shielding layer 400 is disposed on the bottom electrode 300.
  • the light shielding layer 400 has a first via hole 410 therein, and the first via hole 410 exposes the bottom electrode 300.
  • the patterned light shielding layer 400 may be made of, for example, an opaque and insulating silicon-rich oxide or silicon-rich nitride, but the invention is not limited thereto.
  • the silicon-rich oxide may be, for example, SiO x containing more silicon, and the ratio of SiH 4 :N 2 O is 1:10 when depositing the SiO x by CVD (Chemical Weather Precipitation) method, thereby containing more SiH 4 .
  • the silicon-rich nitride may be, for example, SiN x containing more silicon, and the ratio of SiH 4 :NH 3 used in deposition of SiN x by CVD (Chemical Weather Precipitation) is 1:8, thereby containing a large amount of SiH 4 .
  • the pixel defining layer 500 is disposed on the flat layer 280, the bottom electrode 300, and the light shielding layer 400.
  • Pixel limit The fixed layer 500 has a second via 510 having a larger aperture than the first via 410 and the second via 510 completely exposing the first via 410. Further, preferably, the central axis of the second via 510 coincides with the central axis of the first via 410.
  • the pixel defining layer 500 may be made of, for example, polymethyl methacrylate or polyimide, but the present invention is not limited thereto.
  • the organic electroluminescent device 600 is disposed on the exposed bottom electrode 300, and the edge of the organic electroluminescent device 600 is located on the light shielding layer 400.
  • the organic electroluminescent device 600 sequentially includes a hole injection layer (HIL) 610, a hole transport layer (HTL) 620, an organic light emitting layer (EML) 630, and electron transport from the bottom electrode 300 to the top electrode 700.
  • HIL hole injection layer
  • HTL hole transport layer
  • EML organic light emitting layer
  • the layer (ETL) 640 and the electron injection layer (EIL) 650 the organic electroluminescent device 600 of the present invention is not limited to the structure herein.
  • the top electrode 700 is disposed on the organic electroluminescent device 600.
  • the top electrode 700 is typically provided as a cathode.
  • the top electrode 700 is also a mirror.
  • the top electrode 700 can be made of a reflective metal and should be thick enough to be substantially opaque and to be a full mirror.
  • FIGS. 2A through 2Q are process diagrams of an organic electroluminescent display panel in accordance with an embodiment of the present invention.
  • Step 1 Referring to FIG. 2A, a substrate 100 is provided.
  • the substrate 100 may be, for example, a transparent glass substrate or a resin substrate, but the present invention is not limited thereto.
  • Step 2 Referring to FIG. 2B, a buffer layer 210 is formed on the substrate 100.
  • the buffer layer 210 may be, for example, a SiN x /SiO x structure, but the present invention is not limited thereto.
  • the buffer layer 210 may also be a single-layer SiN x structure or a SiO x structure.
  • step two may be omitted.
  • Step 3 Referring to FIG. 2C, a polysilicon layer 220 is formed on the buffer layer 210.
  • the polysilicon layer 220 is directly formed on the substrate 100.
  • the polysilicon layer 220 is formed by specifically forming an amorphous silicon layer on the buffer layer 210 by plasma enhanced chemical vapor deposition (PECVD); then, recrystallizing the amorphous silicon layer by using excimer laser A polysilicon layer 220 is formed.
  • the polysilicon layer 220 includes undoped The layer 221 is respectively disposed on the two sides of the undoped layer 221 and the lightly doped layer 222 disposed between the heavily doped layer 223 and the undoped layer 221 .
  • the lightly doped layer 222 is an N-type lightly doped layer
  • the heavily doped layer 223 is an N-type heavily doped layer.
  • the invention is not limited thereto, for example, the lightly doped layer 222 may also be a P-type lightly doped layer.
  • the hetero-layer, heavily doped layer 223 may also be a P-type heavily doped layer.
  • a gate insulating layer 230 is formed on the polysilicon layer 220 and the buffer layer 210.
  • the gate insulating layer 230 may be, for example, a SiN x /SiO x structure, but the present invention is not limited thereto.
  • the gate insulating layer 230 may also be a single-layer SiN x structure or a SiO x structure.
  • the gate insulating layer 230 is formed on the polysilicon layer 220 and the substrate 100.
  • Step 5 Referring to FIG. 2E, a gate 240 formed on the polysilicon layer 220 is formed on the gate insulating layer 230.
  • the gate electrode 240 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • an interlayer insulating layer 250 is formed on the gate electrode 240 and the gate insulating layer 230.
  • the interlayer insulating layer 250 may be, for example, a SiN x /SiO x structure, but the present invention is not limited thereto.
  • the interlayer insulating layer 250 may also be a single-layer SiN x structure or a SiO x structure.
  • Step 7 Referring to FIG. 2G, a third via 251 and a fourth via 252 are formed in the interlayer insulating layer 250 to form the interlayer insulating layer 250 and the gate insulating layer 230 to expose the heavily doped layer 223, respectively. .
  • Step 8 Referring to FIG. 2H, a source 260 and a filled fourth via 252 and a corresponding heavily doped layer 223 are formed on the interlayer insulating layer 250 to form a filled via 251 in contact with the corresponding heavily doped layer 223.
  • Contacted drain 270 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto. .
  • Step 9 Referring to FIG. 2I, a planarization layer 280 is formed on the interlayer insulating layer 250, the source 260, and the drain 270.
  • Step 10 Referring to FIG. 2J, a fifth via 281 is formed in the planarization layer 280, and the fifth via 281 exposes the drain 270.
  • the above steps 2 to 10 complete the fabrication of the thin film transistor 200 according to an embodiment of the present invention. process. It should be noted that the above steps of fabricating the thin film transistor are adaptively adjusted according to thin film transistors having different structures.
  • Step 11 Referring to FIG. 2K, a bottom electrode 300 is formed on the flat layer 280 to form a fifth via 281 to be in contact with the exposed drain 270.
  • the bottom electrode 300 is typically provided as an anode.
  • the bottom electrode 300 is transparent or translucent.
  • Step 12 Referring to FIG. 2L, a patterned light shielding layer 400 is formed on the bottom electrode 300.
  • the patterned light shielding layer 400 may be made of, for example, an opaque and insulating silicon-rich oxide or silicon-rich nitride, but the invention is not limited thereto.
  • Step 13 Referring to FIG. 2M, a first via 410 forming the exposed bottom electrode 300 is formed in the light shielding layer 400.
  • Step 14 Referring to FIG. 2N, a pixel defining layer 500 is formed on the flat layer 280, the bottom electrode 300, and the light shielding layer 400.
  • the pixel defining layer 500 may be made of, for example, polymethyl methacrylate or polyimide, but the present invention is not limited thereto.
  • Step 15 Referring to FIG. 2O, a second via 510 is formed in the pixel defining layer 500, the aperture of the second via 510 is larger than the aperture of the first via 410, and the second via 510 is completely exposed to the first Via 410. Further, preferably, the central axis of the second via 510 coincides with the central axis of the first via 410.
  • an organic electroluminescent device 600 is formed on the exposed bottom electrode 300 and the light shielding layer 400.
  • the organic electroluminescent device 600 sequentially includes a hole injection layer (HIL) 610, a hole transport layer (HTL) 620, an organic light emitting layer (EML) 630, and electron transport from the bottom electrode 300 to the top electrode 700.
  • Step 17 Referring to FIG. 2Q, a top electrode 700 is formed on the organic electroluminescent device 600.
  • the top electrode 700 is opaque and fully reflective.
  • the organic electroluminescent display panel and the manufacturing method thereof according to the embodiment of the present invention use the light shielding layer to block the edge of the organic electroluminescent device, thereby improving the phenomenon of uneven brightness of the edge of the organic electroluminescent device. .

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Abstract

提供了一种有机电致发光显示面板，其包括：基板（100）；薄膜晶体管（200），设置于所述基板（100）上；底电极（300），设置于所述薄膜晶体管（200）的漏极（270）上；遮光层（400），设置于所述底电极（300）上，所述遮光层（400）中具有第一过孔（410），所述第一过孔（410）暴露所述底电极（300）；像素限定层（500），设置于所述薄膜晶体管（200）、所述底电极（300）和所述遮光层（400）上，所述像素限定层（500）具有第二过孔（510），所述第二过孔（510）的孔径大于所述第一过孔（410）的孔径，且所述第二过孔（510）完全暴露所述第一过孔（410）；有机电致发光器件（600），设置于所述底电极（300）上；顶电极（700），设置于所述有机电致发光器件（600）上。还提供了一种有机电致发光显示面板的制作方法。利用遮光层（400）将有机电致发光器件（600）的边沿遮挡，从而改善有机电致发光器件（600）边沿发光亮度不均匀的现象。

Description

有机电致发光显示面板及其制作方法 技术领域
本发明属于有机电致发光显示技术领域，具体地讲，涉及一种有机电致发光显示面板及其制作方法。
背景技术
近年来，有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板成为国内外非常热门的新兴平面显示面板产品，这是因为OLED显示面板具有自发光、广视角、短反应时间、高发光效率、广色域、薄厚度、可制作大尺寸与可挠曲的显示面板及制程简单等特性，而且它还具有低成本的潜力。
目前，在现有的OLED显示面板中，通过有机光阻的涂布、曝光、显影、烘烤等工序得到的像素限定层(PDL层)会出现顶表面疏水而侧面亲水的状况，这样在后续的有机电致发光器件制作时，将由各功能层材料形成的墨水(ink)打印到像素限定层中之后，各功能层出现中间薄边沿厚的现象，最终导致电流流过各功能层的边沿时出现发光亮度不均匀的现象。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种能够消除有机电致发光器件的边沿发光亮度不均匀现象的有机电致发光显示面板及其制作方法。
根据本发明的一方面，提供了一种有机电致发光显示面板，其包括：基板；薄膜晶体管，设置于所述基板上；底电极，设置于所述薄膜晶体管的漏极上；遮光层，设置于所述底电极上，所述遮光层中具有第一过孔，所述第一过孔暴露所述底电极；像素限定层，设置于所述薄膜晶体管、所述底电极和所述遮光层上，所述像素限定层具有第二过孔，所述第二过孔的孔径大于所述第一过孔的孔径，且所述第二过孔完全暴露所述第一过孔；有机电致发光器件，设置于所述底电极上；顶电极，设置于所述有机电致发光器件上。
进一步地，所述第二过孔的中心轴与所述第一过孔的中心轴重合。
进一步地，所述遮光层由不透明的且绝缘的富硅氧化物或富硅氮化物制成。
进一步地，所述像素限定层由聚甲基丙烯酸甲酯或聚酰亚胺制成。
进一步地，所述薄膜晶体管包括：多晶硅层，设置于所述基板上，所述多晶硅层包括未掺杂层、分别设置于所述未掺杂层两侧的重掺杂层及设置于所述重掺杂层和所述未掺杂层之间的轻掺杂层；栅极绝缘层，设置于所述多晶硅层和所述基板上；栅极，设置于所述栅极绝缘层上且位于所述多晶硅层上；层间绝缘层，设置于所述栅极和所述栅极绝缘层上；第三过孔和第四过孔，分别贯穿所述层间绝缘层和所述栅极绝缘层；源极和漏极，设置于所述层间绝缘层上，所述源极和所述漏极分别通过所述第一过孔和所述第二过孔与对应的所述重掺杂层接触；平坦层，设置于所述层间绝缘层、所述源极和所述漏极上；第五过孔，贯穿所述平坦层，以将所述漏极暴露。
进一步地，所述薄膜晶体管还包括：缓冲层，设置于所述基板与所述多晶硅层和所述栅极绝缘层之间。
进一步地，所述有机电致发光器件从底电极到顶电极顺序包括：空穴注入层、空穴传输层、有机发光层、电子传输层及电子注入层。
进一步地，所述底电极和所述顶电极中的一个是透明的或半透明的，另一个是不透明的且反射光的。
根据本发明的另一方面，还提供了一种有机电致发光显示面板的制作方法，其包括步骤：提供一基板；在所述基板上制作形成薄膜晶体管；在所述薄膜晶体管的漏极上制作形成底电极；在所述底电极上制作形成遮光层；在所述遮光层中制作形成暴露所述底电极的第一过孔；在所述薄膜晶体管、所述底电极和所述遮光层上制作形成像素限定层；在所述像素限定层中制作形成完全暴露所述第一过孔的第二过孔，所述第二过孔的孔径大于所述第一过孔的孔径；在所述底电极上制作形成有机电致发光器件；在所述有机电致发光器件上制作形成顶电极。
进一步地，实现步骤“在所述基板上制作形成薄膜晶体管”的步骤包括：在所述基板上制作形成缓冲层；在所述缓冲层上制作形成多晶硅层；所述多晶硅层包括未掺杂层、分别设置于所述未掺杂层两侧的重掺杂层及设置于所述重掺杂层和所述未掺杂层之间的轻掺杂层；在所述多晶硅层和所述缓冲层上制作形成栅极绝缘层；在所述栅极绝缘层上制作形成位于所述多晶硅层上的栅极；在所述栅极和所述栅极绝缘层上制作形成层间绝缘层；在所述层间绝缘层中制作形成贯穿所述层间绝缘层和所述栅极绝缘层的第三过孔和第四过孔；在所述层间绝缘层上制作形成填充所述第三过孔与对应的所述重掺杂层接触的源极以及填充所述第四过孔与对应的所述重掺杂层接触的漏极；在所述层间绝缘层、所述源极和所述漏极上制作形成平坦层；在所述平坦层中制作形成将所述漏极暴露的第五过孔。
本发明的有益效果：本发明利用遮光层将有机电致发光器件的边沿遮挡，从而改善有机电致发光器件边沿发光亮度不均匀的现象。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的有机电致发光显示面板的结构示意图；
图2A至图2Q是根据本发明的实施例的有机电致发光显示面板的制程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚器件，夸大了层和区域的厚度。相同的标号在整个说明书和附图中表示相同的元器件。
将理解的是，当诸如层、膜、区域或基板的元件被称作“在”另一元件“上” 时，该元件可以直接在所述另一元件上，或者也可以存在中间元件。可选择地，当元件被称作“直接在”另一元件“上”时，不存在中间元件。
图1是根据本发明的实施例的有机电致发光显示面板的结构示意图。
参照图1，根据本发明的实施例的有机电致发光显示面板包括基板100、薄膜晶体管200、底电极300、遮光层400、像素限定层500、有机电致发光器件600和顶电极700。此外，作为本发明的一个实施例，薄膜晶体管200包括缓冲层210、多晶硅层220、栅极绝缘层230、栅极240、层间绝缘层250、源极260、漏极270、平坦层280，但本发明的薄膜晶体管的结构并不限于此，其还可以是非晶硅薄膜晶体管、金属氧化物薄膜晶体管等其他类型的薄膜晶体管。
具体而言，在本实施例中，基板100可例如是透明的玻璃基板或者树脂基板，但本发明并不限制于此。
缓冲层210设置于基板100上。缓冲层210可例如是SiNx/SiOx结构，但本发明并不限制于此，例如缓冲层210也可以是单层的SiNx结构或SiOx结构。作为本发明的另一实施方式，也可以不存在缓冲层210。
多晶硅层220设置于缓冲层200上。此外，当不存在缓冲层210上时，多晶硅层220直接设置于基板100上。多晶硅层220包括未掺杂层221、分别设置于未掺杂层221两侧的重掺杂层223及设置于重掺杂层223和未掺杂层221之间的轻掺杂层222。这里，轻掺杂层222为N型轻掺杂层，重掺杂层223为N型重掺杂层，单本发明并不限制于此，例如轻掺杂层222也可以为P型轻掺杂层，重掺杂层223也可以为P型重掺杂层。
栅极绝缘层230设置于多晶硅层220和缓冲层210上。这里，栅极绝缘层230可例如是SiNx/SiOx结构，但本发明并不限制于此，例如栅极绝缘层230也可以是单层的SiNx结构或SiOx结构。此外，当不存在缓冲层210上时，栅极绝缘层230设置于多晶硅层220和基板100上。
栅极240设置于栅极绝缘层230上，并且栅极240位于多晶硅层220上。栅极240可以是钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是 单层的钼结构或者单层的铝结构，但本发明并不限制于此。
层间绝缘层250设置于栅极240和栅极绝缘层230上。这里，层间绝缘层250可例如是SiNx/SiOx结构，但本发明并不限制于此，例如层间绝缘层250也可以是单层的SiNx结构或SiOx结构。
层间绝缘层250中设置有第三过孔251和第四过孔252，其中，第三过孔251贯穿栅极绝缘层230，第四过孔252亦贯穿栅极绝缘层230，以分别将重掺杂层223暴露。
源极260和漏极270设置于层间绝缘层250上。源极260填充第三过孔251以与对应的所述重掺杂层223接触；漏极270填充第四过孔252以与对应的所述重掺杂层223接触。源极260和漏极270可采用钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
平坦层280设置于层间绝缘层250、源极260和漏极270上。平坦层280中具有第五过孔281，该第五过孔281将漏极270暴露。
底电极300设置于平坦层280上，并且底电极300填充第五过孔281，以与暴露的漏极270接触。底电极300通常被设置为阳极。底电极300可以由反射性金属制成，并且应该足够薄以便在发射光的波长下具有部分透光率，这被称为是半透明的，或者底电极300可以由透明的金属氧化物制成，诸如氧化铟锡或氧化锌锡等。
图案化的遮光层400设置于底电极300上。遮光层400中具有第一过孔410，该第一过孔410暴露底电极300。在本实施例中，图案化的遮光层400可例如由不透明的且绝缘的富硅氧化物或富硅氮化物制成，但本发明并不限制于此。例如，富硅氧化物可例如是含硅较多的SiOx，在利用CVD(化学气象沉淀)法沉积该SiOx时使用SiH4：N2O的比例为1:10，从而含有较多的SiH4。富硅氮化物可例如是含硅较多的SiNx，在利用CVD(化学气象沉淀)法沉积SiNx时使用SiH4：NH3的比例为1:8，从而含有较多的SiH4。
像素限定层500设置于平坦层280、底电极300和遮光层400上。像素限 定层500中具有第二过孔510，该第二过孔510的孔径大于第一过孔410的孔径，且该第二过孔510完全暴露第一过孔410。进一步地，优选地，第二过孔510的中心轴与第一过孔410的中心轴重合。像素限定层500可例如是由聚甲基丙烯酸甲酯或聚酰亚胺制成，但本发明并不限制于此。
有机电致发光器件600设置于暴露的底电极300上，且有机电致发光器件600的边沿位于遮光层400上。在本实施例中，有机电致发光器件600从底电极300到顶电极700顺序包括：空穴注入层(HIL)610、空穴传输层(HTL)620、有机发光层(EML)630、电子传输层(ETL)640以及电子注入层(EIL)650；但本发明的有机电致发光器件600并不限制于这里的结构。
顶电极700设置于有机电致发光器件600上。顶电极700通常被设置为阴极。顶电极700也是反光镜。顶电极700可以由反射性金属制成，并且应该足够厚，以使其基本上是不透光的且是全反光镜。
以下将对根据本发明的实施例的有机电致发光显示面板的制作过程进行详细描述。
图2A至图2Q是根据本发明的实施例的有机电致发光显示面板的制程图。
根据本发明的实施例的有机电致发光显示面板的制作方法包括：
步骤一：参照图2A，提供一基板100。这里，基板100可例如是透明的玻璃基板或者树脂基板，但本发明并不限制于此。
步骤二：参照图2B，在基板100上制作形成缓冲层210。缓冲层210可例如是SiNx/SiOx结构，但本发明并不限制于此，例如缓冲层210也可以是单层的SiNx结构或SiOx结构。此外，作为本发明的另一实施方式，步骤二可以被省略。
步骤三：参照图2C，在缓冲层210上制作形成多晶硅层220。作为本发明的另一实施方式，当步骤二被省略时，在基板100上直接制作形成多晶硅层220。多晶硅层220的形成方式具体为：利用等离子体增强化学气相沉积法(PECVD)在缓冲层210上制作形成非晶硅层；接着，以利用准分子镭射使所述非晶硅层再结晶，从而生成多晶硅层220。此外，多晶硅层220包括未掺杂 层221、分别设置于未掺杂层221两侧的重掺杂层223及设置于重掺杂层223和未掺杂层221之间的轻掺杂层222。这里，轻掺杂层222为N型轻掺杂层，重掺杂层223为N型重掺杂层，单本发明并不限制于此，例如轻掺杂层222也可以为P型轻掺杂层，重掺杂层223也可以为P型重掺杂层。
步骤四：参照图2D，在多晶硅层220和缓冲层210上制作形成栅极绝缘层230。这里，栅极绝缘层230可例如是SiNx/SiOx结构，但本发明并不限制于此，例如栅极绝缘层230也可以是单层的SiNx结构或SiOx结构。当步骤二被省略时，在多晶硅层220和基板100上制作形成栅极绝缘层230。
步骤五：参照图2E，在栅极绝缘层230上制作形成位于多晶硅层220上的栅极240。这里，栅极240可以是钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
步骤六：参照图2F，在栅极240和栅极绝缘层230上制作形成层间绝缘层250。这里，层间绝缘层250可例如是SiNx/SiOx结构，但本发明并不限制于此，例如层间绝缘层250也可以是单层的SiNx结构或SiOx结构。
步骤七：参照图2G，在层间绝缘层250中制作形成贯穿层间绝缘层250和栅极绝缘层230的第三过孔251和第四过孔252，以分别将重掺杂层223暴露。
步骤八：参照图2H，在层间绝缘层250上制作形成填充第三过孔251与对应的重掺杂层223接触的源极260和填充第四过孔252与对应的重掺杂层223接触的漏极270。这里，源极260和漏极270可采用钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
步骤九：参照图2I，在层间绝缘层250、源极260和漏极270上制作形成平坦层280。
步骤十：参照图2J，在平坦层280中制作形成第五过孔281，该第五过孔281将漏极270暴露。
上述步骤二至步骤十完成了根据本发明的实施例的薄膜晶体管200的制作 过程。需要说明的是，上述制作薄膜晶体管的步骤根据不同结构的薄膜晶体管而被适应性调整。
步骤十一：参照图2K，在平坦层280上制作形成填充第五过孔281而与暴露的漏极270接触的底电极300。底电极300通常被设置为阳极。底电极300是透明的或者半透明的。
步骤十二：参照图2L，在底电极300上制作形成图案化的遮光层400。这里，图案化的遮光层400可例如由不透明的且绝缘的富硅氧化物或富硅氮化物制成，但本发明并不限制于此。
步骤十三：参照图2M，在遮光层400中制作形成暴露底电极300的第一过孔410。
步骤十四：参照图2N，在平坦层280、底电极300和遮光层400上形成像素限定层500。像素限定层500可例如是由聚甲基丙烯酸甲酯或聚酰亚胺制成，但本发明并不限制于此。
步骤十五：参照图2O，在像素限定层500中制作形成第二过孔510，该第二过孔510的孔径大于第一过孔410的孔径，且该第二过孔510完全暴露第一过孔410。进一步地，优选地，第二过孔510的中心轴与第一过孔410的中心轴重合。
步骤十六：参照图2P，在暴露的底电极300和遮光层400上制作形成有机电致发光器件600。在本实施例中，有机电致发光器件600从底电极300到顶电极700顺序包括：空穴注入层(HIL)610、空穴传输层(HTL)620、有机发光层(EML)630、电子传输层(ETL)640以及电子注入层(EIL)650；但本发明的有机电致发光器件600并不限制于这里的结构。
步骤十七：参照图2Q，在有机电致发光器件600上制作形成顶电极700。这里，顶电极700是不透光的且是全反光的。
综上所述，根据本发明的实施例有机电致发光显示面板及其制作方法，利用遮光层将有机电致发光器件的边沿遮挡，从而改善有机电致发光器件边沿发光亮度不均匀的现象工。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (12)

  1. 一种有机电致发光显示面板，其中，包括：
    基板；
    薄膜晶体管，设置于所述基板上；
    底电极，设置于所述薄膜晶体管的漏极上；
    遮光层，设置于所述底电极上，所述遮光层中具有第一过孔，所述第一过孔暴露所述底电极；
    像素限定层，设置于所述薄膜晶体管、所述底电极和所述遮光层上，所述像素限定层具有第二过孔，所述第二过孔的孔径大于所述第一过孔的孔径，且所述第二过孔完全暴露所述第一过孔；
    有机电致发光器件，设置于所述底电极上，所述有机电致发光器件的边沿设置于所述遮光层上；
    顶电极，设置于所述有机电致发光器件上。
  2. 根据权利要求1所述的有机电致发光显示面板，其中，所述第二过孔的中心轴与所述第一过孔的中心轴重合。
  3. 根据权利要求1所述的有机电致发光显示面板，其中，所述遮光层由不透明的且绝缘的富硅氧化物或富硅氮化物制成。
  4. 根据权利要求1所述的有机电致发光显示面板，其中，所述像素限定层由聚甲基丙烯酸甲酯或聚酰亚胺制成。
  5. 根据权利要求1所述的有机电致发光显示面板，其中，所述薄膜晶体管包括：
    多晶硅层，设置于所述基板上，所述多晶硅层包括未掺杂层、分别设置于所述未掺杂层两侧的重掺杂层及设置于所述重掺杂层和所述未掺杂层之间的 轻掺杂层；
    栅极绝缘层，设置于所述多晶硅层和所述基板上；
    栅极，设置于所述栅极绝缘层上且位于所述多晶硅层上；
    层间绝缘层，设置于所述栅极和所述栅极绝缘层上；
    第三过孔和第四过孔，分别贯穿所述层间绝缘层和所述栅极绝缘层；
    源极和漏极，设置于所述层间绝缘层上，所述源极和所述漏极分别通过所述第一过孔和所述第二过孔与对应的所述重掺杂层接触；
    平坦层，设置于所述层间绝缘层、所述源极和所述漏极上；
    第五过孔，贯穿所述平坦层，以将所述漏极暴露。
  6. 根据权利要求5所述的有机电致发光显示面板，其中，所述薄膜晶体管还包括：缓冲层，设置于所述基板与所述多晶硅层和所述栅极绝缘层之间。
  7. 根据权利要求1所述的有机电致发光显示面板，其中，所述有机电致发光器件从底电极到顶电极顺序包括：空穴注入层、空穴传输层、有机发光层、电子传输层及电子注入层。
  8. 根据权利要求5所述的有机电致发光显示面板，其中，所述有机电致发光器件从底电极到顶电极顺序包括：空穴注入层、空穴传输层、有机发光层、电子传输层及电子注入层。
  9. 根据权利要求6所述的有机电致发光显示面板，其中，所述有机电致发光器件从底电极到顶电极顺序包括：空穴注入层、空穴传输层、有机发光层、电子传输层及电子注入层。
  10. 根据权利要求1所述的有机电致发光显示面板，其中，所述底电极是透明的或半透明的，所述顶电极是不透明的且反射光的。
  11. 一种有机电致发光显示面板的制作方法，其中，包括步骤：
    提供一基板；
    在所述基板上制作形成薄膜晶体管；
    在所述薄膜晶体管的漏极上制作形成底电极；
    在所述底电极上制作形成遮光层；
    在所述遮光层中制作形成暴露所述底电极的第一过孔；
    在所述薄膜晶体管、所述底电极和所述遮光层上制作形成像素限定层；
    在所述像素限定层中制作形成完全暴露所述第一过孔的第二过孔，所述第二过孔的孔径大于所述第一过孔的孔径；
    在所述底电极和所述遮光层上制作形成有机电致发光器件，以使所述有机电致发光器件的边沿位于所述遮光层上；
    在所述有机电致发光器件上制作形成顶电极。
  12. 根据权利要求11所述的有机电致发光显示面板，其中，实现步骤“在所述基板上制作形成薄膜晶体管”的步骤包括：
    在所述基板上制作形成缓冲层；
    在所述缓冲层上制作形成多晶硅层；所述多晶硅层包括未掺杂层、分别设置于所述未掺杂层两侧的重掺杂层及设置于所述重掺杂层和所述未掺杂层之间的轻掺杂层；
    在所述多晶硅层和所述缓冲层上制作形成栅极绝缘层；
    在所述栅极绝缘层上制作形成位于所述多晶硅层上的栅极；
    在所述栅极和所述栅极绝缘层上制作形成层间绝缘层；
    在所述层间绝缘层中制作形成贯穿所述层间绝缘层和所述栅极绝缘层的第三过孔和第四过孔；
    在所述层间绝缘层上制作形成填充所述第三过孔与对应的所述重掺杂层接触的源极以及填充所述第四过孔与对应的所述重掺杂层接触的漏极；
    在所述层间绝缘层、所述源极和所述漏极上制作形成平坦层；
    在所述平坦层中制作形成将所述漏极暴露的第五过孔。
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