WO2014205892A1 - 像素单元、阵列基板及其制造、修复方法和显示装置 - Google Patents

像素单元、阵列基板及其制造、修复方法和显示装置 Download PDF

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Publication number
WO2014205892A1
WO2014205892A1 PCT/CN2013/081301 CN2013081301W WO2014205892A1 WO 2014205892 A1 WO2014205892 A1 WO 2014205892A1 CN 2013081301 W CN2013081301 W CN 2013081301W WO 2014205892 A1 WO2014205892 A1 WO 2014205892A1
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Prior art keywords
film transistor
thin film
line
isolated
repair
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PCT/CN2013/081301
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English (en)
French (fr)
Inventor
姚之晓
刘家荣
林鸿涛
王章涛
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/346,036 priority Critical patent/US9366926B2/en
Publication of WO2014205892A1 publication Critical patent/WO2014205892A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136268—Switch defects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/10—Dealing with defective pixels

Definitions

  • the present invention relates to the field of display, and in particular, to a pixel unit, an array substrate, and a manufacturing, repairing, and display device therefor.
  • Thin film transistor liquid crystal display (TFT-L €D) is mainly formed by aligning the array substrate and the color filter substrate into a liquid crystal, and a thin film transistor is disposed on the array substrate (Thin Film Transistor, TFT), a color filter is disposed on the color filter substrate, and a signal and a voltage change applied to each pixel are controlled by the thin film transistor to control the rotation direction of the liquid crystal molecules, thereby controlling whether the polarized light of each pixel is emitted or not Display purpose.
  • TFT Thin film transistor liquid crystal display
  • the standby thin film transistor In the process of manufacturing the array substrate, various defects such as thin film transistor damage may not work properly due to the limitation of the process conditions.
  • the standby thin film transistor In order to improve the yield, the standby thin film transistor is generally required to be formed on the array substrate at the same time, when the thin film transistor is not working normally, The post-repair is used to make the standby thin film transistor a working thin film transistor, controlling the signal and voltage changes applied to the pixel.
  • the existing repairable array substrate is shown in FIG. i, and the working thin film transistor and the spare thin film transistor are formed on the same gate metal layer 21.
  • the metal layer is deposited by the CVD method to form the first connecting bridge 12 and the first
  • the second connection bridge 13 connects the source 33 of the standby thin film transistor to the data line 31 by laser puncturing, and the drain 32 of the standby thin film transistor is connected to the pixel electrode 11, but obviously, this design makes the repair limited to the array process ( In the array stage), the damage of the thin film transistor after the array process cannot be repaired, and the repair process is complicated, and the implementation process is long.
  • Embodiments of the present invention provide a pixel unit, an array substrate, a manufacturing method thereof, a repairing method, and a display device, which solve the problem that the repair of the damage of the conventional thin film transistor is limited to the array process, and the thin film transistor after the array process cannot be repaired, and Can also reduce the electricity caused by the backup thin film transistor Capacity, product performance is guaranteed, product repair rate and product yield are improved.
  • a pixel unit comprising: a pixel electrode, a data line, and a thin film transistor, further comprising: a standby thin film transistor disposed adjacent to the thin film transistor for replacing the thin film transistor when the thin film transistor is damaged, a source of the standby thin film transistor is isolated from the data line, and a drain of the standby thin film transistor is isolated from the pixel electrode;
  • a first repair line one end of which is isolated from the source of the standby thin film transistor and has an overlapping region; the other end is isolated from the data line or the source of the thin film transistor and has an overlapping region;
  • the second repair line has one end separated from the drain of the standby thin film transistor and has an overlapping region; the other end is isolated from the drain of the pixel electrode or the thin film transistor and has an overlapping region.
  • the first repair line and/or the second repair line are disposed in the same layer as the gate of the thin film transistor.
  • the first repair line and/or the second repair line are disposed in the same layer as the pixel electrode.
  • the pixel unit further includes: a common electrode,
  • the first repair line and/or the second repair line are disposed in the same layer as the common electrode.
  • the pixel unit further includes: a gate line;
  • the thin film transistor and the standby thin film transistor are located at intersections of the gate line and the data line, and the thin film transistor and the standby thin film transistor are disposed on the same gate line.
  • the gate of the standby thin film transistor is disposed in the same layer as the gate of the thin film transistor;
  • the semiconductor layer of the standby thin film transistor is disposed in the same layer as the semiconductor layer of the thin film transistor;
  • the source and drain of the standby thin film transistor are disposed in the same layer as the source and drain of the thin film transistor.
  • the present invention also provides an array substrate comprising a plurality of pixel units, the pixel m-element comprising: a pixel electrode, a data line, and a thin film transistor for loading a display signal of the data line onto the pixel electrode, further comprising: Provided next to the thin film transistor, a thin film transistor for replacing the operation of the thin film transistor when the thin film transistor is damaged, the source of the standby thin film transistor is isolated from the data line, the standby thin film transistor The drain is isolated from the pixel electrode;
  • a first repair line one end of which is isolated from the source of the standby thin film transistor and has an overlapping region; the other end is isolated from the data line or the source of the thin film transistor and has an overlapping region;
  • the second repair line has one end isolated from the drain of the standby thin film transistor and has an overlapping region; the other end is isolated from the pixel electrode or the drain of the thin film transistor and has an overlapping region.
  • the first repair line and/or the second repair line are disposed in the same layer as the gate of the thin film transistor.
  • the first repair line and/or the second repair line are disposed in the same layer as the pixel electrode.
  • the pixel unit further includes: a common electrode,
  • the first repair line and/or the second repair line are disposed in the same layer as the common electrode.
  • the pixel unit on the array substrate further includes: a gate line;
  • the thin film transistor, the standby thin film transistor and the transparent pixel electrode are located at an intersection of the gate line and the data line, and the thin film transistor and the thin film transistor are disposed in the same.
  • the present invention further provides a display device
  • the invention includes the array substrate according to any one of the preceding claims.
  • the present invention provides a method of fabricating an array substrate, including:
  • a gate metal layer on the substrate Forming a gate metal layer on the substrate, forming a gate line, a gate of the thin film transistor, a gate of the standby thin film transistor, a first repair line, and a second repair line by a patterning process;
  • the source of the standby thin film transistor is isolated from the other end of the first repair line and has an overlap region, and the drain of the standby thin film transistor is isolated from the other end of the second repair line and has a heavy Stacked area
  • a transparent conductive layer is formed on the substrate on which the passivation layer is formed, and a pixel electrode is formed by a patterning process.
  • the present invention also provides a method for repairing an array substrate for repairing when a thin film transistor is damaged, and the repair method includes:
  • Laser cutting is performed to disconnect the source of the damaged thin film transistor from the data line, and the drain of the damaged thin film transistor is disconnected from the pixel electrode;
  • the overlapping area of the second repair line and the drain of the pixel electrode or the thin film transistor is laser-welded, the source of the standby thin film transistor is connected to the data line, and the drain of the standby thin film transistor is connected to the pixel electrode.
  • the pixel unit, the array substrate, the manufacturing method thereof, the repairing method and the display device provided by the invention are provided with an isolated standby thin film transistor, and when the thin film transistor is damaged and cannot work normally, the laser thin film transistor is used to stop the damaged thin film transistor, and then the method is adopted.
  • the laser welding method connects the source of the standby thin film transistor to the data line, and the drain is connected to the pixel electrode, thereby allowing the standby thin film transistor to operate in place of the damaged thin film transistor.
  • the repairing method of the present invention is not limited to the array process. For the thin film transistor detected after the array substrate and the counter substrate are damaged, the laser cutting and laser welding can be performed from the non-faceted side of the array substrate. The product repair rate and product yield are improved.
  • FIG. 2 is a schematic structural diagram of a pixel unit according to Embodiment 1 of the present invention
  • FIG. 3 is a schematic structural diagram of another pixel unit according to Embodiment 1 of the present invention
  • FIG. 4 is a schematic structural diagram of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 5 is a schematic diagram of a front panel array substrate thin film transistor according to a third embodiment of the present invention.
  • FIG. 6 is a method for repairing a thin film transistor of a rear-array substrate according to a third embodiment of the present invention
  • FIG. 7 is a flow chart of a method for manufacturing an array substrate according to Embodiment 4 of the present invention.
  • FIG. 8(a) to 8(d) are schematic views showing the manufacturing process of the array substrate provided in the fourth embodiment; and Fig. 9 is a schematic cross-sectional view along the A-B direction in Fig. 8(d).
  • drain of 32 spare thin film transistor drain of 33-spare thin film transistor : drain of 22-thin film transistor, source of 23-thin film transistor, 20-thin film transistor,
  • the pixel unit includes: a pixel electrode 11, a data line 31, and a thin film transistor 20 for loading a display signal of the data line 31 onto the pixel electrode 11. Also includes:
  • the standby thin film transistor 30 for replacing the operation of the thin film transistor 20 when the thin film transistor 20 is damaged, the source 33 and the data line of the standby thin film transistor 30 31 is isolated, the drain 32 of the standby thin film transistor 30 is isolated from the pixel electrode ii;
  • the first repair line 43 has one end separated from the source 33 of the standby thin film transistor 30 and has an overlapping region; the other end is isolated from the source 23 (or the data line 31) of the thin film transistor 20 and overlaps the second repair line 42.
  • One end is isolated from the drain 32 of the standby thin film transistor 30 and has an overlapping region; the other end is isolated from the drain 22 (or the pixel electrode 11) of the thin film transistor 20 and has an overlapping region.
  • the standby thin film transistor 30 in this embodiment remains isolated, that is, the source 33 of the standby thin film transistor 30 is isolated from the data line 31, the drain 32 is isolated from the pixel electrode 11, and the standby thin film transistor 30 before repair is not in the Working state; after repair, the damaged thin film transistor is also isolated and not in operation, so the presence of the standby thin film transistor 30 does not affect the display performance of the product.
  • the pixel unit preferably further includes: a gate line 41; the thin film transistor 20 and the spare thin film transistor 30 are located at intersections of the gate line 41 and the data line 31, and the thin film transistor 20 and the standby thin film transistor 30 are disposed on the same gate.
  • the first repair line 43 and the second repair line 42 of the thin film transistor 20 and the backup thin film transistor 30 are parallel to the gate line 4!, and both ends of the first repair line 43 and the source 23 of the thin film transistor 20 are respectively reserved.
  • the source 33 of the thin film transistor 30 is isolated and has an overlapping region.
  • the two ends of the second repair line 42 are respectively separated from the drain 22 of the thin film transistor 20 and the drain 32 of the standby thin film transistor 30, and there is an overlapping region, wherein There is an overlap area, which means that the two are disposed in different layers, and there is a crossover area, and "isolation" means that there is no contact between the two, and of course there is no electrical connection. If the laser welding method is used in the crossover area, the two can be electrically connected.
  • the first repair line 43 and the second repair line 42 are disposed on the gate layer of the thin film transistor 20, and the gate metal layer is formed in addition to the gate line, the drain of the thin film transistor 20, and the gate of the thin film transistor 30.
  • a repair line 43 and a second repair line 42 are disposed on the gate layer of the thin film transistor 20, and the gate metal layer is formed in addition to the gate line, the drain of the thin film transistor 20, and the gate of the thin film transistor 30.
  • a repair line 43 and a second repair line 42 are disposed on the gate layer of the thin film transistor 20, and the gate metal layer is formed in addition to the gate line, the drain of the thin film transistor 20, and the gate of the thin film transistor 30.
  • the first repair line 43 and the second repair line 42 may be disposed in parallel with the gate line 41, and one end of the first repair line 43 is disposed on the thin film crystal via an insulating layer Below (or above) the source 23 of the tube, the other end is disposed below (or above) the source 33 of the standby thin film transistor via the gate insulating layer; one end of the second repair line 42 is disposed on the thin film via the gate insulating layer
  • the lower side (or upper side) of the drain 22 of the transistor is disposed below (or above) the drain 32 of the standby thin film transistor with the gate insulating layer interposed therebetween.
  • one end of the first repairing line 43 is disposed under the data line 31 (or above) via a gate insulating layer, and the other end is disposed at the source 33 of the standby thin film transistor via a gate insulating layer.
  • One end of the second repairing line 43 may be disposed under (or above) the pixel electrode 1 1 via a gate insulating layer, and the other end may be disposed below (or above) the drain 32 of the standby thin film transistor via a gate insulating layer.
  • the first repair line 43 and/or the second repair line 42 may also be disposed as a transparent conductive layer, that is, the first repair line 43 and/or the second repair line 42 may also be combined with the pixel electrode 11 or the common
  • the electrodes are disposed in the same layer, except that the line widths of the first repair line 43 and the second repair line 42 are designed to take into account the transparent conductive layer and the metal film layer (the first repair line 43 and the second repair line 42 are disposed on the gate metal). There is a difference in the resistivity of the layer), which avoids the display effect due to the difference in resistance after repair.
  • the gate of the standby thin film transistor 30 is disposed in the same layer as the gate of the thin film transistor 20; the semiconductor layer of the standby thin film transistor 30 is disposed in the same layer as the semiconductor layer of the thin film transistor 20; the source and drain of the standby thin film transistor 30 are The source and drain of the thin film transistor 20 are disposed in the same layer.
  • the standby thin film transistor 30 can be formed in synchronization with the thin film transistor 20.
  • the thin film transistor 20 and the backup thin film transistor 30 may be a bottom gate structure or a top gate structure. However, in order to facilitate repair from the back surface of the array substrate (on the side opposite to the surface of the substrate), it is preferable to use the method shown in FIG. Bottom gate structure.
  • the pixel unit provided by the invention is provided with an isolated spare thin film transistor.
  • the damaged thin film transistor is stopped by laser cutting, and the source and the data line of the standby thin film transistor are made by the ffi laser welding method.
  • the drain is connected to the pixel electrode, thereby allowing the standby thin film transistor to operate in place of the damaged thin film transistor.
  • the laser cutting and laser splicing can be performed from the non-faceted side of the array substrate, which is not limited to the array process, thereby improving the product repair. Rate and Product yield, and the spare thin-film transistor is isolated and not in operation before repair.
  • the damaged thin-film transistor is also isolated and not in operation. Therefore, it can avoid the extra capacitance generated by setting the standby thin film transistor. , to ensure the display performance of the product.
  • the present invention also provides an array substrate, as shown in FIG. 4, and referring to FIG. 2, the array substrate includes a plurality of pixel units.
  • the pixel unit includes: a pixel electrode I data line 31 and
  • the thin film transistor 20 for loading the display signal of the data line 31 onto the pixel electrode 11 further includes: a standby thin film transistor 30 disposed beside the thin film transistor 20 for replacing the operation of the thin film transistor 20 when the thin film transistor 20 is damaged,
  • the source 33 of the standby thin film transistor 30 is isolated from the data line 31, and the drain 32 of the standby thin film transistor 30 is isolated from the pixel electrode 11;
  • the first repair line 43 has one end separated from the source 33 of the thin film transistor 30 and overlapped.
  • the other end is isolated from the source 23 (or the data line 31) of the thin film transistor 20 and has an overlapping region; the second repair line 42 has one end separated from the drain 32 of the standby thin film transistor 30 and has an overlapping region;
  • the drain 22 (or the pixel electrode 11) of the thin film transistor 20 is isolated and has an overlap region.
  • the first repair line 43 and/or the second repair line 42 are disposed in the same layer as the gate of the thin film transistor 20.
  • the second selection repair line 43 and/or the second repair line 42 may also be disposed in the same layer as the pixel electrode 11 or the common electrode.
  • the pixel unit on the array substrate further includes: a gate line 41; the thin film transistor 20, the standby thin film transistor 30 is located at an intersection of the gate line 41 and the data line 3!, and the thin film transistor 20 and the standby thin film transistor 30 are disposed on the same gate line 41.
  • the source and the drain of the ffi thin film transistor 30 are disposed in the same layer as the source and drain of the thin film transistor 20.
  • the thin film transistor 20 and the backup thin film transistor 30 may be a bottom gate structure or a top» structure, but in order to facilitate repair from the back surface of the array substrate (non-face side)
  • the bottom gate structure shown in Fig. 2 is preferably employed.
  • the array substrate provided by the present invention is provided with an isolated standby thin film transistor for each pixel unit.
  • the source of the standby thin film transistor is connected to the data line, and the drain is connected to the pixel electrode, thereby
  • the thin film transistor works in place of the damaged thin film transistor.
  • the laser cutting and laser splicing can be performed from the non-faceted side of the array substrate, which is not limited to the array process, thereby improving the product repair. Rate and product yield, and, before repair, the spare thin film transistor is isolated. After the thin film transistor is damaged, it is repaired to make the standby thin film transistor in operation, and the damaged thin film transistor is turned off and stopped.
  • the embodiment of the invention further provides a display device comprising any of the above array substrates.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component.
  • the present invention further provides a method for repairing an array substrate, which is used for repairing damage of a thin film transistor, and the repair method includes:
  • Step 1 Laser cutting is performed along cutting marks A1 and A2 shown by broken lines in FIGS. 5 and 6, so that the source 23 of the damaged thin film transistor 20 is disconnected from the data line 31, and the drain 22 and the pixel of the damaged thin film transistor are The electrode 11 is turned off, and the damaged thin film transistor 20 is stopped.
  • Step 2 an overlapping area of the first repair line 43 and the source 33 of the standby thin film transistor, an overlap area of the first repair line 43 and the source 23 (or the data line 31) of the thin film transistor, the second repair line 42 and the spare
  • the overlapping area of the drain electrode 32 of the thin film transistor and the overlapping area of the second repair line 42 and the drain electrode 32 (or the pixel electrode 11) of the thin film transistor are laser-bonded, as shown in FIG. 5, the splicing marks B4, B3, B2, Bi is laser-welded at the places indicated by the welding marks B4, B3, B2, and Bl, so that the source 33 of the ffi thin film transistor is connected to the data line 31, and the drain 32 of the standby thin film transistor is connected to the pixel electrode II.
  • the standby thin film transistor 30 replaces the damaged thin film transistor 20 to operate, and the display signal of the data line is transmitted to the pixel power through the standby thin film transistor 30. Extreme.
  • the laser cutting and laser splicing are performed from the side of the opposite side of the array substrate of the array substrate, as shown in FIG. 6 .
  • Laser cutting through the substrate usually a transparent glass substrate
  • laser welding through the substrate at the positions indicated by the welding marks B4, B3, B2, and B1, thereby replacing the damaged thin film transistor with the standby thin film transistor. Work offline.
  • laser cutting and laser welding may be performed from the side of the array surface of the array substrate, as shown in FIG. 5, or as shown in FIG.
  • the ⁇ of the array substrate is laser cut and laser fused.
  • the array substrate and the repairing method thereof provided by the invention are not limited to the array process, and the product repair rate and the product yield are improved. Moreover, the repairing front film transistor is isolated, and after the thin film transistor is damaged, it is repaired. The standby thin film transistor is operated, and the damaged thin film transistor is turned off and stopped. Therefore, the additional capacitance generated by the provision of the standby thin film transistor can be avoided, and the display performance of the product is ensured.
  • the invention also provides a method for manufacturing an array substrate, as shown in FIG. 7, the method comprises: steps! 01. Form a gate metal layer on the substrate, and form a gate line, a gate of the thin film transistor, a gate of the standby thin film transistor, a first repair line, and a second repair line by a patterning process.
  • the gate of the thin film transistor and the gate of the standby thin film transistor are the gate lines, and the gate metal layer formed in step 101 forms the gate line 41 and the first repair.
  • the pattern of the line 43 and the second repair line 42 is specifically as shown in Fig. 8(a).
  • Step 102 as shown in FIG. 8(b), forming a gate insulating layer, a semiconductor layer, and a source/drain metal layer on the substrate on which the gate line 41, the gate electrode, the first repair line 43 and the second repair line 42 are formed,
  • the patterning process forms the thin film transistor 20, the backup thin film transistor 30, and the data line 31, and the source 23 (or the data line 31) of the thin film transistor is isolated from one end of the first repair line 43 and has an overlapping region, and the drain 22 of the thin film transistor (or the pixel electrode) is isolated from one end of the second repair line 42 and has an overlapping region, and the source 33 of the standby thin film transistor is isolated from the other end of the first repair line 43 and exists In the overlap region, the drain 32 of the spare thin film transistor is isolated from the other end of the second repair line 43 and has an overlap region;
  • This step mainly includes: deposition of a gate insulating layer, a semiconductor layer, and a source/drain metal layer; and channel etching of a data line, a source and a drain of the thin film transistor (the thin film transistor 20 and the backup thin film transistor 30), and a thin film transistor.
  • Step 103 as shown in FIG. 8(c), forming a transparent passivation layer (not shown) and a passivation layer via 50 on the substrate on which the thin film transistor 20, the backup thin film transistor 30, and the data line 31 are formed.
  • the passivation layer via 50 is used to connect the drain 22 of the thin film transistor 20 with a subsequently formed pixel electrode.
  • Step 104 forming a transparent conductive layer on the substrate on which the passivation layer is formed, and forming the pixel electrode 11 by a patterning process, and the array substrate formed is as shown in FIG. 8(d).
  • the cross-sectional structure of the first repairing line 43 (along the broken line AB) is as shown in FIG. 9.
  • the substrate 40 is sequentially arranged from the bottom to the top, and the gate metal layer is disposed on the substrate 40 (the first in the figure) Repair line 43, and gate of thin film transistor and gate of spare thin film transistor), gate insulating layer 44-, semiconductor layer 45, source/drain metal layer 46 (forming source 23 of thin film transistor and standby thin film transistor in the figure) a source 33) and a passivation layer 47, wherein both ends of the first repair line 43 overlap the source 23 of the thin film transistor and the source 33 of the standby thin film transistor via the gate insulating layer 44 and the semiconductor layer 45, respectively
  • the laser welding is performed at the overlapping portion (corresponding to the welding marks B4 and B3 in FIG.
  • the laser welding here may be from the back surface of the substrate 40 (ie, the non-onset side of the array substrate, corresponding to the lower surface of the substrate 40 in FIG. 9).
  • the side may be performed from the top (on the side of the array substrate to the side of the panel, corresponding to the top of FIG. 9), and the source 23 of the thin film transistor is electrically connected to the left end of the first repair line 43 below.
  • Source of the transistor 33 is connected to the right end of the first repair line griefful 43 below.
  • the cross-sectional structure at the second repair line 42 and the repair weld at both ends of the second repair line 42 are similar, and will not be described again.
  • the semiconductor layer between the gate metal layer and the source/drain metal layer in FIG. 9 can also be removed by synchronous etching.
  • the first repair line 43 only needs to be ensured in this embodiment.
  • the two ends are separated from and overlap with the source 23 (or the data line 31) of the thin film transistor and the source 33 of the standby thin film transistor, and both ends of the second repair line 42 and the drain 22 of the thin film transistor (or image)
  • the pixel electrode 1 1 ) and the drain 32 of the standby thin film transistor are isolated and overlap. This embodiment does not limit whether there are other film layers between the gate metal layer and the source/drain metal layer in FIG. 9 .
  • the method for manufacturing an array substrate provided by the present invention comprises an isolated thin film transistor.
  • laser dicing is used to stop the damaged thin film transistor, and the source of the standby thin film transistor is replaced by laser welding.
  • the data lines are connected, and the drain is connected to the pixel electrodes, so that the standby thin film transistors operate in place of the damaged thin film transistors.
  • the laser cutting and laser welding can be performed from the side of the non-opposing surface of the array substrate, which is not limited to the array process, and the product is improved.
  • the repair rate and the yield of the product, and the spare thin film transistor is isolated before the repair, and is not in operation, therefore, the extra capacitance generated by the provision of the standby thin film transistor can be avoided, and the production port is guaranteed.

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Abstract

本发明公开了一种像素单元、阵列基板及其制造、修复方法和显示装置，涉及显示领域，解决了现有薄膜晶体管损坏的修复局限于阵列工序，阵列工序后的薄膜晶体管损坏无法修复的问题，同时还可减少因备用薄膜晶体管导致的电容，保证了产品性能，提高了产品修复率和产品良率。所述像素单元包括：像素电极、数据线和薄膜晶体管，还包括：备用薄膜晶体管，其源极与数据线隔离，其漏极与像素电极隔离；第一修复线，其一端与备用薄膜晶体管的源极隔离并存在重叠区域；另一端与数据线或者薄膜晶体管的源极隔离并存在重叠区域；第二修复线，其一端与备用薄膜晶体管的漏极隔离并存在重叠区域；另一端与像素电极或者薄膜晶体管的漏极隔离并存在重叠区域。

Description

本发明涉及显示领域， 尤其涉及一种像素单元、 阵列基板及其制造、 修 法和显示装置。
薄膜场效应晶体管液晶显示器 （Thm Film Transistor Liquid Crystal Display, TFT-L€D) , 主要由阵列基板和彩膜基板对位贴合后灌入液晶形成， 阵列基板上设置薄膜晶体管（Thin Film Transistor, TFT) , 彩膜基板上设置彩 色滤光片， 通过薄膜晶体管控制加载到每个像素上的信号与电压改变， 来控 制液晶分子的转动方向， 从而控制每个像素点偏振光出射与否而达到显示目 的。
在制造阵列基板过程， 受工艺条件的限制往往会出现各种不良如薄膜晶 体管损坏不能正常工作等， 为提高成品率， 阵列基板上一般需同时形成备用 薄膜晶体管， 在薄膜晶体管不能正常工作时， 通过后期修复使备用薄膜晶体 管成为工作薄膜晶体管， 控制加载到像素上的信号与电压改变。
种现有的可修复阵列基板如图 i所示， 工作薄膜晶体管和备用薄膜 体管形成在同一栅金属层 21上， 后期修复时， 需要利用 CVD方法沉积金属 层形成第一连接桥 12和第二连接桥 13 , 通过激光打孔使备用薄膜晶体管的 源极 33与数据线 31相连， 备用薄膜晶体管的漏极 32与像素电极 11相连， 但显然， 这种设计'使得修复局限于阵列工序 （array阶段）， 阵列工序后的薄 膜晶体管损坏将无法修复， 而且修复工艺复杂， 实施 ^间较长。
本发明的实施例提供一种像素单元、 阵列基板及其制造、 修复方法和显 示装置， 解决了现有薄膜晶体管损坏的修复局限于阵列工序， 阵列工序后的 薄膜晶体管损坏无法修复的问题， 同时还可减少因备用薄膜晶体管导致的电 容， 保证了产品性能， 提高了产品修复率和产品良率。
为达到上述目的， 本发明的实施例采用如下技术方案：
一种像素单元， 包括： 像素电极、 数据线和薄膜晶体管， 还包括： 设置在所述薄膜晶体管的旁边， 用于在所述薄膜晶体管损坏时替代所述 薄膜晶体管工作的备用薄膜晶体管， 所述备用薄膜晶体管的源极与所述数据 线隔离， 所述备用薄膜晶体管的漏极与所述像素电极隔离；
第一修复线，其一端与所述备用薄膜晶体管的源极隔离并存在重叠区域; 另一端与所述数据线或者所述薄膜晶体管的源极隔离并存在重叠区域；
第二修复线，其一端与所述备用薄膜晶体管的漏极隔离并存在重叠区域; 另一端与所述像素电极或者所述薄膜晶体管的漏极隔离并存在重叠区域。
优选所述第一修复线和 /或所述第二修复线与所述薄膜晶体管的栅极同 层设置。
可选地， 所述第一修复线和 /或所述第二修复线与所述像素电极同层设 直。
可选地， 所述像素单元， 还包括： 公共电极，
所述第一修复线和 /或所述第二修复线， 与所述公共电极同层设置。
所述的像素单元， 还包括： 栅线；
所述薄膜晶体管、 所述备用薄膜晶体管位于所述栅线和所述数据线的交 叉区域， 且所述薄膜晶体管和备用薄膜晶体管设置在同一所述栅线上。
优选所述备用薄膜晶体管的栅极与所述薄膜晶体管的栅极同层设置； 所述备用薄膜晶体管的半导体层与所述薄膜晶体管的半导体层同层设 置；
所述备用薄膜晶体管的源极和漏极与所述薄膜晶体管的源极和漏极同层 设置。
本发明还提供一种阵列基板， 包括多个像素单元， 所述像素 m元包括： 像素电极、 数据线和 ^于将数据线的显示信号加载到像素电极上的薄膜晶体 管， 还包括： 设置在所述薄膜晶体管的旁边， 用于在所述薄膜晶体管损坏时替代所述 薄膜晶体管工作的备 ^薄膜晶体管， 所述备用薄膜晶体管的源极与所述数据 线隔离， 所述备用薄膜晶体管的漏极与所述像素电极隔离；
第一修复线，其一端与所述备用薄膜晶体管的源极隔离并存在重叠区域； 另一端与数据线或者所述薄膜晶体管的源极隔离并存在重叠区域；
第二修复线，其一端与所述备用薄膜晶体管的漏极隔离并存在重叠区域; 另一端与像素电极或者所述薄膜晶体管的漏极隔离并存在重叠区域。
优选所述第一修复线和 /或所述第二修复线， 与所述薄膜晶体管的栅极同 层设置。
可选所述第一修复线和 /或所述第二修复线， 与所述像素电极同层设置。 可选所述像素单元还包括： 公共电极，
所述第一修复线和 /或所述第二修复线， 与所述公共电极同层设置。
进一步地， 所述的阵列基板上的所述像素单元还包括： 栅线；
所述薄膜晶体管、 所述备用薄膜晶体管和透明像素电极位于所述栅线和 所述数据线的交叉区域， 且所述薄膜晶体管和备 ^薄膜晶体管设置在同一所 本发明还提供一种显示装置， 包括： 任一项所述的阵列基板。
另一方面， 本发明还提供一种阵列基板的制造方法， 包括：
在基板上形成栅金属层， 采用构图工艺形成栅线、 薄膜晶体管的栅极、 备用薄膜晶体管的栅极、 第一修复线和第二修复线；
在形成有栅线、栅极、第一修复线和第二修复线的基板上形成栅绝缘层、 半导体层和源漏金属层， 采用构图工艺形成薄膜晶体管、 备用薄膜晶体管和 数据线， 并且所述数据线或者所述薄膜晶体管的源极与所述第一修复线的一 端隔离并存在重叠区域， 所述像素电极或者所述薄膜晶体管的漏极与所述第 二修复线的一端隔离并存在重叠区域，
所述备用薄膜晶体管的源极与所述第一修复线的另一端隔离并存在重叠 区域， 所述备用薄膜晶体管的漏极与所述第二修复线的另一端隔离并存在重 叠区域；
在形成有薄膜晶体管、 备用薄膜晶体管和数据线的基板上形成钝化层及 钝化层过孑 L;
在形成有钝化层的基板上形成透明导电层，采用构图工艺形成像素电极。 本发明还提供一种阵列基板的修复方法， 用于在薄膜晶体管损坏时进行 修复， 所述修复方法包括：
迸行激光切割， 使损坏的薄膜晶体管的源极与数据线断开， 损坏的薄膜 晶体管的漏极与像素电极断开；
对第一修复线与备 ffi薄膜晶体管的源极的重叠区域、 第一修复线与数据 线或者薄膜晶体管的源极的重叠区域、 第二修复线与备用薄膜晶体管的漏极 的重叠区域.、 第二修复线与像素电极或者薄膜晶体管的漏极的重叠区域进行 激光熔接， 使备用薄膜晶体管的源极与数据线连接， 备用薄膜晶体管的漏极 与像素电极连接。
迸一步， 对于在阵列基板与对盒基板对盒后检测出的薄膜晶体管损坏， 所述激光切割及所述激光熔接从所述阵列基板的非对盒面的一侧进行。
本发明提供的像素单元、 阵列基板及其制造、 修复方法和显示装置， 设 置一个孤立的备用薄膜晶体管， 在薄膜晶体管损坏不能正常工作时， 采用激 光切割使损坏的薄膜晶体管停止工作， 然后再采用激光熔接法使备用薄膜晶 体管的源极与数据线连接， 漏极与像素电极连接， 从而使备用薄膜晶体管替 代损坏的薄膜晶体管进行工作。 本发明所述修复方法并不局限于阵列工序， 对于在阵列基板与对盒基板对盒后检测出的薄膜晶体管损坏， 可从阵列基板 的非对盒面的一侧迸行激光切割及激光熔接，提高了产品修复率和产品良率， 而且， 备用薄膜晶体管在修复前是孤立的， 并不处于工作状态， 且修复后损 坏的薄膜晶体管也与数据线及像素电极断开， 避免因设置备用薄膜晶体管产 生额外电容影响产品的显示性能。 图 2为本发明实施例一提供的一种像素单元的结构示意图； 图 3为本发明实施例一提供的另一种像素单元的结构示意图；
图 4为本发明实施例二提供的阵列基板的结构示意图；
图 5为本发明实施例三提供的对盒前阵列基板薄膜晶体管
意图一；
图 6为本发明实施例三提供的对盒后阵列基板薄膜晶体管的修复方法; 图 7为本发明实施例四提供的阵列基板制造方法流程图；
图 8 (a) 〜图 8 (d) 为实施例四提供的阵列基板制造过程示意图； 图 9为图 8 (d) 中沿 A- B方向的剖面结构示意图。
附图标记
11 -像素电极， 12第一连接桥， 13-第二连接桥， 21栅金属层，
31-数据线， 32备用薄膜晶体管的漏极， 33-备用薄膜晶体管的源极: 22-薄膜晶体管的漏极， 23-薄膜晶体管的源极， 20-薄膜晶体管，
30-备用薄膜晶体管， 41-栅线， 42-第二修复线， 43-第一修复线
40-基板， 44-栅绝缘层， 45-半导体层， 46源漏金属层， 47-钝化层， 50-钝化层过孔。
下面结合^图对本发明实施例提供的像素单元、 阵列基板、 显示装置及 阵列基板的制造、 修复方法进行详细描述。
实施例一
本发明实施例提供一种像素单元， 如图 2所示， 所述像素单元包括： 像 素电极 11、数据线 31和用于将数据线 31的显示信号加载到像素电极 11上的 薄膜晶体管 20， 还包括：
设置在薄膜晶体管 20的旁边， 用于在薄膜晶体管 20损坏时替代薄膜晶 体管 20工作的备用薄膜晶体管 30， 备用薄膜晶体管 30的源极 33与数据线 31隔离， 备用薄膜晶体管 30的漏极 32与像素电极 i i隔离；
第一修复线 43， 其一端与备用薄膜晶体管 30的源极 33隔离并存在重叠 区域； 另一端与薄膜晶体管 20的源极 23 (或者数据线 31 ) 隔离并存在重叠 第二修复线 42， 其一端与备用薄膜晶体管 30的漏极 32隔离并存在重叠 区域； 另一端与薄膜晶体管 20的漏极 22 (或者像素电极 11 ) 隔离并存在重 叠区域。
在修复前， 本实施例中的备用薄膜晶体管 30保持孤立， 即备用薄膜晶体 管 30的源极 33与数据线 31隔离， 漏极 32与像素电极 11隔离， 修复前的备 用薄膜晶体管 30并不处于工作状态；修复后，损坏的薄膜晶体管也是孤立的， 也不处于工作状态，因此备用薄膜晶体管 30的存在并不会影响产品的显示性 能。
如图 2所示， 优选像素孳元还包括： 栅线 41 ; 薄膜晶体管 20、 备用薄膜 晶体管 30位于栅线 41和数据线 31的交叉区域， 且薄膜晶体管 20和备用薄 膜晶体管 30设置在同一栅线 41上， 薄膜晶体管 20和备用薄膜晶体管 30的 第一修复线 43和第二修复线 42与栅线 4!平行， 第一修复线 43的两端 分别与薄膜晶体管 20的源极 23、 备用薄膜晶体管 30的源极 33隔离并存在 重叠区域， 第二修复线 42的两端分别与薄膜晶体管 20的漏极 22、 备用薄膜 晶体管 30的漏极 32隔离并存在重叠区域， 其中， "隔离并存在重叠区域"， 指二者设置在不同膜层， 且存在交叉重叠区域， "隔离"， 指二者并不存在接 触， 当然也不存在电连接。 如果在该交叉重叠区域采用激光熔接方法， 即可 将二者进行电连接。
优选第一修复线 43和第二修复线 42与薄膜晶体管 20的栅极 层设置， 栅金属层除形成栅线、薄膜晶体管 20的 »极和备 ^薄膜晶体管 30的栅极外, 还形成第一修复线 43和第二修复线 42。 第一修复线 43和第二修复线 42可 与栅线 41平行设置， 且第一修复线 43的一端隔着機绝缘层设置在薄膜晶体 管的源极 23的下方 （或上方）， 另一端隔着栅绝缘层设置在备用薄膜晶体管 的源极 33的下方（或上方）； 第二修复线 42的一端隔着栅绝缘层设置在薄膜 晶体管的漏极 22的下方 （或上方）， 另一端隔着栅绝缘层设置在备用薄膜晶 体管的漏极 32的下方 （或上方）。
当然， 也可如图 3所示， 第一修复线 43的一端隔着栅绝缘层设置在数据 线 31 的下方 （或上方）， 另一端隔着栅绝缘层设置在备用薄膜晶体管的源极 33的下方 （或上方）。 第二修复线 43的一端还可隔着栅绝缘层设置在像素电 极 1 1 的下方 （或上方）， 另一端隔着栅绝缘层设置在备用薄膜晶体管的漏极 32的下方 （或上方）。
此外， 在具体实施中， 第一修复线 43和 /或第二修复线 42还可设置成透 明导电层， 即第一修复线 43和/或第二修复线 42还可与像素电极 11或公共 电极同层设置， 只不过设计时， 第一修复线 43和第二修复线 42的线宽要考 虑到透明导电层与金属膜层 （第一修复线 43和第二修复线 42设置在栅金属 层时） 的电阻率存在差异， 避免修复后因电阻差异影响显示效果。
其中，优选备用薄膜晶体管 30的栅极与薄膜晶体管 20的栅极同层设置; 备用薄膜晶体管 30的半导体层与薄膜晶体管 20的半导体层同层设置； 备用 薄膜晶体管 30的源极和漏极与薄膜晶体管 20的源极和漏极同层设置。这样， 在制备时， 备用薄膜晶体管 30可与薄膜晶体管 20同步形成。
其中， 薄膜晶体管 20和备用薄膜晶体管 30可以是底栅结构， 也可以是 顶栅结构， 但是， 为了便于从阵列基板的背面 （非对盒面一侧） 进行修复优 选釆用图 2所示的底栅结构。
本发明提供的像素单元， 设置一个孤立的备用薄膜晶体管， 在薄膜晶体 管损坏不能正常工作时， 采用激光切割使损坏的薄膜晶体管停止工作， 采 ffi 激光熔接法使备用薄膜晶体管的源极与数据线连接， 漏极与像素电极连接， 从而使备用薄膜晶体管替代损坏的薄膜晶体管进行工作。 对于在阵列基板与 对盒基板对盒后检测出的薄膜晶体管损坏， 可从阵列基板的非对盒面的一侧 进行激光切割及激光瑢接， 并不局限于阵列工序， 因此提高了产品修复率和 产品良率， 而且， 备用薄膜晶体管在修复前是孤立的， 并不处于工作状态， 修复后损坏的薄膜晶体管也是孤立的， 也不处于工作状态， 因此， 可避免因 设置备用薄膜晶体管产生额外电容， 保证了产品的显示性能。 本发明还提供一种阵列基板， 如图 4所示， 同时参照图 2， 该阵列基板 包括多个像素单元， 以左上第一个像素单元为例， 像素单元包括： 像素电极 I 数据线 31和用于将数据线 31的显示信号加载到像素电极 11上的薄膜晶 体管 20， 还包括： 设置在薄膜晶体管 20的旁边， 用于在薄膜晶体管 20损坏 时替代薄膜晶体管 20工作的备用薄膜晶体管 30， 备用薄膜晶体管 30的源极 33与数据线 31隔离， 备用薄膜晶体管 30的漏极 32与像素电极 11隔离； 第 一修复线 43， 其一端与备 ^薄膜晶体管 30的源极 33隔离并存在重叠区域； 另一端与薄膜晶体管 20的源极 23 (或者数据线 31 ) 隔离并存在重叠区域； 第二修复线 42，其一端与备用薄膜晶体管 30的漏极 32隔离并存在重叠区域; 另一端与薄膜晶体管 20的漏极 22 (或者像素电极 11 )隔离并存在重叠区域。
优选第一修复线 43和 /或第二修复线 42 ,与薄膜晶体管 20的栅极同层设 置。 当然， 次选第一修复线 43和 /或第二修复线 42也可与像素电极 11或者 公共电极同层设置。
阵列基板上的像素单元还包括： 栅线 41 ; 薄膜晶体管 20、 备用薄膜晶体 管 30位于栅线 41和数据线 3 !的交叉区域， i薄膜晶体管 20和备用薄膜晶 体管 30设置在同一栅线 41上， 薄膜晶体管 20和备用薄膜晶体管 30的栅极 其中，优选备用薄膜晶体管 30的栅极与薄膜晶体管 20的栅极同层设置; 备用薄膜晶体管 30的半导体层与薄膜晶体管 20的半导体层同层设置； 备 ffi 薄膜晶体管 30的源极和漏极， 与薄膜晶体管 20的源极和漏极同层设置。 这 样， 在制备时， 备用薄膜晶体管 30可与薄膜晶体管 20同步形成。
其中， 薄膜晶体管 20和备用薄膜晶体管 30可以是底栅结构， 也可以是 顶 »结构， 但是， 为了便于从阵列基板的背面 （非对盒面一侧） 进行修复而 优选采用图 2所示的底栅结构。
本发明提供的阵列基板，每个像素单元设置一个孤立的备用薄膜晶体管， 在薄膜晶体管损坏不能正常工作时， 通过修复备用薄膜晶体管的源极与数据 线连接， 漏极与像素电极连接， 从而使备 ^薄膜晶体管替代损坏的薄膜晶体 管进行工作。 对于在阵列基板与对盒基板对盒后检测出的薄膜晶体管损坏， 可从阵列基板的非对盒面的一侧进行激光切割及激光瑢接， 并不局限于阵列 工序， 因此提高了产品修复率和产品良率， 而且， 修复前备用薄膜晶体管是 孤立的， 薄膜晶体管损坏后， 经过修复， 使备用薄膜晶体管处于工作状态， 同时使损坏的薄膜晶体管断开停止工作， 因此， 可避免因设置备用薄膜晶体 管产生额外电容， 保证了产品的显示性能。 本发明实施例还提供一种显示装置， 其包括上述任意一种阵列基板。 所 述显示装置可以为： 液晶面板、 电子纸、 OLED 面板、 手机、 平板电脑、 电 视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品 或部件。
另一方面， 针对本发明实施例提供的阵列基板， 本发明还提供一种阵列 基板的修复方法， 用于在薄膜晶体管损坏进行修复， 该修复方法包括：
步骤一、 沿图 5和图 6中虚线所示的切割标示 A1 和 A2进行激光切割， 使损坏的薄膜晶体管 20的源极 23与数据线 31断开，损坏的薄膜晶体管的漏 极 22与像素电极 11断开， 损坏的薄膜晶体管 20停止工作。
步骤二、 对第一修复线 43与备用薄膜晶体管的源极 33的重叠区域、 第 一修复线 43与薄膜晶体管的源极 23 (或者数据线 31 ) 的重叠区域、 第二修 复线 42与备用薄膜晶体管的漏极 32的重叠区域以及第二修复线 42与薄膜晶 体管的漏极 32 (或者像素电极 11 ) 的重叠区域进行激光瑢接， 具体见图 5所 示的瑢接标示 B4、 B3、 B2、 Bi 在熔接标示 B4、 B3、 B2、 Bl所示的地方 进行激光熔接， 使备 ffi薄膜晶体管的源极 33与数据线 31连接， 备用薄膜晶 体管的漏极 32与像素电极 I I连接。备用薄膜晶体管 30替换已损坏的薄膜晶 体管 20进行工作， 数据线的显示信号遥过备用薄膜晶体管 30加载到像素电 极。
需要说明的是， 对于在阵列基板与对盒基板对盒后检测出薄膜晶体管损 坏， 修复时需从阵列基板的对盒面的一侧进行激光切割及激光瑢接， 具体如 图 6所示， 透过基板（一般为透明玻璃基板）沿切割标示 A1 和 A2进行激光 切割， 对熔接标示 B4、 B3、 B2、 B1所示位置透过基板进行激光熔接， 从而 使备用薄膜晶体管替换损坏的薄膜晶体管迸行工作。
对于阵列基板与对盒基板对盒前检测出的薄膜晶体管损坏， 则可以从阵 列基板的对盒面的一侧进行激光切割及激光熔接， 如图 5所示， 也可以如图 6所示从阵列基板的非对盒面的一惻进行激光切割及激光熔接。
本发明提供的阵列基板及其修复方法， 修复过程并不局限于阵列工序， 提高了产品修复率和产品良率， 而且， 修复前备 ^薄膜晶体管是孤立的， 薄 膜晶体管损坏后， 经过修复， 使备用薄膜晶体管处于工作状态， 同时使损坏 的薄膜晶体管断开停止工作， 因此， 可避免因设置备用薄膜晶体管产生额外 电容， 保证了产品的显示性能。 本发明还提供一种阵列基板的制造方法， 如图 7所示， 该方法包括： 步骤 ！01， 在基板上形成栅金属层， 采用构图工艺形成栅线、 薄膜晶体 管的栅极、 备用薄膜晶体管的栅极、 第一修复线和第二修复线。
优选薄膜晶体管和备用薄膜晶体管可设置在同一栅线上时， 薄膜晶体管 的栅极和备用薄膜晶体管的栅极即该栅线， 此时步骤 101形成的栅金属层形 成栅线 41和第一修复线 43和第二修复线 42的图案， 具体如图 8 ( a) 所示。
步骤 102， 如图 8 ( b ) 所示， 在形成有栅线 41、 栅极、 第一修复线 43 和第二修复线 42的基板上形成栅绝缘层、 半导体层和源漏金属层， 采用构图 工艺形成薄膜晶体管 20、 备用薄膜晶体管 30和数据线 31， 且， 薄膜晶体管 的源极 23 (或者数据线 31 ) 与第一修复线 43的一端隔离并存在重叠区域， 薄膜晶体管的漏极 22 (或者像素电极） 与第二修复线 42 的一端隔离并存在 重叠区域， 备用薄膜晶体管的源极 33与第一修复线 43的另一端隔离并存在 重叠区域， 备用薄膜晶体管的漏极 32与第二修复线 43的另一端隔离并存在 重叠区域；
本步骤主要包括： 栅绝缘层、 半导体层和源漏金属层的沉积； 以及数据 线、薄膜晶体管 (薄膜晶体管 20和备用薄膜晶体管 30)的源漏极及薄膜晶体管 的沟道刻蚀。
步骤 103， 如图 8 ( c) 所示， 在形成有薄膜晶体管 20、 备用薄膜晶体管 30和数据线 31的基板上形成透明的钝化层（图中未示出）及钝化层过孔 50， 钝化层过孔 50用于连接薄膜晶体管 20的漏极 22与后续形成的像素电极。
步骤 104, 在形成有钝化层的基板上形成透明导电层， 釆用构图工艺形 成像素电极 11， 形成的阵列基板如图 8 (d) 所示。
在本实施例中， 第一修复线 43 (沿虚线 AB ) 的剖面结构如图 9所示， 自下而上依次为基板 40， 设置在基板 40上的栅金属层 （形成图中的第一修 复线 43， 以及薄膜晶体管的栅极和备用薄膜晶体管的栅极）、 栅绝缘层 44-、 半导体层 45、 源漏金属层 46 (形成图中的薄膜晶体管的源极 23及备用薄膜 晶体管的源极 33 ) 和钝化层 47， 其中， 第一修复线 43的两端隔着栅绝缘层 44和半导体层 45分别与薄膜晶体管的源极 23及备用薄膜晶体管的源极 33 相重叠， 在重叠处（对应图 6中的熔接标示 B4、 B3 )进行激光熔接， 此处的 激光熔接可以从基板 40的背面（即阵列基板非对盒面一侧， 对应图 9中基板 40的下表面一侧） 进行， 也可以从顶部 （阵列基板对盒面一侧， 对应图 9的 顶部） 进行， 使薄膜晶体管的源极 23与下方的第一修复线 43的左侧端电连 接， 备用薄膜晶体管的源极 33与下方的第一修复线 43的右惻端电连接。 第 二修复线 42处的剖面结构及第二修复线 42两端的修复熔接相类似， 对此不 再赘述。
其中， 步骤 102进行薄膜晶体管沟道刻蚀时， 图 9中栅金属层与源漏金 属层之间的半导体层也可一起同步刻蚀去除， 此外， 本实施例只需保证第一 修复线 43的两端与薄膜晶体管的源极 23 (或数据线 31 ) 及备用薄膜晶体管 的源极 33隔离且重叠， 第二修复线 42的两端与薄膜晶体管的漏极 22 (或像 素电极 1 1 ) 及备用薄膜晶体管的漏极 32隔离且重叠， 本实施例对图 9中栅 金属层与源漏金属层之间是否存在其它膜层不做限定。
本发明提供的阵列基板的制造方法， 设置一个孤立的备用薄膜晶体管， 在薄膜晶体管损坏不能正常工作时， 采用激光切割使损坏的薄膜晶体管停止 工作， 采用激光熔接法使备用薄膜晶体管的源极与数据线连接， 漏极与像素 电极连接， 从而使备用薄膜晶体管替代损坏的薄膜晶体管进行工作。 对于在 阵列基板与对盒基板对盒后检测出的薄膜晶体管损坏， 则可从阵列基板的非 对盒面的一侧进行所述激光切割及激光熔接， 并不局限于阵列工序， 提高了 产品修复率和产品良率， 而且， 备用薄膜晶体管在修复前是孤立的， 并不处 于工作状态， 因此， 可避免因设置备用薄膜晶体管产生的额外电容， 保证产 口 卜 /-卜台匕
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需要注意的是， 本发明实施例所述的技术特征， 在不冲突的情况下， 可 任意相互组合使/¾。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到的变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保

Claims

1. 一种像素单元， 包括： 像素电极、数据线和薄膜晶体管， 其特征在于， 还包括：
设置在所述薄膜晶体管的旁边， 用于在所述薄膜晶体管损坏时替代所述 薄膜晶体管工作的备 ^薄膜晶体管， 所述备用薄膜晶体管的源极与所述数据 线隔离， 所述备用薄膜晶体管的漏极与所述像素电极隔离；
第一修复线，其一端与所述备用薄膜晶体管的源极隔离并存在重叠区域； 另一端与所述数据线或者所述薄膜晶体管的源极隔离并存在重叠区域；
第二修复线，其一端与所述备用薄膜晶体管的漏极隔离并存在重叠区域; 另一端与所述像素电极或者所述薄膜晶体管的漏极隔离并存在重叠区域。
2. 根据权利要求 1 所述的像素单元， 其特征在于， 所述第一修复线和 / 或所述第二修复线与所述薄膜晶体管的栅极同层设置。
3. 根据权利要求 1 所述的像素单元， 其特征在于， 所述第一修复线和 / 或所述第二修复线与所述像素电极同层设置。
4. 根据权利要求 1所述的像素单元， 其特征在于， 还包括： 公共电极， 所述第一修复线和 /或所述第二修复线与所述公共电极同层设置。
5. 根据权利要求 1-4任一项所述的像素单元， 其特征在于， 还包括： 栅 线，
所述薄膜晶体管、 所述备用薄膜晶体管位于所述栅线和所述数据线的交 叉区域， 且所述薄膜晶体管和备 ^薄膜晶体管设置在同一所述栅线上。
6. 根据权利要求 1所述的像素单元， 其特征在于，
所述备用薄膜晶体管的栅极与所述薄膜晶体管的栅极同层设置， 所述备用薄膜晶体管的半导体层与所述薄膜晶体管的半导体层同层设 置，
所述备用薄膜晶体管的源极、 漏极与所述薄膜晶体管的源极、 漏极同层 设置。
7. 一种阵列基板，包括多个像素单元，所述多个像素单元的每一个包括： 像素电极、 数据线和 ^于将所述数据线的显示信号加载到所述像素电极上的 薄膜晶体管， 其特征在于， 还包括：
设置在所述薄膜晶体管的旁边， 用于在所述薄膜晶体管损坏时替代所述 薄膜晶体管工作的备用薄膜晶体管， 所述备用薄膜晶体管的源极与所述数据 线隔离， 所述备用薄膜晶体管的漏极与所述像素电极隔离，
第一修复线，其一端与所述备用薄膜晶体管的源极隔离并存在重叠区域， 另一端与所述数据线或者所述薄膜晶体管的源极隔离并存在重叠区域，
第二修复线，其一端与所述备用薄膜晶体管的漏极隔离并存在重叠区域， 另一端与所述像素电极或者所述薄膜晶体管的漏极隔离并存在重叠区域。
8. 根据权利要求 7所述的阵列基板， 其特征在于， 所述第一修复线和 / 或所述第二修复线与所述薄膜晶体管的機极同层设置。
9. 根据权利要求 7所述的阵列基板， 其特征在于， 所述第一修复线和 / 或所述第二修复线与所述像素电极同层设置。
10. 根据权利要求 7所述的阵列基板， 其特征在于， 所述像素单元还包 括： 公共电极，
所述第一修复线和 Z或所述第二修复线与所述公共电极同层设置。
1 L 根据权利要求 7-10任一项所述的阵列基板， 其特征在于， 所述像素 单元还包括： 栅线，
所述薄膜晶体管、 所述备用薄膜晶体管和透明像素电极位于所述栅线和 所述数据线的交叉区域， 且所述薄膜晶体管和所述备 ffi薄膜晶体管设置在同 一所述襬线上。
12. —种显示装置， 其特征在于， 包括： 权利要求 7- n任一项所述的阵
13. 一种阵列基板的制造方法， 其特征在于， 包括：
在基板上形成栅金属层， 采用构图工艺形成栅线、 薄膜晶体管的栅极、 备用薄膜晶体管的栅极、 第一修复线和第二修复线， 在形成有所述栅线、 所述栅极、 所述第一修复线和所述第二修复线的基 板上形成栅绝缘层、 半导体层和源漏金属层， 采 ^构图工艺形成所述薄膜晶 体管、 所述备用薄膜晶体管和数据线， 并且所述数据线或者所述薄膜晶体管 的源极与所述第一修复线的一端隔离并存在重叠区域， 像素电极或者所述薄 膜晶体管的漏极与所述第二修复线的一端隔离并存在重叠区域，
所述备用薄膜晶体管的源极与所述第一修复线的另一端隔离并存在重叠 区域， 所述备用薄膜晶体管的漏极与所述第二修复线的另一端隔离并存在重 叠区域；
在形成有所述薄膜晶体管、 所述备用薄膜晶体管和所述数据线的基板上 形成钝化层及钝化层过孔；
在形成有所述钝化层的基板上形成透明导电层，采用构图工艺形成所述像 素电极。
14. 一种阵列基板的修复方法， 用于在薄膜晶体管损坏时进行修复， 其 特征在于， 所述修复方法包括：
进行激光切割， 使损坏的薄膜晶体管的源极与数据线断开， 损坏的薄膜 晶体管的漏极与像素电极断开；
对第一修复线与备用薄膜晶体管的源极的重叠区域、 所述第一修复线与 所述数据线或者所述薄膜晶体管的源极的重叠区域、 第二修复线与所述备用 薄膜晶体管的漏极的重叠区域以及所述第二修复线与所述像素电极或者所述 薄膜晶体管的漏极的重叠区域进行激光熔接， 使所述备用薄膜晶体管的源极 与所述数据线连接， 所述备用薄膜晶体管的漏极与所述像素电极连接。
15.根据权利要求 14所述的修复方法， 其特征在于， 对于在阵列基板与 对盒基板对盒后检测出的薄膜晶体管损坏， 所述激光切割及所述激光瑢接从 所述阵列基板的非对盒面的一侧进行。
PCT/CN2013/081301 2013-06-28 2013-08-12 像素单元、阵列基板及其制造、修复方法和显示装置 WO2014205892A1 (zh)

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