WO2014196176A1 - Élément d'imagerie à semi-conducteurs et appareil d'imagerie - Google Patents

Élément d'imagerie à semi-conducteurs et appareil d'imagerie Download PDF

Info

Publication number
WO2014196176A1
WO2014196176A1 PCT/JP2014/002873 JP2014002873W WO2014196176A1 WO 2014196176 A1 WO2014196176 A1 WO 2014196176A1 JP 2014002873 W JP2014002873 W JP 2014002873W WO 2014196176 A1 WO2014196176 A1 WO 2014196176A1
Authority
WO
WIPO (PCT)
Prior art keywords
row
reset
discharge
solid
state imaging
Prior art date
Application number
PCT/JP2014/002873
Other languages
English (en)
Japanese (ja)
Inventor
崇 後藤
Original Assignee
富士フイルム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士フイルム株式会社 filed Critical 富士フイルム株式会社
Priority to KR1020157035513A priority Critical patent/KR101760200B1/ko
Publication of WO2014196176A1 publication Critical patent/WO2014196176A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the present invention relates to a solid-state imaging device including a photoelectric conversion unit that generates electric charge upon irradiation with light, and an imaging device including the solid-state imaging device.
  • a photoelectric conversion unit including a pair of electrodes and a photoelectric conversion layer sandwiched between these electrodes is provided above the silicon substrate, and generated in this photoelectric conversion layer
  • a photoelectric conversion layer stacked type solid-state imaging device is drawing attention, in which a stored charge is transferred from one of the pair of electrodes to a silicon substrate and accumulated, and a signal corresponding to the accumulated charge is read by a signal readout circuit formed on the silicon substrate. ing.
  • a solid-state imaging device for example, in Patent Document 1, as shown in FIG. 21, a photoelectric conversion unit 201 and a floating diffusion FD (hereinafter simply referred to as FD) that accumulates charges generated in the photoelectric conversion unit 201.
  • the output transistor 202 that outputs a voltage corresponding to the charge accumulated in the FD
  • the reset transistor 203 that resets the charge accumulated in the FD
  • the signal output from the output transistor 202 are selectively output to the signal line.
  • a solid-state imaging device has been proposed in which a large number of pixel portions 200 each including a selection transistor 204 are two-dimensionally arranged.
  • This solid-state imaging device is a circuit having a so-called three-transistor structure in which no transistor is provided between the FD and the photoelectric conversion unit 201, and the FD and the photoelectric conversion unit 201 are electrically connected directly. is there.
  • FIG. 22 shows the timing of the discharge operation of the pixel portion 200 and the read operation of the charge signal in the nth to n + 2th rows.
  • FIG. 23 shows changes in driving and FD potential over time when the solid-state imaging device shown in FIG. 21 performs imaging under conditions where uniform light is incident on all pixels.
  • the solid line represents an ideal FD potential when there is no capacitive coupling, and the broken line represents a change in the potential of the FD when affected by capacitive coupling.
  • the change in the FD potential of the pixel of interest with the change in the FD potential of the adjacent pixel is a feature when there is an influence of capacitive coupling.
  • Each line discharges the charge accumulated in the FD until the time of discharge in the figure, and reads out the signal charge accumulated in the FD during the accumulation period from the discharge to the read at the time of reading.
  • the signal reading is completed at the time t1, and the potential of the FD becomes the reference potential.
  • discharging is performed at time t2, accumulation is started after the potential of FD is set to the reference potential.
  • reading is performed at time t5, and a signal corresponding to the signal charge accumulated in the FD between time t2 and time t5 is output.
  • the FD potential of the n-th row also changes with a large change in the FD potential of the n + 1-th row at time t2.
  • the FD potential changes monotonously from time t3 to time t4
  • the FD potential changes monotonically from time t3 to time t2, and then at time t2.
  • the potential decreases once, and the FD potential increases from the potential by accumulation of signal charges until time t4. For this reason, when the signal in the n-th row is read at time t4, the signal level is lower than the original signal level as indicated by the dotted line, compared to the original signal level indicated by the solid line.
  • red filters (R) and green filters (G) are alternately arranged in the column direction of the pixel unit 200.
  • the pixel unit 200 provided with the green filter is arranged in the same column as the pixel unit 200 provided with the red filter.
  • the discharge of the pixel unit 200 provided with the red filter decreases the potential of the FD of the pixel unit 200 provided with the green filter, and the magnitude of the charge signal G1. Will be smaller.
  • the pixel unit 200 provided with the green filter is in the same column as the pixel unit 200 provided with the blue filter, the pixel unit 200 provided with the blue filter is arranged in the lower row of FIG. Since no light is incident and the potential of the FD does not change, the discharge of the pixel portion 200 provided with the blue filter does not affect the potential of the FD of the pixel portion 200 provided with the green filter. A charge signal G2 larger than the charge signal G1 is acquired.
  • the coupling rate is the degree of influence of a potential change between FDs of adjacent pixel portions 200.
  • the coupling rate is determined by the ratio between the parasitic capacitance and the storage capacitance of the FD. The smaller the size of the pixel portion 200, the lower the degree of freedom of layout and the higher the coupling rate.
  • a black sun afterimage corresponding to ⁇ 100 electrons is generated in the (n + 1) th row.
  • an afterimage of accumulated charge amount ⁇ ( ⁇ coupling ratio) is generated due to capacitive coupling between adjacent pixel rows. As the coupling rate increases, the afterimage becomes significantly larger.
  • Patent Document 2 discloses that feedback reset is performed to reduce reset kTC noise.
  • Patent Document 2 does not describe a configuration that achieves both afterimage suppression and reset kTC noise reduction.
  • the present invention obtains an appropriate image signal that can sufficiently suppress an afterimage due to the effect of capacitive coupling formed between adjacent pixel rows and that has reduced reset kTC noise. It is an object of the present invention to provide a solid-state imaging device capable of performing imaging and an imaging apparatus including the solid-state imaging device.
  • the solid-state imaging device of the present invention includes a photoelectric conversion unit that generates a signal charge corresponding to the amount of incident light, a storage unit that stores the signal charge generated in the photoelectric conversion unit, and a signal charge stored in the storage unit.
  • a signal charge that is stored in the storage unit and includes a plurality of pixel units that are electrically connected to the photoelectric conversion unit, the power storage unit, and the input node of the output circuit.
  • Charge accumulation read operation of acquiring the signal charge accumulated in the power storage unit after the discharge, and resetting the power storage unit after acquiring the signal charge to acquire the reset level of the power storage unit are performed sequentially in a row, and before each row is discharged, preliminary discharge is performed to discharge preliminary charges from the power storage unit, and n-th row (n is a natural number) and n + 1-th row preliminary discharge are performed.
  • the power storage unit is a feedback control circuit is provided for performing feedback control so that the reference potential, characterized in that performing feedback control during discharge and reset.
  • feedback control can be performed at the time of resetting.
  • the pixel portion is provided with a row selection circuit connected between the output circuit and a signal line from which signal charges and reset levels are output, and the row selection circuit is made conductive when discharging. In the preliminary discharge, it can be made non-conductive.
  • the discharge of the nth row and the reset of rows other than the nth row can be performed at different timings.
  • the feedback control circuit can be provided with a voltage source for supplying a reference voltage and an inverting amplifier to which the voltage source is connected.
  • the reset of the nth row and the read preliminary reset of the (n + 1) th row can be performed simultaneously.
  • the row selection circuit can be turned on during resetting and non-conducted during read pre-reset.
  • the signal charge can be acquired before the read preliminary reset of the nth row, and the reset level of the nth row can be acquired after the reset of the (n + 1) th row.
  • the storage unit in the nth row can be brought into an electrically floating state.
  • a preliminary discharge shift register that outputs a pulse signal for performing preliminary discharge
  • a discharge shift register that outputs a pulse signal for performing discharge
  • a shift register can be provided.
  • At least three correlated double sampling processing circuits can be provided for each signal line from which signal charges and reset levels are output.
  • the pixel portion includes a first electrode partitioned in units of pixels and a second electrode provided to face the pixel electrode with the photoelectric conversion portion interposed therebetween.
  • These pixel portions can be a common electrode.
  • the photoelectric conversion part can include an organic photoelectric conversion film.
  • the organic photoelectric conversion film can be common to all the pixel portions.
  • the signal charge from the photoelectric conversion part can be made a hole.
  • the signal charge from the photoelectric conversion unit can be converted to electrons.
  • a protection circuit can be provided in the power storage unit.
  • An image pickup apparatus includes the solid-state image pickup element according to the present invention.
  • preliminary discharge for discharging preliminary charges from the power storage unit is performed before discharging of the power storage unit of the pixel unit of each row, and discharge of the nth row and n + 1 are performed. Since the preliminary discharge of the row is performed at the same time, the potential of the FD of the n-th row is obtained even when the capacitive coupling between the n-th row and the n + 1-th row is relatively large as described with reference to FIG. The effect of preliminary discharge on the (n + 1) th row can be reduced, and an appropriate image signal can be acquired. The reason will be described in detail later.
  • the feedback control circuit provided for each column of the pixel unit is used to perform the feedback control so that the power storage unit becomes the reference potential. And an image signal having a high S / N can be acquired.
  • the solid-state imaging device and imaging apparatus of the present invention can realize both suppression of the influence of capacitive coupling between adjacent pixels and reduction of reset kTC noise.
  • FIG. 6 is a diagram showing reset pulses RS (n ⁇ 1) to RS (n + 1) and selection pulses RW (n ⁇ 1) to RW (n + 1) at the time of preliminary discharge, discharge and reading.
  • the figure which shows the state of the reset transistor and selection transistor of each pixel part at the time of performing discharge of the (n-1) th row simultaneously with the preliminary discharge of the nth row The figure which shows the state of the reset transistor and selection transistor of each pixel part at the time of performing preliminary discharge of the (n + 1) th row simultaneously with discharge of the nth row
  • the figure which shows the state of the reset transistor and selection transistor of each pixel part at the time of performing readout reset of the n-th row The figure for demonstrating the influence of the afterimage in 1st Embodiment of the solid-state image sensor of this invention.
  • the figure which shows the positional relationship of the electrical storage part FD at the time of laying out the readout circuit of a pixel part by mirror image relation The figure which shows the electrical potential change of the electrical storage part FD at the time of only discharging
  • the figure which shows the structure and capacitive coupling of the pixel part of the conventional solid-state image sensor Timing chart for explaining discharge of conventional solid-state imaging device and reading of charge signal The figure for demonstrating the influence of the capacitive coupling in the conventional solid-state image sensor.
  • the figure for demonstrating the influence of the false signal by the capacitive coupling in the conventional solid-state image sensor The figure for demonstrating the influence of the afterimage by the capacitive coupling in the conventional solid-state image sensor
  • FIG. 1 is a diagram illustrating a pixel unit constituting the solid-state imaging device of the present embodiment.
  • the solid-state imaging device of the present embodiment has a large number of pixel portions 10 shown in FIG.
  • the pixel unit 10 includes a photoelectric conversion unit 11, a floating diffusion FD (corresponding to an accumulation unit) (hereinafter simply referred to as FD), an output transistor 12 (corresponding to an output circuit), a reset, A transistor 13 and a selection transistor 14 (corresponding to a selection circuit) are provided.
  • the output transistor 12, the reset transistor 13, and the selection transistor 14 are each composed of an n-channel MOS transistor. Note that the size of the pixel portion 10 is desirably 5 ⁇ m or less.
  • the photoelectric conversion unit 11 includes a pixel electrode 104 (corresponding to the first electrode), a counter electrode 108 (corresponding to the second electrode) provided to face the pixel electrode 104, the pixel electrode 104, and the counter electrode. And a photoelectric conversion layer 107 provided between them.
  • the pixel electrode 104 is a thin film electrode divided for each pixel portion 10 and is formed of a transparent or opaque conductive material such as ITO, aluminum, titanium nitride, copper, tungsten, or the like.
  • the pixel electrode 104 collects charges generated in the photoelectric conversion layer 107 for each pixel unit 10.
  • the counter electrode 108 is an electrode for applying a voltage to the photoelectric conversion layer 107 between the pixel electrode 104 and generating an electric field in the photoelectric conversion layer 107. Since the counter electrode 108 is provided on the light incident surface side of the photoelectric conversion layer 107 and needs to be transmitted through the counter electrode 108 and incident on the photoelectric conversion layer 107, the counter electrode 108 is transparent to the incident light. It is formed from a conductive material such as ITO. Note that the counter electrode 108 in the present embodiment is configured by one electrode common to all the pixel units 10, but may be configured to be divided for each pixel unit 10.
  • the photoelectric conversion layer 107 includes an organic photoelectric conversion film or an inorganic photoelectric conversion film that absorbs incident light and generates charges according to the absorbed light quantity. Note that a function of a charge blocking layer or the like that suppresses charge injection from the electrode to the photoelectric conversion layer 107 between the photoelectric conversion layer 107 and the counter electrode 108 or between the photoelectric conversion layer 107 and the pixel electrode 104. A layer may be provided.
  • a bias voltage is applied to the counter electrode 108 so that holes out of the charges generated in the photoelectric conversion layer 107 move to the pixel electrode 104 and electrons move to the counter electrode 108.
  • a bias voltage a voltage higher than the power supply voltage Vdd (a voltage supplied to the drain of the output transistor 12 in FIG. 1, for example, 3 V) is used as a bias voltage so that the photoelectric conversion layer 107 exhibits sufficiently high sensitivity. It is desirable to use about 5 to 20 V, for example 10 V).
  • FD is composed of an n-type impurity region electrically connected to the pixel electrode 104. Since the potential of the FD changes according to the amount of holes collected by the pixel electrode 104, the FD functions as a charge storage portion.
  • the output transistor 12 converts the charge signal accumulated in the FD into a voltage signal and outputs it to the signal line SL.
  • the gate terminal of the output transistor 12 is electrically connected to the FD, and the drain terminal is connected to the power supply voltage Vdd of the solid-state imaging device.
  • the source terminal of the output transistor 12 is connected to the drain terminal of the selection transistor 14.
  • the pixel unit 10 in the present embodiment is a so-called three-transistor circuit in which the FD, the pixel electrode 104 of the photoelectric conversion unit 11, and the gate terminal of the output transistor 12 are directly connected.
  • the reset transistor 13 resets the potential of the FD to a reference potential.
  • the FD is electrically connected to the drain terminal of the reset transistor 13, and the reset drain line RL is connected to the source terminal.
  • the reset drain line RL is provided for each column of the pixel units 10 and is shared by a plurality of pixel units 10 belonging to each column.
  • a feedback control circuit 16 is connected to one end of each reset drain line RL.
  • the feedback control circuit 16 is provided for each column of the pixel unit 10, and includes an inverting amplifier 16a and a voltage source 16b for supplying a reference voltage Vref.
  • the signal line SL is connected to the inverting input terminal ( ⁇ ) of the inverting amplifier 16a, the voltage source 16b is connected to the non-inverting input terminal (+), and the reset drain line RL is connected to the output terminal.
  • the reset transistor 13 When the reset pulse RS applied to the gate terminal of the reset transistor 13 becomes high level, the reset transistor 13 is turned on, and electrons are injected from the source to the drain of the reset transistor 13. Then, the injection of electrons causes the potential of the FD to drop and the potential of the FD to be reset to the reference potential.
  • the selection transistor 14 When the selection transistor 14 is turned on at this time, the potential of the FD is changed to the output transistor. 12, input to the feedback control circuit 16 via the selection transistor 14 and the signal line SL.
  • the feedback control circuit 16 feedback-controls the FD potential based on the current potential of the FD and the reference voltage Vref supplied from the voltage source 16b. At this time, if the gain of the output transistor 12 is 1 and the threshold voltage of the output transistor is Vth, the potential of the signal line SL is Vref, the potentials of the reset drain lines RL and FD are Vref + Vth, and the FD potential is constant. Maintained. Thus, by performing feedback control of the potential of the FD, reset kTC noise of the reset transistor 13 can be reduced.
  • the selection transistor 14 has a source terminal connected to the signal line SL, and selectively outputs a signal output from the output transistor 12 of each pixel unit 10 to the signal line SL provided for each column. belongs to.
  • the selection pulse RW applied to the gate terminal of the selection transistor 14 becomes a high level, the selection transistor 14 is turned on, whereby a signal output from the output transistor 12 of each pixel unit 10 is output to the signal line SL.
  • FIG. 2 is a schematic cross-sectional view of a solid-state imaging device 100 in which a large number of pixel portions 10 shown in FIG. 1 are two-dimensionally arranged.
  • the same name and reference numeral are assigned to the same configuration as the pixel unit 10 shown in FIG.
  • the solid-state imaging device 100 includes a substrate 101, an insulating layer 102, a connection electrode 103, a pixel electrode 104, a connection portion 105, a connection portion 106, a photoelectric conversion layer 107, and a counter electrode. 108, a sealing layer 110, a color filter 111, a light shielding layer 113, a protective layer 114, a counter electrode voltage supply unit 115, and a readout circuit 116.
  • the substrate 101 is a glass substrate or a semiconductor substrate such as Si.
  • An insulating layer 102 is formed on the substrate 101.
  • a plurality of pixel electrodes 104 and one or more connection electrodes 103 are formed on the surface of the insulating layer 102.
  • the photoelectric conversion layer 107 generates an electric charge according to the received light as described above.
  • the photoelectric conversion layer 107 is provided so as to cover the plurality of pixel electrodes 104.
  • the photoelectric conversion layer 107 has a constant film thickness on the pixel electrode 104, but there is no problem even if the film thickness changes outside the pixel portion (outside the effective pixel area).
  • the counter electrode 108 is an electrode facing the pixel electrode 104, and is provided so as to cover the photoelectric conversion layer 107.
  • the counter electrode 108 is formed up to the connection electrode 103 arranged outside the photoelectric conversion layer 107 and is electrically connected to the connection electrode 103.
  • connection unit 106 is embedded in the insulating layer 102 and is a plug or the like for electrically connecting the connection electrode 103 and the counter electrode voltage supply unit 115.
  • the counter electrode voltage supply unit 115 is formed on the substrate 101 and applies a predetermined voltage to the counter electrode 108 via the connection unit 106 and the connection electrode 103. Note that the counter voltage supply unit 115 may be configured not directly on the substrate 101 but directly connected to an external power source.
  • the readout circuit 116 includes the FD, the output transistor 12, the reset transistor 13, and the selection transistor 14 shown in FIG. 1, and is wired by a metal wiring (not shown) in the insulating layer 102.
  • the readout circuit 116 is provided on the substrate 101 corresponding to each of the plurality of pixel electrodes 104, and reads out a signal corresponding to the charge collected by the corresponding pixel electrode 104. Note that the reading circuit 116 is shielded from light by a light shielding layer (not shown) disposed in the insulating layer 102.
  • the sealing layer 110 is provided so as to cover the counter electrode 108.
  • the sealing layer 110 is provided in order to prevent the photoelectric conversion layer 107 from being deteriorated by water or oxygen in the atmosphere, and may be formed not by a single layer but by a stack of a plurality of inorganic material films.
  • a laminated film of an AlO x film formed by an atomic layer deposition method (ALCVD method) and a SiO x N y film formed by a chemical vapor deposition method (CVD method) may be used.
  • the color filter 111 is formed at a position facing each pixel electrode 104 on the sealing layer 110.
  • the light shielding layer 113 is formed in a region other than the region where the color filter 111 is provided on the sealing layer 110, and prevents light from entering the photoelectric conversion layer 107 formed outside the effective pixel region.
  • a Bayer color filter can be used as the color filter 111.
  • the color filter is not limited to this, and a complementary color filter or other known color filters can be used.
  • the protective layer 114 is formed on the color filter 111 and the light shielding layer 113, and protects the entire solid-state imaging device.
  • FIG. 3 is a diagram showing an overall configuration including peripheral circuits of the solid-state imaging device 100 shown in FIG.
  • the solid-state imaging device 100 includes a vertical driver 121, a control unit 122, a signal processing circuit 123, a horizontal driver 124, an LVDS 125, a serial conversion unit 126, and a pad 127. It has.
  • the pixel area shown in FIG. 3 represents an area where the pixel portions 10 of the solid-state imaging device 100 shown in FIG. 2 are arranged.
  • a signal line SL for outputting a signal from the output transistor 12 of each pixel unit 10 and the reset drain line RL described above are provided for each column of the pixel unit 10.
  • the feedback control circuit 16 is provided for each column of the pixel unit 10.
  • the control unit 122 includes a timing generator and the like, outputs the frame synchronization signal VD and the row synchronization signal HD, and controls the operation of the vertical driver 121 and the horizontal driver 124 to control the charge signal in the pixel unit 10. It controls reading and the like.
  • the vertical driver 121 outputs a reset pulse RS and a selection pulse RW to the readout circuit 116 based on the frame synchronization signal VD and the row synchronization signal HD output from the control unit 122, and controls the operation of the readout circuit 116.
  • the vertical driver 121 of this embodiment performs preliminary discharge of the FD before discharging the accumulated charge in the so-called FD conventionally performed, and also performs preliminary discharge of the (n + 1) th row at the same time as the discharge of the nth row.
  • the readout circuit 116 is controlled so as to be performed. The preliminary discharge of FD will be described in detail later.
  • the signal processing circuit 123 is provided corresponding to each column of the readout circuit 116.
  • the signal processing circuit 123 includes an ADC circuit that performs correlated double sampling (CDS) processing on the signals output from the corresponding columns and converts the processed signals into digital signals.
  • CDS correlated double sampling
  • the signal processed by the signal processing circuit 123 is stored in a memory provided for each column.
  • the horizontal driver 124 performs control to sequentially read out signals for one row of the pixel unit 10 stored in the memory of the signal processing circuit 123 and output the signals to the LVDS 125.
  • the LVDS 125 transmits a digital signal in accordance with LVDS (low voltage differential).
  • the serial conversion unit 126 converts an input parallel digital signal into a serial signal and outputs it.
  • the pad 127 is an interface used for input / output with the outside.
  • preliminary discharge, discharge, and readout operations are sequentially performed for each row of the pixel unit 10.
  • preliminary discharge, discharge, and readout operations for each row of the pixel unit 10 are performed by sequentially scanning in the column direction of the pixel unit 10.
  • the reading operation here includes both acquisition of signal charges accumulated in the FD after the charge accumulation period after discharge and acquisition of a reset level when the FD is reset after acquisition of the signal charges. Shall be included.
  • FIG. 4 shows an example of preliminary discharge, discharge, and readout timings in the (n ⁇ 1) th row (n is a natural number of 2 or more), the nth row, and the (n + 1) th row of the solid-state imaging device 100 of the present embodiment.
  • FIG. 5 shows reset pulses RS (n ⁇ 1) to RS (n + 1) and selection pulses RW (n ⁇ 1) to RW at the time of preliminary discharge, discharge and reading from the (n ⁇ 1) th row to the (n + 1) th row. (N + 1) is shown.
  • preliminary discharge, discharge, and readout are sequentially performed for the n ⁇ 1th row, the nth row, and the n + 1th row.
  • preliminary discharge of the pixel unit 10 of the n-th row is performed simultaneously with discharge of the pixel unit 10 of the n ⁇ 1-th row
  • reserve of the pixel unit 10 of the n + 1-th row is performed simultaneously with discharge of the pixel unit 10 of the n-th row. Discharge.
  • the n-1th line is discharged simultaneously with the nth preliminary discharge.
  • the reset pulse RS (n-1) for discharging is output from the vertical driver 121 to the pixel unit 10 in the (n-1) th row.
  • the reset transistor 13 of the pixel portion 10 is turned on by the reset pulse RS (n ⁇ 1), the potential of the FD is reset, and the discharge is performed.
  • the selection pulse RW (n ⁇ 1) is output from the vertical driver 121, and the selection transistor 14 of the pixel unit 10 in the (n ⁇ 1) th row is turned on.
  • a preliminary reset pulse RS (n) for preliminary discharge is output from the vertical driver 121 to the pixel unit 10 in the n-th row. Then, as shown in FIG. 6, the reset transistor 13 of the pixel unit 10 is turned on by the preliminary reset pulse RS (n), the potential of the FD is reset, and preliminary discharge is performed.
  • the selection pulse RW (n) is not output from the vertical driver 121, and the selection transistor 14 is not turned on. Accordingly, the potential of the FD of the pixel portion 10 in the n-th row is reset to Vref + Vth (n ⁇ 1) that is the potential of the reset drain line RL.
  • the potential of the FD of the pixel unit 10 in the n-th row changes greatly.
  • the reset transistor 13 is turned on in the pixel unit 10 in the n ⁇ 1th row, the potential of the FD of the pixel unit 10 in the n ⁇ 1th row is fixed. Therefore, the FD of the pixel unit 10 in the (n ⁇ 1) th row is not affected by the potential change of the FD of the pixel unit 10 in the nth row, and a false signal due to coupling between adjacent pixels is not generated.
  • the discharge reset pulse RS (n) for discharge is output from the vertical driver 121 to the pixel unit 10 in the n-th row when the n-th row is discharged. Is done. Then, as shown in FIG. 7, the discharge reset pulse RS (n) turns on the reset transistor 13 of the pixel portion 10, and the potential of the FD is reset to the reference potential again, thereby discharging. At this time, the selection pulse RW (n) is also output from the vertical driver 121, whereby the selection transistor 14 is turned on and feedback control is performed on the potential of the FD of the pixel unit 10 in the n-th row. As a result, the potential of the FD of the pixel unit 10 in the nth row is reset to Vref + Vth (n).
  • the preliminary discharge of the (n + 1) th row is performed simultaneously with the above-mentioned discharge of the nth row.
  • the feedback control of the potential of the FD of the (n + 1) th row is not performed during the preliminary discharge in the (n + 1) th row.
  • the potential of the FD of the pixel unit 10 in the (n + 1) th row is reset to Vref + Vth (n).
  • the potential of the FD of the pixel unit 10 in the (n + 1) th row also changes greatly during the preliminary discharge in the (n + 1) th row, but the reset transistor 13 is turned on in the pixel unit 10 in the nth row.
  • the potential of the FD of the pixel portion 10 is fixed. Therefore, no false signal is generated due to coupling between adjacent pixels.
  • the selection pulse RW (n (n) is applied from the vertical driver 121 to the pixel unit 10 in the n-th row when a predetermined charge accumulation period has elapsed. ) Is output.
  • the selection transistor 14 is turned on by the selection pulse RW (n), whereby the signal charge accumulated in the FD is converted into a voltage signal by the output transistor 12, and the signal line SL is converted into a signal level. Is output.
  • a read reset pulse RS (n) for acquiring a reset level is output from the vertical driver 121 to the pixel unit 10 in the n-th row.
  • the reset transistor 13 of the pixel unit 10 is turned on by this read reset pulse RS (n), and the potential of the FD of the n-th row is feedback-controlled again.
  • the potential of FD is reset to Vref + Vth (n).
  • the read reset pulse RS (n) is turned off, whereby the reset transistor 13 is turned off and a signal immediately after the reset is completed is output to the signal line SL as a reset level.
  • the signal processing circuit 123 calculates a difference between the signal level and the reset level, and uses this difference as an image signal.
  • the potential of the FD in the nth row is reset to Vref + Vth (n ⁇ 1) during preliminary discharge.
  • the potential of the FD in the nth row is reset to Vref + Vth (n). That is, the potential of the FD at the time of preliminary discharge is different from the potential of the FD at the time of discharge and reading.
  • the potential of the FD after preliminary discharge is reset again by the subsequent discharge, there is no practical problem even if this potential is different.
  • the potential of the FD at the time of discharging and reading is the same feedback-controlled potential, and the reset kTC noise is suppressed. Therefore, according to the present embodiment, it is possible to acquire images with less fixed pattern noise and reset kTC noise.
  • a feedback loop is formed by the feedback control circuit 16 when discharging is performed in a predetermined row, and the other rows are connected to the feedback control circuit 16.
  • the discharge of the nth row for which feedback control is performed and the resetting of reading of the rows other than the nth row are performed at different timings.
  • the afterimage suppression effect in the solid-state imaging device of the first embodiment will be described with reference to FIG.
  • the coupling rate between adjacent pixels is assumed to be a%.
  • the description will focus on the nth row.
  • the potential of the FD after discharging the nth row becomes Vref + Vth (n) by the feedback control in the nth row discharging.
  • the potential of the FD of the (n + 1) th row immediately before the discharge of the (n + 1) th row becomes Vref ⁇ Vth (n) because it becomes the potential after the discharge of the nth row.
  • the potential of the FD after discharging the n-th row is Vref + Vth (n) as described above.
  • the FD of the n-th row is in an electrically floating state.
  • the reading of the nth row is performed, and the signal corresponding to the potential of the FD in the above equation is added and read out.
  • the term of the above equation includes the threshold voltage Vth of the output transistor 12 and the feedback control circuit. Only 16 reference voltages Vref are included. That is, since the signal due to the afterimage is not added to the read signal, it is not affected by the afterimage.
  • the charge signal in the nth row is the spare signal in the (n + 1) th row.
  • the potential of the FD in the nth row when the preliminary discharge in the (n + 1) th row is completed can be set to the reference potential Vref + Vth (n).
  • the charge signal in the (n ⁇ 1) th row is not affected by the preliminary discharge in the nth row.
  • the potential of the FD of the (n ⁇ 1) th row when the preliminary discharge is completed can be set to the reference potential Vref + Vth (n ⁇ 1). That is, with such preliminary discharge, the potential of each row before discharge can be made constant, so that the signal superimposed by adjacent pixel coupling is constant regardless of the amount of signal charge accumulated in the adjacent pixel. is there.
  • the present invention is more effective as the coupling rate becomes higher.
  • the coupling rate becomes so large that it cannot be ignored, so the effect of the present invention is remarkable.
  • the solid-state imaging device 100 of the above-described embodiment it is possible to achieve both suppression of the influence of capacitive coupling between adjacent pixels and reduction of reset kTC noise.
  • the afterimage suppression effect can be obtained as described above.
  • the threshold voltage of the output transistor 12 is affected by the coupling between adjacent pixels when each row is discharged. A signal depending on Vth is added to the read signal.
  • the table below shows the signal level and reset level acquired in reading in each row and the image signal which is the difference between them.
  • the solid-state imaging device of the second embodiment is configured so as to cancel the noise caused by the Vth variation of the output transistor 12 as described above.
  • the solid-state imaging device of the second embodiment is configured to further perform a read preliminary reset after discharge of each row in the solid-state imaging device of the first embodiment and before resetting of reading. is there.
  • a reset at the time of reading is referred to as a read reset.
  • FIG. 11 shows an example of preliminary discharge, discharge, read preliminary reset, and read reset timing in the (n ⁇ 1) th row, the nth row, and the (n + 1) th row of the solid-state imaging device of the second embodiment.
  • FIG. 12 shows reset pulses RS (n ⁇ 1) to RS (n + 1) and selection pulses RW (n) at the time of preliminary discharge, discharge, read preliminary reset and read reset from the (n ⁇ 1) th row to the (n + 1) th row. -1) to RW (n + 1) are shown as examples.
  • FIGS. 11 and 12 it is assumed that time progresses from left to right in the upper stage, and then time progresses from left to right in the lower stage.
  • preliminary discharge, discharge, read preliminary reset, and read reset are sequentially performed on the n ⁇ 1th row, the nth row, and the n + 1th row.
  • the nth preliminary discharge is performed simultaneously with the n ⁇ 1th discharge
  • the n + 1th preliminary discharge is performed simultaneously with the nth discharge.
  • the read preliminary reset of the nth row is performed simultaneously with the read reset of the (n ⁇ 1) th row
  • the read preliminary reset of the (n + 1) th row is performed simultaneously with the read reset of the nth row.
  • the signal level of the nth row is acquired immediately before the read preliminary reset of the nth row, and the reset level of the nth row is acquired immediately after the read reset of the (n + 1) th row.
  • the signal level acquisition timing in each row is indicated by a circle, and the reset level acquisition timing is indicated by a cross.
  • the signal level and the reset level are acquired at the same timing as the nth row.
  • FIG. 13 is a diagram illustrating an overall configuration including a peripheral circuit of the solid-state imaging device according to the second embodiment.
  • the solid-state imaging device of the second embodiment is similar to the solid-state imaging device of the first embodiment in the configuration of the pixel unit 10 and the like, and the following points are mainly different from the solid-state imaging device of the first embodiment.
  • the following points are mainly different from the solid-state imaging device of the first embodiment.
  • the solid-state imaging device outputs a reset pulse and a selection pulse corresponding to each drive of preliminary ejection, ejection, signal level acquisition, readout preliminary reset, readout reset, and reset level acquisition in each row described above.
  • Five shift registers are provided.
  • a preliminary discharge shift register 121a includes a preliminary discharge shift register 121a, a discharge shift register 121b, a signal level acquisition / read preliminary reset shift register 121c, a read reset shift register 121d, and a reset level acquisition shift register 121e.
  • These five shift registers output a reset pulse or a selection pulse at a preset timing for each row based on a control signal output from a TG (timing generator) 122a in the control unit 122.
  • signal level acquisition and read preliminary reset are performed in the same row within the same row selection period, they can be performed by a pulse signal from one shift register. Since discharge, readout reset and reset level acquisition are performed in different rows within the same row selection period, a shift register is required for each operation.
  • the signal processing circuit 123 of the solid-state imaging device of the second embodiment has three CDS circuits (correlated doubles) of the first, second, and third CDS circuits 123a, 123b, and 123c for each signal line SL.
  • a sampling processing circuit performs correlated double sampling processing.
  • the first, second, and third CDS circuits 123a, 123b, and 123c are provided for the respective signal lines SL. Note that the number of CDS circuits is not limited to three, and three or more CDS circuits may be provided for each signal line SL.
  • the first, second, and third CDS circuits 123a, 123b, and 123c are sequentially switched at the signal level acquisition timing of each row. For example, when the signal level of the (n ⁇ 1) th row is acquired, the signal level is acquired by the first CDS circuit 123a. When the signal level of the nth row is acquired, the signal level is acquired by the second CDS circuit 123b. When the signal level is acquired, the signal level is acquired by the third CDS circuit 123c. The switching from the first CDS circuit 123a to the third CDS circuit 123c is sequentially repeated every time the signal levels of the three rows are acquired.
  • the signal level of the n-th row is acquired when a predetermined charge accumulation period has elapsed.
  • the selection pulse RW (n) is output from the signal level acquisition / readout preliminary reset shift register 121c to the nth row.
  • the selection transistor 14 of the pixel unit 10 is turned on by the selection pulse RW (n), whereby the signal charge accumulated in the FD is converted into a voltage signal by the output transistor 12 and output as a signal level to the signal line SL.
  • the read preliminary reset of the nth row is performed simultaneously with the read reset of the n ⁇ 1th row.
  • a reset pulse RS (n ⁇ 1) for read reset is output from the read reset shift register 121d to the (n ⁇ 1) th row.
  • the reset pulse RS (n ⁇ 1) turns on the reset transistor 13 in the (n ⁇ 1) th row, resets the potential of the FD, and discharges.
  • the selection pulse RW (n ⁇ 1) is also output, and the selection transistor 14 in the (n ⁇ 1) th row is turned on.
  • a feedback loop is completed for the pixel unit 10 in the n ⁇ 1th row, and the potential of the FD is reset to Vref + Vth (n ⁇ 1).
  • the selection pulse RW (n ⁇ 1) falls after the reset pulse RS (n ⁇ 1) during the read reset. That is, the selection transistor 14 is turned off after the reset transistor 13. This is because if the selection transistor 14 is turned off first, the feedback loop may not be established and the reset level of the FD may fluctuate.
  • the read preliminary reset pulse RS (n) for the read preliminary reset is output from the read preliminary reset shift register 121c to the nth row. Then, as shown in FIG. 14, the read preliminary reset pulse RS (n) turns on the reset transistor 13 in the n-th row, resets the potential of the FD, and performs the read preliminary reset. However, at this time, since the feedback loop is established for the pixel unit 10 in the (n ⁇ 1) th row, the selection pulse RW (n) is not output and the selection transistor 14 is not turned on. Accordingly, the potential of the FD of the pixel portion 10 in the n-th row is reset to Vref + Vth (n ⁇ 1) that is the potential of the reset drain line RL.
  • the read reset of the nth row is performed simultaneously with the read preliminary reset of the (n + 1) th row.
  • the reset transistor 13 and select transistor 14 of the nth row are turned on as shown in FIG.
  • a feedback loop is completed for the pixel unit 10 in the n-th row, and the potential of the FD is reset to Vref + Vth (n).
  • the reset transistor of the (n + 1) th row is turned on and the selection transistor 14 is not turned on, similarly to the read preliminary reset of the nth row described above.
  • the potential of the FD of the pixel unit 10 in the (n + 1) th row changes during the read pre-reset in the (n + 1) th row.
  • the reset transistor 13 since the reset transistor 13 is turned on in the pixel unit 10 in the n-th row, the FD potential of the pixel unit 10 in the n-th row is fixed. Therefore, the FD of the pixel unit 10 in the n-th row is not affected by the potential change of the FD of the pixel unit 10 in the n + 1-th row.
  • the reset level of the nth row is acquired.
  • This reset level is acquired after the read reset of the (n + 1) th row.
  • the reason why the reset level is acquired at such timing is to reduce the influence of the Vth variation of the output transistor 12 to zero when the image signal is acquired by subtracting the reset level from the signal level of the nth row. Details will be described later.
  • the selection pulse RW (n) is output from the reset level acquisition shift register 121e, and only the selection transistor 14 in the nth row is turned on. Is done. As a result, the potential of the FD of the pixel unit 10 in the n-th row is output to the signal line SL as a reset level.
  • the difference between the signal level and the reset level is calculated in the CDS circuit of the signal processing circuit 123, and this difference is acquired as an image signal.
  • the potential of the FD after the discharge of the nth row is affected by the change in the potential of the FD of the (n + 1) th row due to the discharge of the (n + 1) th row.
  • the signal level of the n-th row is acquired at the elapse of a predetermined charge accumulation period.
  • the above-mentioned n rows A signal corresponding to the potential of the FD after the eye is discharged is acquired as a signal level.
  • the read preliminary reset of the n-th row is performed.
  • the read reset of the (n ⁇ 1) -th row is also performed at the same time. Is Vref + Vth (n ⁇ 1) as shown in FIG.
  • the readout reset of the nth row is performed, and the potential of the FD of the nth row becomes Vref + Vth (n) as shown in FIG.
  • the read reset of the (n + 1) th row is performed after the read reset of the nth row and before the acquisition of the reset level of the nth row.
  • the potential of the FD immediately before the read reset of the (n + 1) th row is Vref + Vth (n) by the feedback control of the read reset of the nth row as shown in FIG.
  • the potential of the FD immediately after the read reset of the (n + 1) th row is Vref + Vth (n + 1) as shown in FIG.
  • the FD of the nth row is in an electrically floating state, so that the potential of the FD of the nth row is coupled between adjacent pixels by the read reset of the (n + 1) th row.
  • the potential difference before and after the read reset of the (n + 1) th row ⁇ the coupling rate a% is affected. Therefore, the potential of the FD of the nth row after the read reset of the (n + 1) th row is as shown in FIG.
  • Vref + Vth (n) + ⁇ Vref + Vth (n) ⁇ ⁇ Vref + Vth (n + 1) ⁇ ⁇ a% Vref + Vth (n) + ⁇ Vth (n) ⁇ Vth (n + 1) ⁇ ⁇ a% It becomes.
  • both the signal level and the reset level are Vref + Vth (n) + ⁇ Vth (n) ⁇ Vth (n + 1) ⁇ ⁇ a% Therefore, zero is acquired as the image signal.
  • the table below shows the signal level and reset level acquired in each row and the image signal which is the difference between them.
  • the image signals in all rows can be set to zero.
  • the signal level is acquired before the read preliminary reset of the nth row, and the read preliminary reset of the (n + 1) th row is performed at the same time as the read reset of the nth row. Since the potential is set to Vref + Vth (n) and then the FD potential is set to Vref + Vth (n + 1) by the read reset of the (n + 1) th row, the reset level of the nth row is acquired. In other words, the influence of the Vth variation of the output transistor 12 on the image signal can be canceled.
  • the readout circuit of each pixel unit 10 may be laid out in a pattern having periodicity in the pixel unit column direction.
  • the readout circuit of the pixel portion when laid out in a mirror image relationship, the readout circuit is laid out in a pattern of 2 rows in the column direction, and the coupling capacitance between adjacent pixels is also 2 rows.
  • the capacitive coupling between the pixel units 10 in the nth row (odd row) and the n + 1th row (even row) is relatively large, and the n + 1th row (even row).
  • the (n + 2) -th row (odd-numbered row) pixel portions 10 are relatively small in capacitive coupling.
  • the capacitive coupling between the pixel portions 10 of the (n + 2) th row (odd row) and the (n + 3) th row (even row) becomes relatively large.
  • FIG. 19 shows a change in the potential of the FD when only discharging is performed as in the prior art without performing the above-described preliminary discharge in such a configuration.
  • the figure shows the time variation of the drive and FD potential when imaging is performed under conditions where uniform light is incident on all pixels.
  • a solid line indicates an ideal potential change when there is no capacitive coupling
  • a dotted line indicates an actual potential change.
  • the influence of the discharge of the (n + 1) th row on the potential of the FD of the pixel portions 10 and 20 of the nth row and the discharge of the (n + 3) th row are n + 2 rows.
  • the influence on the FD potential of the pixel portions 10 and 20 of the eye is large, the influence of the discharge of the (n + 2) th row on the potential of the FD of the pixel portions 10 and 20 on the (n + 1) th row is small.
  • the even-numbered lines n + 1 and n + 3 can obtain an output almost equal to the case without capacitive coupling, while the odd-numbered lines n and n + 2 have no capacitive coupling.
  • the output will be very different. That is, even if uniform light is incident on the pixel portions 10 and 20 from the n-th row to the n + 3-th row, the charges read out by the odd-numbered pixel portions 10 and 20 and the even-numbered pixel portions 10 and 20 are read.
  • the magnitudes of the signals are different, and horizontal lines appear every other line on the read image.
  • the influence of the capacitive coupling described above can be suppressed, so that the occurrence of horizontal stripes can be prevented. it can.
  • the readout circuit of the pixel unit 10 is not limited to the 2-row cycle, and may be laid out with a pattern of a 3-row cycle or a 4-row cycle, for example.
  • the capacitive coupling formed between adjacent pixels in the column direction is a pattern that periodically changes in the column direction, it may be laid out in any periodic structure. The effect of the present invention becomes remarkable.
  • the reset transistor 13, the output transistor 12, and the selection transistor 14 are composed of n-channel MOS transistors, and holes are collected by the pixel electrode 104.
  • the present invention is not limited to this, and the reset transistor 13, the output transistor 12, and the selection transistor 14 are configured by p-channel MOS transistors, and electrons are collected by the pixel electrode 104 and a charge signal corresponding to the amount of the electrons is collected. May be read by the signal read circuit 116 formed of a p-channel MOS transistor.
  • holes are collected by the pixel electrode 104 and read out by the signal read circuit 116 formed of an n-channel MOS transistor, or as described above, the pixel electrode
  • the signal read circuit 116 formed of an n-channel MOS transistor, or as described above, the pixel electrode
  • the electrons are collected by the pixel electrode, and this is read out by an n-channel MOS transistor.
  • the voltage amplitude of the FD is large as compared with the case where it is configured to read by a circuit.
  • the FD of the pixel portion 10 of the first and second embodiments is shown in FIG. In this way, the protection circuit 17 may be provided. Since the number of components of the readout circuit 116 increases, the coupling rate increases. However, according to the present embodiment, there is no problem because it is possible to suppress deterioration in image quality due to the coupling rate.
  • the solid-state imaging device of the above-described embodiment can be used for various imaging devices.
  • the imaging device include a digital camera, a digital video camera, an electronic endoscope, and a camera-equipped mobile phone.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

　L'invention concerne un élément d'imagerie à semi-conducteurs sur lequel de multiples unités de pixel sont agencées dans deux dimensions, et un appareil d'imagerie pourvu de l'élément d'imagerie à semi-conducteurs, dans lesquels est obtenu un signal d'image approprié dans lequel l'effet de couplage capacitif formé entre des rangées de pixels adjacentes peut être supprimé de manière adéquate, et le bruit kTC de réinitialisation est réduit. Lorsqu'une charge de signal stockée dans une unité de stockage (FD) d'une unité de pixel (10) est déchargée, la charge de signal stockée dans l'unité de stockage (FD) durant le temps de stockage de charge est obtenue par la suite, l'unité de stockage (FD) est réinitialisée après l'obtention de la charge de signal, et une opération de lecture de stockage de charge pour obtenir le niveau de réinitialisation de l'unité de stockage (FD) est réalisée dans un ordre de rangée, une décharge préliminaire est réalisée avant la décharge pour chaque rangée pour décharger une charge préliminaire provenant de l'unité de stockage (FD), la décharge de la nième rangée (n étant un nombre entier) et la décharge préliminaire de la n+1ième rangée sont réalisées simultanément, et une commande de rétroaction est réalisée au moment de la décharge à l'aide d'un circuit de commande de rétroaction (16) fourni pour chaque ligne de l'unité de pixel.
PCT/JP2014/002873 2013-06-04 2014-05-30 Élément d'imagerie à semi-conducteurs et appareil d'imagerie WO2014196176A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020157035513A KR101760200B1 (ko) 2013-06-04 2014-05-30 고체 촬상 소자 및 촬상 장치

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013117891A JP6134979B2 (ja) 2013-06-04 2013-06-04 固体撮像素子および撮像装置
JP2013-117891 2013-06-04

Publications (1)

Publication Number Publication Date
WO2014196176A1 true WO2014196176A1 (fr) 2014-12-11

Family

ID=52007833

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/002873 WO2014196176A1 (fr) 2013-06-04 2014-05-30 Élément d'imagerie à semi-conducteurs et appareil d'imagerie

Country Status (4)

Country Link
JP (1) JP6134979B2 (fr)
KR (1) KR101760200B1 (fr)
TW (1) TWI611696B (fr)
WO (1) WO2014196176A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109564083A (zh) * 2016-08-30 2019-04-02 英特尔公司 电容式邻近度感测

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6323813B2 (ja) * 2014-12-26 2018-05-16 パナソニックＩｐマネジメント株式会社 撮像装置
CN105744183B (zh) * 2014-12-26 2020-08-11 松下知识产权经营株式会社 摄像装置
KR20180060308A (ko) 2016-11-28 2018-06-07 삼성전자주식회사 이미지 센서

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012147302A1 (fr) * 2011-04-28 2012-11-01 パナソニック株式会社 Dispositif d'imagerie à semi-conducteurs et système de caméra qui utilise ce dernier
JP2013090219A (ja) * 2011-10-19 2013-05-13 Sony Corp 撮像装置および撮像表示システム

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471515A (en) * 1994-01-28 1995-11-28 California Institute Of Technology Active pixel sensor with intra-pixel charge transfer
US5461425A (en) * 1994-02-15 1995-10-24 Stanford University CMOS image sensor with pixel level A/D conversion
US5631704A (en) * 1994-10-14 1997-05-20 Lucent Technologies, Inc. Active pixel sensor and imaging system having differential mode
US5892540A (en) * 1996-06-13 1999-04-06 Rockwell International Corporation Low noise amplifier for passive pixel CMOS imager
US6222175B1 (en) * 1998-03-10 2001-04-24 Photobit Corporation Charge-domain analog readout for an image sensor
US6493030B1 (en) * 1998-04-08 2002-12-10 Pictos Technologies, Inc. Low-noise active pixel sensor for imaging arrays with global reset
JP4444371B1 (ja) 2009-09-01 2010-03-31 富士フイルム株式会社 撮像素子及び撮像装置
JP5714982B2 (ja) * 2011-02-01 2015-05-07 浜松ホトニクス株式会社 固体撮像素子の制御方法
WO2012137445A1 (fr) 2011-04-08 2012-10-11 パナソニック株式会社 Procédé de pilotage de dispositif d'imagerie à semi-conducteurs

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012147302A1 (fr) * 2011-04-28 2012-11-01 パナソニック株式会社 Dispositif d'imagerie à semi-conducteurs et système de caméra qui utilise ce dernier
JP2013090219A (ja) * 2011-10-19 2013-05-13 Sony Corp 撮像装置および撮像表示システム

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109564083A (zh) * 2016-08-30 2019-04-02 英特尔公司 电容式邻近度感测
US11112521B2 (en) 2016-08-30 2021-09-07 Intel Corporation Capacitive proximity sensing

Also Published As

Publication number Publication date
TW201507475A (zh) 2015-02-16
KR20160008632A (ko) 2016-01-22
KR101760200B1 (ko) 2017-07-20
JP2014236422A (ja) 2014-12-15
TWI611696B (zh) 2018-01-11
JP6134979B2 (ja) 2017-05-31

Similar Documents

Publication Publication Date Title
US10567691B2 (en) Solid-state imaging device, method for driving solid-state imaging device, and electronic apparatus
JP6776011B2 (ja) 撮像装置及び撮像システム
US8816266B2 (en) Solid-state imaging device, method for driving solid-state imaging device, and electronic apparatus
JP6727938B2 (ja) 撮像装置、撮像装置の制御方法、及び撮像システム
JP5516960B2 (ja) 固体撮像装置、固体撮像装置の駆動方法、および、電子機器
US8854518B2 (en) Solid-state imaging device, method of driving the same, and electronic system including the device
TWI495341B (zh) Solid state camera device
WO2013140872A1 (fr) Dispositif d'imagerie à semi-conducteurs et équipement électronique
US9560285B2 (en) Image pickup apparatus and image pickup system
US10645327B2 (en) Solid-state imaging device, method for driving solid-state imaging device, and electronic apparatus
JP6351423B2 (ja) 撮像装置及び撮像システム
JP2014078870A (ja) 固体撮像素子および撮像装置
WO2011083541A1 (fr) Dispositif de capture d'image à semi-conducteurs et dispositif de capture d'image
WO2014196176A1 (fr) Élément d'imagerie à semi-conducteurs et appareil d'imagerie
JP6195728B2 (ja) 固体撮像素子および撮像装置
JP2007129473A (ja) 固体撮像装置及び撮像システム
WO2011105018A1 (fr) Dispositif d'imagerie à semi-conducteurs et système de caméra
JP6217338B2 (ja) 固体撮像素子及び撮像装置
JP5893372B2 (ja) 固体撮像装置、撮像装置、および信号読み出し方法
JP7160129B2 (ja) 撮像素子および撮像装置
JP7198675B2 (ja) 固体撮像素子、その駆動回路および撮像装置
JP2013197697A (ja) 固体撮像装置及び電子機器
JP2015076722A (ja) 固体撮像素子および撮像装置
JP5945463B2 (ja) 固体撮像装置
WO2015111370A1 (fr) Dispositif de prise de vues à semi-conducteur, et dispositif de prise de vues à semi-conducteur

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14807061

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20157035513

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 14807061

Country of ref document: EP

Kind code of ref document: A1