WO2011083541A1 - Dispositif de capture d'image à semi-conducteurs et dispositif de capture d'image - Google Patents

Dispositif de capture d'image à semi-conducteurs et dispositif de capture d'image Download PDF

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Publication number
WO2011083541A1
WO2011083541A1 PCT/JP2010/007419 JP2010007419W WO2011083541A1 WO 2011083541 A1 WO2011083541 A1 WO 2011083541A1 JP 2010007419 W JP2010007419 W JP 2010007419W WO 2011083541 A1 WO2011083541 A1 WO 2011083541A1
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Prior art keywords
pixel
row
row selection
signal
imaging device
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PCT/JP2010/007419
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English (en)
Japanese (ja)
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剛 曽和
邦彦 原
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パナソニック株式会社
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H04N25/42—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the present invention relates to a solid-state imaging device in which pixels that photoelectrically convert incident light are two-dimensionally arranged on a semiconductor substrate, and particularly to achieve a solid-state imaging device that can obtain a high-quality pixel mixture image.
  • MOS Metal Oxide Semiconductor
  • DSLR digital single-lens reflex cameras
  • FIG. 16 is a diagram showing an overall configuration of a conventional solid-state imaging device described in Patent Document 1.
  • the solid-state imaging device shown in FIG. 1 includes an imaging unit 200, pixels 202, and a pixel readout circuit 250.
  • the pixel 202 includes a photodiode 211, a reset transistor 214, an amplification transistor 215, and a selection transistor 216.
  • the pixel readout circuit 250 includes a current source 253, a ground connection transistor 254, a load transistor 255, and a power supply connection transistor 256.
  • a first vertical wiring 221 and a second vertical wiring 222 are provided as output wirings for pixel signals, and a first pixel output 257 and a second pixel output 258 are provided as output terminals.
  • the ground connection transistor 254 is turned off and the power connection transistor 256 is turned on.
  • a current source 253 is connected to the source / drain terminal on the selection transistor side of the amplification transistor 215 of the pixel via the first vertical wiring 221, and a power source is connected to the source / drain terminal on the opposite side via the second vertical wiring 222.
  • the amplification transistor 215 and the current source 253 of the pixel 202 function as a source follower amplifier, and a pixel signal is read from the first pixel output 257. At this time, if pixel signals are read by sequentially turning on the selection transistors 216 row by row, the signals of all the pixels 202 are read.
  • the ground connection transistor 254 is turned on and the power supply connection transistor 256 is turned off.
  • a load transistor 255 is connected to the source / drain terminal on the selection transistor 216 side of the amplification transistor 215 of the pixel 202 via the first vertical wiring 221 and a load transistor 255 is connected to the opposite source / drain terminal via the second vertical wiring 222.
  • the amplification transistor 215 and the load transistor 255 of the pixel 202 function as a source-grounded amplifier, and if two rows of selection transistors 216 are simultaneously turned on, a mixed signal of two upper and lower pixels is obtained from the second pixel output 258. If the pixel signals are read by sequentially turning on the selection transistors 216 two rows at a time, the mixed signal of the entire imaging unit 200 is read.
  • the imaging unit 200 includes an effective part used as image information in the camera and a peripheral part such as a light-shielding pixel arranged around the effective part.
  • the operation of each drive mode is the same in the effective part and the peripheral part.
  • correction data is generated from an output signal of a light-shielded pixel arranged in the peripheral portion of the image pickup unit, and correction is performed by a digital signal processor in the subsequent stage.
  • the number of rows for creating correction data in the pixel mixture mode is significantly smaller than that in the all-pixel readout mode. Since the pixel readout signal includes random noise due to power fluctuation, device-specific noise, and the like, a reduction in the number of correction lines leads to a reduction in accuracy of the correction data, resulting in a problem that image quality is deteriorated.
  • an object of the present invention is to provide a solid-state imaging device that suppresses a reduction in accuracy of correction data in the pixel mixing mode.
  • a solid-state imaging device is a pixel row including an imaging unit having a plurality of pixels arranged in a two-dimensional manner and the plurality of pixels arranged in a horizontal direction.
  • a row selection circuit that selects a pixel circuit, a column circuit unit that temporarily holds pixel signals output from the plurality of pixels of the selected pixel row, and a row that designates a pixel row to be selected during a single row readout period
  • a controller that supplies an address signal to the row selection circuit, wherein the plurality of pixels includes a plurality of first pixels that output a pixel signal corresponding to the amount of received light, and a plurality of second pixels that output a fixed pixel signal.
  • the imaging unit includes an effective unit in which the plurality of first pixels are arranged and a peripheral unit in which the plurality of second pixels are arranged, and in at least one of the driving modes,
  • the control unit corresponds to the effective unit.
  • the first row selection sequence including the row address signal and the second row selection sequence including the row address signal corresponding to the peripheral portion are simultaneously specified in the first row selection sequence and the second row selection sequence.
  • the number of pixel rows to be generated or the number of times each row is designated is generated and supplied to the row selection circuit.
  • the driving mode of the solid-state imaging device is a pixel mixing mode that mixes and outputs the pixel signals of the effective part, it can be output without reducing the number of pixel signals in the peripheral part obtained as correction data. It is possible to suppress a decrease in accuracy of the business data.
  • control unit is configured such that the number of pixel rows designated in a single row readout period in the first row selection sequence is a pixel row designated in a single row readout period in the second row selection sequence.
  • the first row selection sequence and the second row selection sequence may be generated so as to be greater than
  • control unit may be configured such that the number of times each pixel row is designated by the first row selection sequence is smaller than the number of times each pixel row is designated by the second row selection sequence in one frame period.
  • the first row selection sequence and the second row selection sequence may be generated.
  • the number of pixel rows from which pixel signals are simultaneously read out is small, or the number of times each pixel row is designated increases. Even in the pixel mixing mode in which signals are mixed and output, it is possible to suppress a decrease in accuracy of the correction data.
  • the control unit designates two or more pixel rows as a single row readout period, and in the second row selection sequence, reads one pixel row as a single row. You may make it designate in a period.
  • pixel signals of two or more pixel rows are mixed and output when reading the pixel signals of the effective portion, and pixel signals of the pixel rows are output one by one when reading the pixel signals of the peripheral portion. Therefore, the pixel signals of the peripheral pixel rows used for generating the correction data are output without being mixed. Thereby, it is possible to suppress a decrease in accuracy of the correction data without reducing the number of correction data in the pixel mixing mode.
  • control unit designates two or more pixel rows in a single row readout period in the first row selection sequence, and pixels designated in the first row selection sequence in the second row selection sequence. Two or more pixel rows different from the number of rows may be designated in a single row readout period.
  • the control unit designates two or more pixel rows as a single row readout period
  • the control unit designates the Nth pixel row (N is an integer of 1 or more).
  • N is an integer of 1 or more
  • M is an integer equal to or greater than 1 and M ⁇ N
  • the Nth pixel row is changed multiple times by changing the value of M in one frame period. You may make it specify.
  • the pixel signals of the Nth pixel row and the Mth pixel row are mixed and output when reading out the pixel signals of the effective portion and the peripheral portion, the pixel signals are efficiently output by reducing the number of times of reading. Obtainable.
  • the pixel signals of the Nth pixel row and the Mth pixel row are mixed and output a plurality of times in different combinations, so that the correction data is generated even in the pixel mixture mode. The accuracy of correction data can be prevented from decreasing without reducing the number of peripheral pixel signals used for the correction.
  • the plurality of times may be two times.
  • the pixel signals in the Nth pixel row and the Mth pixel row are mixed and each pixel is designated twice. It is possible to obtain the same number of pixel signals as when reading out one row at a time. Therefore, regardless of the difference in driving mode, there is no concern that an offset will occur in the output even in the pixel mixing mode compared to the mode in which pixel mixing is not performed, and the correction data is created with high accuracy. Can do.
  • the size of the parasitic component of the circuit is the same as that in the mode in which pixel mixing is not performed, and it is possible to suppress a reduction in accuracy of correction data in the pixel mixing mode without increasing power consumption.
  • the second pixel may include a light-shielded light-shielded pixel or a reference voltage output pixel that outputs a reference voltage.
  • the pixel signal output from the second pixel can be accurately set to a constant value.
  • peripheral part may be arranged on the peripheral side of the imaging unit with respect to the effective part.
  • an imaging device includes a solid-state imaging device having the above-described characteristics and a digital that performs correction processing on the pixel signal of the effective portion output from the solid-state imaging device.
  • a signal processing unit, and a storage unit that holds the pixel signal of the peripheral part output from the solid-state imaging device and the correction data generated using the pixel signal of the peripheral part.
  • the solid-state imaging device According to the solid-state imaging device according to the present invention, it is possible to suppress a reduction in accuracy of correction data in the pixel mixing mode.
  • FIG. 1 is a diagram illustrating an overall configuration of a solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 2 is a diagram illustrating a configuration of the pixel in FIG.
  • FIG. 3 is a diagram showing the configuration of the column circuit section in FIG.
  • FIG. 4 is a diagram showing the configuration of the multiplexer and column selection circuit in FIG.
  • FIG. 5 is a diagram showing a configuration of the row selection circuit in FIG.
  • FIG. 6 is a timing chart showing the reading operation of the pixel signal of the effective portion in the all-pixel reading mode.
  • FIG. 7 is a timing chart showing the reading operation of the pixel signal of the effective portion in the vertical 2-pixel horizontal 2-pixel mixed read mode.
  • FIG. 8A and 8B are diagrams showing a row selection sequence in the all-pixel readout mode, where FIG. 8A is a diagram showing row numbers of each row in the effective portion and the peripheral portion, and FIG. 8B is a sequence of row address signals supplied to each row.
  • FIG. FIG. 9 is a diagram showing a row selection sequence in the vertical two-pixel horizontal two-pixel mixed readout mode, where (a) shows the row numbers of the rows in the effective portion and the peripheral portion, and (b) is supplied to each row. It is a figure which shows the sequence of a row address signal.
  • FIG. 10 is a diagram showing a row selection sequence in the vertical two-pixel horizontal two-pixel mixed readout mode of the solid-state imaging device according to the second embodiment of the present invention.
  • FIG. 10 is a diagram showing a row selection sequence in the vertical two-pixel horizontal two-pixel mixed readout mode of the solid-state imaging device according to the second embodiment of the present invention.
  • FIG. 10A is a row of each row in the effective portion and the peripheral portion.
  • the figure which shows a number and (b) are the figures which show the sequence of the row address signal supplied to each row.
  • FIG. 11 is a diagram illustrating an overall configuration of a solid-state imaging device according to the third embodiment of the present invention.
  • FIG. 12 is a diagram showing the configuration of the column ADC in FIG.
  • FIG. 13 is a timing chart showing the operation of the column ADC.
  • FIG. 14 is a diagram illustrating a configuration of an imaging apparatus according to the fourth embodiment of the present invention.
  • FIG. 15 is a flowchart of the imaging operation of the imaging apparatus in FIG.
  • FIG. 16 is a diagram illustrating a configuration of a solid-state imaging device in the related art.
  • an imaging unit having a plurality of pixels arranged two-dimensionally, a row selection circuit that selects a pixel row composed of a plurality of pixels arranged in the horizontal direction, and the selected pixel row
  • a column circuit unit that temporarily holds pixel signals output from the plurality of pixels
  • a control unit that supplies a row address signal specifying a pixel row to be selected to the row selection circuit during a single row readout period.
  • the plurality of pixels include a plurality of first pixels that output pixel signals corresponding to the amount of received light, and a plurality of second pixels that output a fixed pixel signal
  • the imaging unit includes a plurality of first pixels.
  • the control unit includes a first row selection sequence including a row address signal corresponding to the effective unit, and a peripheral portion in which a plurality of second pixels are arranged. Second including a row address signal corresponding to the peripheral portion
  • a solid-state imaging device that generates a selection sequence so that the number of pixel rows specified simultaneously in the first row selection sequence and the second row selection sequence, or the number of times each row is specified differs, and supplies the selection sequence to the row selection circuit Will be described.
  • the driving mode of the solid-state imaging device is a pixel mixing mode in which the pixel signals of the effective portion are mixed and output
  • the output can be performed without reducing the number of pixel signals in the peripheral portion obtained as correction data. It is possible to suppress a decrease in accuracy of the business data.
  • FIG. 1 is a diagram showing an overall configuration of a solid-state imaging device 1 according to the first embodiment of the present invention.
  • the solid-state imaging device 1 includes an imaging unit 2 in which a plurality of pixels 11a and 11b are two-dimensionally arranged, a row selection circuit 3, a pixel current source circuit 4, a clamp circuit 5, and a sample hold (S / H).
  • the circuit 6 includes a multiplexer (MUX) 7, a column selection circuit 8, a control unit 9, an output amplifier 10, a vertical signal line 19, and a horizontal common signal line 39.
  • MUX multiplexer
  • the imaging unit 2 includes a pixel row including pixels 11 a and 11 b arranged in the horizontal direction, and includes an effective unit 16 and a peripheral unit 17.
  • the effective portion 16 pixels 11 a that photoelectrically convert incident light and output pixel signals according to the amount of received light are arranged in a two-dimensional manner.
  • the peripheral portion 17 is provided adjacent to the effective portion 16, and pixels 11 b that output a constant pixel signal are arranged in the peripheral portion 17.
  • the pixel 11b is a light-shielded pixel that is shielded in advance.
  • the pixel 11b is not limited to a light-shielded pixel, and may be a reference voltage output pixel that outputs a constant reference voltage.
  • the pixel 11a and the pixel 11b correspond to the first pixel and the second pixel in the present invention.
  • FIG. 1 shows an example of 24 pixels arranged in a 6 ⁇ 4 two-dimensional shape as an example, but the actual total number of pixels is several million or more.
  • the peripheral portion 17 is not limited to being provided at a position adjacent to one side of the effective portion 16 as shown in the figure.
  • the peripheral portion 17 is disposed on the peripheral side of the imaging portion 2 so as to surround the effective portion 16. Also good.
  • the pixel current source circuit 4 includes a pixel current source circuit basic unit 4a in each column in an array (see FIG. 3 to be described later), and supplies pixel signals output from the pixels 11a and 11b to the clamp circuit 5.
  • the clamp circuit 5 includes a basic unit 5a of the clamp circuit in each column in an array, and a fixed pattern generated in the pixels 11a and 11b from the pixel signal output from the pixel current source circuit 4 via the vertical signal line 19. Remove noise components.
  • the sample hold circuit 6 includes a basic unit 6a of the sample hold circuit in each column in an array, and holds the pixel signal output from the clamp circuit 5.
  • the pixel current source circuit 4, the clamp circuit 5, and the sample hold circuit 6 constitute a column circuit unit 20.
  • the multiplexer 7 switches the connection between the sample hold circuit 6 and the output amplifier 10.
  • the column selection circuit 8 includes a column selection signal line 40 and sequentially selects columns of the multiplexer 7 (see FIG. 4 described later).
  • the output amplifier 10 receives the output signal of the sample hold circuit 6 from the multiplexer 7 via the horizontal common signal line 39, amplifies it, and outputs it.
  • control unit 9 supplies the row selection circuit 3 with a row address signal ADR that selects pixels in units of pixel rows in accordance with the drive mode for driving the solid-state imaging device 1 and the region of the imaging unit 2 that performs readout.
  • the first row selection sequence including the row address signal corresponding to the valid portion 16 and the second row selection sequence including the row address signal corresponding to the peripheral portion 17 are divided into the first row selection sequence and the second row selection sequence.
  • the number of pixel rows specified simultaneously in the row selection sequence or the number of times each row is specified is generated and supplied to the row selection circuit 3.
  • FIG. 2 is a circuit diagram showing details of the pixels 11a arranged in the effective unit 16 of the imaging unit 2.
  • the pixel 11a includes a photodiode (PD) 21 that photoelectrically converts incident light and outputs a charge, a floating diffusion (FD) 23 that accumulates the charge generated by the photodiode 21, and outputs the accumulated charge as a voltage signal.
  • PD photodiode
  • FD floating diffusion
  • the reset transistor (reset Tr) 24 that resets the voltage indicated by the floating diffusion 23 to the initial voltage (VDD in this case), and the transfer transistor (transfer Tr) that supplies the charge output from the photodiode 21 to the floating diffusion 23 ) 22, an amplification transistor (amplification Tr) 25 that outputs a voltage that changes following the voltage indicated by the floating diffusion 23, and the output of the amplification transistor 25 when a row selection signal is received from the row selection circuit 3.
  • the supplied selection transistor includes a (selection Tr) 26, and a power supply line 27 for supplying a power supply voltage to the source or drain of the reset transistor 24 and amplifying transistor 25.
  • the pixel 11b has the same configuration as the pixel 11a.
  • the selection circuit 3 gives a row selection signal for line selection, a pixel reset signal for reset, and a charge transfer signal for read, and controls each operation.
  • the pixel circuit configuration of the pixel 11a of the effective portion 16 and the pixel 11b of the peripheral portion 17 are the same, but the pixel 11b of the peripheral portion 17 is a light-shielded pixel in which the photodiode 21 is shielded in advance. As a result, an output signal in a dark state is always obtained from the pixel 11b. Thereby, the pixel 11b outputs the reset voltage obtained by amplifying the voltage at the time of initialization and the read voltage obtained by amplifying the voltage at the time of reading (output voltage in the dark state) to the vertical signal line 19.
  • the pixel 11a includes a plurality of photodiodes 21 in a unit cell, and further has a structure in which any one or all of the floating diffusion 23, the reset transistor 24, and the amplification transistor 25 are shared in the unit cell, so-called many. You may have a pixel 1 cell structure.
  • the pixel 11a may constitute a so-called back-illuminated image sensor (back-illuminated solid-state imaging device) structure in which the pixel 11a is formed on the gate and wiring of the transistor and on the back surface side.
  • the pixel 11b is the same as the pixel 11a.
  • FIG. 3 is a diagram showing details of the column circuit unit 20 according to the first embodiment of the present invention, which includes the pixel current source circuit 4, the clamp circuit 5, and the sample hold circuit 6.
  • the function of the column circuit unit 20 is to temporarily hold a pixel signal indicated by the difference between the reset voltage and the read voltage output from the imaging unit 2 and then output the pixel signal to the multiplexer 7.
  • the basic unit 4a of the pixel current source circuit 4 includes a current source transistor 30 that supplies current to the amplification transistor 25 when a pixel signal is read from the pixels 11a and 11b, and a current source transistor. And a bias terminal 31 for supplying a current source bias potential to 30 gates.
  • the basic unit 5a of the clamp circuit 5 includes a sampling transistor 32 that inputs a pixel signal output from the pixel current source circuit 4, and a difference between a reset signal and a read signal from the input pixel signal.
  • a clamp capacitor 33 (capacitance value Ccl) for obtaining a pixel signal indicated by the following: a clamp voltage input terminal 35 for setting a terminal potential on the opposite side of the clamp capacitor 33 to a clamp potential (VCL); a clamp capacitor 33 and a clamp A clamp transistor 34 that switches connection with the voltage input terminal 35 is provided.
  • the sample hold circuit 6 has a basic unit 6a of the sample hold circuit in each column.
  • the basic unit 6a of the sample and hold circuit includes an S / H capacitor input transistor 36 for inputting the pixel signal output from the clamp circuit 5, and an S / H capacitor 37 (capacitance value Csh) for temporarily holding the pixel signal.
  • an S / H capacitor input signal is supplied to the gate of the S / H capacitor input transistor 36, the pixel signal output from the clamp circuit 5 is held in the S / H capacitor 37.
  • FIG. 4 is a diagram showing details of the multiplexer 7, the column selection circuit 8, and the output amplifier 10.
  • the multiplexer 7 has a multiplexer basic unit 7a in each column.
  • the basic unit 7 a of the multiplexer includes a column selection transistor 38, and each column selection transistor 38 is connected to a horizontal common signal line 39. That is, the column selection transistor 38 is arranged between each S / H capacitor 37 of the S / H circuit 6 and the horizontal common signal line 39.
  • the column selection transistor 38 sequentially applies the pixel signal held in the S / H capacitor 37 for each column in accordance with the column selection signal H [k] supplied to the gate. Output to 39.
  • the signal supplied to the output amplifier 10 via the horizontal common signal line 39 is amplified and then output to the outside of the solid-state imaging device 1 formed on the chip.
  • FIG. 5 is a diagram showing details of the row selection circuit 3.
  • the row selection circuit 3 includes an address decoder 41 and a row selection logic circuit 42 arranged for each row.
  • the address decoder 41 outputs a Hi (High) level signal to the row selection logic circuit 42 of the corresponding row in accordance with the row address signal supplied from the control unit 9.
  • the write enable signal WE of the flip-flop (FF) 43 of the corresponding row selection logic circuit 42 is input from the control unit 9, a Hi level signal is set in the flip-flop 43, and the row is selected. become.
  • the solid-state imaging device 1 is characterized by including an all-pixel readout mode that can be used for camera still photography and a pixel mixture mode that can be used for a moving image recording function as drive modes.
  • the signal reading operation of the effective unit 16 of the imaging unit 2 will be described.
  • FIG. 6 is a diagram illustrating the timing of each control signal supplied to the imaging unit 2 and the column circuit unit 20 in the readout operation of the effective unit 16 in the all-pixel readout mode.
  • the row selection signal supplied to the control line SEL [1] is at the Hi level, and the first row of the pixel rows is selected.
  • the charge transfer signal supplied to the control line TRAN [1] is Lo level, and the pixel reset signal supplied to the control line RST [1] is Hi level.
  • the charge transfer signal and the pixel reset signal supplied to the control line TRAN [1] and the control line RST [1] are at the Lo level. That is, since the transfer transistor 22 and the reset transistor 24 are off, the reset state of the FD potential is maintained.
  • the row selection signal supplied to the control line SEL [1] is at the Hi level, that is, the selection transistor 26 is on. Therefore, assuming that the threshold voltage of the amplification transistor 25 is Vth, Vfdrst ⁇ Vth is vertical as the reset voltage. It is output to the signal line 19 (precisely Vfdrst ⁇ Vth ⁇ , but ⁇ is omitted here).
  • both the clamp signal (gate signal of the clamp transistor 34) and the sampling signal (gate of the S / H capacitor input transistor 36) are at the Hi level, that is, the clamp transistor 34 and the S / H capacitor input. Since the transistor 36 is on, the other terminal of the clamp capacitor 33 and the potential of the S / H capacitor 37 are set to the clamp potential VCL.
  • the charge transfer signal supplied to the control line TRAN [1] is at the Hi level, that is, the transfer transistor 22 is turned on, so that the charge accumulated in the photodiode 21 is transferred to the floating diffusion 23, and at Vfdrst
  • the existing FD potential Vfd is lowered by a voltage Vfdsig corresponding to the signal charge amount, and becomes Vfdrst ⁇ Vfdsig.
  • the charge transfer signal supplied to the control line TRAN [1] is Lo level
  • the row selection signal supplied to the control line SEL [1] is Hi level, that is, the transfer transistor 22 is off and the selection transistor 26 is off.
  • Vfdrst ⁇ Vfdsig ⁇ Vth is output to the vertical signal line 19 as a read voltage.
  • the input voltage of the clamp capacitor 33 changes by Vfdsig.
  • the potential of the other terminal of the clamp capacitor 33 (capacitance value: Ccl), that is, the potential of the S / H capacitor 37 (capacitance value: Csh) is It changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, a pixel signal.
  • the sampling signal becomes Lo level, and this pixel signal is accumulated in the S / H capacitor 37. As described above, the pixel signals for one row are held in the sample hold circuit 6.
  • the column selection signal H [1] of the first column of the column selection circuit 8 becomes Hi level, and the column selection transistor 38 of the first column of the multiplexer 7 is turned on.
  • the signal of the S / H capacitor 37 in the first column is output to the horizontal common signal line 39 and output to the outside via the output amplifier 10.
  • the column selection signal H [2] of the second column becomes Hi level, and the column selection transistor 38 of the second column of the multiplexer 7 is turned on.
  • the signal of the S / H capacitor 37 in the second column is output to the horizontal common signal line 39 and output to the outside via the output amplifier 10.
  • the column selection signal of each column of the column selection circuit 8 is set to Hi level, the signal of the S / H capacitor 37 of each column is sequentially output.
  • FIG. 7 is a diagram illustrating the timing of each control signal supplied to the imaging unit 2 and the column circuit unit 20 in the read operation of the effective unit 16 in the vertical 2-pixel horizontal 2-pixel mixing mode as an example of the pixel mixing mode. .
  • the row selection signal supplied to the control lines SEL [1] and SEL [2] is at the Hi level, and the first and second rows are selected. Further, the charge transfer signal supplied to the control lines TRAN [1] and TRAN [2] is Lo level, and the pixel reset signal supplied to the control lines RST [1] and RST [2] is Hi level, that is, one row.
  • the respective row address signals are sequentially supplied to the address decoder 41 of the row selection circuit 3, and the row selection logic circuit 42. This can be achieved by sequentially setting the selection states in the flip-flops 43.
  • the charge transfer signal and the pixel reset signal supplied to the control lines TRAN [1] and TRAN [2] and the control lines RST [1] and RST [2] are at the Lo level, that is, the first and second rows. Since the transfer transistor 22 and the reset transistor 24 of the eye are off, the reset state of the FD potential is maintained.
  • the row selection signals supplied to the control lines SEL [1] and SEL [2] are at the Hi level, that is, the selection transistors 26 in the first and second rows are on, so that Vfdrst ⁇ Vth is used as the reset voltage. It is output to the vertical signal line 19 (precisely Vfdrst ⁇ Vth ⁇ , but ⁇ is omitted here).
  • the reset voltage Vfdrst ⁇ Vth is output to one terminal of the clamp capacitor 33 of the clamp circuit 5 through the vertical signal line 19.
  • both the clamp signal (gate signal of the clamp transistor 34) and the sampling signal (gate signal of the S / H capacitor input transistor 36) are at the Hi level, that is, the clamp transistor 34 and the S / H capacitor. Since the input transistor 36 is on, the other terminal of the clamp capacitor 33 and the potential of the S / H capacitor 37 are set to the clamp potential VCL.
  • the charge transfer signals supplied to the control lines TRAN [1] and TRAN [2] are at the Hi level, that is, the transfer transistors 22 in the first row and the second row are turned on.
  • the charges accumulated in the photodiodes 21 in the row are transferred to the floating diffusion 23, and the respective FD potentials Vfd1 and Vfd2 are reduced by voltages Vfdsig1 and Vfdsig2 corresponding to these signal charge amounts, and Vfdrst ⁇ Vfdsig1 and Vfdrst ⁇ Vfdsig2.
  • the charge transfer signals supplied to the control lines TRAN [1] and TRAN [2] are at the Lo level, and the row selection signals supplied to the control lines SEL [1] and SEL [2] are at the Hi level.
  • Vfdrst ⁇ Vfdsig ⁇ Vth is output to the vertical signal line 19 as a read voltage.
  • This read signal corresponds to the mixed signal in the first and second rows. Due to the potential change of the vertical signal line 19, the input of the clamp capacitor 33 also changes by Vfdsig.
  • the clamp transistor 34 since the clamp transistor 34 is off, the potential of the other terminal of the clamp capacitor 33, that is, the potential of the S / H capacitor 37 changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, an averaged pixel signal (vertical pixel mixed signal) in the first and second rows.
  • the row selection signal and the sampling signal supplied to the control lines SEL [1] and SEL [2] are set to the Lo level, and the vertical mixed pixel signals of the selected first row and second row are S / S. Accumulated in the H capacity 37.
  • the sampling signal is at the Lo level
  • the column selection signals H [1] and H [2] of the first column and the second column of the column selection circuit 8 are at the Hi level
  • the first column of the multiplexer 7 The column selection transistor 38 in the second column is turned on.
  • the averaged pixel signal (horizontal pixel mixed signal) of the S / H capacitor 37 in the first column and the S / H capacitor 37 in the second column is output to the horizontal common signal line 39, via the output amplifier 10.
  • Output to the outside That is, a vertical two-pixel horizontal two-pixel mixed signal in which pixel signals of the pixels in the first and second columns of the first and second rows are mixed is output.
  • the column selection signals H [3] and H [4] for the third column and the fourth column are set to the Hi level, and the column selection transistors 38 for the third column and the fourth column of the multiplexer 7 are turned on.
  • the horizontal pixel mixed signal of the S / H capacitor 37 in the third column and the S / H capacitor 37 in the fourth column is output to the horizontal common signal line 39, and the first and second rows are output via the output amplifier 10.
  • a vertical 2-pixel horizontal 2-pixel mixed signal obtained by mixing the pixel signals of the pixels in the third and fourth columns is output to the outside.
  • the column selection signal of each column of the column selection circuit 8 is set to Hi level, the signal of the S / H capacitor 37 of each column is sequentially output.
  • the clamp potential VCL of the column circuit unit 20 has a distribution in the horizontal direction, and as a result, the reference potential of each column is different for each column. This means that nonuniformity in the horizontal direction occurs in the dark state output that is the reference of the output image, and horizontal shading occurs in the image.
  • FIG. 8 is a row selection sequence showing the supply timing of the row address signal supplied from the control unit 9 to the row selection circuit 3 in the all-pixel readout mode.
  • a row selection sequence for one frame period in which pixel signals for one screen are output is shown by taking the imaging unit 2 of 16 rows as an example.
  • FIG. 5A shows the row numbers of the pixel rows corresponding to the effective portion 16 and the peripheral portion 17.
  • Line numbers 1 to 10 indicate the peripheral portion 17, and line numbers 11 to 16 indicate the effective portion 16.
  • FIG. 4B shows a sequence of row address signals supplied to each row having the row number shown in FIG. 2A.
  • the sequence corresponding to the row numbers 11 to 16 is the first row selection.
  • the sequence corresponding to the row numbers 1 to 10 is the second row selection sequence.
  • a period during which one row address signal is output is a row reading period. Since signals other than the row address signal are the same as those in FIG. 6, the description thereof is omitted here.
  • one row address signal is output in a single row readout period in both the first row selection sequence and the second row selection sequence in one frame period.
  • Sequence that is, a sequence including row address signals for sequentially designating one pixel row at a time.
  • the row selection circuit 3 sequentially selects the pixels 11a of the effective portion 16 from the row numbers 11 to 16 one by one in order, and the peripheral portion 17 similarly to the effective portion 16 has the pixels 11b of the peripheral portion 17 as well.
  • FIG. 9 is a row selection sequence showing the supply timing of the row address signal supplied from the control unit 9 to the row selection circuit 3 in the vertical 2-pixel horizontal 2-pixel mixing mode which is an example of the pixel mixing mode.
  • FIG. 8A shows the row numbers of the pixel rows corresponding to the effective portion 16 and the peripheral portion 17 as in FIG.
  • Line numbers 1 to 10 indicate the peripheral portion 17, and line numbers 11 to 16 indicate the effective portion 16.
  • FIG. 4B shows a sequence of row address signals supplied to each row having the row number shown in FIG. 2A.
  • the sequence corresponding to the row numbers 11 to 16 is the first row selection.
  • the sequence corresponding to the row numbers 1 to 10 is the second row selection sequence. Since signals other than the row address signal are the same as those in FIG. 7, the description thereof is omitted here.
  • the first row selection sequence a sequence in which two different row address signals are output in a single row readout period, that is, two pixels.
  • a sequence including a row address signal that sequentially designates each row is formed.
  • the second row selection sequence a sequence in which one pixel row is designated in a single row readout period, that is, a sequence including a row address signal that designates one row at a time is configured. Therefore, the first row selection sequence and the second row selection sequence differ in the number of pixel rows specified at the same time.
  • the row selection circuit 3 selects two rows from the row numbers 11 to 16 simultaneously in the valid portion 16 and selects one row from the row numbers 1 to 10 in the peripheral portion 17 one by one.
  • pixel signals used for correction data having the same number of physical pixel rows as that of the peripheral portion 17 can be obtained. This means that correction data of a plurality of rows can be obtained in the pixel mixture mode as well as the all-pixel readout mode, and horizontal shading correction data can be created with high accuracy.
  • the pixel signals of the peripheral portion 17 can be output without being mixed in accordance with the mixing of the pixel signals of the effective portion 16.
  • the number of pixel rows in the peripheral portion 17 is the same as in the prior art, and the size of parasitic components in the circuit is also the same. This means that high image quality in the pixel mixing mode can be realized with low power consumption.
  • the number of pixels for mixing pixel signals may be changed without being limited to the mixing of pixel signals of two vertical pixels and two horizontal pixels.
  • the effective portion 16 and the peripheral portion 17 do not have to have the same number of rows and pixels in which pixel signals are mixed, and may have different numbers of rows and pixels. For example, a sequence for selecting three or more rows at the same time in the first row selection sequence, and a sequence for selecting two or more rows at the same time in the second row selection sequence, and the valid portion 16 mixes the pixel signals of three rows. In the peripheral portion 17, the pixel signals of two rows may be mixed and output.
  • the second embodiment is different from the first embodiment in that in the vertical two-pixel horizontal two-pixel mixed mode which is an example of the pixel mixed mode shown in the first embodiment, two or more pixel rows are single.
  • the Nth pixel row (N is an integer greater than or equal to 1) is designated with the Mth pixel row (M is an integer greater than or equal to 1 and M ⁇ N) in a single row readout period.
  • the point is that the value of M is changed multiple times during one frame period.
  • the circuit configuration of the solid-state imaging device, the readout operation of the effective part, and the readout operation of the peripheral part in the all-pixel readout mode are the same as in the first embodiment.
  • FIG. 10 is a row selection sequence showing the supply timing of the row address signal supplied from the control unit 9 to the row selection circuit 3 in the vertical 2-pixel horizontal 2-pixel mixed mode.
  • the row selection sequence for one frame period in which pixel signals for one screen are output is shown by taking the imaging unit 2 of 16 rows as an example.
  • FIG. 6A shows pixel rows provided in the effective portion 16 and the peripheral portion 17 with consecutive row numbers.
  • the row numbers N and M of the Nth pixel row (N is an integer of 1 or more) and the Mth pixel row (M is 1 or more and M ⁇ N) correspond to any of these.
  • Row numbers 1 to 10 indicate the peripheral portion 17, and row numbers 11 to 16 indicate the pixel rows of the effective portion 16.
  • FIG. 4B shows a sequence of row address signals supplied to each row having the row number shown in FIG. 2A.
  • the sequence corresponding to the row numbers 11 to 16 is the first row selection.
  • the sequence corresponding to the row numbers 1 to 10 is the second row selection sequence.
  • selection of line number 1 is the second time, but line number 2 is selected at the same time in the first selection of line number 1, whereas line number 6 is selected at the same time in the second selection of line number 1.
  • the combined row is different from the first time.
  • line numbers 2 and 7, line numbers 3 and 8, line numbers 4 and 9, and line numbers 5 and 10 are selected, respectively.
  • ten sets of pixel signals are obtained as the pixel signals used for the correction data.
  • the same number of pixel signals as the pixel signals for 10 rows obtained when read out are obtained.
  • row numbers 11 and 12, row numbers 13 and 14, and row numbers 15 and 16 are selected in order according to the first row selection sequence. Then, the pixel signal of the effective unit 16 is read out. As a result, the number of times each row is designated is 1 in the first row selection sequence, and the number of times each row is designated is 2 in the second row selection sequence. It is possible to obtain the same number of pixel signals as when reading.
  • Such a sequence makes it possible to create correction data for horizontal shading with high accuracy and to realize a high-quality mixed mode.
  • the number of rows designated at the same time in the reading of the effective portion 16 and the reading of the peripheral portion 17 is the same, there is no concern that an offset will be generated between the outputs due to the difference in the drive mode, and the subsequent correction process is easier. There is also an advantage of becoming.
  • the pixel signals of the two pixel rows are mixed and designated twice, but the number and the number of pixel rows to be mixed may be changed.
  • pixel signals of three pixel rows may be mixed and specified three times.
  • the third embodiment is different from the first embodiment in that a column ADC and a digital mixer are provided instead of the multiplexer and the column selection circuit shown in the first embodiment.
  • FIG. 11 is a diagram showing an overall configuration of a solid-state imaging device according to the third embodiment of the present invention.
  • the solid-state imaging device 101 includes an imaging unit 102, a row selection circuit 103, a pixel current source circuit 104, a clamp circuit 105, and a sample hold (S / H) circuit 106.
  • the pixel current source circuit 104, the clamp circuit 105, and the sample hold circuit 106 constitute a column circuit unit 120.
  • the output unit output amplifier
  • the basic units 144a of the column ADC 144 are arranged in an array in the column direction (see FIG. 12 described later), and the row-unit analog pixel signals held in the sample hold circuit 106 are converted into digital signals.
  • the basic units (not shown) of the digital mixer are arranged in an array in the column direction, and the output data of the column ADC 144 is mixed.
  • the imaging unit 102 includes a peripheral unit having an effective unit 116 in which pixels 111a that output pixel signals corresponding to the amount of received light are two-dimensionally arranged, and a pixel 111b that is a light-shielding pixel and always obtains a dark state output. 117.
  • the pixel 111a and the pixel 111b correspond to the first pixel and the second pixel in the present invention, respectively.
  • FIG. 12 is a diagram showing the configuration of the column ADC 144.
  • the column ADC 144 includes a column ADC input terminal 146, a comparator 147, a ramp waveform generation circuit 148, a latch 149, and a counter 150.
  • a basic unit 144a of a column ADC 144 is arranged in each vertical signal line 119.
  • the pixel signal from the sample hold circuit 106 input to the column ADC input terminal 146 is input to the comparator 147.
  • the comparator 147 compares the ramp waveform generated by the ramp waveform generation circuit 148 with the pixel signal, and outputs a Hi level latch signal when the ramp waveform is lower than the pixel signal.
  • the latch 149 has a basic unit corresponding to the number of bits of the digital value after AD conversion.
  • the output of the counter 150 is input to each basic unit, and the latch signal from the comparator 147 is switched from the Hi level to the Lo level. When you write it.
  • the counter 150 counts up in synchronization with the ramp waveform.
  • the digital mixer 145 mixes pixel signals of a plurality of columns that are AD-converted by the basic unit 144a of the column ADC 144 in each column. As a result, a mixed pixel signal having a digital value in which pixel signals in a plurality of rows and columns are mixed is generated.
  • a pixel signal is input to the column ADC input terminal 146 of the column ADC 144, the ramp waveform output from the ramp waveform generation circuit 148 is set to the minimum value of the pixel signal, and the counter value of the counter 150 is set. Set to 0.
  • the latch signal output from the comparator 147 is at the Hi level.
  • the ramp waveform level starts to rise.
  • the rising slope is set to reach the maximum value of the pixel signal at timing t3.
  • the counter value of the counter 150 is also counted up in synchronization with the ramp waveform rise.
  • the latch signal is switched to the Lo level, and the counter value at that time is written in the latch 149.
  • the counter value is written in the latch 149.
  • the counter value (digital value) written in the latch 149 is a value corresponding to the magnitude of the pixel signal. .
  • the above operation is performed in parallel in the basic unit 144a of the column ADC 144 provided in each column, and analog pixel signals for one row are AD-converted in parallel, and the digital signal is held in the latch 149 in each column. .
  • the solid-state imaging device 101 includes an all-pixel readout mode for still image shooting and a pixel mixing mode for moving image shooting as drive modes. Next, the signal reading operation of the valid unit 116 will be described for each driving mode.
  • pixel signals for one row are read out from the imaging unit 102 and are held in the sample hold circuit 106.
  • the column ADC 144 performs AD conversion on the pixel signals for one row.
  • these digital signals are sequentially output to the outside of the chip via an output unit not shown in FIG. If the above operation is repeated for the number of rows of the effective unit 116, a pixel signal is output from the pixels 111a of the entire imaging unit 102.
  • the imaging unit 102 first, two rows are simultaneously selected by the imaging unit 102, the pixel signals of the pixels 111b for two rows are read, and the two rows mixed by the vertical signal line 119 are read.
  • the mixed pixel signal is held in the sample hold circuit 106.
  • the mixed signal is AD converted by the column ADC 144.
  • pixel signals (digital values) for two columns are mixed by the digital mixer 145. Finally, these mixed pixel signals are sequentially output to the outside of the chip via an output unit not shown in FIG. If the above operation is repeated by the number of pixel rows / 2 of the effective unit 116, the pixel signal of the entire imaging unit 102 is output.
  • the clamp potential of the column circuit unit 120 is distributed in the horizontal direction, and as a result, the reference potential of each column is different for each column. This means that nonuniformity in the horizontal direction occurs in the dark state output that is the reference of the output image, and horizontal shading occurs in the image.
  • the peripheral part 117 sequentially selects the pixels 111b from which pixel signals are read from the row number 1 in the same manner as the effective part 116. Thereby, the pixel signal used for the correction data having the same number of rows as the physical number of the peripheral portion 117 is obtained.
  • the effective unit 116 selects two rows at the same time, but the peripheral unit 117 selects one row from row number 1 at a time. select.
  • pixel signals used for correction data having the same number of rows as the physical number of the peripheral portion 117 can be obtained.
  • correction data for multiple rows can be obtained in the pixel mixing mode as well as the all-pixel readout mode, and horizontal shading correction data can be created with high accuracy, and a high-quality pixel mixing mode can be realized. become.
  • correction of horizontal shading may be performed by incorporating a digital signal processing circuit in the solid-state imaging device.
  • FIG. 14 is a diagram illustrating an overall configuration of an imaging apparatus (camera) according to the fourth embodiment of the present invention.
  • the imaging device 151 includes a solid-state imaging device 1 described in the first embodiment, an analog front end (AFE) 152, a digital signal processor (DSP) 153, and a memory 154.
  • AFE analog front end
  • DSP digital signal processor
  • the analog front end 152 converts the pixel signals (analog signals) of the effective unit 16 and the peripheral unit 17 output from the solid-state imaging device 1 into digital signals so that the digital image signal processing device can handle them.
  • the digital signal processor 153 corrects the pixel signal of the effective unit 16 converted into the digital signal with the correction data stored in the memory 154.
  • the memory 154 is a pixel signal for the peripheral portion 17 output from the solid-state imaging device 1, that is, a peripheral portion data for newly generating correction data and a correction portion generated using the pixel signal of the peripheral portion 17. Memorize data.
  • the imaging device 151 is driven by an all-pixel readout mode that can be used for camera still photography and a pixel mixture mode that can be used for a moving image recording function.
  • FIG. 15 shows a flowchart for explaining the operation in the all-pixel readout mode in the imaging apparatus 151.
  • step 1 peripheral data (pixel signals) are read out line by line from the pixels 11b arranged in the peripheral part 17 shown in FIG. 1 (ST1). At this time, for the imaging unit 2 of the solid-state imaging device 1, only one row is selected, and pixel signals are read from the pixels 11b in the selected row.
  • step 2 new correction data is created using the peripheral data detected in step 1 and the correction data value stored in the memory 154 (ST2).
  • step 3 it is determined whether or not the reading of the peripheral portion 17 is completed. If not, the process returns to step 1 (ST3). As described above, when Step 1 and Step 2 are performed on all the rows of the peripheral portion 17, correction data including the average of the output of each column of the peripheral portion 17 is obtained. This correction data corresponds to dark horizontal shading data. This correction data is held in the memory 154.
  • step 4 pixel signals are read out row by row from the pixels 11a arranged in the effective section 16 (ST4). At this time, for the imaging unit 2 of the solid-state imaging device 1, only one row is selected, and pixel signals are read from the pixels 11a in the selected row.
  • step 5 horizontal shading correction is performed by subtracting the correction data held in the memory 154 from the data obtained in step 4 (ST5).
  • step 6 it is determined whether or not the readout of the pixel signal from the pixels 11a in each pixel row of the effective unit 16 is completed. If not, the process returns to step 4 (ST6).
  • Step 4 and Step 5 are performed on the entire effective section 16, a high-quality image in which horizontal shading is corrected on the entire effective section 16 can be obtained.
  • step 1 peripheral data is read line by line from the pixels 11b arranged in the peripheral part 17 shown in FIG. At this time, for the imaging unit 2 of the solid-state imaging device 1, only one row is selected, and pixel signals are read from the pixels 11b in the selected row (ST1).
  • step 2 new correction data is created using the peripheral data detected in step 1 and the correction data value stored in the memory 154 (ST2).
  • step 3 it is determined whether or not the reading of the peripheral portion 17 is completed. If not, the process returns to step 1 (ST3). As described above, when Step 1 and Step 2 are performed on all the rows of the peripheral portion 17, correction data including the average of the output of each column of the peripheral portion 17 is obtained. This correction data corresponds to dark horizontal shading data. This correction data is held in the memory 154.
  • step 4 pixel signals are read out row by row from the pixels 11a arranged in the effective portion 16 (ST4).
  • the imaging unit 2 of the solid-state imaging device 1 two rows are simultaneously selected, and pixel signals are read from the pixels 11a in the selected row.
  • a pixel mixture signal is output from the solid-state imaging device 1 by the mixing operation of the vertical and horizontal signals at the time of signal readout.
  • step 5 horizontal shading correction is performed by subtracting the correction data held in the memory 154 from the data obtained in step 4 (ST5).
  • step 6 it is determined whether or not the readout of the pixel signal from the pixels 11a in each pixel row of the effective unit 16 is completed. If not, the process returns to step 4 (ST6).
  • Step 4 and Step 5 are performed on the entire effective portion 16, a high-quality mixed image in which horizontal shading is corrected on the entire effective portion 16 can be obtained.
  • the correction data at this time is also generated from a large number of peripheral data equivalent to the all-pixel readout mode, and high-precision correction is possible.
  • the pixels arranged in the effective portion and the peripheral portion are not limited to the number and arrangement described above, and may be changed as appropriate.
  • the peripheral pixels are not limited to light-shielded pixels that are shielded in advance, but may be pixels that output a constant reference voltage.
  • the readout of the pixel signals of the effective portion and the peripheral portion in the pixel mixture mode is not limited to the readout method shown in the above-described embodiment, and other methods may be used.
  • the present invention is not limited to the vertical two-pixel horizontal two-pixel mixed mode in which pixel signals of two vertical pixels and two horizontal pixels are mixed, and other mixed modes may be used.
  • the combination of rows for reading out pixel signals by mixing is not limited to the above-described embodiment, and any combination may be used.
  • the configuration of the solid-state imaging device and the imaging device according to the present invention is not limited to the above-described embodiment, and may be any configuration.
  • the pixel current source circuit, the clamp circuit, the sample hold circuit, the multiplexer, the column selection circuit, the column ADC, the digital mixer, or a combination thereof may be changed.
  • the solid-state imaging device according to the present invention includes other embodiments realized by combining arbitrary components in the above-described embodiments, and other embodiments that do not depart from the gist of the present invention. Modifications obtained by various modifications conceived by a trader and various devices including the solid-state imaging device according to the present invention are also included in the present invention. For example, a movie camera including the solid-state imaging device according to the present invention is also included in the present invention.
  • the solid-state imaging device according to the present invention is useful as an image sensor for imaging equipment that requires high image quality and high functionality such as a digital single-lens reflex camera and a high-end compact camera.

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Abstract

L'invention porte sur un dispositif de capture d'image à semi-conducteurs et sur un dispositif de capture d'image qui comporte une unité de capture d'image (2), comportant en outre une partie effective (16) et une partie périphérique (17) ; un circuit de sélection de rangée (3) qui sélectionne des pixels (11a, 11b) par unité de rangée ; une unité de circuit de colonne (20) qui retient temporairement des signaux de pixel de sortie, et une unité de commande (9) qui fournit des signaux d'adresse de rangée qui désignent des rangées devant être sélectionnées au circuit de sélection de rangée (3). En ce qui concerne au moins un mode de pilotage, l'unité de commande (9) génère une première séquence de sélection de rangées qui comprend les signaux d'adresse de rangée correspondant à la partie effective (16) et une seconde séquence de sélection de rangées qui comprend les signaux d'adresse de rangée correspondant à la partie périphérique (17), et les fournit au circuit de sélection de rangée (3) de telle manière que soit le nombre de rangées de pixels simultanément désignées dans chacune de la première séquence de sélection de rangées et de la seconde séquence de sélection de rangées, soit le nombre de cycles dans chaque rangée désignée de chaque séquence de sélection de rangées respective, varie entre les séquences de sélection de rangées.
PCT/JP2010/007419 2010-01-08 2010-12-22 Dispositif de capture d'image à semi-conducteurs et dispositif de capture d'image WO2011083541A1 (fr)

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WO2013129646A1 (fr) 2012-03-01 2013-09-06 株式会社ニコン Circuit de conversion a/n et appareil de capture d'images à semi-conducteurs
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US10277848B2 (en) 2015-01-13 2019-04-30 Sony Corporation Solid-state imaging device, method of driving the same, and electronic apparatus
JP6579782B2 (ja) * 2015-04-09 2019-09-25 キヤノン株式会社 撮像装置
JP6579178B2 (ja) * 2017-10-27 2019-09-25 株式会社ニコン 撮像素子及び撮像装置
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JP7286323B2 (ja) * 2019-01-16 2023-06-05 キヤノン株式会社 撮像装置および撮像装置の制御方法

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