WO2014174911A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2014174911A1
WO2014174911A1 PCT/JP2014/055712 JP2014055712W WO2014174911A1 WO 2014174911 A1 WO2014174911 A1 WO 2014174911A1 JP 2014055712 W JP2014055712 W JP 2014055712W WO 2014174911 A1 WO2014174911 A1 WO 2014174911A1
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Prior art keywords
igbt
trench gate
active mesa
gate
mesa portion
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PCT/JP2014/055712
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English (en)
Japanese (ja)
Inventor
川上　剛史
古川　彰彦
裕二 村上
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三菱電機株式会社
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Priority to JP2015513609A priority Critical patent/JPWO2014174911A1/ja
Publication of WO2014174911A1 publication Critical patent/WO2014174911A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Definitions

  • the present invention relates to a semiconductor device, and more specifically to a power semiconductor device having a buried insulating gate.
  • An insulated gate bipolar transistor is widely used as a power electronics semiconductor device having a rated voltage of 600 V or more.
  • an IGBT having a trench gate electrons are injected from a channel formed in an active mesa portion in a gate-on state, and holes are supplied from a collector layer on the back side of the substrate in response thereto, thereby producing a conductivity modulation effect. As a result, a low on-resistance can be obtained.
  • Patent Document 2 discloses an IGBT that exhibits an IE effect using an invalid trench gate (referred to as a dummy trench gate).
  • the IGBT of Patent Document 2 has dummy trench gates on both sides of the trench gate.
  • the distance between the active mesa portions can be increased by increasing the number of dummy trench gates arranged between the trench gates.
  • the mesa portions on both sides of the trench gate are active mesa portions, but electrons are injected only from the channel on the trench gate side, and electrons are not injected from the channel on the dummy trench gate side.
  • the narrowing of the active mesa portion requires refinement of the semiconductor process design rules. Further, the deep digging of the trench requires a fine processing technique and causes a decrease in breakdown voltage. For this reason, it is easiest to obtain a low on-resistance by widening the separation distance of the active mesa portions.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device that achieves both a sufficiently low on-resistance and a relatively large saturation current.
  • a semiconductor device is disposed between a semiconductor substrate, a trench gate embedded in the semiconductor substrate on a substrate surface side of the semiconductor substrate, and the trench gate and the semiconductor substrate. And a gate insulating film.
  • the semiconductor substrate includes an active mesa portion which is a mesa portion facing a side surface of the trench gate through the gate insulating film and into which carriers of the same conductivity type as the conductivity type of the semiconductor substrate are injected.
  • the active mesa portion is composed of a plurality of types of portions extending in a constant width, although extending in a plan view of the substrate surface. The plurality of types of portions are periodically and repeatedly connected so as to form a series of meandering active mesa portions. In the semiconductor substrate, there is a portion where the distance between the adjacent active mesa portions is larger than the width of the active mesa portion.
  • a relatively low on-resistance can be obtained while suppressing a decrease in saturation current.
  • the warpage of the wafer in the manufacturing process of the semiconductor device can be suppressed.
  • FIG. 1 is a plan view showing a semiconductor device according to a first example of Embodiment 1.
  • FIG. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 7 is a plan view showing a semiconductor device according to a second example of the first embodiment;
  • FIG. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5.
  • FIG. 6 is a plan view showing a semiconductor device according to a fifth example of the first embodiment.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG.
  • FIG. 6 is a plan view showing a semiconductor device according to a first example of Embodiment 2.
  • FIG. 10 is a cross-sectional view taken along line XX in FIG. 9.
  • FIG. 10 is a plan view showing a semiconductor device according to a second example of the second embodiment.
  • FIG. 9 is a plan view showing a semiconductor device according to a third example of the second embodiment.
  • FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG.
  • FIG. 11 is a plan view showing a semiconductor device according to a first example of Embodiment 3;
  • FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 14.
  • FIG. 11 is a plan view showing a semiconductor device according to a second example of the third embodiment.
  • FIG. 10 is a plan view showing a semiconductor device according to a third example of the third embodiment.
  • FIG. 11 is a plan view showing a semiconductor device according to a fourth example of the third embodiment.
  • FIG. 11 is a plan view showing a semiconductor device according to a fifth example of the third embodiment.
  • FIG. 11 is a plan view showing a semiconductor device according to a first example of the fourth embodiment.
  • FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 20.
  • FIG. 10 is a plan view showing a semiconductor device according to a second example of the fourth embodiment.
  • FIG. 10 is a plan view showing a semiconductor device according to a third example of the fourth embodiment.
  • FIG. 10 is a plan view showing a semiconductor device according to a fourth example of the fourth embodiment.
  • FIG. 10 is a plan view showing a semiconductor device according to a first example of the fifth embodiment.
  • FIG. 10 is a plan view showing a semiconductor device according to a second example of the fifth embodiment.
  • FIG. 10 is a plan view showing a semiconductor device according to a third example of the fifth embodiment.
  • FIG. 10 is a plan view showing a semiconductor device according to a fourth example of the fifth embodiment.
  • FIG. 23 is a plan view showing a semiconductor device according to a first example of the sixth embodiment.
  • FIG. 23 is a plan view showing a semiconductor device according to a second example of the sixth embodiment.
  • FIG. 24 is a plan view showing a semiconductor device according to a third example of the sixth embodiment.
  • FIG. 23 is a plan view showing a semiconductor device according to a fourth example of the sixth embodiment.
  • an IGBT is exemplified as a semiconductor device according to the present invention.
  • the effect of suppressing the warpage of the wafer in the manufacturing process of the semiconductor device according to the present invention is also effective for semiconductor devices other than IGBT, for example, unipolar transistors such as power MISFET (Metal-Insulator-Semiconductor-Field-Effect-Transistor).
  • the MIS structure is particularly called a MOS (Metal-Oxide-Semiconductor) structure when the insulating film is an oxide film.
  • FIG. 1 shows a plan view (partially enlarged plan view) of IGBT 100 according to the first example of the first embodiment
  • FIG. 2 shows a cross-sectional view taken along the line II-II in FIG.
  • FIG. 1 and the following plan view the structure above the substrate surface is omitted.
  • a cross section (transverse cross section) taken along line II in FIG. 2 corresponds to FIG. Note that hatching in FIGS. 1 and 2 and the subsequent drawings is made easy to see each element.
  • the low-concentration n-type semiconductor substrate 1 has a plurality of trenches opened in the substrate surface.
  • the trench is formed from the substrate surface to the substrate back surface, that is, in the substrate thickness direction.
  • the trench does not reach the back surface of the substrate, and has a trench bottom inside the substrate.
  • a portion of the semiconductor substrate 1 extending from the trench bottom to the substrate surface is referred to as a mesa portion 90.
  • a portion between adjacent trenches is a mesa portion 90
  • a space between adjacent mesa portions 90 is a trench.
  • each trench a trench gate 2 which is an insulated gate electrode is embedded.
  • Each trench gate 2 is insulated from the semiconductor substrate 1 by a gate insulating film 3 surrounding the trench gate 2.
  • the gate insulating film 3 is disposed between the trench gate 2 and the mesa portion 90.
  • the mesa unit 90 meanders in a plan view of the substrate surface, in other words, when the substrate surface is viewed from vertically above the substrate surface. If the example of FIG. 1 is expressed more specifically, the mesa unit 90 has a zigzag shape. However, the mesa portion 90 as a whole extends in a certain direction (in the example of FIG. 1, a diagonally downward 45 ° direction).
  • the mesa portion 90 is roughly divided into two types of portions having different extending directions (in other words, longitudinal directions). That is, one is a portion extending in the first direction (vertical direction or horizontal direction in the example of FIG. 1), and the other is a second direction different from the first direction (horizontal direction or in the example of FIG. 1). This is a portion extending in the vertical direction). These two types of portions are alternately arranged and are joined at the ends of the adjacent ones. In other words, these two types of portions are periodically and repeatedly connected so as to form a series of meandering active mesas 90.
  • the overall extending direction of the mesa unit 90 is grasped, for example, as a direction connecting the midpoints of the above-described parts constituting the mesa unit 90 (more specifically, the midpoint in the extending direction of each part).
  • the two types of parts constituting the mesa unit 90 have the same width, and both parts extend with a constant width (in other words, a uniform width). Note that the width of these portions (and hence the width of the mesa portion 90) is a dimension in a direction orthogonal to the extending direction of each portion in plan view of the substrate main surface.
  • the expression that the widths are the same is not limited to the case where the dimension values of the widths are exactly the same, but may be considered to be substantially the same considering the allowable range for the dimension values. Including. Such a point also applies to the expression that the width is constant, and also applies to dimensions other than the width.
  • the separation distance between the adjacent mesa portions 90 (specifically, the distance in the direction perpendicular to the overall extending direction of the mesa portions 90) is constant.
  • the separation distance between adjacent mesa portions 90 can be grasped as the width of the trench existing between them.
  • the separation distance between the adjacent mesa portions 90 is several times larger than the width of the mesa portion 90.
  • the mesa unit 90 may be configured with three or more types of portions having different extending directions, and the mesa unit 90 configured with three or more types of portions is exemplified in the third embodiment (for example, FIG. 14). reference).
  • the trench and the trench gate 2 also have a meandering portion (a portion corresponding to the side surface of the trench and the trench gate 2) in plan view of the substrate surface.
  • the mesa portion 90 is provided with a base layer 4 which is a p-type impurity layer.
  • a base layer 4 which is a p-type impurity layer.
  • an emitter layer 5 that is an n-type impurity layer having a higher concentration than the semiconductor substrate 1 and a base contact layer 6 that is a p-type impurity layer having a higher concentration than the base layer 4 And are provided.
  • the base contact layer 6 extends along the mesa portion 90 in the center of the mesa portion 90 in the width direction.
  • Emitter layers 5 are provided along the base contact layer 6 on both sides of the base contact layer 6, and the emitter layer 5 is in contact with the base contact layer 6. That is, the base contact layer 6 is sandwiched between the emitter layers 5.
  • Each emitter layer 5 is in contact with the gate insulating film 3 on the side opposite to the base contact layer 6 side.
  • the emitter layer 5 and the base contact layer 6 are connected to the emitter electrode 7 on the substrate surface.
  • An interlayer insulating film 8 is provided between the emitter electrode 7 and the trench gate 2, and the emitter electrode 7 is insulated from the trench gate 2 by the interlayer insulating film 8.
  • a buffer layer 9 that is an n-type impurity layer and a collector layer 10 that is a p-type impurity layer are provided on the back side of the semiconductor substrate 1.
  • the impurity concentration of the buffer layer 9 is set higher than the impurity concentration of the semiconductor substrate 1 and lower than the impurity concentration of the emitter layer 5.
  • the impurity concentration of the collector layer 10 is set lower than the impurity concentration of the base contact layer 6.
  • the collector layer 10 is provided from the back surface of the substrate to a predetermined depth, and is provided on one surface along the back surface of the substrate.
  • the buffer layer 9 is provided inside the substrate following the collector layer 10, and is provided on one surface along the back surface of the substrate.
  • the collector layer 10 is connected to the collector electrode 11 on the back surface of the substrate.
  • the low-concentration n-type semiconductor layer that is a portion from directly below the base layer 4 to immediately above the buffer layer 9 may be referred to as a drift layer.
  • the trench gate 2 is connected to a gate electrode (not shown) at a location not shown in FIGS.
  • the gate of the IGBT 100 When the gate of the IGBT 100 is turned on (that is, an on voltage is applied to the trench gate 2), a channel is formed in a portion of the base layer 4 in contact with the gate insulating film 3, and the emitter layer 5 is interposed through the channel. To the drift layer, electrons which are carriers of the same conductivity type as the semiconductor substrate 1 are injected.
  • the mesa portion facing the side surface of the trench gate 2 through the gate insulating film 3 and into which carriers of the same conductivity type as the semiconductor substrate 1 are injected is referred to as an active mesa portion.
  • the mesa part into which the carrier is not injected is called an inactive mesa part. Note that all mesa portions 90 of the IGBT 100 are active mesa portions, and therefore, reference numeral 90 is used for the active mesa portion.
  • the active mesa portion 90 is composed of a plurality of types of portions having different extending directions, whereby the active mesa portion 90 and the trench gate 2 meander. Therefore, the MIS structure constituted by the active mesa portion 90, the gate insulating film 3, and the trench gate 2 meanders. Therefore, the channel width (here, the total length of the channels along the active mesa portion in a plan view of the substrate surface) is increased as compared with the configuration in which the active mesa portion and the trench gate extend linearly. be able to. More specifically, in the zigzag shape shown in FIG. 1, the channel width can be doubled. As a result, the saturation current increases.
  • the separation distance of the active mesa portion 90 is larger than the width of the active mesa portion 90 (as described above, the separation distance between the mesa portions 90 is several times larger than the width of the mesa portion 90. ),
  • the separation distance of the active mesa unit 90 is set to be relatively large. For this reason, a relatively large IE effect is obtained, and as a result, a relatively low on-resistance is obtained.
  • the saturation current can be increased as described above.
  • the IGBT 100 it is possible to obtain a relatively low on-resistance while suppressing a decrease in saturation current under a constant area of the active region.
  • the separation distance of the active mesa unit 90 is constant, it is easier to obtain the IE effect than when the separation distance is not constant. For this reason, even if the active mesa portion 90 has a meandering shape, a sufficient IE effect can be maintained.
  • the width of the active mesa portion 90 is narrow, in other words, when the distance between the adjacent trench gates 2 is small, a configuration in which the base contact layer 6 is sandwiched between the emitter layers 5 due to the restrictions of the design rules of the semiconductor process (see FIG. 1 and FIG. 2) may be difficult.
  • FIG. 3 shows a structure suitable for such a case.
  • FIG. 3 is a plan view of IGBT 100a according to the second example of the first embodiment.
  • the IGBT 100a corresponds to an example in which an emitter layer 5a and a base contact layer 6a are provided in place of the emitter layer 5 and the base contact layer 6 with respect to the IGBT 100 (see FIGS. 1 and 2).
  • the other configuration of the IGBT 100a is basically the same as that of the IGBT 100.
  • the emitter layer 5 a and the base contact layer 6 a are alternately provided on the surface of the active mesa unit 90 along the active mesa unit 90.
  • the alignment accuracy of the contact hole leading to the emitter layer and the contact hole leading to the base contact layer can be relaxed.
  • such a configuration leads to a decrease in saturation current because the channel width existing immediately below the emitter layer is shortened.
  • the active mesa portion 90 meanders even in the IGBT 100a, it is possible to compensate for a decrease in saturation current.
  • the base contact layer 6 a is in contact with the gate insulating film 3, but the base contact layer 6 a may not be in contact with the gate insulating film 3.
  • FIG. 4 shows a plan view of the IGBT 100b according to the third example of the first embodiment. Note that the cross-sectional view taken along line IIb-IIb in FIG. 4 is the same as FIG.
  • the first movement is a direction in which one mesa unit 90 is orthogonal to the overall extending direction of the one mesa unit 90 (in the example of FIG. 4, a 45 ° upward diagonal direction along the line IIb-IIb). Is to move to.
  • the second movement is to move one mesa portion 90 in the overall extending direction of the one mesa portion 90 by a distance that is half the meandering period.
  • the peak portion and the peak portion or the valley portion and the valley portion of the adjacent mesa portions 90 face each other.
  • the other configuration of the IGBT 100b is basically the same as that of the IGBT 100.
  • the separation distance between the adjacent mesa portions 90 (specifically, the distance in the direction orthogonal to the overall extending direction of the mesa portions 90) periodically varies.
  • the fluctuation range of the separation distance between the adjacent mesa portions 90 is sufficiently smaller than the average value of the separation distances between the adjacent mesa portions 90, the separation distance between the adjacent mesa portions 90 may be regarded as substantially constant.
  • the IGBT 100b has the same effect as the IGBT 100.
  • FIG. 5 shows a plan view of the IGBT 101 according to the fourth example of the first embodiment
  • FIG. 6 shows a cross-sectional view taken along line VI-VI in FIG. Note that a cross section taken along line VV in FIG. 6 corresponds to FIG.
  • the IGBT 101 corresponds to an example in which a trench gate 12 and a gate insulating film 13 are provided in place of the trench gate 2 and the gate insulating film 3 with respect to the IGBT 100 (see FIGS. 1 and 2). Further, a P well layer 14 which is a deep P type injection layer is added to the IGBT 101. Other configurations of the IGBT 101 are basically the same as those of the IGBT 100.
  • the trench gates 12 are arranged on both sides of the active mesa unit 90.
  • the trench gate 12 is narrower than the trench gate 2 (see FIGS. 1 and 2), and extends along the active mesa portion 90 with a constant width. For this reason, the trench gate 12 has a meandering shape like the active mesa portion 90.
  • the width of the trench gate 12 is not significantly different from the width of the active mesa portion 90.
  • the trench gate 12 is surrounded by a gate insulating film 13 and is insulated from the semiconductor substrate 1 by the gate insulating film 13.
  • a mesa portion 91 is present on the opposite side of the active mesa portion 90 from the trench gate 12.
  • a mesa portion 91 extends between adjacent trench gates 12.
  • the mesa portion 91 is provided with a P-well layer 14, and the P-well layer 14 is provided from the substrate surface to the same depth as the trench bottom.
  • the impurity concentration of the P well layer 14 is, for example, approximately the same as the impurity concentration of the base layer 4.
  • the P well layer 14 is not provided with a contact hole leading to the emitter electrode 7.
  • the P well layer 14 is provided to alleviate electric field concentration at the bottom of the trench gate.
  • the mesa portion 91 in which the P well layer 14 is formed is an inactive mesa portion because it is not used for electron injection through the emitter layer 5. For this reason, reference numeral 91 is used for the inactive mesa portion.
  • the IE effect can be obtained without forming the wide trench gate 2 (see FIG. 1).
  • FIG. 7 is a plan view of the IGBT 102 according to the fifth example of the first embodiment
  • FIG. 8 is a cross-sectional view taken along the line VIII-VIII in FIG. Note that a cross section taken along line VII-VII in FIG. 8 corresponds to FIG.
  • the IGBT 102 corresponds to an example in which an inactive (in other words, not driven) trench gate 15 and a base layer 16 are provided in place of the P-well layer 14 with respect to the IGBT 101 (see FIGS. 5 and 6).
  • the inactive trench gate 15 is also referred to as a dummy trench gate 15.
  • the other configuration of the IGBT 102 is basically the same as that of the IGBT 101.
  • the dummy trench gate 15 is provided on the side opposite to the active mesa portion 90 when viewed from the trench gate 12 and spaced from the trench gate 12.
  • the dummy trench gate 15 has the same shape as the trench gate 12 and extends along the trench gate 12.
  • the dummy trench gate 15 is provided so that the separation distance between the adjacent trench gates 12 is divided by a predetermined dimension or less. In the example of FIGS. 7 and 8, two dummy trench gates 15 are provided at equal intervals between adjacent trench gates 12.
  • the dummy trench gate 15 is surrounded by the gate insulating film 20.
  • the gate insulating film 20 may be referred to as a dummy gate insulating film 20.
  • the same potential as the emitter electrode 7 is applied to the dummy trench gate 15.
  • a gate potential may be applied instead of the emitter potential.
  • Different potentials may be applied to the individual dummy trench gates 15.
  • a base layer 16 similar to the base layer 4 is provided in the mesa portion sandwiched between the trench gate 12 and the dummy trench gate 15 and the mesa portion sandwiched between the dummy trenches 15.
  • the base layer 16 is not provided with contact holes that lead to the emitter layer 5, the base contact layer 6, and the emitter electrode 7.
  • the inactive mesa portion 91 since the mesa portion sandwiched between the trench gate 12 and the dummy trench gate 15 and the mesa portion sandwiched between the dummy trenches 15 are not used for injection of electrons through the emitter layer 5, the inactive mesa portion 91.
  • the IE effect can be obtained without forming the wide trench gate 2 (see FIG. 1) and the P well layer 14 (see FIG. 5).
  • the electric field concentration at the bottom of the trench can be alleviated without forming the P well layer 14. This is because the adjacent trench bottoms are relatively close to each other, so that each other's electric field is relaxed.
  • a strong electric field concentration occurs at the corner at the bottom of the trench gate 12.
  • 45 ° chamfering may be applied to a right-angled shape formed by two continuous side surfaces of the trench.
  • the maximum channel mobility can be obtained by configuring most of the side surfaces of the trench gates 2 and 12 with the (100) plane or a crystal plane equivalent thereto.
  • the IGBTs 100, 100a, 100b, 101, 102 great advantages can be obtained in addition to the electrical characteristics.
  • the wafer is likely to warp during the manufacturing process of the IGBT. This is because the stress generated by forming the trench gate has strong anisotropy. Therefore, by applying a meandering shape like the trench gates 2 and 12, the direction in which the stress is applied is dispersed and the warpage of the wafer can be suppressed.
  • the meandering trench gates 2 and 12 are useful, for example, when the width of the active mesa portion is narrowed due to miniaturization and the density of the trench gate is increased. This is because the stress increases as the density of the trench gate increases. Further, the meandering trench gates 2 and 12 are useful, for example, when the diameter of the wafer is increased. This is because a large-diameter wafer has a large amount of warping even with the same stress.
  • FIG. 9 is a plan view of the IGBT 200 according to the first example of the second embodiment
  • FIG. 10 is a sectional view taken along line XX in FIG.
  • a cross section taken along line IX-IX in FIG. 10 corresponds to FIG.
  • the IGBT 200 has a configuration similar to the IGBT 102 (see FIGS. 7 and 8), but differs from the IGBT 102 in that active mesa portions 90 are disposed on both sides of the trench gate 12, respectively.
  • the other configuration of the IGBT 200 is basically the same as that of the IGBT 102.
  • each active mesa portion 90 on both sides of the trench gate 12 is provided with the emitter layer 5 on the trench gate 12 side and the base contact layer 6 on the dummy trench gate 15 side.
  • the base layer 4 is provided under the emitter layer 5 and the base contact layer 6.
  • the base contact layer 6 is in contact with the dummy gate insulating film 20, but the base contact layer 6 may not be in contact with the dummy gate insulating film 20.
  • the ratio of the number of dummy trench gates 15 to the number of trench gates 12 can be increased.
  • the IE effect can be increased as the ratio is higher. That is, according to the IGBT 200, it is possible to obtain a low on-resistance as compared with the IGBT 102 (see FIGS. 7 and 8).
  • FIG. 11 shows a plan view of an IGBT 200a according to a second example of the second embodiment.
  • the IGBT 200a corresponds to an example in which the emitter layer 5a and the base contact layer 6a of the IGBT 100a (see FIG. 3) are applied to the IGBT 200 (see FIG. 9).
  • the other configuration of the IGBT 200a is basically the same as that of the IGBT 200. According to the IGBT 200a, the same effect as the IGBTs 200 and 100a can be obtained.
  • the base contact layer 6a is also provided between the emitter layer 5a and the dummy gate insulating film 20. However, it is sufficient that the base contact layer 6 a is provided so as to fill between the emitter layers 5 a scattered along the trench gate 12.
  • FIG. 12 shows a plan view of an IGBT 201 according to the third example of the second embodiment
  • FIG. 13 shows a cross-sectional view taken along line XIII-XIII in FIG.
  • a cross section taken along line XII-XII in FIG. 13 corresponds to FIG.
  • the IGBT 201 corresponds to an example in which the IGBT 200 (see FIGS. 9 and 10) is changed to a wide dummy trench gate 21 by connecting all three dummy trench gates 15 between adjacent trench gates 12. Due to the application of the dummy trench gate 21, the IGBT 201 does not have the inactive mesa portion 91 (see FIGS. 9 and 10). Other configurations of the IGBT 201 are basically the same as those of the IGBT 200. According to the IGBT 201, the emitter-collector capacitance can be reduced.
  • a relatively large IE effect as expected in the present invention is not obtained by merely meandering a linear active mesa for any IGBT. This is because, by meandering the active mesa, the resistance component in the depth direction of the active mesa felt by holes is reduced. Therefore, in order to obtain a relatively large IE effect, it is more preferable to increase the resistance component in the horizontal direction between active mesas sensed by holes than the resistance component in the depth direction of active mesas sensed by holes. It is. Therefore, (i) an IGBT having a relatively large distance between active mesa portions and a relatively shallow trench gate, or (ii) an IGBT having a relatively large distance between active mesa portions and a relatively wide active mesa portion.
  • the meandering period of the active mesa is relatively large for the sake of simplicity.
  • the meandering period is large, a portion where the shortest distance between adjacent active mesas is significantly smaller than the distance between adjacent active mesas occurs, and a relatively large IE as expected in the present invention. The effect may not be obtained. Therefore, in order to obtain a relatively large IE effect, it is more preferable to reduce the meandering period of the active mesa.
  • the active mesa and the trench gate are bent at right angles for the sake of simplicity.
  • a trench gate bent at a right angle can cause problems in the manufacturing process, and can cause significant electric field concentration at the bottom of the trench gate when the IGBT current is cut off. This problem is alleviated by chamfering or rounding the right angle part of the trench gate in the 45 ° direction.
  • the fourth example of the first embodiment, the fifth example of the first embodiment, the first example of the second embodiment, the second example of the second embodiment, and the third example of the second embodiment can be increased by meandering the trench gate.
  • the gate-collector capacitance which is a feedback capacitance, the controllability of dV / dt at the turn-on time of the IGBT by the gate resistance is improved.
  • FIG. 14 is a plan view of the IGBT 300 according to the first example of the third embodiment
  • FIG. 15 is a sectional view taken along line XV-XV in FIG. Note that a cross section taken along line XIV-XIV in FIG. 15 corresponds to FIG.
  • the IGBT 300 corresponds to an example in which a trench gate 30 is applied instead of the trench gate 2 to the IGBT 100 (see FIGS. 1 and 2). Moreover, the shape and arrangement of the active mesa unit 90 are different from those of the IGBT 100. The other configuration of the IGBT 300 is basically the same as that of the IGBT 100.
  • the active mesa unit 90 in the IGBT 300 is roughly divided into three types having different extending directions. That is, the first portion extends in the first direction (vertical direction or horizontal direction in the example of FIG. 1). The second portion extends in a second direction (lateral direction or vertical direction in the example of FIG. 1) different from the first direction. The third portion extends in a direction inclined by 45 ° with respect to the first direction and the second direction (in the example of FIG. 1, a diagonally downward 45 ° direction).
  • Each active mesa unit 90 has a peak portion of one active mesa unit 90 in a direction perpendicular to the entire extending direction of the one active mesa unit 90 (in the example of FIG. 14, the direction is 45 degrees upward to the right).
  • the other active mesa portions 90 are arranged so as to face each other.
  • the trench gate 30 is disposed between the adjacent active mesa portions 90 similarly to the trench gate 2 (see FIG. 1). However, while the width of the trench gate 2 is constant, the width of the trench gate 30 varies depending on the location. Specifically, due to the arrangement relationship of the active mesa portions 90, the separation distance of the active mesa portions 90 periodically changes according to the points in the extending direction of the active mesa portions 90. The width also changes periodically according to the point in the extending direction of the trench gate 30.
  • the adjacent trench gates 30 are arranged such that the crests and troughs face each other in plan view of the substrate surface, in other words, the widest part of one trench gate 30 and the narrowest part of the other trench gate 30. It is arranged so that this part faces.
  • the channel width is up to ⁇ 2 times.
  • the IE effect is somewhat lower than that of the IGBT 100.
  • FIG. 14 is a plan view of the substrate surface
  • the midpoint 31 in the width direction of the widest portion of the trench gate 30 is selected as the rotation axis (in other words, the rotation center)
  • the rotation axis in other words, the rotation center
  • most of the stress generated from the periphery of the midpoints 31 and 32 in the width direction is canceled out.
  • the on-resistance is comparable.
  • the warpage of the wafer that occurs in the manufacturing process as described above can be greatly suppressed, so that the IGBT 300 is superior in manufacturing.
  • the IGBT 300 has a plan view pattern in which the channel is nearly four times rotationally symmetric, the current distribution in the semiconductor substrate 1 is less biased at a position deeper than the trench gate 30.
  • FIG. 16 shows a plan view of an IGBT 300a according to a second example of the third embodiment.
  • the IGBT 300a corresponds to an example in which the emitter layer 5a and the base contact layer 6a of the IGBT 100a (see FIG. 3) are applied to the IGBT 300 (see FIG. 14).
  • the other configuration of the IGBT 300a is basically the same as that of the IGBT 300. According to the IGBT 300a, the same effect as the IGBTs 300 and 100a can be obtained.
  • FIG. 17 is a plan view of the IGBT 301 according to the third example of the third embodiment.
  • the IGBT 301 corresponds to an example in which a trench gate 33 and a P well layer 34 corresponding to the trench gate 12 and the P well layer 14 of the IGBT 101 (see FIGS. 5 and 6) are applied to the IGBT 300 (see FIG. 14).
  • the other configuration of the IGBT 301 is basically the same as that of the IGBT 300. According to the IGBT 301, the same effect as the IGBT 101 can be obtained.
  • the electric field tends to concentrate on the corner portion at the bottom portion of the trench gate 33 (see the corresponding corner portion 35 on the substrate surface).
  • such electric field concentration can be alleviated to some extent.
  • FIG. 18 is a plan view of the IGBT 302 according to the fourth example of the third embodiment.
  • the IGBT 302 corresponds to an example in which the dummy trench gate 15 and the base layer 16 of the IGBT 102 (see FIGS. 7 and 8) are applied to the IGBT 301 (see FIG. 17) instead of the P-well layer 34.
  • the other configuration of the IGBT 302 is basically the same as that of the IGBT 301.
  • the dummy trench gate 36 corresponding to the dummy trench gate 15 is provided so that the separation distance between the adjacent trench gates 33 is divided by a certain dimension or less. Specifically, in the example of FIG. 18, one dummy trench gate 36 extends between adjacent trench gates 33 in a place where the distance between the trench gates 33 is small. On the other hand, the dummy trench gates 36 are arranged concentrically at a place where the distance between the trench gates 33 is large.
  • individual dummy trench gates 36 between adjacent trench gates 33 are sequentially connected to constitute an integrated dummy trench gate 36.
  • the dummy trench gate 36 is surrounded by the dummy gate insulating film 20 similarly to the dummy trench gate 15 (see FIGS. 5 and 7).
  • the mesa portion sandwiched between the trench gate 36 and the dummy trench gate 36 and the mesa portion sandwiched between the dummy trenches 36 are inactive mesa portions 91.
  • the inactive base layer 16 is provided in the same manner as the IGBT 102.
  • FIG. 19 is a plan view of the IGBT 303 according to the fifth example of the third embodiment.
  • the IGBT 303 corresponds to an example in which the individual dummy trench gates 36 are not connected in the IGBT 302 (see FIG. 18).
  • the other configuration of the IGBT 303 is basically the same as that of the IGBT 302. Since the individual dummy trench gates 36 are not connected, each dummy trench gate 37 is isolated in the IGBT 303 as shown in FIG. Each dummy trench gate 37 is connected to the emitter electrode on the substrate surface directly above each dummy trench gate 37, for example.
  • the dummy trench gates 37 are concentrically arranged in a place where the separation distance between adjacent trench gates 33 is large, while the separation distance between the adjacent trench gates 33 is small. No dummy trench gate 37 is provided.
  • the same effect as that of the IGBT 102 (see FIGS. 7 and 8) having the dummy trench gate 15 can be obtained.
  • FIG. 20 is a plan view of the IGBT 400 according to the first example of the fourth embodiment, and FIG. 21 is a sectional view taken along line XXI-XXI in FIG. Note that FIG. 20 is a cross section taken along line XX-XX in FIG.
  • the IGBT 400 applies the shape and arrangement of the trench gate 33 of the IGBT 301 (see FIG. 17) to the IGBT 200 (see FIGS. 9 and 10), and the P well layer 14 of the IGBT 101 (see FIGS. 5 and 6). This is an applied example.
  • each trench gate 40 has the same shape as the trench gate 33 (see FIG. 17), and these trench gates 40 are arranged in the same manner as the arrangement of the trench gates 33 in the IGBT 301. ing.
  • the trench gate 40 is surrounded by the gate insulating film 13.
  • Dummy trench gates 41 are provided on both sides of the trench gate 40, respectively.
  • the dummy trench gate 41 on each side extends along the trench gate 40 at a position spaced apart from the trench gate 40 by a certain distance.
  • the dummy trench gate 41 is surrounded by the dummy gate insulating film 20.
  • the mesa portion between the trench gate 40 and the dummy trench gate 41 is an active mesa portion 90, and the base layer 4, the emitter layer 5, and the base contact layer 6 are formed in the mesa portion 90 with the IGBT 200 (FIGS. 9 and 10).
  • the emitter layer 5 is disposed on the trench gate 40 side
  • the base contact layer 6 is disposed on the dummy trench gate 41 side.
  • a mesa portion between adjacent dummy trench gates 41 is an inactive mesa portion 90, and a P well layer 42 corresponding to the P well layer 14 (see FIGS. 5 and 6) is provided.
  • the other configuration of the IGBT 400 is basically the same as that of the IGBT 200.
  • the same effect as the IGBTs 200, 301, and 101 can be obtained.
  • the electric field tends to concentrate on the corners at the bottom of the dummy trench gate 41 (see the corresponding corners 43 on the substrate surface).
  • the electric field concentration can be alleviated to some extent.
  • FIG. 22 shows a plan view of the IGBT 401 according to the second example of the fourth embodiment.
  • the IGBT 401 is an example in which the isolated dummy trench gate 37 of the IGBT 303 (see FIG. 19) is applied to the IGBT 400 (see FIGS. 20 and 21).
  • the additional dummy trench gates 44 are arranged concentrically at a place where the separation distance between the adjacent dummy trench gates 41 is large.
  • the dummy trench gates 44 are not connected to each other and are not connected to the dummy trench gate 41. Therefore, each dummy trench gate 44 is isolated from the other dummy trench gates 44 and 41.
  • the dummy trench gates 44 are provided so that the separation distance between the adjacent dummy trench gates 41 is divided by a certain dimension or less.
  • Each dummy trench gate 44 is connected to the emitter electrode on the substrate surface directly above each dummy trench gate 44, for example.
  • the dummy trench gate 44 is not provided in a place where the distance between the dummy trench gates 41 is small.
  • the mesa portion between the dummy trench gates 44 and 41 and the mesa portion between the dummy trench gates 44 and 44 are inactive mesa portions 91, and the base layer 16 is provided.
  • the other configuration of the IGBT 401 is basically the same as that of the IGBT 400.
  • the P well layer 42 can be omitted.
  • FIG. 23 shows a plan view of an IGBT 402 according to a third example of the fourth embodiment.
  • the IGBT 402 corresponds to an example in which dummy trench gates 41 and 44 are connected in the IGBT 401 (see FIG. 22). Specifically, all the dummy trench gates 44 existing between the adjacent dummy trench gates 41 are connected to both of the adjacent dummy trench gates 41 by the dummy trench gate 45.
  • the other configuration of the IGBT 402 is basically the same as that of the IGBT 401. According to the IGBT 402, it is not always necessary to connect each dummy trench gate 44 to the emitter electrode on the substrate surface directly above each dummy trench gate 44.
  • FIG. 24 is a plan view of the IGBT 403 according to the fourth example of the fourth embodiment.
  • the IGBT 403 corresponds to an example in which all the portions between the adjacent dummy trench gates 41 in the IGBT 401 (see FIG. 22) are changed to dummy trench gates.
  • the dummy trench gate 46 extends in the trench between the adjacent active mesa portions 90. Since the active mesa portion 90 extends along the trench gate 40, the width of the dummy trench gate 46 changes periodically according to the separation distance between the adjacent trench gates 40.
  • the other configuration of the IGBT 403 is basically the same as that of the IGBT 401.
  • the trench gate is drawn out to a gate electrode on the substrate surface, and the gate electrode is connected to a metal wiring provided so as to surround the emitter electrode on the substrate surface.
  • the emitter electrode is provided on the substrate surface so as to cover the IGBT cell region.
  • the trench gate and gate electrode are often formed of polysilicon.
  • Polysilicon has a higher resistance than metal, and when a trench gate made of polysilicon is spread throughout the IGBT cell region, a signal delay due to parasitic resistance of the trench gate occurs at a location away from the metal wiring.
  • the trench gates exemplified in the first to fourth embodiments are electrically insulated until they are connected to the metal wiring, the parasitic resistance tends to increase especially when the width of the trench gate is narrow.
  • the meandering trench gate exemplified in the first to fourth embodiments has a longer overall length than the straight trench gate, and therefore the parasitic resistance is increased.
  • FIG. 25 is a plan view of IGBT 500 according to the first example of the fifth embodiment.
  • the trench gate 50 of the IGBT 500 corresponds to an example in which the adjacent trench gates 33 are connected to each other at the location where the adjacent active mesa portions 90 are closest to each other in the IGBT 301 (see FIG. 17).
  • the other configuration of the IGBT 500 is basically the same as that of the IGBT 301. According to the trench gate 50, the parasitic resistance can be halved. As a result, the delay of the gate signal can be suppressed.
  • FIG. 26 is a plan view of the IGBT 501 according to the second example of the fifth embodiment.
  • the IGBT 501 corresponds to an example in which the adjacent trench gates 50 are connected by the trench gate 52 via the active mesa portion 90 in the IGBT 500 (see FIG. 25).
  • Such a trench gate 52 will be referred to as a bypass trench gate 52.
  • the bypass trench gate 52 is embedded in the semiconductor substrate 1 in the same manner as the trench gate 52.
  • the other configuration of the IGBT 501 is basically the same as that of the IGBT 501. According to the IGBT 501, since all the trench gates 50 are connected by the bypass trench gate 52, the parasitic resistance of the trench gate can be further reduced. As a result, the delay of the gate signal can be further suppressed.
  • the active mesa portion 90 is divided into an L-shape by the bypass trench gate 52 traversing the active mesa portion 90.
  • the active mesa portion 90 has a continuous meandering shape as a whole. Further, since the separation distance of the active mesa unit 90 does not change, the IE effect can be obtained without any problem.
  • the emitter layer 5 may be provided on both sides of the bypass trench gate 52. According to this, the channel width reduced by the bypass trench gate 52 can be compensated.
  • FIG. 27 shows a plan view of an IGBT 502 according to a third example of the fifth embodiment.
  • the IGBT 502 corresponds to an example in which the bypass trench gate 52 is applied to the IGBT 300 (see FIG. 14). That is, the bypass trench gate 52 can also be applied to the trench gate 30 whose width changes.
  • the other configuration of the IGBT 502 is basically the same as that of the IGBT 300.
  • FIG. 28 shows a plan view of an IGBT 503 according to a fourth example of the fifth embodiment.
  • the IGBT 503 corresponds to an example in which the bypass trench gate 52 is applied to the IGBT 403 (see FIG. 24).
  • the other configuration of the IGBT 503 is basically the same as that of the IGBT 403.
  • the dummy trench gate 46 (see FIG. 24) of the IGBT 403 becomes an isolated dummy trench gate 53 in the IGBT 503. For this reason, the isolated dummy trench gate 53 is connected to the emitter electrode on the substrate surface directly above the isolated dummy trench gate 53, for example.
  • FIG. 29 is a plan view of IGBT 600 according to the first example of the sixth embodiment.
  • the IGBT 600 corresponds to an example in which the active mesa portions 90 adjacent to each other in the IGBT 100 (see FIG. 1) are joined to each other (that is, peak portions) protruding to each other.
  • the active mesa portion 92 of the IGBT 600 has a lattice shape in a plan view of the substrate surface.
  • the active mesa portion 92 has an intersecting shape with a portion extending in the vertical direction and a portion extending in the horizontal direction.
  • the lattice-shaped active mesa portion 92 also includes a first portion extending in the first direction (vertical direction or horizontal direction in the example of FIG. 29) and a second direction (horizontal direction or vertical direction in the example of FIG. 29). ) And a second portion extending.
  • the first part can be grasped as a part extending over the entire length in the first direction, for example. Or you may grasp
  • Each part has a certain width, and the first part and the second part have the same width.
  • the separation distance of the active mesa portion 90 (here, the distance between adjacent first portions is larger than the width of the active mesa portion 92. And the separation distance between the adjacent second parts) is larger.
  • the lattice-shaped active mesa portion 92 can also be regarded as an example in which the frame-shaped active mesa portion is coupled at each corner portion. Further, the frame-shaped active mesa portion can be regarded as an example in which the first portion and the second portion are alternately and annularly coupled. In this case, the frame-shaped active mesa portion extends. It consists of two types of parts with different directions.
  • a trench gate 60 having a plan view shape corresponding to the opening shape is arranged in the lattice opening formed by the active mesa portion 92.
  • the trench gate 60 is also square in plan view.
  • the trench gates 60 are isolated, and the sides of the adjacent trench gates 60 face each other through the active mesa portion 92.
  • the other configuration of the IGBT 600 is basically the same as that of the IGBT 100.
  • Rotational symmetry is increased when the active mesa portion 92 has an intersecting shape.
  • the planar view pattern of the substrate surface has fourfold rotational symmetry. As a result, the warpage of the wafer in the IGBT manufacturing process can be suppressed.
  • the corners of the four trench gates 60 adjacent to each other are close to each other. For this reason, the electric field concentration at the bottom of the trench can be alleviated to some extent by the electric fields at the four corners acting on each other.
  • FIG. 30 shows a plan view of the IGBT 601 according to the second example of the sixth embodiment.
  • the IGBT 601 corresponds to an example in which the trench gate 60 in the IGBT 600 (see FIG. 29) is changed to a trench gate 61 having a frame shape in plan view of the substrate surface.
  • the frame-shaped trench gate 61 extends with a constant width along the active mesa portion 92 in a lattice opening formed by the active mesa portion 92 in a plan view of the substrate surface.
  • an inactive mesa portion 93 is provided over the entire inner side of the frame shape formed by the trench gate 61, and the P well layer 14 (see FIGS. 5 and 6) is provided in the inactive mesa portion 93.
  • a P well layer 62 corresponding to is provided.
  • the other configuration of the IGBT 601 is basically the same as that of the IGBT 600.
  • the same effect as the IGBT 600 can be obtained. Further, the effect due to the P well layer 14 can be obtained by the P well layer 62.
  • an isolated dummy trench gate (see, for example, the dummy trench gate 37 in FIG. 19) may be disposed.
  • the trench gates 60 and 61 are isolated, it is necessary to provide polysilicon wiring across the active mesa portion 92. However, the parasitic resistance of the gate can be reduced by increasing the thickness of the polysilicon wiring.
  • FIG. 31 shows a plan view of an IGBT 602 according to a third example of the sixth embodiment.
  • the trench gate 63 contrary to the IGBT 601, the trench gate 63 has a lattice shape, and the active mesa portion 94 has a frame shape.
  • the lattice-shaped trench gates 63 are, for example, zigzag trench gates (see the trench gate 12 illustrated in FIG. 5) or frame-shaped trench gates (see the trench gate 61 illustrated in FIG. 30). It can be grasped as a combined state. For this reason, according to the lattice-shaped trench gate 63, the parasitic resistance can be reduced. As a result, the delay of the gate signal can be suppressed.
  • the frame-shaped active mesa portion 94 can be regarded as an example in which two types of portions having different extending directions are coupled alternately and annularly.
  • An emitter layer 5 and a base contact layer 6 are formed in the active mesa portion 94. More specifically, as shown in FIG. 31, the emitter layer 5 is provided on the trench gate 63 side, and the base contact layer 6 is provided on the dummy trench gate 64 side.
  • Such a configuration is the same as that of the IGBT 200 (see FIGS. 9 and 10).
  • a frame-shaped dummy trench gate 64 is provided concentrically and isolated in a frame shape formed by the active mesa portion 94.
  • the outer dummy trench gate 64 is disposed immediately inside the frame-shaped active mesa portion 94.
  • the effect resulting from the dummy trench gate 15 and the like described above can be obtained.
  • the other configuration of the IGBT 602 is basically the same as that of the IGBT 600.
  • FIG. 32 is a plan view of the IGBT 603 according to the fourth example of the sixth embodiment.
  • the IGBT 603 corresponds to an example in which a dummy trench gate 65 is provided in the entire region surrounded by the active mesa portion 94 in the IGBT 602.
  • the other configuration of the IGBT 603 is basically the same as that of the IGBT 602.
  • the dummy trench gates 64 and 65 are isolated, for example, they are connected to the emitter electrode on the substrate surface directly above the dummy trench gates 64 and 65.
  • the shapes of the trench gates and the dummy trench gates of the IGBTs 600 to 603 have a four-fold rotational symmetry, the warpage of the wafer in the IGBT manufacturing process can be most suppressed.
  • the IGBT 603 illustrated in FIG. 32 can be considered to have improved the rotational symmetry of the IGBT 503 illustrated in FIG.
  • the material of the semiconductor substrate is not limited to silicon.
  • a semiconductor material having a wide band gap for example, a substrate made of SiC (silicon carbide) -based material, GaN (gallium nitride) -based material, or diamond may be used.
  • the switching element and the diode element configured by such a wide band gap semiconductor have high withstand voltage (voltage resistance) and high allowable current density. Therefore, the size can be reduced as compared with the silicon semiconductor.
  • the semiconductor device module incorporating these elements can be reduced in size.
  • the wide band gap semiconductor has high heat resistance, it is possible to downsize the heat sink fins of the heat sink. Further, cooling by air cooling instead of water cooling is also applicable. As a result, the semiconductor device module can be further miniaturized.
  • Impurities used for implantation are activated by substituting atoms of a semiconductor material such as B (boron), N (nitrogen), Al (aluminum), P (phosphorus), As (arsenic), and In (indium). Any material may be used as long as it is a material.
  • SiO 2 silicon oxide
  • Al 2 O 3 aluminum oxide
  • AlON aluminum oxynitride
  • HfSiO hafnium silicate
  • HfO 2 hafnium oxide
  • Y 2 O 3 Any material having high insulating properties such as (yttrium oxide) may be used.
  • the interlayer insulating film As a material for the interlayer insulating film, SiO 2 (silicon oxide), Si 3 N 4 (silicon nitride), and TEOS (normal tetraethyl silicate) can be used. Further, the interlayer insulating film may be formed of a ceramic material such as SiOF (fluorine-added silicon oxide) or SiOC (carbon-added silicon oxide) which is a low dielectric constant material. Further, the interlayer insulating film may be formed of a resin such as polyimide, an organic polymer, or the like. That is, any material can be used for the interlayer insulating film as long as the insulating property can be obtained. In particular, the lower the dielectric constant, the smaller the parasitic capacitance between the wirings.
  • SiO 2 silicon oxide
  • Si 3 N 4 silicon nitride
  • TEOS normal tetraethyl silicate
  • the interlayer insulating film may be formed of a ceramic material such as SiOF

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Abstract

Afin d'obtenir un dispositif à semi-conducteur, tel qu'un transistor bipolaire à porte isolée, présentant une résistance à l'état passant relativement faible, tout en diminuant au minimum la réduction du courant de saturation, un substrat à semi-conducteur comprend des parties mesa actives (90), lesquelles sont des parties mesa tournées vers les côtés des grilles de tranchée (2), un film isolant de grille (3) étant situé entre ces dernières, et dans lesquelles sont injectés des porteurs de charge présentant le même type de conductivité que le substrat à semi-conducteur. Chaque partie mesa active (90) comprend une pluralité de types de parties s'étendant dans différentes directions mais d'une largeur uniforme, comme on le constate dans une vue en plan de la surface du substrat. La pluralité de types de parties sont connectés les uns aux autres en alternance et périodiquement, de telle manière que la partie mesa active (90) s'étend selon une configuration en zigzag. Le substrat à semi-conducteur présente des endroits dans lesquels des parties mesa actives (90) adjacentes sont espacées les unes des autres par une distance supérieure à la largeur des parties mesa actives (90).
PCT/JP2014/055712 2013-04-23 2014-03-06 Dispositif à semi-conducteur WO2014174911A1 (fr)

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JP2017143195A (ja) * 2016-02-10 2017-08-17 株式会社デンソー 半導体装置
CN107293585A (zh) * 2017-06-30 2017-10-24 东南大学 一种快关断绝缘体上硅横向绝缘栅双极型晶体管器件
JPWO2017033315A1 (ja) * 2015-08-26 2018-04-19 三菱電機株式会社 半導体素子
JP2018170441A (ja) * 2017-03-30 2018-11-01 豊田合成株式会社 半導体装置およびその製造方法
CN108899318A (zh) * 2018-08-30 2018-11-27 无锡摩斯法特电子有限公司 一种增加vdmos沟道密度的蛇形布图结构和布图方法
US10505027B2 (en) 2017-09-14 2019-12-10 Mitsubishi Electric Corporation Semiconductor device, method of manufacturing semiconductor device and power conversion device
JP2021048251A (ja) * 2019-09-18 2021-03-25 株式会社東芝 半導体装置
EP3823037A1 (fr) * 2019-11-18 2021-05-19 Renesas Electronics Corporation Transistor bipolaire à grille isolée, igbt, avec trenches de grille ou d'émetteur à angles
CN113066861A (zh) * 2019-12-16 2021-07-02 株洲中车时代半导体有限公司 沟槽栅功率半导体器件及其制作方法
WO2023045414A1 (fr) * 2021-09-26 2023-03-30 苏州东微半导体股份有限公司 Dispositif de puissance à super-jonction semi-conductrice
WO2024062664A1 (fr) * 2022-09-22 2024-03-28 株式会社日立パワーデバイス Dispositif à semi-conducteur

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JPWO2017033315A1 (ja) * 2015-08-26 2018-04-19 三菱電機株式会社 半導体素子
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